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Author SHA1 Message Date
TSRBerry
9becbd7d72 [Ryujinx.Graphics.Shader] Address dotnet-format issues (#5373)
* dotnet format style --severity info

Some changes were manually reverted.

* Restore a few unused methods and variables

* Silence dotnet format IDE0060 warnings

* Silence dotnet format IDE0052 warnings

* Silence dotnet format IDE0059 warnings

* Address or silence dotnet format CA1069 warnings

* Address or silence dotnet format CA2211 warnings

* Address review comments

* Fix formatting for switch expressions

* Address most dotnet format whitespace warnings

* Apply dotnet format whitespace formatting

A few of them have been manually reverted and the corresponding warning was silenced

* Format if-blocks correctly

* Run dotnet format whitespace after rebase

* Run dotnet format style after rebase

* Run dotnet format whitespace after rebase

* Run dotnet format style after rebase

* Run dotnet format after rebase and remove unused usings

- analyzers
- style
- whitespace

* Disable 'prefer switch expression' rule

* Add comments to disabled warnings

* Fix naming rule violation, Convert shader properties to auto-property and convert values to const

* Simplify properties and array initialization, Use const when possible, Remove trailing commas

* Run dotnet format after rebase

* Address IDE0251 warnings

* Address a few disabled IDE0060 warnings

* Silence IDE0060 in .editorconfig

* Run dotnet format after rebase

* Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas"

This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e.

* dotnet format whitespace after rebase

* First dotnet format pass

* Fix naming rule violations

* Add trailing commas

* Remove unused members and most unnecessary value assignments

* Remove more unnecessary assignments

* Remove NRE suppressor
2023-06-28 08:59:13 +02:00
TSRBerry
e055217292 [Ryujinx.Horizon.Kernel.Generators] Address dotnet-format issues (#5376)
* Address most dotnet format whitespace warnings

* Apply dotnet format whitespace formatting

A few of them have been manually reverted and the corresponding warning was silenced

* Simplify properties and array initialization, Use const when possible, Remove trailing commas

* Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas"

This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e.

* dotnet format whitespace after rebase

* Run dotnet format pass

* Remove left-over files and adjust namespaces

* Fix alignment
2023-06-27 23:27:48 +00:00
TSRBerry
fbaf62c230 Apply new naming rule to all projects except Vp9 (#5407) 2023-06-28 01:18:19 +02:00
207 changed files with 1953 additions and 1970 deletions

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@@ -1296,11 +1296,11 @@ namespace ARMeilleure.CodeGen.X86
}
else
{
const byte mask = 0b01_00_11_10;
const byte Mask = 0b01_00_11_10;
context.Assembler.Pshufd(src1, src1, mask);
context.Assembler.Pshufd(src1, src1, Mask);
context.Assembler.Movq(dest, src1);
context.Assembler.Pshufd(src1, src1, mask);
context.Assembler.Pshufd(src1, src1, Mask);
}
}
else
@@ -1853,9 +1853,9 @@ namespace ARMeilleure.CodeGen.X86
// that the OS will map all pages that we'll use. We do that by
// doing a dummy read on those pages, forcing a page fault and
// the OS to map them. If they are already mapped, nothing happens.
const int pageMask = PageSize - 1;
const int PageMask = PageSize - 1;
size = (size + pageMask) & ~pageMask;
size = (size + PageMask) & ~PageMask;
Operand rsp = Register(X86Register.Rsp);
Operand temp = Register(CallingConvention.GetIntReturnRegister());

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@@ -304,9 +304,9 @@ namespace ARMeilleure.Decoders
}
else if (opCode is IOpCode32MemMult opMemMult)
{
const int pcMask = 1 << RegisterAlias.Aarch32Pc;
const int PCMask = 1 << RegisterAlias.Aarch32Pc;
rt = (opMemMult.RegisterMask & pcMask) != 0 ? RegisterAlias.Aarch32Pc : 0;
rt = (opMemMult.RegisterMask & PCMask) != 0 ? RegisterAlias.Aarch32Pc : 0;
rn = opMemMult.Rn;
wBack = opMemMult.PostOffset != 0;
isLoad = opMemMult.IsLoad;

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@@ -17,7 +17,7 @@ namespace ARMeilleure.Decoders.Optimizations
throw new InvalidOperationException("Function entry point is not contained in a block.");
}
const ulong allowance = 4;
const ulong Allowance = 4;
Block entryBlock = blocks[entryBlockId];
@@ -31,7 +31,7 @@ namespace ARMeilleure.Decoders.Optimizations
{
Block block = blocks[i];
if (endBlock.EndAddress < block.Address - allowance)
if (endBlock.EndAddress < block.Address - Allowance)
{
break; // End of contiguous function.
}
@@ -44,7 +44,7 @@ namespace ARMeilleure.Decoders.Optimizations
{
Block block = blocks[i];
if (startBlock.Address > block.EndAddress + allowance)
if (startBlock.Address > block.EndAddress + Allowance)
{
break; // End of contiguous function.
}

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@@ -1299,17 +1299,17 @@ namespace ARMeilleure.Instructions
Debug.Assert((op.Size & 1) == 0 && op.RegisterSize == RegisterSize.Simd128);
const int sm0 = 0 << 6 | 0 << 4 | 0 << 2 | 0 << 0;
const int sm1 = 1 << 6 | 1 << 4 | 1 << 2 | 1 << 0;
const int sm2 = 2 << 6 | 2 << 4 | 2 << 2 | 2 << 0;
const int sm3 = 3 << 6 | 3 << 4 | 3 << 2 | 3 << 0;
const int SM0 = 0 << 6 | 0 << 4 | 0 << 2 | 0 << 0;
const int SM1 = 1 << 6 | 1 << 4 | 1 << 2 | 1 << 0;
const int SM2 = 2 << 6 | 2 << 4 | 2 << 2 | 2 << 0;
const int SM3 = 3 << 6 | 3 << 4 | 3 << 2 | 3 << 0;
Operand nCopy = context.Copy(GetVec(op.Rn));
Operand part0 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(sm0));
Operand part1 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(sm1));
Operand part2 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(sm2));
Operand part3 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(sm3));
Operand part0 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(SM0));
Operand part1 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(SM1));
Operand part2 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(SM2));
Operand part3 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, nCopy, Const(SM3));
Operand res = emit(emit(part0, part1), emit(part2, part3));
@@ -1340,13 +1340,13 @@ namespace ARMeilleure.Instructions
if ((op.Size & 1) == 0)
{
const int sm0 = 2 << 6 | 2 << 4 | 2 << 2 | 0 << 0;
const int sm1 = 2 << 6 | 2 << 4 | 2 << 2 | 1 << 0;
const int SM0 = 2 << 6 | 2 << 4 | 2 << 2 | 0 << 0;
const int SM1 = 2 << 6 | 2 << 4 | 2 << 2 | 1 << 0;
Operand zeroN = context.VectorZeroUpper64(n);
op0 = context.AddIntrinsic(Intrinsic.X86Pshufd, zeroN, Const(sm0));
op1 = context.AddIntrinsic(Intrinsic.X86Pshufd, zeroN, Const(sm1));
op0 = context.AddIntrinsic(Intrinsic.X86Pshufd, zeroN, Const(SM0));
op1 = context.AddIntrinsic(Intrinsic.X86Pshufd, zeroN, Const(SM1));
}
else /* if ((op.Size & 1) == 1) */
{
@@ -1412,11 +1412,11 @@ namespace ARMeilleure.Instructions
}
else /* if (op.RegisterSize == RegisterSize.Simd128) */
{
const int sm0 = 2 << 6 | 0 << 4 | 2 << 2 | 0 << 0;
const int sm1 = 3 << 6 | 1 << 4 | 3 << 2 | 1 << 0;
const int SM0 = 2 << 6 | 0 << 4 | 2 << 2 | 0 << 0;
const int SM1 = 3 << 6 | 1 << 4 | 3 << 2 | 1 << 0;
Operand part0 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, mCopy, Const(sm0));
Operand part1 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, mCopy, Const(sm1));
Operand part0 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, mCopy, Const(SM0));
Operand part1 = context.AddIntrinsic(Intrinsic.X86Shufps, nCopy, mCopy, Const(SM1));
context.Copy(GetVec(op.Rd), emit(part0, part1));
}

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@@ -408,7 +408,7 @@ namespace ARMeilleure.Instructions
if (Optimizations.UseGfni)
{
const long bitMatrix =
const long BitMatrix =
(0b10000000L << 56) |
(0b01000000L << 48) |
(0b00100000L << 40) |
@@ -418,7 +418,7 @@ namespace ARMeilleure.Instructions
(0b00000010L << 8) |
(0b00000001L << 0);
Operand vBitMatrix = X86GetAllElements(context, bitMatrix);
Operand vBitMatrix = X86GetAllElements(context, BitMatrix);
Operand res = context.AddIntrinsic(Intrinsic.X86Gf2p8affineqb, GetVec(op.Rn), vBitMatrix, Const(0));
@@ -469,12 +469,12 @@ namespace ARMeilleure.Instructions
Operand n = GetVec(op.Rn);
const long maskE0 = 06L << 56 | 07L << 48 | 04L << 40 | 05L << 32 | 02L << 24 | 03L << 16 | 00L << 8 | 01L << 0;
const long maskE1 = 14L << 56 | 15L << 48 | 12L << 40 | 13L << 32 | 10L << 24 | 11L << 16 | 08L << 8 | 09L << 0;
const long MaskE0 = 06L << 56 | 07L << 48 | 04L << 40 | 05L << 32 | 02L << 24 | 03L << 16 | 00L << 8 | 01L << 0;
const long MaskE1 = 14L << 56 | 15L << 48 | 12L << 40 | 13L << 32 | 10L << 24 | 11L << 16 | 08L << 8 | 09L << 0;
Operand mask = X86GetScalar(context, maskE0);
Operand mask = X86GetScalar(context, MaskE0);
mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3);
mask = EmitVectorInsert(context, mask, Const(MaskE1), 1, 3);
Operand res = context.AddIntrinsic(Intrinsic.X86Pshufb, n, mask);
@@ -503,21 +503,21 @@ namespace ARMeilleure.Instructions
if (op.Size == 0)
{
const long maskE0 = 04L << 56 | 05L << 48 | 06L << 40 | 07L << 32 | 00L << 24 | 01L << 16 | 02L << 8 | 03L << 0;
const long maskE1 = 12L << 56 | 13L << 48 | 14L << 40 | 15L << 32 | 08L << 24 | 09L << 16 | 10L << 8 | 11L << 0;
const long MaskE0 = 04L << 56 | 05L << 48 | 06L << 40 | 07L << 32 | 00L << 24 | 01L << 16 | 02L << 8 | 03L << 0;
const long MaskE1 = 12L << 56 | 13L << 48 | 14L << 40 | 15L << 32 | 08L << 24 | 09L << 16 | 10L << 8 | 11L << 0;
mask = X86GetScalar(context, maskE0);
mask = X86GetScalar(context, MaskE0);
mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3);
mask = EmitVectorInsert(context, mask, Const(MaskE1), 1, 3);
}
else /* if (op.Size == 1) */
{
const long maskE0 = 05L << 56 | 04L << 48 | 07L << 40 | 06L << 32 | 01L << 24 | 00L << 16 | 03L << 8 | 02L << 0;
const long maskE1 = 13L << 56 | 12L << 48 | 15L << 40 | 14L << 32 | 09L << 24 | 08L << 16 | 11L << 8 | 10L << 0;
const long MaskE0 = 05L << 56 | 04L << 48 | 07L << 40 | 06L << 32 | 01L << 24 | 00L << 16 | 03L << 8 | 02L << 0;
const long MaskE1 = 13L << 56 | 12L << 48 | 15L << 40 | 14L << 32 | 09L << 24 | 08L << 16 | 11L << 8 | 10L << 0;
mask = X86GetScalar(context, maskE0);
mask = X86GetScalar(context, MaskE0);
mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3);
mask = EmitVectorInsert(context, mask, Const(MaskE1), 1, 3);
}
Operand res = context.AddIntrinsic(Intrinsic.X86Pshufb, n, mask);
@@ -547,30 +547,30 @@ namespace ARMeilleure.Instructions
if (op.Size == 0)
{
const long maskE0 = 00L << 56 | 01L << 48 | 02L << 40 | 03L << 32 | 04L << 24 | 05L << 16 | 06L << 8 | 07L << 0;
const long maskE1 = 08L << 56 | 09L << 48 | 10L << 40 | 11L << 32 | 12L << 24 | 13L << 16 | 14L << 8 | 15L << 0;
const long MaskE0 = 00L << 56 | 01L << 48 | 02L << 40 | 03L << 32 | 04L << 24 | 05L << 16 | 06L << 8 | 07L << 0;
const long MaskE1 = 08L << 56 | 09L << 48 | 10L << 40 | 11L << 32 | 12L << 24 | 13L << 16 | 14L << 8 | 15L << 0;
mask = X86GetScalar(context, maskE0);
mask = X86GetScalar(context, MaskE0);
mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3);
mask = EmitVectorInsert(context, mask, Const(MaskE1), 1, 3);
}
else if (op.Size == 1)
{
const long maskE0 = 01L << 56 | 00L << 48 | 03L << 40 | 02L << 32 | 05L << 24 | 04L << 16 | 07L << 8 | 06L << 0;
const long maskE1 = 09L << 56 | 08L << 48 | 11L << 40 | 10L << 32 | 13L << 24 | 12L << 16 | 15L << 8 | 14L << 0;
const long MaskE0 = 01L << 56 | 00L << 48 | 03L << 40 | 02L << 32 | 05L << 24 | 04L << 16 | 07L << 8 | 06L << 0;
const long MaskE1 = 09L << 56 | 08L << 48 | 11L << 40 | 10L << 32 | 13L << 24 | 12L << 16 | 15L << 8 | 14L << 0;
mask = X86GetScalar(context, maskE0);
mask = X86GetScalar(context, MaskE0);
mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3);
mask = EmitVectorInsert(context, mask, Const(MaskE1), 1, 3);
}
else /* if (op.Size == 2) */
{
const long maskE0 = 03L << 56 | 02L << 48 | 01L << 40 | 00L << 32 | 07L << 24 | 06L << 16 | 05L << 8 | 04L << 0;
const long maskE1 = 11L << 56 | 10L << 48 | 09L << 40 | 08L << 32 | 15L << 24 | 14L << 16 | 13L << 8 | 12L << 0;
const long MaskE0 = 03L << 56 | 02L << 48 | 01L << 40 | 00L << 32 | 07L << 24 | 06L << 16 | 05L << 8 | 04L << 0;
const long MaskE1 = 11L << 56 | 10L << 48 | 09L << 40 | 08L << 32 | 15L << 24 | 14L << 16 | 13L << 8 | 12L << 0;
mask = X86GetScalar(context, maskE0);
mask = X86GetScalar(context, MaskE0);
mask = EmitVectorInsert(context, mask, Const(maskE1), 1, 3);
mask = EmitVectorInsert(context, mask, Const(MaskE1), 1, 3);
}
Operand res = context.AddIntrinsic(Intrinsic.X86Pshufb, n, mask);

View File

@@ -175,10 +175,10 @@ namespace ARMeilleure.Instructions
public static ushort FPRoundCv(double real, ExecutionContext context)
{
const int minimumExp = -14;
const int MinimumExp = -14;
const int e = 5;
const int f = 10;
const int E = 5;
const int F = 10;
bool sign;
double mantissa;
@@ -208,15 +208,15 @@ namespace ARMeilleure.Instructions
exponent++;
}
uint biasedExp = (uint)Math.Max(exponent - minimumExp + 1, 0);
uint biasedExp = (uint)Math.Max(exponent - MinimumExp + 1, 0);
if (biasedExp == 0u)
{
mantissa /= Math.Pow(2d, minimumExp - exponent);
mantissa /= Math.Pow(2d, MinimumExp - exponent);
}
uint intMant = (uint)Math.Floor(mantissa * Math.Pow(2d, f));
double error = mantissa * Math.Pow(2d, f) - (double)intMant;
uint intMant = (uint)Math.Floor(mantissa * Math.Pow(2d, F));
double error = mantissa * Math.Pow(2d, F) - (double)intMant;
if (biasedExp == 0u && (error != 0d || (context.Fpcr & FPCR.Ufe) != 0))
{
@@ -256,12 +256,12 @@ namespace ARMeilleure.Instructions
{
intMant++;
if (intMant == 1u << f)
if (intMant == 1u << F)
{
biasedExp = 1u;
}
if (intMant == 1u << (f + 1))
if (intMant == 1u << (F + 1))
{
biasedExp++;
intMant >>= 1;
@@ -272,7 +272,7 @@ namespace ARMeilleure.Instructions
if ((context.Fpcr & FPCR.Ahp) == 0)
{
if (biasedExp >= (1u << e) - 1u)
if (biasedExp >= (1u << E) - 1u)
{
resultBits = overflowToInf ? FPInfinity(sign) : FPMaxNormal(sign);
@@ -287,7 +287,7 @@ namespace ARMeilleure.Instructions
}
else
{
if (biasedExp >= 1u << e)
if (biasedExp >= 1u << E)
{
resultBits = (ushort)((sign ? 1u : 0u) << 15 | 0x7FFFu);
@@ -354,10 +354,10 @@ namespace ARMeilleure.Instructions
private static float FPRoundCv(double real, ExecutionContext context)
{
const int minimumExp = -126;
const int MinimumExp = -126;
const int e = 8;
const int f = 23;
const int E = 8;
const int F = 23;
bool sign;
double mantissa;
@@ -387,22 +387,22 @@ namespace ARMeilleure.Instructions
exponent++;
}
if ((context.Fpcr & FPCR.Fz) != 0 && exponent < minimumExp)
if ((context.Fpcr & FPCR.Fz) != 0 && exponent < MinimumExp)
{
context.Fpsr |= FPSR.Ufc;
return SoftFloat32.FPZero(sign);
}
uint biasedExp = (uint)Math.Max(exponent - minimumExp + 1, 0);
uint biasedExp = (uint)Math.Max(exponent - MinimumExp + 1, 0);
if (biasedExp == 0u)
{
mantissa /= Math.Pow(2d, minimumExp - exponent);
mantissa /= Math.Pow(2d, MinimumExp - exponent);
}
uint intMant = (uint)Math.Floor(mantissa * Math.Pow(2d, f));
double error = mantissa * Math.Pow(2d, f) - (double)intMant;
uint intMant = (uint)Math.Floor(mantissa * Math.Pow(2d, F));
double error = mantissa * Math.Pow(2d, F) - (double)intMant;
if (biasedExp == 0u && (error != 0d || (context.Fpcr & FPCR.Ufe) != 0))
{
@@ -442,12 +442,12 @@ namespace ARMeilleure.Instructions
{
intMant++;
if (intMant == 1u << f)
if (intMant == 1u << F)
{
biasedExp = 1u;
}
if (intMant == 1u << (f + 1))
if (intMant == 1u << (F + 1))
{
biasedExp++;
intMant >>= 1;
@@ -456,7 +456,7 @@ namespace ARMeilleure.Instructions
float result;
if (biasedExp >= (1u << e) - 1u)
if (biasedExp >= (1u << E) - 1u)
{
result = overflowToInf ? SoftFloat32.FPInfinity(sign) : SoftFloat32.FPMaxNormal(sign);
@@ -529,10 +529,10 @@ namespace ARMeilleure.Instructions
private static double FPRoundCv(double real, ExecutionContext context)
{
const int minimumExp = -1022;
const int MinimumExp = -1022;
const int e = 11;
const int f = 52;
const int E = 11;
const int F = 52;
bool sign;
double mantissa;
@@ -562,22 +562,22 @@ namespace ARMeilleure.Instructions
exponent++;
}
if ((context.Fpcr & FPCR.Fz) != 0 && exponent < minimumExp)
if ((context.Fpcr & FPCR.Fz) != 0 && exponent < MinimumExp)
{
context.Fpsr |= FPSR.Ufc;
return SoftFloat64.FPZero(sign);
}
uint biasedExp = (uint)Math.Max(exponent - minimumExp + 1, 0);
uint biasedExp = (uint)Math.Max(exponent - MinimumExp + 1, 0);
if (biasedExp == 0u)
{
mantissa /= Math.Pow(2d, minimumExp - exponent);
mantissa /= Math.Pow(2d, MinimumExp - exponent);
}
ulong intMant = (ulong)Math.Floor(mantissa * Math.Pow(2d, f));
double error = mantissa * Math.Pow(2d, f) - (double)intMant;
ulong intMant = (ulong)Math.Floor(mantissa * Math.Pow(2d, F));
double error = mantissa * Math.Pow(2d, F) - (double)intMant;
if (biasedExp == 0u && (error != 0d || (context.Fpcr & FPCR.Ufe) != 0))
{
@@ -617,12 +617,12 @@ namespace ARMeilleure.Instructions
{
intMant++;
if (intMant == 1ul << f)
if (intMant == 1ul << F)
{
biasedExp = 1u;
}
if (intMant == 1ul << (f + 1))
if (intMant == 1ul << (F + 1))
{
biasedExp++;
intMant >>= 1;
@@ -631,7 +631,7 @@ namespace ARMeilleure.Instructions
double result;
if (biasedExp >= (1u << e) - 1u)
if (biasedExp >= (1u << E) - 1u)
{
result = overflowToInf ? SoftFloat64.FPInfinity(sign) : SoftFloat64.FPMaxNormal(sign);

View File

@@ -5,7 +5,6 @@ using ARMeilleure.Translation.Cache;
using System;
using System.Runtime.CompilerServices;
using System.Runtime.InteropServices;
using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
namespace ARMeilleure.Signal
@@ -261,20 +260,20 @@ namespace ARMeilleure.Signal
{
if (OperatingSystem.IsMacOS())
{
const ulong mcontextOffset = 48; // uc_mcontext
Operand ctxPtr = context.Load(OperandType.I64, context.Add(ucontextPtr, Const(mcontextOffset)));
const ulong McontextOffset = 48; // uc_mcontext
Operand ctxPtr = context.Load(OperandType.I64, context.Add(ucontextPtr, Const(McontextOffset)));
if (RuntimeInformation.ProcessArchitecture == Architecture.Arm64)
{
const ulong esrOffset = 8; // __es.__esr
Operand esr = context.Load(OperandType.I64, context.Add(ctxPtr, Const(esrOffset)));
const ulong EsrOffset = 8; // __es.__esr
Operand esr = context.Load(OperandType.I64, context.Add(ctxPtr, Const(EsrOffset)));
return context.BitwiseAnd(esr, Const(0x40ul));
}
if (RuntimeInformation.ProcessArchitecture == Architecture.X64)
{
const ulong errOffset = 4; // __es.__err
Operand err = context.Load(OperandType.I64, context.Add(ctxPtr, Const(errOffset)));
const ulong ErrOffset = 4; // __es.__err
Operand err = context.Load(OperandType.I64, context.Add(ctxPtr, Const(ErrOffset)));
return context.BitwiseAnd(err, Const(2ul));
}
}
@@ -287,10 +286,10 @@ namespace ARMeilleure.Signal
Operand loopLabel = Label();
Operand successLabel = Label();
const ulong auxOffset = 464; // uc_mcontext.__reserved
const uint esrMagic = 0x45535201;
const ulong AuxOffset = 464; // uc_mcontext.__reserved
const uint EsrMagic = 0x45535201;
context.Copy(auxPtr, context.Add(ucontextPtr, Const(auxOffset)));
context.Copy(auxPtr, context.Add(ucontextPtr, Const(AuxOffset)));
context.MarkLabel(loopLabel);
@@ -299,7 +298,7 @@ namespace ARMeilleure.Signal
// _aarch64_ctx::size
Operand size = context.Load(OperandType.I32, context.Add(auxPtr, Const(4ul)));
context.BranchIf(successLabel, magic, Const(esrMagic), Comparison.Equal);
context.BranchIf(successLabel, magic, Const(EsrMagic), Comparison.Equal);
context.Copy(auxPtr, context.Add(auxPtr, context.ZeroExtend32(OperandType.I64, size)));
@@ -314,8 +313,8 @@ namespace ARMeilleure.Signal
if (RuntimeInformation.ProcessArchitecture == Architecture.X64)
{
const int errOffset = 192; // uc_mcontext.gregs[REG_ERR]
Operand err = context.Load(OperandType.I64, context.Add(ucontextPtr, Const(errOffset)));
const int ErrOffset = 192; // uc_mcontext.gregs[REG_ERR]
Operand err = context.Load(OperandType.I64, context.Add(ucontextPtr, Const(ErrOffset)));
return context.BitwiseAnd(err, Const(2ul));
}
}

View File

@@ -880,7 +880,7 @@ namespace ARMeilleure.Translation.PTC
private void ReportProgress(object state)
{
const int refreshRate = 50; // ms.
const int RefreshRate = 50; // ms.
AutoResetEvent endEvent = (AutoResetEvent)state;
@@ -896,7 +896,7 @@ namespace ARMeilleure.Translation.PTC
count = newCount;
}
}
while (!endEvent.WaitOne(refreshRate));
while (!endEvent.WaitOne(RefreshRate));
}
public static Hash128 ComputeHash(IMemoryManager memory, ulong address, ulong guestSize)

View File

@@ -43,7 +43,7 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command
public void Process(CommandList context)
{
const int targetChannelCount = 2;
const int TargetChannelCount = 2;
ulong currentOffset = CurrentOffset;
@@ -59,10 +59,10 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command
for (int y = 0; y < context.SampleCount; y++)
{
context.MemoryManager.Write(targetOffset + (ulong)y * targetChannelCount, PcmHelper.Saturate(inputBuffer[y]));
context.MemoryManager.Write(targetOffset + (ulong)y * TargetChannelCount, PcmHelper.Saturate(inputBuffer[y]));
}
currentOffset += context.SampleCount * targetChannelCount;
currentOffset += context.SampleCount * TargetChannelCount;
if (currentOffset >= CircularBufferSize)
{
@@ -73,4 +73,4 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command
}
}
}
}
}

View File

@@ -56,7 +56,7 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command
[MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)]
private unsafe void ProcessDelayMono(ref DelayState state, float* outputBuffer, float* inputBuffer, uint sampleCount)
{
const ushort channelCount = 1;
const ushort ChannelCount = 1;
float feedbackGain = FixedPointHelper.ToFloat(Parameter.FeedbackGain, FixedPointPrecision);
float inGain = FixedPointHelper.ToFloat(Parameter.InGain, FixedPointPrecision);
@@ -70,7 +70,7 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command
float temp = input * inGain + delayLineValue * feedbackGain;
state.UpdateLowPassFilter(ref temp, channelCount);
state.UpdateLowPassFilter(ref temp, ChannelCount);
outputBuffer[i] = (input * dryGain + delayLineValue * outGain) / 64;
}
@@ -79,7 +79,7 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command
[MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)]
private unsafe void ProcessDelayStereo(ref DelayState state, Span<IntPtr> outputBuffers, ReadOnlySpan<IntPtr> inputBuffers, uint sampleCount)
{
const ushort channelCount = 2;
const ushort ChannelCount = 2;
float delayFeedbackBaseGain = state.DelayFeedbackBaseGain;
float delayFeedbackCrossGain = state.DelayFeedbackCrossGain;
@@ -106,7 +106,7 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command
Vector2 temp = MatrixHelper.Transform(ref delayLineValues, ref delayFeedback) + channelInput * inGain;
state.UpdateLowPassFilter(ref Unsafe.As<Vector2, float>(ref temp), channelCount);
state.UpdateLowPassFilter(ref Unsafe.As<Vector2, float>(ref temp), ChannelCount);
*((float*)outputBuffers[0] + i) = (channelInput.X * dryGain + delayLineValues.X * outGain) / 64;
*((float*)outputBuffers[1] + i) = (channelInput.Y * dryGain + delayLineValues.Y * outGain) / 64;
@@ -116,7 +116,7 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command
[MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)]
private unsafe void ProcessDelayQuadraphonic(ref DelayState state, Span<IntPtr> outputBuffers, ReadOnlySpan<IntPtr> inputBuffers, uint sampleCount)
{
const ushort channelCount = 4;
const ushort ChannelCount = 4;
float delayFeedbackBaseGain = state.DelayFeedbackBaseGain;
float delayFeedbackCrossGain = state.DelayFeedbackCrossGain;
@@ -150,7 +150,7 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command
Vector4 temp = MatrixHelper.Transform(ref delayLineValues, ref delayFeedback) + channelInput * inGain;
state.UpdateLowPassFilter(ref Unsafe.As<Vector4, float>(ref temp), channelCount);
state.UpdateLowPassFilter(ref Unsafe.As<Vector4, float>(ref temp), ChannelCount);
*((float*)outputBuffers[0] + i) = (channelInput.X * dryGain + delayLineValues.X * outGain) / 64;
*((float*)outputBuffers[1] + i) = (channelInput.Y * dryGain + delayLineValues.Y * outGain) / 64;
@@ -162,7 +162,7 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command
[MethodImpl(MethodImplOptions.AggressiveInlining | MethodImplOptions.AggressiveOptimization)]
private unsafe void ProcessDelaySurround(ref DelayState state, Span<IntPtr> outputBuffers, ReadOnlySpan<IntPtr> inputBuffers, uint sampleCount)
{
const ushort channelCount = 6;
const ushort ChannelCount = 6;
float feedbackGain = FixedPointHelper.ToFloat(Parameter.FeedbackGain, FixedPointPrecision);
float delayFeedbackBaseGain = state.DelayFeedbackBaseGain;
@@ -202,7 +202,7 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command
Vector6 temp = MatrixHelper.Transform(ref delayLineValues, ref delayFeedback) + channelInput * inGain;
state.UpdateLowPassFilter(ref Unsafe.As<Vector6, float>(ref temp), channelCount);
state.UpdateLowPassFilter(ref Unsafe.As<Vector6, float>(ref temp), ChannelCount);
*((float*)outputBuffers[0] + i) = (channelInput.X * dryGain + delayLineValues.X * outGain) / 64;
*((float*)outputBuffers[1] + i) = (channelInput.Y * dryGain + delayLineValues.Y * outGain) / 64;
@@ -277,4 +277,4 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command
ProcessDelay(context, ref state);
}
}
}
}

View File

@@ -65,7 +65,7 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command
int channelCount = (int)device.GetChannelCount();
uint bufferCount = Math.Min(device.GetChannelCount(), InputCount);
const int sampleCount = Constants.TargetSampleCount;
const int SampleCount = Constants.TargetSampleCount;
uint inputCount;
@@ -79,13 +79,13 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command
inputCount = bufferCount;
}
short[] outputBuffer = new short[inputCount * sampleCount];
short[] outputBuffer = new short[inputCount * SampleCount];
for (int i = 0; i < bufferCount; i++)
{
ReadOnlySpan<float> inputBuffer = GetBuffer(InputBufferIndices[i], sampleCount);
ReadOnlySpan<float> inputBuffer = GetBuffer(InputBufferIndices[i], SampleCount);
for (int j = 0; j < sampleCount; j++)
for (int j = 0; j < SampleCount; j++)
{
outputBuffer[i + j * channelCount] = PcmHelper.Saturate(inputBuffer[j]);
}
@@ -100,4 +100,4 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command
}
}
}
}
}

View File

@@ -96,7 +96,7 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command
private unsafe void ProcessReverb3dGeneric(ref Reverb3dState state, ReadOnlySpan<IntPtr> outputBuffers, ReadOnlySpan<IntPtr> inputBuffers, uint sampleCount, ReadOnlySpan<int> outputEarlyIndicesTable, ReadOnlySpan<int> targetEarlyDelayLineIndicesTable, ReadOnlySpan<int> targetOutputFeedbackIndicesTable)
{
const int delayLineSampleIndexOffset = 1;
const int DelayLineSampleIndexOffset = 1;
bool isMono = Parameter.ChannelCount == 1;
bool isSurround = Parameter.ChannelCount == 6;
@@ -111,14 +111,14 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command
{
outputValues.Fill(0);
float tapOut = state.PreDelayLine.TapUnsafe(state.ReflectionDelayTime, delayLineSampleIndexOffset);
float tapOut = state.PreDelayLine.TapUnsafe(state.ReflectionDelayTime, DelayLineSampleIndexOffset);
for (int i = 0; i < targetEarlyDelayLineIndicesTable.Length; i++)
{
int earlyDelayIndex = targetEarlyDelayLineIndicesTable[i];
int outputIndex = outputEarlyIndicesTable[earlyDelayIndex];
float tempTapOut = state.PreDelayLine.TapUnsafe(state.EarlyDelayTime[earlyDelayIndex], delayLineSampleIndexOffset);
float tempTapOut = state.PreDelayLine.TapUnsafe(state.EarlyDelayTime[earlyDelayIndex], DelayLineSampleIndexOffset);
outputValues[outputIndex] += tempTapOut * state.EarlyGain[earlyDelayIndex];
}
@@ -251,4 +251,4 @@ namespace Ryujinx.Audio.Renderer.Dsp.Command
ProcessReverb3d(context, ref state);
}
}
}
}

View File

@@ -44,9 +44,9 @@ namespace Ryujinx.Audio.Renderer.Dsp
public static void ProcessWaveBuffers(IVirtualMemoryManager memoryManager, Span<float> outputBuffer, ref WaveBufferInformation info, Span<WaveBuffer> wavebuffers, ref VoiceUpdateState voiceState, uint targetSampleRate, int sampleCount)
{
const int tempBufferSize = 0x3F00;
const int TempBufferSize = 0x3F00;
Span<short> tempBuffer = stackalloc short[tempBufferSize];
Span<short> tempBuffer = stackalloc short[TempBufferSize];
float sampleRateRatio = (float)info.SourceSampleRate / targetSampleRate * info.Pitch;
@@ -60,11 +60,11 @@ namespace Ryujinx.Audio.Renderer.Dsp
int totalNeededSize = (int)MathF.Truncate(fraction + sampleRateRatio * sampleCount);
if (totalNeededSize + pitchMaxLength <= tempBufferSize && totalNeededSize >= 0)
if (totalNeededSize + pitchMaxLength <= TempBufferSize && totalNeededSize >= 0)
{
int sourceSampleCountToProcess = sampleCount;
int maxSampleCountPerIteration = Math.Min((int)MathF.Truncate((tempBufferSize - fraction) / sampleRateRatio), sampleCount);
int maxSampleCountPerIteration = Math.Min((int)MathF.Truncate((TempBufferSize - fraction) / sampleRateRatio), sampleCount);
bool isStarving = false;
@@ -463,4 +463,4 @@ namespace Ryujinx.Audio.Renderer.Dsp
}
}
}
}
}

View File

@@ -32,13 +32,13 @@ namespace Ryujinx.Audio.Renderer.Dsp
float BlackmanWindow(float x)
{
const float a = 0.18f;
const float a0 = 0.5f - 0.5f * a;
const float a1 = -0.5f;
const float a2 = 0.5f * a;
return a0 + a1 * MathF.Cos(2 * MathF.PI * x) + a2 * MathF.Cos(4 * MathF.PI * x);
const float A = 0.18f;
const float A0 = 0.5f - 0.5f * A;
const float A1 = -0.5f;
const float A2 = 0.5f * A;
return A0 + A1 * MathF.Cos(2 * MathF.PI * x) + A2 * MathF.Cos(4 * MathF.PI * x);
}
Array20<float> result = new Array20<float>();
for (int i = 0; i < FilterBankLength; i++)
@@ -112,7 +112,7 @@ namespace Ryujinx.Audio.Renderer.Dsp
int inputBufferIndex = 0;
switch (state.Scale)
{
{
case 6.0f:
for (int i = 0; i < outputSampleCount; i++)
{
@@ -189,4 +189,4 @@ namespace Ryujinx.Audio.Renderer.Dsp
}
}
}
}
}

View File

@@ -60,7 +60,7 @@ namespace Ryujinx.Audio.Renderer.Server
public uint Estimate(MixRampGroupedCommand command)
{
const float costPerSample = 7.245f;
const float CostPerSample = 7.245f;
Debug.Assert(_sampleCount == 160 || _sampleCount == 240);
@@ -74,7 +74,7 @@ namespace Ryujinx.Audio.Renderer.Server
}
}
return (uint)(_sampleCount * costPerSample * volumeCount);
return (uint)(_sampleCount * CostPerSample * volumeCount);
}
public uint Estimate(MixRampCommand command)
@@ -549,4 +549,4 @@ namespace Ryujinx.Audio.Renderer.Server
return 0;
}
}
}
}

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@@ -256,19 +256,19 @@ namespace Ryujinx.Audio.Renderer.Server.MemoryPool
MemoryPoolUserState outputState;
const uint pageSize = 0x1000;
const uint PageSize = 0x1000;
if (inputState != MemoryPoolUserState.RequestAttach && inputState != MemoryPoolUserState.RequestDetach)
{
return UpdateResult.Success;
}
if (inParameter.CpuAddress == 0 || (inParameter.CpuAddress % pageSize) != 0)
if (inParameter.CpuAddress == 0 || (inParameter.CpuAddress % PageSize) != 0)
{
return UpdateResult.InvalidParameter;
}
if (inParameter.Size == 0 || (inParameter.Size % pageSize) != 0)
if (inParameter.Size == 0 || (inParameter.Size % PageSize) != 0)
{
return UpdateResult.InvalidParameter;
}
@@ -363,4 +363,4 @@ namespace Ryujinx.Audio.Renderer.Server.MemoryPool
}
}
}
}
}

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@@ -10,8 +10,8 @@ using Ryujinx.Ava.UI.Helpers;
using Ryujinx.Ava.UI.ViewModels;
using Ryujinx.Ava.UI.Windows;
using Ryujinx.Common.Configuration;
using Ryujinx.Ui.App.Common;
using Ryujinx.HLE.HOS;
using Ryujinx.Ui.App.Common;
using Ryujinx.Ui.Common.Helper;
using System;
using System.Collections.Generic;

View File

@@ -40,9 +40,9 @@ namespace Ryujinx.Ava.UI.Models
private string GetSizeString()
{
const int scale = 1024;
const int Scale = 1024;
string[] orders = { "GiB", "MiB", "KiB" };
long max = (long)Math.Pow(scale, orders.Length);
long max = (long)Math.Pow(Scale, orders.Length);
foreach (string order in orders)
{
@@ -51,7 +51,7 @@ namespace Ryujinx.Ava.UI.Models
return $"{decimal.Divide(Size, max):##.##} {order}";
}
max /= scale;
max /= Scale;
}
return "0 KiB";
@@ -109,4 +109,4 @@ namespace Ryujinx.Ava.UI.Models
}
}
}
}

View File

@@ -622,7 +622,7 @@ namespace Ryujinx.Ava.UI.ViewModels
OnPropertyChanged();
}
}
public double WindowWidth
{
get => _windowWidth;
@@ -1124,13 +1124,13 @@ namespace Ryujinx.Ava.UI.ViewModels
var dominantColor = IconColorPicker.GetFilteredColor(gameIconBmp).ToPixel<Bgra32>();
const float colorMultiple = 0.5f;
const float ColorMultiple = 0.5f;
Color progressFgColor = Color.FromRgb(dominantColor.R, dominantColor.G, dominantColor.B);
Color progressBgColor = Color.FromRgb(
(byte)(dominantColor.R * colorMultiple),
(byte)(dominantColor.G * colorMultiple),
(byte)(dominantColor.B * colorMultiple));
(byte)(dominantColor.R * ColorMultiple),
(byte)(dominantColor.G * ColorMultiple),
(byte)(dominantColor.B * ColorMultiple));
ProgressBarForegroundColor = new SolidColorBrush(progressFgColor);
ProgressBarBackgroundColor = new SolidColorBrush(progressBgColor);
@@ -1677,4 +1677,4 @@ namespace Ryujinx.Ava.UI.ViewModels
#endregion
}
}
}

View File

@@ -18,14 +18,14 @@ using Ryujinx.HLE.FileSystem;
using Ryujinx.HLE.HOS.Services.Time.TimeZone;
using Ryujinx.Ui.Common.Configuration;
using Ryujinx.Ui.Common.Configuration.System;
using Silk.NET.Vulkan;
using System;
using System.Collections.Generic;
using System.Collections.ObjectModel;
using System.Linq;
using System.Runtime.InteropServices;
using System.Net.NetworkInformation;
using System.Runtime.InteropServices;
using TimeZone = Ryujinx.Ava.UI.Models.TimeZone;
using Silk.NET.Vulkan;
namespace Ryujinx.Ava.UI.ViewModels
{

View File

@@ -44,10 +44,10 @@ namespace Ryujinx.Common.SystemInfo
return 0;
}
const int flavor = 4; // HOST_VM_INFO64
const int Flavor = 4; // HOST_VM_INFO64
uint count = (uint)(Marshal.SizeOf<VMStatistics64>() / sizeof(int)); // HOST_VM_INFO64_COUNT
VMStatistics64 stats = new();
result = host_statistics64(port, flavor, ref stats, ref count);
result = host_statistics64(port, Flavor, ref stats, ref count);
if (result != 0)
{
@@ -154,4 +154,4 @@ namespace Ryujinx.Common.SystemInfo
[LibraryImport(SystemLibraryName, SetLastError = true)]
private static partial int host_statistics64(uint host_priv, int host_flavor, ref VMStatistics64 host_info64_out, ref uint host_info64_outCnt);
}
}
}

View File

@@ -29,10 +29,10 @@ namespace Ryujinx.Common.SystemInterop
[SupportedOSPlatform("macos")]
private void RegisterPosix()
{
const int stdErrFileno = 2;
const int StdErrFileno = 2;
(int readFd, int writeFd) = MakePipe();
dup2(writeFd, stdErrFileno);
dup2(writeFd, StdErrFileno);
_pipeReader = CreateFileDescriptorStream(readFd);
_pipeWriter = CreateFileDescriptorStream(writeFd);

View File

@@ -6,8 +6,8 @@ using Ryujinx.Memory.Range;
using Ryujinx.Memory.Tracking;
using System;
using System.Collections.Generic;
using System.Runtime.InteropServices;
using System.Linq;
using System.Runtime.InteropServices;
using System.Threading;
namespace Ryujinx.Graphics.Gpu.Memory

View File

@@ -9,6 +9,6 @@ namespace Ryujinx.Graphics.Shader
Greater,
NotEqual,
GreaterOrEqual,
Always
Always,
}
}
}

View File

@@ -8,7 +8,7 @@ namespace Ryujinx.Graphics.Shader
// Generic types.
Float,
Sint,
Uint
Uint,
}
static class AttributeTypeExtensions
@@ -20,7 +20,7 @@ namespace Ryujinx.Graphics.Shader
AttributeType.Float => "vec4",
AttributeType.Sint => "ivec4",
AttributeType.Uint => "uvec4",
_ => throw new ArgumentException($"Invalid attribute type \"{type}\".")
_ => throw new ArgumentException($"Invalid attribute type \"{type}\"."),
};
}
@@ -31,8 +31,8 @@ namespace Ryujinx.Graphics.Shader
AttributeType.Float => AggregateType.FP32,
AttributeType.Sint => AggregateType.S32,
AttributeType.Uint => AggregateType.U32,
_ => throw new ArgumentException($"Invalid attribute type \"{type}\".")
_ => throw new ArgumentException($"Invalid attribute type \"{type}\"."),
};
}
}
}
}

View File

@@ -37,4 +37,4 @@ namespace Ryujinx.Graphics.Shader
return this;
}
}
}
}

View File

@@ -13,6 +13,6 @@ namespace Ryujinx.Graphics.Shader
/// <summary>
/// Buffer is written to.
/// </summary>
Write = 1 << 0
Write = 1 << 0,
}
}

View File

@@ -92,4 +92,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
return indentation;
}
}
}
}

View File

@@ -244,16 +244,6 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
}
}
private static string GetTfLayout(TransformFeedbackOutput tfOutput)
{
if (tfOutput.Valid)
{
return $"layout (xfb_buffer = {tfOutput.Buffer}, xfb_offset = {tfOutput.Offset}, xfb_stride = {tfOutput.Stride}) ";
}
return string.Empty;
}
public static void DeclareLocals(CodeGenContext context, StructuredFunction function)
{
foreach (AstOperand decl in function.Locals)
@@ -294,7 +284,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
AggregateType.Vector4 | AggregateType.FP64 => "dvec4",
AggregateType.Vector4 | AggregateType.S32 => "ivec4",
AggregateType.Vector4 | AggregateType.U32 => "uvec4",
_ => throw new ArgumentException($"Invalid variable type \"{type}\".")
_ => throw new ArgumentException($"Invalid variable type \"{type}\"."),
};
}
@@ -315,7 +305,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
string layout = buffer.Layout switch
{
BufferLayout.Std140 => "std140",
_ => "std430"
_ => "std430",
};
string set = string.Empty;
@@ -507,7 +497,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
{
PixelImap.Constant => "flat ",
PixelImap.ScreenLinear => "noperspective ",
_ => string.Empty
_ => string.Empty,
};
}
@@ -524,7 +514,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
2 => "vec2",
3 => "vec3",
4 => "vec4",
_ => "float"
_ => "float",
};
context.AppendLine($"layout (location = {attr}) in {type} {name};");
@@ -611,7 +601,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
2 => "vec2",
3 => "vec3",
4 => "vec4",
_ => "float"
_ => "float",
};
string xfb = string.Empty;
@@ -647,7 +637,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
{
AttributeType.Sint => "ivec4",
AttributeType.Uint => "uvec4",
_ => "vec4"
_ => "vec4",
};
if (context.Config.GpuAccessor.QueryHostReducedPrecision() && context.Config.Stage == ShaderStage.Vertex && attr == 0)
@@ -721,4 +711,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
context.AppendLine();
}
}
}
}

View File

@@ -5,7 +5,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
public const string LocalNamePrefix = "temp";
public const string SamplerNamePrefix = "tex";
public const string ImageNamePrefix = "img";
public const string ImageNamePrefix = "img";
public const string PerPatchAttributePrefix = "patch_attr_";
public const string IAttributePrefix = "in_attr";
@@ -15,4 +15,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
public const string UndefinedName = "undef";
}
}
}

View File

@@ -13,7 +13,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
public static string Generate(StructuredProgramInfo info, ShaderConfig config)
{
CodeGenContext context = new CodeGenContext(info, config);
CodeGenContext context = new(info, config);
Declarations.Declare(context, info);
@@ -74,7 +74,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
private static void PrintBlock(CodeGenContext context, AstBlock block, bool isMainFunction)
{
AstBlockVisitor visitor = new AstBlockVisitor(block);
AstBlockVisitor visitor = new(block);
visitor.BlockEntered += (sender, e) =>
{
@@ -96,7 +96,8 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
context.AppendLine($"if ({GetCondExpr(context, e.Block.Condition)})");
break;
default: throw new InvalidOperationException($"Found unexpected block type \"{e.Block.Type}\".");
default:
throw new InvalidOperationException($"Found unexpected block type \"{e.Block.Type}\".");
}
context.EnterScope();
@@ -173,4 +174,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
return ReinterpretCast(context, cond, srcType, AggregateType.Bool);
}
}
}
}

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@@ -5,10 +5,10 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
public static string MultiplyHighS32 = "Helper_MultiplyHighS32";
public static string MultiplyHighU32 = "Helper_MultiplyHighU32";
public static string Shuffle = "Helper_Shuffle";
public static string Shuffle = "Helper_Shuffle";
public static string ShuffleDown = "Helper_ShuffleDown";
public static string ShuffleUp = "Helper_ShuffleUp";
public static string ShuffleXor = "Helper_ShuffleXor";
public static string SwizzleAdd = "Helper_SwizzleAdd";
public static string ShuffleUp = "Helper_ShuffleUp";
public static string ShuffleXor = "Helper_ShuffleXor";
public static string SwizzleAdd = "Helper_SwizzleAdd";
}
}
}

View File

@@ -197,4 +197,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
throw new InvalidOperationException($"Unexpected instruction type \"{info.Type}\".");
}
}
}
}

View File

@@ -24,4 +24,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
}
}
}
}
}

View File

@@ -26,4 +26,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
return $"{function.Name}({string.Join(", ", args)})";
}
}
}
}

View File

@@ -26,4 +26,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
return null;
}
}
}
}

View File

@@ -14,6 +14,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
{
_infoTable = new InstInfo[(int)Instruction.Count];
#pragma warning disable IDE0055 // Disable formatting
Add(Instruction.AtomicAdd, InstType.AtomicBinary, "atomicAdd");
Add(Instruction.AtomicAnd, InstType.AtomicBinary, "atomicAnd");
Add(Instruction.AtomicCompareAndSwap, InstType.AtomicTernary, "atomicCompSwap");
@@ -125,6 +126,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
Add(Instruction.VoteAll, InstType.CallUnary, "allInvocationsARB");
Add(Instruction.VoteAllEqual, InstType.CallUnary, "allInvocationsEqualARB");
Add(Instruction.VoteAny, InstType.CallUnary, "anyInvocationARB");
#pragma warning restore IDE0055
}
private static void Add(Instruction inst, InstType flags, string opName = null, int precedence = 0)
@@ -163,7 +165,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
{
// If the node isn't a operation, then it can only be a operand,
// and those never needs to be surrounded in parenthesis.
if (!(node is AstOperation operation))
if (node is not AstOperation operation)
{
// This is sort of a special case, if this is a negative constant,
// and it is consumed by a unary operation, we need to put on the parenthesis,
@@ -208,7 +210,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
private static bool IsNegativeConst(IAstNode node)
{
if (!(node is AstOperand operand))
if (node is not AstOperand operand)
{
return false;
}
@@ -216,4 +218,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
return operand.Type == OperandType.Constant && operand.Value < 0;
}
}
}
}

View File

@@ -3,7 +3,6 @@ using Ryujinx.Graphics.Shader.StructuredIr;
using Ryujinx.Graphics.Shader.Translation;
using System;
using System.Text;
using static Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions.InstGenHelper;
using static Ryujinx.Graphics.Shader.StructuredIr.InstructionInfo;
@@ -42,14 +41,16 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
}
}
bool isArray = (texOp.Type & SamplerType.Array) != 0;
bool isArray = (texOp.Type & SamplerType.Array) != 0;
bool isIndexed = (texOp.Type & SamplerType.Indexed) != 0;
var texCallBuilder = new StringBuilder();
if (texOp.Inst == Instruction.ImageAtomic)
{
texCallBuilder.Append((texOp.Flags & TextureFlags.AtomicMask) switch {
texCallBuilder.Append((texOp.Flags & TextureFlags.AtomicMask) switch
{
#pragma warning disable IDE0055 // Disable formatting
TextureFlags.Add => "imageAtomicAdd",
TextureFlags.Minimum => "imageAtomicMin",
TextureFlags.Maximum => "imageAtomicMax",
@@ -61,6 +62,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
TextureFlags.Swap => "imageAtomicExchange",
TextureFlags.CAS => "imageAtomicCompSwap",
_ => "imageAtomicAdd",
#pragma warning restore IDE0055
});
}
else
@@ -131,7 +133,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
{
AggregateType.S32 => NumberFormatter.FormatInt(0),
AggregateType.U32 => NumberFormatter.FormatUint(0),
_ => NumberFormatter.FormatFloat(0)
_ => NumberFormatter.FormatFloat(0),
};
}
}
@@ -140,7 +142,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
{
AggregateType.S32 => "i",
AggregateType.U32 => "u",
_ => string.Empty
_ => string.Empty,
};
Append($"{prefix}vec4({string.Join(", ", cElems)})");
@@ -159,7 +161,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
{
TextureFlags.Increment => NumberFormatter.FormatInt(1, type), // TODO: Clamp value
TextureFlags.Decrement => NumberFormatter.FormatInt(-1, type), // TODO: Clamp value
_ => Src(type)
_ => Src(type),
};
Append(value);
@@ -248,25 +250,25 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
{
AstTextureOperation texOp = (AstTextureOperation)operation;
bool isBindless = (texOp.Flags & TextureFlags.Bindless) != 0;
bool isGather = (texOp.Flags & TextureFlags.Gather) != 0;
bool isBindless = (texOp.Flags & TextureFlags.Bindless) != 0;
bool isGather = (texOp.Flags & TextureFlags.Gather) != 0;
bool hasDerivatives = (texOp.Flags & TextureFlags.Derivatives) != 0;
bool intCoords = (texOp.Flags & TextureFlags.IntCoords) != 0;
bool hasLodBias = (texOp.Flags & TextureFlags.LodBias) != 0;
bool hasLodLevel = (texOp.Flags & TextureFlags.LodLevel) != 0;
bool hasOffset = (texOp.Flags & TextureFlags.Offset) != 0;
bool hasOffsets = (texOp.Flags & TextureFlags.Offsets) != 0;
bool intCoords = (texOp.Flags & TextureFlags.IntCoords) != 0;
bool hasLodBias = (texOp.Flags & TextureFlags.LodBias) != 0;
bool hasLodLevel = (texOp.Flags & TextureFlags.LodLevel) != 0;
bool hasOffset = (texOp.Flags & TextureFlags.Offset) != 0;
bool hasOffsets = (texOp.Flags & TextureFlags.Offsets) != 0;
bool isArray = (texOp.Type & SamplerType.Array) != 0;
bool isIndexed = (texOp.Type & SamplerType.Indexed) != 0;
bool isArray = (texOp.Type & SamplerType.Array) != 0;
bool isIndexed = (texOp.Type & SamplerType.Indexed) != 0;
bool isMultisample = (texOp.Type & SamplerType.Multisample) != 0;
bool isShadow = (texOp.Type & SamplerType.Shadow) != 0;
bool isShadow = (texOp.Type & SamplerType.Shadow) != 0;
bool colorIsVector = isGather || !isShadow;
SamplerType type = texOp.Type & SamplerType.Mask;
bool is2D = type == SamplerType.Texture2D;
bool is2D = type == SamplerType.Texture2D;
bool isCube = type == SamplerType.TextureCube;
// 2D Array and Cube shadow samplers with LOD level or bias requires an extension.
@@ -500,14 +502,14 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
if (hasLodBias)
{
Append(Src(AggregateType.FP32));
Append(Src(AggregateType.FP32));
}
// textureGather* optional extra component index,
// not needed for shadow samplers.
if (isGather && !isShadow)
{
Append(Src(AggregateType.S32));
Append(Src(AggregateType.S32));
}
texCall += ")" + (colorIsVector ? GetMaskMultiDest(texOp.Index) : "");
@@ -584,7 +586,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
{
case StorageKind.ConstantBuffer:
case StorageKind.StorageBuffer:
if (!(operation.GetSource(srcIndex++) is AstOperand bindingIndex) || bindingIndex.Type != OperandType.Constant)
if (operation.GetSource(srcIndex++) is not AstOperand bindingIndex || bindingIndex.Type != OperandType.Constant)
{
throw new InvalidOperationException($"First input of {operation.Inst} with {storageKind} storage must be a constant operand.");
}
@@ -594,7 +596,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
? context.Config.Properties.ConstantBuffers[binding]
: context.Config.Properties.StorageBuffers[binding];
if (!(operation.GetSource(srcIndex++) is AstOperand fieldIndex) || fieldIndex.Type != OperandType.Constant)
if (operation.GetSource(srcIndex++) is not AstOperand fieldIndex || fieldIndex.Type != OperandType.Constant)
{
throw new InvalidOperationException($"Second input of {operation.Inst} with {storageKind} storage must be a constant operand.");
}
@@ -606,7 +608,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
case StorageKind.LocalMemory:
case StorageKind.SharedMemory:
if (!(operation.GetSource(srcIndex++) is AstOperand bindingId) || bindingId.Type != OperandType.Constant)
if (operation.GetSource(srcIndex++) is not AstOperand { Type: OperandType.Constant } bindingId)
{
throw new InvalidOperationException($"First input of {operation.Inst} with {storageKind} storage must be a constant operand.");
}
@@ -623,7 +625,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
case StorageKind.InputPerPatch:
case StorageKind.Output:
case StorageKind.OutputPerPatch:
if (!(operation.GetSource(srcIndex++) is AstOperand varId) || varId.Type != OperandType.Constant)
if (operation.GetSource(srcIndex++) is not AstOperand varId || varId.Type != OperandType.Constant)
{
throw new InvalidOperationException($"First input of {operation.Inst} with {storageKind} storage must be a constant operand.");
}
@@ -636,7 +638,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
if (context.Config.HasPerLocationInputOrOutput(ioVariable, isOutput))
{
if (!(operation.GetSource(srcIndex++) is AstOperand vecIndex) || vecIndex.Type != OperandType.Constant)
if (operation.GetSource(srcIndex++) is not AstOperand vecIndex || vecIndex.Type != OperandType.Constant)
{
throw new InvalidOperationException($"Second input of {operation.Inst} with {storageKind} storage must be a constant operand.");
}
@@ -733,4 +735,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
return swizzle;
}
}
}
}

View File

@@ -53,4 +53,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
return $".{"xy".AsSpan(index, 1)}";
}
}
}
}

View File

@@ -29,4 +29,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
}
}
}
}
}

View File

@@ -10,9 +10,9 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
public InstInfo(InstType type, string opName, int precedence)
{
Type = type;
OpName = opName;
Type = type;
OpName = opName;
Precedence = precedence;
}
}
}
}

View File

@@ -1,33 +1,35 @@
using System;
using System.Diagnostics.CodeAnalysis;
namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
{
[Flags]
[SuppressMessage("Design", "CA1069: Enums values should not be duplicated")]
enum InstType
{
OpNullary = Op | 0,
OpUnary = Op | 1,
OpBinary = Op | 2,
OpNullary = Op | 0,
OpUnary = Op | 1,
OpBinary = Op | 2,
OpBinaryCom = Op | 2 | Commutative,
OpTernary = Op | 3,
OpTernary = Op | 3,
CallNullary = Call | 0,
CallUnary = Call | 1,
CallBinary = Call | 2,
CallTernary = Call | 3,
CallNullary = Call | 0,
CallUnary = Call | 1,
CallBinary = Call | 2,
CallTernary = Call | 3,
CallQuaternary = Call | 4,
// The atomic instructions have one extra operand,
// for the storage slot and offset pair.
AtomicBinary = Call | Atomic | 3,
AtomicBinary = Call | Atomic | 3,
AtomicTernary = Call | Atomic | 4,
Commutative = 1 << 8,
Op = 1 << 9,
Call = 1 << 10,
Atomic = 1 << 11,
Special = 1 << 12,
Op = 1 << 9,
Call = 1 << 10,
Atomic = 1 << 11,
Special = 1 << 12,
ArityMask = 0xff
ArityMask = 0xff,
}
}
}

View File

@@ -28,7 +28,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
IoVariable.FragmentOutputColor => GetFragmentOutputColorVariableName(config, location),
IoVariable.FragmentOutputDepth => ("gl_FragDepth", AggregateType.FP32),
IoVariable.FrontColorDiffuse => ("gl_FrontColor", AggregateType.Vector4 | AggregateType.FP32), // Deprecated.
IoVariable.FrontColorSpecular => ("gl_FrontSecondaryColor", AggregateType.Vector4 | AggregateType.FP32), // Deprecated.
IoVariable.FrontColorSpecular => ("gl_FrontSecondaryColor", AggregateType.Vector4 | AggregateType.FP32), // Deprecated.
IoVariable.FrontFacing => ("gl_FrontFacing", AggregateType.Bool),
IoVariable.InstanceId => ("gl_InstanceID", AggregateType.S32),
IoVariable.InstanceIndex => ("gl_InstanceIndex", AggregateType.S32),
@@ -56,7 +56,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
IoVariable.VertexIndex => ("gl_VertexIndex", AggregateType.S32),
IoVariable.ViewportIndex => ("gl_ViewportIndex", AggregateType.S32),
IoVariable.ViewportMask => ("gl_ViewportMask", AggregateType.Array | AggregateType.S32),
_ => (null, AggregateType.Invalid)
_ => (null, AggregateType.Invalid),
};
}
@@ -139,4 +139,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl.Instructions
return (name, config.GetUserDefinedType(location, isOutput));
}
}
}
}

View File

@@ -101,4 +101,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
return "0x" + value.ToString("X", CultureInfo.InvariantCulture) + "u";
}
}
}
}

View File

@@ -5,7 +5,6 @@ using Ryujinx.Graphics.Shader.Translation;
using System;
using System.Collections.Generic;
using System.Diagnostics;
using static Ryujinx.Graphics.Shader.StructuredIr.InstructionInfo;
namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
@@ -14,7 +13,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
{
private static readonly string[] _stagePrefixes = new string[] { "cp", "vp", "tcp", "tep", "gp", "fp" };
private Dictionary<AstOperand, string> _locals;
private readonly Dictionary<AstOperand, string> _locals;
public OperandManager()
{
@@ -38,7 +37,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
OperandType.Constant => NumberFormatter.FormatInt(operand.Value),
OperandType.LocalVariable => _locals[operand],
OperandType.Undefined => DefaultNames.UndefinedName,
_ => throw new ArgumentException($"Invalid operand type \"{operand.Type}\".")
_ => throw new ArgumentException($"Invalid operand type \"{operand.Type}\"."),
};
}
@@ -96,11 +95,6 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
return _stagePrefixes[index];
}
private static char GetSwizzleMask(int value)
{
return "xyzw"[value];
}
public static string GetArgumentName(int argIndex)
{
return $"{DefaultNames.ArgumentNamePrefix}{argIndex}";
@@ -119,12 +113,12 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
{
case StorageKind.ConstantBuffer:
case StorageKind.StorageBuffer:
if (!(operation.GetSource(0) is AstOperand bindingIndex) || bindingIndex.Type != OperandType.Constant)
if (operation.GetSource(0) is not AstOperand bindingIndex || bindingIndex.Type != OperandType.Constant)
{
throw new InvalidOperationException($"First input of {operation.Inst} with {operation.StorageKind} storage must be a constant operand.");
}
if (!(operation.GetSource(1) is AstOperand fieldIndex) || fieldIndex.Type != OperandType.Constant)
if (operation.GetSource(1) is not AstOperand fieldIndex || fieldIndex.Type != OperandType.Constant)
{
throw new InvalidOperationException($"Second input of {operation.Inst} with {operation.StorageKind} storage must be a constant operand.");
}
@@ -138,7 +132,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
case StorageKind.LocalMemory:
case StorageKind.SharedMemory:
if (!(operation.GetSource(0) is AstOperand bindingId) || bindingId.Type != OperandType.Constant)
if (operation.GetSource(0) is not AstOperand { Type: OperandType.Constant } bindingId)
{
throw new InvalidOperationException($"First input of {operation.Inst} with {operation.StorageKind} storage must be a constant operand.");
}
@@ -153,7 +147,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
case StorageKind.InputPerPatch:
case StorageKind.Output:
case StorageKind.OutputPerPatch:
if (!(operation.GetSource(0) is AstOperand varId) || varId.Type != OperandType.Constant)
if (operation.GetSource(0) is not AstOperand varId || varId.Type != OperandType.Constant)
{
throw new InvalidOperationException($"First input of {operation.Inst} with {operation.StorageKind} storage must be a constant operand.");
}
@@ -166,7 +160,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
if (context.Config.HasPerLocationInputOrOutput(ioVariable, isOutput))
{
if (!(operation.GetSource(1) is AstOperand vecIndex) || vecIndex.Type != OperandType.Constant)
if (operation.GetSource(1) is not AstOperand vecIndex || vecIndex.Type != OperandType.Constant)
{
throw new InvalidOperationException($"Second input of {operation.Inst} with {operation.StorageKind} storage must be a constant operand.");
}
@@ -232,4 +226,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
}
}
}
}
}

View File

@@ -10,9 +10,9 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
{
public static string ReinterpretCast(
CodeGenContext context,
IAstNode node,
AggregateType srcType,
AggregateType dstType)
IAstNode node,
AggregateType srcType,
AggregateType dstType)
{
if (node is AstOperand operand && operand.Type == OperandType.Constant)
{
@@ -38,18 +38,24 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
{
switch (dstType)
{
case AggregateType.Bool: return $"(floatBitsToInt({expr}) != 0)";
case AggregateType.S32: return $"floatBitsToInt({expr})";
case AggregateType.U32: return $"floatBitsToUint({expr})";
case AggregateType.Bool:
return $"(floatBitsToInt({expr}) != 0)";
case AggregateType.S32:
return $"floatBitsToInt({expr})";
case AggregateType.U32:
return $"floatBitsToUint({expr})";
}
}
else if (dstType == AggregateType.FP32)
{
switch (srcType)
{
case AggregateType.Bool: return $"intBitsToFloat({ReinterpretBoolToInt(expr, node, AggregateType.S32)})";
case AggregateType.S32: return $"intBitsToFloat({expr})";
case AggregateType.U32: return $"uintBitsToFloat({expr})";
case AggregateType.Bool:
return $"intBitsToFloat({ReinterpretBoolToInt(expr, node, AggregateType.S32)})";
case AggregateType.S32:
return $"intBitsToFloat({expr})";
case AggregateType.U32:
return $"uintBitsToFloat({expr})";
}
}
else if (srcType == AggregateType.Bool)
@@ -76,7 +82,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
private static string ReinterpretBoolToInt(string expr, IAstNode node, AggregateType dstType)
{
string trueExpr = NumberFormatter.FormatInt(IrConsts.True, dstType);
string trueExpr = NumberFormatter.FormatInt(IrConsts.True, dstType);
string falseExpr = NumberFormatter.FormatInt(IrConsts.False, dstType);
expr = InstGenHelper.Enclose(expr, node, Instruction.ConditionalSelect, isLhs: false);
@@ -84,4 +90,4 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
return $"({expr} ? {trueExpr} : {falseExpr})";
}
}
}
}

View File

@@ -1,13 +1,14 @@
using Ryujinx.Graphics.Shader.StructuredIr;
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
using Ryujinx.Graphics.Shader.StructuredIr;
using Ryujinx.Graphics.Shader.Translation;
using Spv.Generator;
using System;
using System.Collections.Generic;
using static Spv.Specification;
using Instruction = Spv.Generator.Instruction;
namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
{
using IrConsts = IntermediateRepresentation.IrConsts;
using IrOperandType = IntermediateRepresentation.OperandType;
partial class CodeGenContext : Module
@@ -36,15 +37,15 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
public Dictionary<IoDefinition, Instruction> OutputsPerPatch { get; } = new Dictionary<IoDefinition, Instruction>();
public StructuredFunction CurrentFunction { get; set; }
private readonly Dictionary<AstOperand, Instruction> _locals = new Dictionary<AstOperand, Instruction>();
private readonly Dictionary<int, Instruction[]> _localForArgs = new Dictionary<int, Instruction[]>();
private readonly Dictionary<int, Instruction> _funcArgs = new Dictionary<int, Instruction>();
private readonly Dictionary<int, (StructuredFunction, Instruction)> _functions = new Dictionary<int, (StructuredFunction, Instruction)>();
private readonly Dictionary<AstOperand, Instruction> _locals = new();
private readonly Dictionary<int, Instruction[]> _localForArgs = new();
private readonly Dictionary<int, Instruction> _funcArgs = new();
private readonly Dictionary<int, (StructuredFunction, Instruction)> _functions = new();
private class BlockState
{
private int _entryCount;
private readonly List<Instruction> _labels = new List<Instruction>();
private readonly List<Instruction> _labels = new();
public Instruction GetNextLabel(CodeGenContext context)
{
@@ -67,7 +68,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
}
}
private readonly Dictionary<AstBlock, BlockState> _labels = new Dictionary<AstBlock, BlockState>();
private readonly Dictionary<AstBlock, BlockState> _labels = new();
public Dictionary<AstBlock, (Instruction, Instruction)> LoopTargets { get; set; }
@@ -98,7 +99,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
InputTopology.LinesAdjacency => 2,
InputTopology.Triangles => 3,
InputTopology.TrianglesAdjacency => 3,
_ => throw new InvalidOperationException($"Invalid input topology \"{inPrimitive}\".")
_ => throw new InvalidOperationException($"Invalid input topology \"{inPrimitive}\"."),
};
}
@@ -222,7 +223,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
IrOperandType.Constant => GetConstant(type, operand),
IrOperandType.LocalVariable => GetLocal(type, operand),
IrOperandType.Undefined => GetUndefined(type),
_ => throw new ArgumentException($"Invalid operand type \"{operand.Type}\".")
_ => throw new ArgumentException($"Invalid operand type \"{operand.Type}\"."),
};
}
@@ -259,7 +260,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
AggregateType.Bool => ConstantFalse(TypeBool()),
AggregateType.FP32 => Constant(TypeFP32(), 0f),
AggregateType.FP64 => Constant(TypeFP64(), 0d),
_ => Constant(GetType(type), 0)
_ => Constant(GetType(type), 0),
};
}
@@ -272,7 +273,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
AggregateType.FP64 => Constant(TypeFP64(), (double)BitConverter.Int32BitsToSingle(operand.Value)),
AggregateType.S32 => Constant(TypeS32(), operand.Value),
AggregateType.U32 => Constant(TypeU32(), (uint)operand.Value),
_ => throw new ArgumentException($"Invalid type \"{type}\".")
_ => throw new ArgumentException($"Invalid type \"{type}\"."),
};
}
@@ -328,7 +329,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
AggregateType.Vector2 => 2,
AggregateType.Vector3 => 3,
AggregateType.Vector4 => 4,
_ => 1
_ => 1,
};
return TypeVector(GetType(type & ~AggregateType.ElementCountMask), vectorLength);
@@ -342,7 +343,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
AggregateType.FP64 => TypeFP64(),
AggregateType.S32 => TypeS32(),
AggregateType.U32 => TypeU32(),
_ => throw new ArgumentException($"Invalid attribute type \"{type}\".")
_ => throw new ArgumentException($"Invalid attribute type \"{type}\"."),
};
}
@@ -359,7 +360,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
}
else if (srcType == AggregateType.Bool)
{
var intTrue = Constant(TypeS32(), IrConsts.True);
var intTrue = Constant(TypeS32(), IrConsts.True);
var intFalse = Constant(TypeS32(), IrConsts.False);
return BitcastIfNeeded(dstType, AggregateType.S32, Select(TypeS32(), value, intTrue, intFalse));

View File

@@ -1,5 +1,4 @@
using Ryujinx.Common;
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
using Ryujinx.Graphics.Shader.StructuredIr;
using Ryujinx.Graphics.Shader.Translation;
using Spv.Generator;
@@ -14,7 +13,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
{
static class Declarations
{
private static readonly string[] StagePrefixes = new string[] { "cp", "vp", "tcp", "tep", "gp", "fp" };
private static readonly string[] _stagePrefixes = { "cp", "vp", "tcp", "tep", "gp", "fp" };
public static void DeclareParameters(CodeGenContext context, StructuredFunction function)
{
@@ -107,7 +106,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
private static void DeclareBuffers(CodeGenContext context, IEnumerable<BufferDefinition> buffers, bool isBuffer)
{
HashSet<SpvInstruction> decoratedTypes = new HashSet<SpvInstruction>();
HashSet<SpvInstruction> decoratedTypes = new();
foreach (BufferDefinition buffer in buffers)
{
@@ -199,7 +198,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
SamplerType.Texture3D => Dim.Dim3D,
SamplerType.TextureCube => Dim.Cube,
SamplerType.TextureBuffer => Dim.Buffer,
_ => throw new InvalidOperationException($"Invalid sampler type \"{descriptor.Type & SamplerType.Mask}\".")
_ => throw new InvalidOperationException($"Invalid sampler type \"{descriptor.Type & SamplerType.Mask}\"."),
};
var imageType = context.TypeImage(
@@ -282,7 +281,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
SamplerType.Texture3D => Dim.Dim3D,
SamplerType.TextureCube => Dim.Cube,
SamplerType.TextureBuffer => Dim.Buffer,
_ => throw new ArgumentException($"Invalid sampler type \"{type & SamplerType.Mask}\".")
_ => throw new ArgumentException($"Invalid sampler type \"{type & SamplerType.Mask}\"."),
};
}
@@ -330,7 +329,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
TextureFormat.R10G10B10A2Unorm => ImageFormat.Rgb10A2,
TextureFormat.R10G10B10A2Uint => ImageFormat.Rgb10a2ui,
TextureFormat.R11G11B10Float => ImageFormat.R11fG11fB10f,
_ => throw new ArgumentException($"Invalid texture format \"{format}\".")
_ => throw new ArgumentException($"Invalid texture format \"{format}\"."),
};
}
@@ -352,7 +351,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
(_, AggregateType varType) = IoMap.GetSpirvBuiltIn(ioVariable);
AggregateType elemType = varType & AggregateType.ElementTypeMask;
if (elemType == AggregateType.S32 || elemType == AggregateType.U32)
if (elemType is AggregateType.S32 or AggregateType.U32)
{
iq = PixelImap.Constant;
}
@@ -410,7 +409,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
2 => AggregateType.Vector2,
3 => AggregateType.Vector3,
4 => AggregateType.Vector4,
_ => AggregateType.Invalid
_ => AggregateType.Invalid,
};
}
@@ -420,7 +419,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
if (!isPerPatch && IoMap.IsPerVertex(ioVariable, context.Config.Stage, isOutput))
{
int arraySize = context.Config.Stage == ShaderStage.Geometry ? context.InputVertices : 32;
spvType = context.TypeArray(spvType, context.Constant(context.TypeU32(), (LiteralInteger)arraySize));
spvType = context.TypeArray(spvType, context.Constant(context.TypeU32(), arraySize));
if (context.Config.GpPassthrough && context.Config.GpuAccessor.QueryHostSupportsGeometryShaderPassthrough())
{
@@ -542,7 +541,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
private static string GetStagePrefix(ShaderStage stage)
{
return StagePrefixes[(int)stage];
return _stagePrefixes[(int)stage];
}
}
}

View File

@@ -15,7 +15,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
ShaderStage.TessellationEvaluation => ExecutionModel.TessellationEvaluation,
ShaderStage.Geometry => ExecutionModel.Geometry,
ShaderStage.Fragment => ExecutionModel.Fragment,
_ => throw new ArgumentException($"Invalid shader stage \"{stage}\".")
_ => throw new ArgumentException($"Invalid shader stage \"{stage}\"."),
};
}
}

View File

@@ -14,19 +14,20 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
static class Instructions
{
private const MemorySemanticsMask DefaultMemorySemantics =
private const MemorySemanticsMask DefaultMemorySemantics =
MemorySemanticsMask.ImageMemory |
MemorySemanticsMask.AtomicCounterMemory |
MemorySemanticsMask.WorkgroupMemory |
MemorySemanticsMask.UniformMemory |
MemorySemanticsMask.AcquireRelease;
private static readonly Func<CodeGenContext, AstOperation, OperationResult>[] InstTable;
private static readonly Func<CodeGenContext, AstOperation, OperationResult>[] _instTable;
static Instructions()
{
InstTable = new Func<CodeGenContext, AstOperation, OperationResult>[(int)Instruction.Count];
_instTable = new Func<CodeGenContext, AstOperation, OperationResult>[(int)Instruction.Count];
#pragma warning disable IDE0055 // Disable formatting
Add(Instruction.Absolute, GenerateAbsolute);
Add(Instruction.Add, GenerateAdd);
Add(Instruction.AtomicAdd, GenerateAtomicAdd);
@@ -141,16 +142,17 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
Add(Instruction.VoteAll, GenerateVoteAll);
Add(Instruction.VoteAllEqual, GenerateVoteAllEqual);
Add(Instruction.VoteAny, GenerateVoteAny);
#pragma warning restore IDE0055
}
private static void Add(Instruction inst, Func<CodeGenContext, AstOperation, OperationResult> handler)
{
InstTable[(int)(inst & Instruction.Mask)] = handler;
_instTable[(int)(inst & Instruction.Mask)] = handler;
}
public static OperationResult Generate(CodeGenContext context, AstOperation operation)
{
var handler = InstTable[(int)(operation.Inst & Instruction.Mask)];
var handler = _instTable[(int)(operation.Inst & Instruction.Mask)];
if (handler != null)
{
return handler(context, operation);
@@ -305,7 +307,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
Debug.Assert(funcId.Type == OperandType.Constant);
(var function, var spvFunc) = context.GetFunction(funcId.Value);
var (function, spvFunc) = context.GetFunction(funcId.Value);
var args = new SpvInstruction[operation.SourcesCount - 1];
var spvLocals = context.GetLocalForArgsPointers(funcId.Value);
@@ -615,7 +617,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
});
}
bool isArray = (texOp.Type & SamplerType.Array) != 0;
bool isArray = (texOp.Type & SamplerType.Array) != 0;
bool isIndexed = (texOp.Type & SamplerType.Indexed) != 0;
int srcIndex = isBindless ? 1 : 0;
@@ -625,11 +627,9 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
return context.Get(type, texOp.GetSource(srcIndex++));
}
SpvInstruction index = null;
if (isIndexed)
{
index = Src(AggregateType.S32);
Src(AggregateType.S32);
}
int coordsCount = texOp.Type.GetDimensions();
@@ -657,9 +657,9 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
SpvInstruction value = Src(componentType);
(var imageType, var imageVariable) = context.Images[new TextureMeta(texOp.CbufSlot, texOp.Handle, texOp.Format)];
(SpvInstruction imageType, SpvInstruction imageVariable) = context.Images[new TextureMeta(texOp.CbufSlot, texOp.Handle, texOp.Format)];
var image = context.Load(imageType, imageVariable);
context.Load(imageType, imageVariable);
SpvInstruction resultType = context.GetType(componentType);
SpvInstruction imagePointerType = context.TypePointer(StorageClass.Image, resultType);
@@ -670,21 +670,21 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
var result = (texOp.Flags & TextureFlags.AtomicMask) switch
{
TextureFlags.Add => context.AtomicIAdd(resultType, pointer, one, zero, value),
TextureFlags.Minimum => componentType == AggregateType.S32
TextureFlags.Add => context.AtomicIAdd(resultType, pointer, one, zero, value),
TextureFlags.Minimum => componentType == AggregateType.S32
? context.AtomicSMin(resultType, pointer, one, zero, value)
: context.AtomicUMin(resultType, pointer, one, zero, value),
TextureFlags.Maximum => componentType == AggregateType.S32
TextureFlags.Maximum => componentType == AggregateType.S32
? context.AtomicSMax(resultType, pointer, one, zero, value)
: context.AtomicUMax(resultType, pointer, one, zero, value),
TextureFlags.Increment => context.AtomicIIncrement(resultType, pointer, one, zero),
TextureFlags.Decrement => context.AtomicIDecrement(resultType, pointer, one, zero),
TextureFlags.Increment => context.AtomicIIncrement(resultType, pointer, one, zero),
TextureFlags.Decrement => context.AtomicIDecrement(resultType, pointer, one, zero),
TextureFlags.BitwiseAnd => context.AtomicAnd(resultType, pointer, one, zero, value),
TextureFlags.BitwiseOr => context.AtomicOr(resultType, pointer, one, zero, value),
TextureFlags.BitwiseOr => context.AtomicOr(resultType, pointer, one, zero, value),
TextureFlags.BitwiseXor => context.AtomicXor(resultType, pointer, one, zero, value),
TextureFlags.Swap => context.AtomicExchange(resultType, pointer, one, zero, value),
TextureFlags.CAS => context.AtomicCompareExchange(resultType, pointer, one, zero, zero, Src(componentType), value),
_ => context.AtomicIAdd(resultType, pointer, one, zero, value),
TextureFlags.Swap => context.AtomicExchange(resultType, pointer, one, zero, value),
TextureFlags.CAS => context.AtomicCompareExchange(resultType, pointer, one, zero, zero, Src(componentType), value),
_ => context.AtomicIAdd(resultType, pointer, one, zero, value),
};
return new OperationResult(componentType, result);
@@ -704,7 +704,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
return GetZeroOperationResult(context, texOp, componentType, isVector: true);
}
bool isArray = (texOp.Type & SamplerType.Array) != 0;
bool isArray = (texOp.Type & SamplerType.Array) != 0;
bool isIndexed = (texOp.Type & SamplerType.Indexed) != 0;
int srcIndex = isBindless ? 1 : 0;
@@ -714,11 +714,9 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
return context.Get(type, texOp.GetSource(srcIndex++));
}
SpvInstruction index = null;
if (isIndexed)
{
index = Src(AggregateType.S32);
Src(AggregateType.S32);
}
int coordsCount = texOp.Type.GetDimensions();
@@ -744,7 +742,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
pCoords = Src(AggregateType.S32);
}
(var imageType, var imageVariable) = context.Images[new TextureMeta(texOp.CbufSlot, texOp.Handle, texOp.Format)];
var (imageType, imageVariable) = context.Images[new TextureMeta(texOp.CbufSlot, texOp.Handle, texOp.Format)];
var image = context.Load(imageType, imageVariable);
var imageComponentType = context.GetType(componentType);
@@ -768,7 +766,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
return OperationResult.Invalid;
}
bool isArray = (texOp.Type & SamplerType.Array) != 0;
bool isArray = (texOp.Type & SamplerType.Array) != 0;
bool isIndexed = (texOp.Type & SamplerType.Indexed) != 0;
int srcIndex = isBindless ? 1 : 0;
@@ -778,11 +776,9 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
return context.Get(type, texOp.GetSource(srcIndex++));
}
SpvInstruction index = null;
if (isIndexed)
{
index = Src(AggregateType.S32);
Src(AggregateType.S32);
}
int coordsCount = texOp.Type.GetDimensions();
@@ -833,7 +829,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
var texel = context.CompositeConstruct(context.TypeVector(context.GetType(componentType), ComponentsCount), cElems);
(var imageType, var imageVariable) = context.Images[new TextureMeta(texOp.CbufSlot, texOp.Handle, texOp.Format)];
var (imageType, imageVariable) = context.Images[new TextureMeta(texOp.CbufSlot, texOp.Handle, texOp.Format)];
var image = context.Load(imageType, imageVariable);
@@ -886,11 +882,9 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
return context.Get(type, texOp.GetSource(srcIndex++));
}
SpvInstruction index = null;
if (isIndexed)
{
index = Src(AggregateType.S32);
Src(AggregateType.S32);
}
int pCount = texOp.Type.GetDimensions();
@@ -916,7 +910,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
var meta = new TextureMeta(texOp.CbufSlot, texOp.Handle, texOp.Format);
(_, var sampledImageType, var sampledImageVariable) = context.Samplers[meta];
var (_, sampledImageType, sampledImageVariable) = context.Samplers[meta];
var image = context.Load(sampledImageType, sampledImageVariable);
@@ -973,7 +967,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
loopBlock = loopBlock.Parent;
}
(var loopTarget, var continueTarget) = context.LoopTargets[loopBlock];
(_, SpvInstruction continueTarget) = context.LoopTargets[loopBlock];
context.Branch(continueTarget);
@@ -1278,19 +1272,19 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
{
AstTextureOperation texOp = (AstTextureOperation)operation;
bool isBindless = (texOp.Flags & TextureFlags.Bindless) != 0;
bool isGather = (texOp.Flags & TextureFlags.Gather) != 0;
bool isBindless = (texOp.Flags & TextureFlags.Bindless) != 0;
bool isGather = (texOp.Flags & TextureFlags.Gather) != 0;
bool hasDerivatives = (texOp.Flags & TextureFlags.Derivatives) != 0;
bool intCoords = (texOp.Flags & TextureFlags.IntCoords) != 0;
bool hasLodBias = (texOp.Flags & TextureFlags.LodBias) != 0;
bool hasLodLevel = (texOp.Flags & TextureFlags.LodLevel) != 0;
bool hasOffset = (texOp.Flags & TextureFlags.Offset) != 0;
bool hasOffsets = (texOp.Flags & TextureFlags.Offsets) != 0;
bool intCoords = (texOp.Flags & TextureFlags.IntCoords) != 0;
bool hasLodBias = (texOp.Flags & TextureFlags.LodBias) != 0;
bool hasLodLevel = (texOp.Flags & TextureFlags.LodLevel) != 0;
bool hasOffset = (texOp.Flags & TextureFlags.Offset) != 0;
bool hasOffsets = (texOp.Flags & TextureFlags.Offsets) != 0;
bool isArray = (texOp.Type & SamplerType.Array) != 0;
bool isIndexed = (texOp.Type & SamplerType.Indexed) != 0;
bool isArray = (texOp.Type & SamplerType.Array) != 0;
bool isIndexed = (texOp.Type & SamplerType.Indexed) != 0;
bool isMultisample = (texOp.Type & SamplerType.Multisample) != 0;
bool isShadow = (texOp.Type & SamplerType.Shadow) != 0;
bool isShadow = (texOp.Type & SamplerType.Shadow) != 0;
bool colorIsVector = isGather || !isShadow;
@@ -1307,11 +1301,9 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
return context.Get(type, texOp.GetSource(srcIndex++));
}
SpvInstruction index = null;
if (isIndexed)
{
index = Src(AggregateType.S32);
Src(AggregateType.S32);
}
int coordsCount = texOp.Type.GetDimensions();
@@ -1395,7 +1387,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
derivatives = new[]
{
AssembleDerivativesVector(coordsCount), // dPdx
AssembleDerivativesVector(coordsCount) // dPdy
AssembleDerivativesVector(coordsCount), // dPdy
};
}
@@ -1445,7 +1437,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
AssembleOffsetVector(coordsCount),
AssembleOffsetVector(coordsCount),
AssembleOffsetVector(coordsCount),
AssembleOffsetVector(coordsCount)
AssembleOffsetVector(coordsCount),
};
}
@@ -1474,7 +1466,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
// not needed for shadow samplers.
if (isGather && !isShadow)
{
compIdx = Src(AggregateType.S32);
compIdx = Src(AggregateType.S32);
}
var operandsList = new List<SpvInstruction>();
@@ -1521,7 +1513,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
var meta = new TextureMeta(texOp.CbufSlot, texOp.Handle, texOp.Format);
(var imageType, var sampledImageType, var sampledImageVariable) = context.Samplers[meta];
var (imageType, sampledImageType, sampledImageVariable) = context.Samplers[meta];
var image = context.Load(sampledImageType, sampledImageVariable);
@@ -1595,16 +1587,14 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
bool isIndexed = (texOp.Type & SamplerType.Indexed) != 0;
SpvInstruction index = null;
if (isIndexed)
{
index = context.GetS32(texOp.GetSource(0));
context.GetS32(texOp.GetSource(0));
}
var meta = new TextureMeta(texOp.CbufSlot, texOp.Handle, texOp.Format);
(var imageType, var sampledImageType, var sampledImageVariable) = context.Samplers[meta];
(SpvInstruction imageType, SpvInstruction sampledImageType, SpvInstruction sampledImageVariable) = context.Samplers[meta];
var image = context.Load(sampledImageType, sampledImageVariable);
image = context.Image(imageType, image);
@@ -1809,12 +1799,12 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
{
case StorageKind.ConstantBuffer:
case StorageKind.StorageBuffer:
if (!(operation.GetSource(srcIndex++) is AstOperand bindingIndex) || bindingIndex.Type != OperandType.Constant)
if (operation.GetSource(srcIndex++) is not AstOperand bindingIndex || bindingIndex.Type != OperandType.Constant)
{
throw new InvalidOperationException($"First input of {operation.Inst} with {storageKind} storage must be a constant operand.");
}
if (!(operation.GetSource(srcIndex) is AstOperand fieldIndex) || fieldIndex.Type != OperandType.Constant)
if (operation.GetSource(srcIndex) is not AstOperand fieldIndex || fieldIndex.Type != OperandType.Constant)
{
throw new InvalidOperationException($"Second input of {operation.Inst} with {storageKind} storage must be a constant operand.");
}
@@ -1833,7 +1823,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
case StorageKind.LocalMemory:
case StorageKind.SharedMemory:
if (!(operation.GetSource(srcIndex++) is AstOperand bindingId) || bindingId.Type != OperandType.Constant)
if (operation.GetSource(srcIndex++) is not AstOperand { Type: OperandType.Constant } bindingId)
{
throw new InvalidOperationException($"First input of {operation.Inst} with {storageKind} storage must be a constant operand.");
}
@@ -1856,7 +1846,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
case StorageKind.InputPerPatch:
case StorageKind.Output:
case StorageKind.OutputPerPatch:
if (!(operation.GetSource(srcIndex++) is AstOperand varId) || varId.Type != OperandType.Constant)
if (operation.GetSource(srcIndex++) is not AstOperand varId || varId.Type != OperandType.Constant)
{
throw new InvalidOperationException($"First input of {operation.Inst} with {storageKind} storage must be a constant operand.");
}
@@ -1869,7 +1859,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
if (context.Config.HasPerLocationInputOrOutput(ioVariable, isOutput))
{
if (!(operation.GetSource(srcIndex++) is AstOperand vecIndex) || vecIndex.Type != OperandType.Constant)
if (operation.GetSource(srcIndex++) is not AstOperand vecIndex || vecIndex.Type != OperandType.Constant)
{
throw new InvalidOperationException($"Second input of {operation.Inst} with {storageKind} storage must be a constant operand.");
}
@@ -1964,7 +1954,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
private static SpvInstruction GetScalarInput(CodeGenContext context, IoVariable ioVariable)
{
(_, var varType) = IoMap.GetSpirvBuiltIn(ioVariable);
var (_, varType) = IoMap.GetSpirvBuiltIn(ioVariable);
varType &= AggregateType.ElementTypeMask;
var ioDefinition = new IoDefinition(StorageKind.Input, ioVariable);
@@ -2061,10 +2051,10 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
return new OperationResult(AggregateType.Bool, emitB(context.TypeBool(), context.Get(AggregateType.Bool, source)));
}
private static OperationResult GenerateUnaryFP32(
CodeGenContext context,
AstOperation operation,
Func<SpvInstruction, SpvInstruction, SpvInstruction> emit)
private static OperationResult GenerateUnaryFP32(
CodeGenContext context,
AstOperation operation,
Func<SpvInstruction, SpvInstruction, SpvInstruction> emit)
{
var source = operation.GetSource(0);
return new OperationResult(AggregateType.FP32, emit(context.TypeFP32(), context.GetFP32(source)));

View File

@@ -45,7 +45,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
IoVariable.VertexIndex => (BuiltIn.VertexIndex, AggregateType.S32),
IoVariable.ViewportIndex => (BuiltIn.ViewportIndex, AggregateType.S32),
IoVariable.ViewportMask => (BuiltIn.ViewportMaskNV, AggregateType.Array | AggregateType.S32),
_ => (default, AggregateType.Invalid)
_ => (default, AggregateType.Invalid),
};
}
@@ -58,7 +58,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
IoVariable.TessellationLevelOuter => 4,
IoVariable.ViewportMask => 1,
IoVariable.UserDefined => MaxAttributes,
_ => 1
_ => 1,
};
}
@@ -74,13 +74,11 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
case IoVariable.ClipDistance:
case IoVariable.PointCoord:
case IoVariable.ViewportMask:
return !isOutput &&
(stage == ShaderStage.TessellationControl ||
stage == ShaderStage.TessellationEvaluation ||
stage == ShaderStage.Geometry);
return !isOutput &&
stage is ShaderStage.TessellationControl or ShaderStage.TessellationEvaluation or ShaderStage.Geometry;
}
return false;
}
}
}
}

View File

@@ -5,7 +5,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
{
readonly struct OperationResult
{
public static OperationResult Invalid => new OperationResult(AggregateType.Invalid, null);
public static OperationResult Invalid => new(AggregateType.Invalid, null);
public AggregateType Type { get; }
public Instruction Value { get; }

View File

@@ -17,15 +17,15 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
{
// Resource pools for Spirv generation. Note: Increase count when more threads are being used.
private const int GeneratorPoolCount = 1;
private static ObjectPool<SpvInstructionPool> InstructionPool;
private static ObjectPool<SpvLiteralIntegerPool> IntegerPool;
private static object PoolLock;
private static readonly ObjectPool<SpvInstructionPool> _instructionPool;
private static readonly ObjectPool<SpvLiteralIntegerPool> _integerPool;
private static readonly object _poolLock;
static SpirvGenerator()
{
InstructionPool = new (() => new SpvInstructionPool(), GeneratorPoolCount);
IntegerPool = new (() => new SpvLiteralIntegerPool(), GeneratorPoolCount);
PoolLock = new object();
_instructionPool = new(() => new SpvInstructionPool(), GeneratorPoolCount);
_integerPool = new(() => new SpvLiteralIntegerPool(), GeneratorPoolCount);
_poolLock = new object();
}
private const HelperFunctionsMask NeedsInvocationIdMask =
@@ -40,13 +40,13 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
SpvInstructionPool instPool;
SpvLiteralIntegerPool integerPool;
lock (PoolLock)
lock (_poolLock)
{
instPool = InstructionPool.Allocate();
integerPool = IntegerPool.Allocate();
instPool = _instructionPool.Allocate();
integerPool = _integerPool.Allocate();
}
CodeGenContext context = new CodeGenContext(info, config, instPool, integerPool);
CodeGenContext context = new(info, config, instPool, integerPool);
context.AddCapability(Capability.GroupNonUniformBallot);
context.AddCapability(Capability.GroupNonUniformShuffle);
@@ -133,10 +133,10 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
byte[] result = context.Generate();
lock (PoolLock)
lock (_poolLock)
{
InstructionPool.Release(instPool);
IntegerPool.Release(integerPool);
_instructionPool.Release(instPool);
_integerPool.Release(integerPool);
}
return result;
@@ -144,7 +144,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
private static void Generate(CodeGenContext context, StructuredProgramInfo info, int funcIndex)
{
(var function, var spvFunc) = context.GetFunction(funcIndex);
var (function, spvFunc) = context.GetFunction(funcIndex);
context.CurrentFunction = function;
context.AddFunction(spvFunc);
@@ -160,7 +160,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
Generate(context, function.MainBlock);
// Functions must always end with a return.
if (!(function.MainBlock.Last is AstOperation operation) ||
if (function.MainBlock.Last is not AstOperation operation ||
(operation.Inst != Instruction.Return && operation.Inst != Instruction.Discard))
{
context.Return();
@@ -232,7 +232,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
InputTopology.LinesAdjacency => ExecutionMode.InputLinesAdjacency,
InputTopology.Triangles => ExecutionMode.Triangles,
InputTopology.TrianglesAdjacency => ExecutionMode.InputTrianglesAdjacency,
_ => throw new InvalidOperationException($"Invalid input topology \"{inputTopology}\".")
_ => throw new InvalidOperationException($"Invalid input topology \"{inputTopology}\"."),
});
context.AddExecutionMode(spvFunc, ExecutionMode.Invocations, (SpvLiteralInteger)context.Config.ThreadsPerInputPrimitive);
@@ -242,7 +242,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
OutputTopology.PointList => ExecutionMode.OutputPoints,
OutputTopology.LineStrip => ExecutionMode.OutputLineStrip,
OutputTopology.TriangleStrip => ExecutionMode.OutputTriangleStrip,
_ => throw new InvalidOperationException($"Invalid output topology \"{context.Config.OutputTopology}\".")
_ => throw new InvalidOperationException($"Invalid output topology \"{context.Config.OutputTopology}\"."),
});
int maxOutputVertices = context.Config.GpPassthrough ? context.InputVertices : context.Config.MaxOutputVertices;
@@ -294,7 +294,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
private static void Generate(CodeGenContext context, AstBlock block)
{
AstBlockVisitor visitor = new AstBlockVisitor(block);
AstBlockVisitor visitor = new(block);
var loopTargets = new Dictionary<AstBlock, (SpvInstruction, SpvInstruction)>();
@@ -346,7 +346,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
// if the condition is true.
AstBlock mergeBlock = e.Block.Parent;
(var loopTarget, var continueTarget) = loopTargets[e.Block];
var (loopTarget, continueTarget) = loopTargets[e.Block];
context.Branch(continueTarget);
context.AddLabel(continueTarget);

View File

@@ -1,4 +1,4 @@
namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
{
readonly record struct TextureMeta(int CbufSlot, int Handle, TextureFormat Format);
}
}

View File

@@ -17,4 +17,4 @@ namespace Ryujinx.Graphics.Shader
public const int TfeBufferBaseBinding = 1;
public const int TfeBuffersCount = 4;
}
}
}

View File

@@ -92,7 +92,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
pushOpInfo.Consumers.Add(rightBlock, local);
}
foreach ((ulong key, SyncTarget value) in SyncTargets)
foreach ((ulong key, SyncTarget value) in SyncTargets)
{
rightBlock.SyncTargets.Add(key, value);
}
@@ -148,7 +148,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
{
if (OpCodes.Count != 0)
{
return OpCodes[OpCodes.Count - 1];
return OpCodes[^1];
}
return default;
@@ -165,4 +165,4 @@ namespace Ryujinx.Graphics.Shader.Decoders
PushOpCodes.Add(new PushOpInfo(op));
}
}
}
}

View File

@@ -45,4 +45,4 @@ namespace Ryujinx.Graphics.Shader.Decoders
}
}
}
}
}

View File

@@ -54,4 +54,4 @@ namespace Ryujinx.Graphics.Shader.Decoders
return GetEnumerator();
}
}
}
}

View File

@@ -3,7 +3,6 @@ using System;
using System.Collections.Generic;
using System.Linq;
using System.Runtime.CompilerServices;
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
namespace Ryujinx.Graphics.Shader.Decoders
@@ -12,8 +11,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
{
public static DecodedProgram Decode(ShaderConfig config, ulong startAddress)
{
Queue<DecodedFunction> functionsQueue = new Queue<DecodedFunction>();
Dictionary<ulong, DecodedFunction> functionsVisited = new Dictionary<ulong, DecodedFunction>();
Queue<DecodedFunction> functionsQueue = new();
Dictionary<ulong, DecodedFunction> functionsVisited = new();
DecodedFunction EnqueueFunction(ulong address)
{
@@ -30,9 +29,9 @@ namespace Ryujinx.Graphics.Shader.Decoders
while (functionsQueue.TryDequeue(out DecodedFunction currentFunction))
{
List<Block> blocks = new List<Block>();
Queue<Block> workQueue = new Queue<Block>();
Dictionary<ulong, Block> visited = new Dictionary<ulong, Block>();
List<Block> blocks = new();
Queue<Block> workQueue = new();
Dictionary<ulong, Block> visited = new();
Block GetBlock(ulong blkAddress)
{
@@ -168,7 +167,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
{
index = 0;
int left = 0;
int left = 0;
int right = blocks.Count - 1;
while (left <= right)
@@ -273,12 +272,12 @@ namespace Ryujinx.Graphics.Shader.Decoders
int offset;
int count = 1;
bool isStore = false;
bool indexed = false;
bool indexed;
bool perPatch = false;
if (name == InstName.Ast)
{
InstAst opAst = new InstAst(opCode);
InstAst opAst = new(opCode);
count = (int)opAst.AlSize + 1;
offset = opAst.Imm11;
indexed = opAst.Phys;
@@ -287,7 +286,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
}
else if (name == InstName.Ald)
{
InstAld opAld = new InstAld(opCode);
InstAld opAld = new(opCode);
count = (int)opAld.AlSize + 1;
offset = opAld.Imm11;
indexed = opAld.Phys;
@@ -296,7 +295,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
}
else /* if (name == InstName.Ipa) */
{
InstIpa opIpa = new InstIpa(opCode);
InstIpa opIpa = new(opCode);
offset = opIpa.Imm10;
indexed = opIpa.Idx;
}
@@ -370,7 +369,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
private static bool IsUnconditional(ref InstOp op)
{
InstConditional condOp = new InstConditional(op.RawOpCode);
InstConditional condOp = new(op.RawOpCode);
if ((op.Name == InstName.Bra || op.Name == InstName.Exit) && condOp.Ccc != Ccc.T)
{
@@ -391,9 +390,9 @@ namespace Ryujinx.Graphics.Shader.Decoders
if (lastOp.Name == InstName.Brx && block.Successors.Count == (hasNext ? 1 : 0))
{
HashSet<ulong> visited = new HashSet<ulong>();
HashSet<ulong> visited = new();
InstBrx opBrx = new InstBrx(lastOp.RawOpCode);
InstBrx opBrx = new(lastOp.RawOpCode);
ulong baseOffset = lastOp.GetAbsoluteAddress();
// An indirect branch could go anywhere,
@@ -437,7 +436,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
// On a successful match, "BaseOffset" is the offset in bytes where the jump offsets are
// located on the constant buffer, and "UpperBound" is the total number of offsets for the BRX, minus 1.
HashSet<Block> visited = new HashSet<Block>();
HashSet<Block> visited = new();
var ldcLocation = FindFirstRegWrite(visited, new BlockLocation(block, block.OpCodes.Count - 1), brxReg);
if (ldcLocation.Block == null || ldcLocation.Block.OpCodes[ldcLocation.Index].Name != InstName.Ldc)
@@ -507,7 +506,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
private static BlockLocation FindFirstRegWrite(HashSet<Block> visited, BlockLocation location, int regIndex)
{
Queue<BlockLocation> toVisit = new Queue<BlockLocation>();
Queue<BlockLocation> toVisit = new();
toVisit.Enqueue(location);
visited.Add(location.Block);
@@ -554,10 +553,10 @@ namespace Ryujinx.Graphics.Shader.Decoders
{
Brk,
Cont,
Sync
Sync,
}
private struct PathBlockState
private readonly struct PathBlockState
{
public Block Block { get; }
@@ -565,37 +564,37 @@ namespace Ryujinx.Graphics.Shader.Decoders
{
None,
PopPushOp,
PushBranchOp
PushBranchOp,
}
private RestoreType _restoreType;
private readonly RestoreType _restoreType;
private ulong _restoreValue;
private MergeType _restoreMergeType;
private readonly ulong _restoreValue;
private readonly MergeType _restoreMergeType;
public bool ReturningFromVisit => _restoreType != RestoreType.None;
public PathBlockState(Block block)
{
Block = block;
_restoreType = RestoreType.None;
_restoreValue = 0;
Block = block;
_restoreType = RestoreType.None;
_restoreValue = 0;
_restoreMergeType = default;
}
public PathBlockState(int oldStackSize)
{
Block = null;
_restoreType = RestoreType.PopPushOp;
_restoreValue = (ulong)oldStackSize;
Block = null;
_restoreType = RestoreType.PopPushOp;
_restoreValue = (ulong)oldStackSize;
_restoreMergeType = default;
}
public PathBlockState(ulong syncAddress, MergeType mergeType)
{
Block = null;
_restoreType = RestoreType.PushBranchOp;
_restoreValue = syncAddress;
Block = null;
_restoreType = RestoreType.PushBranchOp;
_restoreValue = syncAddress;
_restoreMergeType = mergeType;
}
@@ -622,9 +621,9 @@ namespace Ryujinx.Graphics.Shader.Decoders
Block target = blocks[pushOp.GetAbsoluteAddress()];
Stack<PathBlockState> workQueue = new Stack<PathBlockState>();
HashSet<Block> visited = new HashSet<Block>();
Stack<(ulong, MergeType)> branchStack = new Stack<(ulong, MergeType)>();
Stack<PathBlockState> workQueue = new();
HashSet<Block> visited = new();
Stack<(ulong, MergeType)> branchStack = new();
void Push(PathBlockState pbs)
{
@@ -759,7 +758,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
{
InstName.Pbk => MergeType.Brk,
InstName.Pcnt => MergeType.Cont,
_ => MergeType.Sync
_ => MergeType.Sync,
};
}
@@ -769,8 +768,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
{
InstName.Brk => MergeType.Brk,
InstName.Cont => MergeType.Cont,
_ => MergeType.Sync
_ => MergeType.Sync,
};
}
}
}
}

File diff suppressed because it is too large Load Diff

View File

@@ -185,4 +185,4 @@ namespace Ryujinx.Graphics.Shader.Decoders
Vshr,
Xmad,
}
}
}

View File

@@ -24,4 +24,4 @@ namespace Ryujinx.Graphics.Shader.Decoders
return (ulong)((long)Address + (((int)(RawOpCode >> 20) << 8) >> 8) + 8);
}
}
}
}

View File

@@ -26,6 +26,6 @@ namespace Ryujinx.Graphics.Shader.Decoders
Tex = 1 << 12,
TexB = 1 << 13,
Bra = 1 << 14,
NoPred = 1 << 15
NoPred = 1 << 15,
}
}
}

View File

@@ -24,13 +24,14 @@ namespace Ryujinx.Graphics.Shader.Decoders
}
}
private static TableEntry[] _opCodes;
private static readonly TableEntry[] _opCodes;
static InstTable()
{
_opCodes = new TableEntry[1 << EncodingBits];
#region Instructions
#pragma warning disable IDE0055 // Disable formatting
Add("1110111110100xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Al2p, InstEmit.Al2p, InstProps.Rd | InstProps.Ra);
Add("1110111111011xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Ald, InstEmit.Ald, InstProps.Rd | InstProps.Ra);
Add("1110111111110xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Ast, InstEmit.Ast, InstProps.Ra | InstProps.Rb2 | InstProps.Rc);
@@ -325,6 +326,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
Add("0011011x00xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Xmad, InstEmit.XmadI, InstProps.Rd | InstProps.Ra | InstProps.Ib | InstProps.Rc);
Add("0100111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Xmad, InstEmit.XmadC, InstProps.Rd | InstProps.Ra | InstProps.Rc);
Add("010100010xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Xmad, InstEmit.XmadRc, InstProps.Rd | InstProps.Ra | InstProps.Rc);
#pragma warning restore IDE0055
#endregion
}
@@ -357,7 +359,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
xMask = ~xMask;
TableEntry entry = new TableEntry(name, emitter, props, xBits);
TableEntry entry = new(name, emitter, props, xBits);
for (int index = 0; index < (1 << xBits); index++)
{
@@ -387,4 +389,4 @@ namespace Ryujinx.Graphics.Shader.Decoders
return new InstOp(address, opCode, InstName.Invalid, null, InstProps.None);
}
}
}
}

View File

@@ -8,13 +8,13 @@ namespace Ryujinx.Graphics.Shader.Decoders
public RegisterType Type { get; }
public bool IsRZ => Type == RegisterType.Gpr && Index == RegisterConsts.RegisterZeroIndex;
public bool IsRZ => Type == RegisterType.Gpr && Index == RegisterConsts.RegisterZeroIndex;
public bool IsPT => Type == RegisterType.Predicate && Index == RegisterConsts.PredicateTrueIndex;
public Register(int index, RegisterType type)
{
Index = index;
Type = type;
Type = type;
}
public override int GetHashCode()
@@ -30,7 +30,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
public bool Equals(Register other)
{
return other.Index == Index &&
other.Type == Type;
other.Type == Type;
}
}
}
}

View File

@@ -2,12 +2,12 @@ namespace Ryujinx.Graphics.Shader.Decoders
{
static class RegisterConsts
{
public const int GprsCount = 255;
public const int GprsCount = 255;
public const int PredsCount = 7;
public const int FlagsCount = 4;
public const int TotalCount = GprsCount + PredsCount + FlagsCount;
public const int RegisterZeroIndex = GprsCount;
public const int RegisterZeroIndex = GprsCount;
public const int PredicateTrueIndex = PredsCount;
}
}
}

View File

@@ -6,4 +6,4 @@ namespace Ryujinx.Graphics.Shader.Decoders
Gpr,
Predicate,
}
}
}

View File

@@ -6,7 +6,7 @@ namespace Ryujinx.Graphics.Shader
Lines,
LinesAdjacency,
Triangles,
TrianglesAdjacency
TrianglesAdjacency,
}
static class InputTopologyExtensions
@@ -20,7 +20,7 @@ namespace Ryujinx.Graphics.Shader
InputTopology.LinesAdjacency => "lines_adjacency",
InputTopology.Triangles => "triangles",
InputTopology.TrianglesAdjacency => "triangles_adjacency",
_ => "points"
_ => "points",
};
}
@@ -33,8 +33,8 @@ namespace Ryujinx.Graphics.Shader
InputTopology.LinesAdjacency => 2,
InputTopology.Triangles or
InputTopology.TrianglesAdjacency => 3,
_ => 1
_ => 1,
};
}
}
}
}

View File

@@ -1,7 +1,6 @@
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
using Ryujinx.Graphics.Shader.Translation;
using System.Collections.Generic;
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
namespace Ryujinx.Graphics.Shader.Instructions
@@ -21,10 +20,10 @@ namespace Ryujinx.Graphics.Shader.Instructions
Tessellation = TessellationControl | TessellationEvaluation,
VertexTessellationGeometry = Vertex | Tessellation | Geometry,
TessellationGeometryFragment = Tessellation | Geometry | Fragment,
AllGraphics = Vertex | Tessellation | Geometry | Fragment
AllGraphics = Vertex | Tessellation | Geometry | Fragment,
}
private struct AttributeEntry
private readonly struct AttributeEntry
{
public int BaseOffset { get; }
public AggregateType Type { get; }
@@ -344,8 +343,8 @@ namespace Ryujinx.Graphics.Shader.Instructions
AggregateType.Vector2 => 2,
AggregateType.Vector3 => 3,
AggregateType.Vector4 => 4,
_ => 1
_ => 1,
};
}
}
}
}

View File

@@ -7,352 +7,352 @@ namespace Ryujinx.Graphics.Shader.Instructions
{
public static void AtomCas(EmitterContext context)
{
InstAtomCas op = context.GetOp<InstAtomCas>();
context.GetOp<InstAtomCas>();
context.Config.GpuAccessor.Log("Shader instruction AtomCas is not implemented.");
}
public static void AtomsCas(EmitterContext context)
{
InstAtomsCas op = context.GetOp<InstAtomsCas>();
context.GetOp<InstAtomsCas>();
context.Config.GpuAccessor.Log("Shader instruction AtomsCas is not implemented.");
}
public static void B2r(EmitterContext context)
{
InstB2r op = context.GetOp<InstB2r>();
context.GetOp<InstB2r>();
context.Config.GpuAccessor.Log("Shader instruction B2r is not implemented.");
}
public static void Bpt(EmitterContext context)
{
InstBpt op = context.GetOp<InstBpt>();
context.GetOp<InstBpt>();
context.Config.GpuAccessor.Log("Shader instruction Bpt is not implemented.");
}
public static void Cctl(EmitterContext context)
{
InstCctl op = context.GetOp<InstCctl>();
context.GetOp<InstCctl>();
context.Config.GpuAccessor.Log("Shader instruction Cctl is not implemented.");
}
public static void Cctll(EmitterContext context)
{
InstCctll op = context.GetOp<InstCctll>();
context.GetOp<InstCctll>();
context.Config.GpuAccessor.Log("Shader instruction Cctll is not implemented.");
}
public static void Cctlt(EmitterContext context)
{
InstCctlt op = context.GetOp<InstCctlt>();
context.GetOp<InstCctlt>();
context.Config.GpuAccessor.Log("Shader instruction Cctlt is not implemented.");
}
public static void Cs2r(EmitterContext context)
{
InstCs2r op = context.GetOp<InstCs2r>();
context.GetOp<InstCs2r>();
context.Config.GpuAccessor.Log("Shader instruction Cs2r is not implemented.");
}
public static void FchkR(EmitterContext context)
{
InstFchkR op = context.GetOp<InstFchkR>();
context.GetOp<InstFchkR>();
context.Config.GpuAccessor.Log("Shader instruction FchkR is not implemented.");
}
public static void FchkI(EmitterContext context)
{
InstFchkI op = context.GetOp<InstFchkI>();
context.GetOp<InstFchkI>();
context.Config.GpuAccessor.Log("Shader instruction FchkI is not implemented.");
}
public static void FchkC(EmitterContext context)
{
InstFchkC op = context.GetOp<InstFchkC>();
context.GetOp<InstFchkC>();
context.Config.GpuAccessor.Log("Shader instruction FchkC is not implemented.");
}
public static void Getcrsptr(EmitterContext context)
{
InstGetcrsptr op = context.GetOp<InstGetcrsptr>();
context.GetOp<InstGetcrsptr>();
context.Config.GpuAccessor.Log("Shader instruction Getcrsptr is not implemented.");
}
public static void Getlmembase(EmitterContext context)
{
InstGetlmembase op = context.GetOp<InstGetlmembase>();
context.GetOp<InstGetlmembase>();
context.Config.GpuAccessor.Log("Shader instruction Getlmembase is not implemented.");
}
public static void Ide(EmitterContext context)
{
InstIde op = context.GetOp<InstIde>();
context.GetOp<InstIde>();
context.Config.GpuAccessor.Log("Shader instruction Ide is not implemented.");
}
public static void IdpR(EmitterContext context)
{
InstIdpR op = context.GetOp<InstIdpR>();
context.GetOp<InstIdpR>();
context.Config.GpuAccessor.Log("Shader instruction IdpR is not implemented.");
}
public static void IdpC(EmitterContext context)
{
InstIdpC op = context.GetOp<InstIdpC>();
context.GetOp<InstIdpC>();
context.Config.GpuAccessor.Log("Shader instruction IdpC is not implemented.");
}
public static void ImadspR(EmitterContext context)
{
InstImadspR op = context.GetOp<InstImadspR>();
context.GetOp<InstImadspR>();
context.Config.GpuAccessor.Log("Shader instruction ImadspR is not implemented.");
}
public static void ImadspI(EmitterContext context)
{
InstImadspI op = context.GetOp<InstImadspI>();
context.GetOp<InstImadspI>();
context.Config.GpuAccessor.Log("Shader instruction ImadspI is not implemented.");
}
public static void ImadspC(EmitterContext context)
{
InstImadspC op = context.GetOp<InstImadspC>();
context.GetOp<InstImadspC>();
context.Config.GpuAccessor.Log("Shader instruction ImadspC is not implemented.");
}
public static void ImadspRc(EmitterContext context)
{
InstImadspRc op = context.GetOp<InstImadspRc>();
context.GetOp<InstImadspRc>();
context.Config.GpuAccessor.Log("Shader instruction ImadspRc is not implemented.");
}
public static void Jcal(EmitterContext context)
{
InstJcal op = context.GetOp<InstJcal>();
context.GetOp<InstJcal>();
context.Config.GpuAccessor.Log("Shader instruction Jcal is not implemented.");
}
public static void Jmp(EmitterContext context)
{
InstJmp op = context.GetOp<InstJmp>();
context.GetOp<InstJmp>();
context.Config.GpuAccessor.Log("Shader instruction Jmp is not implemented.");
}
public static void Jmx(EmitterContext context)
{
InstJmx op = context.GetOp<InstJmx>();
context.GetOp<InstJmx>();
context.Config.GpuAccessor.Log("Shader instruction Jmx is not implemented.");
}
public static void Ld(EmitterContext context)
{
InstLd op = context.GetOp<InstLd>();
context.GetOp<InstLd>();
context.Config.GpuAccessor.Log("Shader instruction Ld is not implemented.");
}
public static void Lepc(EmitterContext context)
{
InstLepc op = context.GetOp<InstLepc>();
context.GetOp<InstLepc>();
context.Config.GpuAccessor.Log("Shader instruction Lepc is not implemented.");
}
public static void Longjmp(EmitterContext context)
{
InstLongjmp op = context.GetOp<InstLongjmp>();
context.GetOp<InstLongjmp>();
context.Config.GpuAccessor.Log("Shader instruction Longjmp is not implemented.");
}
public static void Pexit(EmitterContext context)
{
InstPexit op = context.GetOp<InstPexit>();
context.GetOp<InstPexit>();
context.Config.GpuAccessor.Log("Shader instruction Pexit is not implemented.");
}
public static void Pixld(EmitterContext context)
{
InstPixld op = context.GetOp<InstPixld>();
context.GetOp<InstPixld>();
context.Config.GpuAccessor.Log("Shader instruction Pixld is not implemented.");
}
public static void Plongjmp(EmitterContext context)
{
InstPlongjmp op = context.GetOp<InstPlongjmp>();
context.GetOp<InstPlongjmp>();
context.Config.GpuAccessor.Log("Shader instruction Plongjmp is not implemented.");
}
public static void Pret(EmitterContext context)
{
InstPret op = context.GetOp<InstPret>();
context.GetOp<InstPret>();
context.Config.GpuAccessor.Log("Shader instruction Pret is not implemented.");
}
public static void PrmtR(EmitterContext context)
{
InstPrmtR op = context.GetOp<InstPrmtR>();
context.GetOp<InstPrmtR>();
context.Config.GpuAccessor.Log("Shader instruction PrmtR is not implemented.");
}
public static void PrmtI(EmitterContext context)
{
InstPrmtI op = context.GetOp<InstPrmtI>();
context.GetOp<InstPrmtI>();
context.Config.GpuAccessor.Log("Shader instruction PrmtI is not implemented.");
}
public static void PrmtC(EmitterContext context)
{
InstPrmtC op = context.GetOp<InstPrmtC>();
context.GetOp<InstPrmtC>();
context.Config.GpuAccessor.Log("Shader instruction PrmtC is not implemented.");
}
public static void PrmtRc(EmitterContext context)
{
InstPrmtRc op = context.GetOp<InstPrmtRc>();
context.GetOp<InstPrmtRc>();
context.Config.GpuAccessor.Log("Shader instruction PrmtRc is not implemented.");
}
public static void R2b(EmitterContext context)
{
InstR2b op = context.GetOp<InstR2b>();
context.GetOp<InstR2b>();
context.Config.GpuAccessor.Log("Shader instruction R2b is not implemented.");
}
public static void Ram(EmitterContext context)
{
InstRam op = context.GetOp<InstRam>();
context.GetOp<InstRam>();
context.Config.GpuAccessor.Log("Shader instruction Ram is not implemented.");
}
public static void Rtt(EmitterContext context)
{
InstRtt op = context.GetOp<InstRtt>();
context.GetOp<InstRtt>();
context.Config.GpuAccessor.Log("Shader instruction Rtt is not implemented.");
}
public static void Sam(EmitterContext context)
{
InstSam op = context.GetOp<InstSam>();
context.GetOp<InstSam>();
context.Config.GpuAccessor.Log("Shader instruction Sam is not implemented.");
}
public static void Setcrsptr(EmitterContext context)
{
InstSetcrsptr op = context.GetOp<InstSetcrsptr>();
context.GetOp<InstSetcrsptr>();
context.Config.GpuAccessor.Log("Shader instruction Setcrsptr is not implemented.");
}
public static void Setlmembase(EmitterContext context)
{
InstSetlmembase op = context.GetOp<InstSetlmembase>();
context.GetOp<InstSetlmembase>();
context.Config.GpuAccessor.Log("Shader instruction Setlmembase is not implemented.");
}
public static void St(EmitterContext context)
{
InstSt op = context.GetOp<InstSt>();
context.GetOp<InstSt>();
context.Config.GpuAccessor.Log("Shader instruction St is not implemented.");
}
public static void Stp(EmitterContext context)
{
InstStp op = context.GetOp<InstStp>();
context.GetOp<InstStp>();
context.Config.GpuAccessor.Log("Shader instruction Stp is not implemented.");
}
public static void Txa(EmitterContext context)
{
InstTxa op = context.GetOp<InstTxa>();
context.GetOp<InstTxa>();
context.Config.GpuAccessor.Log("Shader instruction Txa is not implemented.");
}
public static void Vabsdiff(EmitterContext context)
{
InstVabsdiff op = context.GetOp<InstVabsdiff>();
context.GetOp<InstVabsdiff>();
context.Config.GpuAccessor.Log("Shader instruction Vabsdiff is not implemented.");
}
public static void Vabsdiff4(EmitterContext context)
{
InstVabsdiff4 op = context.GetOp<InstVabsdiff4>();
context.GetOp<InstVabsdiff4>();
context.Config.GpuAccessor.Log("Shader instruction Vabsdiff4 is not implemented.");
}
public static void Vadd(EmitterContext context)
{
InstVadd op = context.GetOp<InstVadd>();
context.GetOp<InstVadd>();
context.Config.GpuAccessor.Log("Shader instruction Vadd is not implemented.");
}
public static void Votevtg(EmitterContext context)
{
InstVotevtg op = context.GetOp<InstVotevtg>();
context.GetOp<InstVotevtg>();
context.Config.GpuAccessor.Log("Shader instruction Votevtg is not implemented.");
}
public static void Vset(EmitterContext context)
{
InstVset op = context.GetOp<InstVset>();
context.GetOp<InstVset>();
context.Config.GpuAccessor.Log("Shader instruction Vset is not implemented.");
}
public static void Vshl(EmitterContext context)
{
InstVshl op = context.GetOp<InstVshl>();
context.GetOp<InstVshl>();
context.Config.GpuAccessor.Log("Shader instruction Vshl is not implemented.");
}
public static void Vshr(EmitterContext context)
{
InstVshr op = context.GetOp<InstVshr>();
context.GetOp<InstVshr>();
context.Config.GpuAccessor.Log("Shader instruction Vshr is not implemented.");
}
}
}
}

View File

@@ -2,7 +2,6 @@ using Ryujinx.Graphics.Shader.Decoders;
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
using Ryujinx.Graphics.Shader.Translation;
using System;
using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
@@ -18,7 +17,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
IDstFmt.S16 => short.MinValue,
IDstFmt.U32 => uint.MinValue,
IDstFmt.S32 => int.MinValue,
_ => throw new ArgumentException($"The type \"{type}\" is not a supported integer type.")
_ => throw new ArgumentException($"The type \"{type}\" is not a supported integer type."),
};
}
@@ -30,7 +29,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
IDstFmt.S16 => short.MaxValue,
IDstFmt.U32 => uint.MaxValue,
IDstFmt.S32 => int.MaxValue,
_ => throw new ArgumentException($"The type \"{type}\" is not a supported integer type.")
_ => throw new ArgumentException($"The type \"{type}\" is not a supported integer type."),
};
}
@@ -44,7 +43,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
ISrcDstFmt.S16 => short.MinValue,
ISrcDstFmt.U32 => uint.MinValue,
ISrcDstFmt.S32 => int.MinValue,
_ => throw new ArgumentException($"The type \"{type}\" is not a supported integer type.")
_ => throw new ArgumentException($"The type \"{type}\" is not a supported integer type."),
};
}
@@ -58,7 +57,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
ISrcDstFmt.S16 => short.MaxValue,
ISrcDstFmt.U32 => uint.MaxValue,
ISrcDstFmt.S32 => int.MaxValue,
_ => throw new ArgumentException($"The type \"{type}\" is not a supported integer type.")
_ => throw new ArgumentException($"The type \"{type}\" is not a supported integer type."),
};
}
@@ -69,7 +68,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
BoolOp.And => context.BitwiseAnd(input, pred),
BoolOp.Or => context.BitwiseOr(input, pred),
BoolOp.Xor => context.BitwiseExclusiveOr(input, pred),
_ => input
_ => input,
};
}
@@ -89,7 +88,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
VectorSelect.S8B3 => SignExtendTo32(context, context.ShiftRightU32(src, Const(24)), 8),
VectorSelect.S16H0 => SignExtendTo32(context, context.ShiftRightU32(src, Const(0)), 16),
VectorSelect.S16H1 => SignExtendTo32(context, context.ShiftRightU32(src, Const(16)), 16),
_ => src
_ => src,
};
}
@@ -134,7 +133,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
}
context.Copy(GetZF(), context.FPCompareEqual(dest, zero, fpType));
context.Copy(GetNF(), context.FPCompareLess (dest, zero, fpType));
context.Copy(GetNF(), context.FPCompareLess(dest, zero, fpType));
}
}
@@ -157,4 +156,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
return result;
}
}
}
}

View File

@@ -33,7 +33,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
for (int index = 0; index < (int)op.AlSize + 1; index++)
{
Register rd = new Register(op.Dest + index, RegisterType.Gpr);
Register rd = new(op.Dest + index, RegisterType.Gpr);
if (rd.IsRZ)
{
@@ -91,7 +91,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
break;
}
Register rd = new Register(op.SrcB + index, RegisterType.Gpr);
Register rd = new(op.SrcB + index, RegisterType.Gpr);
if (op.Phys)
{
@@ -380,4 +380,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
return false;
}
}
}
}

View File

@@ -22,7 +22,9 @@ namespace Ryujinx.Graphics.Shader.Instructions
public static void Depbar(EmitterContext context)
{
#pragma warning disable IDE0059 // Remove unnecessary value assignment
InstDepbar op = context.GetOp<InstDepbar>();
#pragma warning restore IDE0059
// No operation.
}
@@ -41,4 +43,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
}
}
}
}
}

View File

@@ -191,4 +191,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
context.Copy(GetDest(rd), res);
}
}
}
}

View File

@@ -1,7 +1,6 @@
using Ryujinx.Graphics.Shader.Decoders;
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
using Ryujinx.Graphics.Shader.Translation;
using static Ryujinx.Graphics.Shader.Instructions.InstEmitAluHelper;
using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
@@ -80,8 +79,8 @@ namespace Ryujinx.Graphics.Shader.Instructions
Ccc.Oft => GetVF(),
Ccc.Rle => context.BitwiseOr(GetNF(), GetZF()),
Ccc.Rgt => context.BitwiseNot(context.BitwiseOr(GetNF(), GetZF())),
_ => Const(defaultCond)
_ => Const(defaultCond),
};
}
}
}
}

View File

@@ -2,7 +2,6 @@ using Ryujinx.Graphics.Shader.Decoders;
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
using Ryujinx.Graphics.Shader.Translation;
using System;
using static Ryujinx.Graphics.Shader.Instructions.InstEmitAluHelper;
using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
@@ -140,7 +139,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
IntegerRound.Floor => context.FPFloor(srcB, srcType.ToInstFPType()),
IntegerRound.Ceil => context.FPCeiling(srcB, srcType.ToInstFPType()),
IntegerRound.Trunc => context.FPTruncate(srcB, srcType.ToInstFPType()),
_ => srcB
_ => srcB,
};
}
@@ -191,7 +190,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
RoundMode2.Floor => context.FPFloor(srcB, fpType),
RoundMode2.Ceil => context.FPCeiling(srcB, fpType),
RoundMode2.Trunc => context.FPTruncate(srcB, fpType),
_ => srcB
_ => srcB,
};
if (!isSignedInt)
@@ -422,4 +421,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
return type == DstFmt.F64 ? Instruction.FP64 : Instruction.FP32;
}
}
}
}

View File

@@ -1,7 +1,6 @@
using Ryujinx.Graphics.Shader.Decoders;
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
using Ryujinx.Graphics.Shader.Translation;
using static Ryujinx.Graphics.Shader.Instructions.InstEmitAluHelper;
using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
@@ -458,7 +457,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
MultiplyScale.M2 => ConstF(2f),
MultiplyScale.M4 => ConstF(4f),
MultiplyScale.M8 => ConstF(8f),
_ => ConstF(1f) // Invalid, behave as if it had no scale.
_ => ConstF(1f), // Invalid, behave as if it had no scale.
};
if (scaleConst.AsFloat() == 1f)
@@ -529,4 +528,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
context.Copy(GetDest(rd), GetHalfPacked(context, swizzle, res, rd));
}
}
}
}

View File

@@ -2,7 +2,6 @@ using Ryujinx.Graphics.Shader.Decoders;
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
using Ryujinx.Graphics.Shader.Translation;
using System;
using static Ryujinx.Graphics.Shader.Instructions.InstEmitAluHelper;
using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
@@ -484,8 +483,8 @@ namespace Ryujinx.Graphics.Shader.Instructions
}
else
{
Operand low = context.BitwiseAnd(res[0], Const(0xffff));
Operand high = context.ShiftLeft (res[1], Const(16));
Operand low = context.BitwiseAnd(res[0], Const(0xffff));
Operand high = context.ShiftLeft(res[1], Const(16));
Operand packed = context.BitwiseOr(low, high);
@@ -546,20 +545,16 @@ namespace Ryujinx.Graphics.Shader.Instructions
}
else
{
Instruction inst;
switch (cond & ~FComp.Nan)
var inst = (cond & ~FComp.Nan) switch
{
case FComp.Lt: inst = Instruction.CompareLess; break;
case FComp.Eq: inst = Instruction.CompareEqual; break;
case FComp.Le: inst = Instruction.CompareLessOrEqual; break;
case FComp.Gt: inst = Instruction.CompareGreater; break;
case FComp.Ne: inst = Instruction.CompareNotEqual; break;
case FComp.Ge: inst = Instruction.CompareGreaterOrEqual; break;
default: throw new ArgumentException($"Unexpected condition \"{cond}\".");
}
FComp.Lt => Instruction.CompareLess,
FComp.Eq => Instruction.CompareEqual,
FComp.Le => Instruction.CompareLessOrEqual,
FComp.Gt => Instruction.CompareGreater,
FComp.Ne => Instruction.CompareNotEqual,
FComp.Ge => Instruction.CompareGreaterOrEqual,
_ => throw new ArgumentException($"Unexpected condition \"{cond}\"."),
};
res = context.Add(inst | fpType, Local(), srcA, srcB);
if ((cond & FComp.Nan) != 0)
@@ -572,4 +567,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
return res;
}
}
}
}

View File

@@ -103,4 +103,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
SetFPZnFlags(context, res, writeCC, fpType);
}
}
}
}

View File

@@ -3,8 +3,6 @@ using Ryujinx.Graphics.Shader.IntermediateRepresentation;
using Ryujinx.Graphics.Shader.Translation;
using System.Collections.Generic;
using System.Linq;
using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
namespace Ryujinx.Graphics.Shader.Instructions
@@ -13,14 +11,14 @@ namespace Ryujinx.Graphics.Shader.Instructions
{
public static void Bra(EmitterContext context)
{
InstBra op = context.GetOp<InstBra>();
context.GetOp<InstBra>();
EmitBranch(context, context.CurrBlock.Successors[^1].Address);
}
public static void Brk(EmitterContext context)
{
InstBrk op = context.GetOp<InstBrk>();
context.GetOp<InstBrk>();
EmitBrkContSync(context);
}
@@ -123,7 +121,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
public static void Cal(EmitterContext context)
{
InstCal op = context.GetOp<InstCal>();
context.GetOp<InstCal>();
DecodedFunction function = context.Program.GetFunctionByAddress(context.CurrOp.GetAbsoluteAddress());
@@ -147,7 +145,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
public static void Cont(EmitterContext context)
{
InstCont op = context.GetOp<InstCont>();
context.GetOp<InstCont>();
EmitBrkContSync(context);
}
@@ -185,28 +183,28 @@ namespace Ryujinx.Graphics.Shader.Instructions
public static void Kil(EmitterContext context)
{
InstKil op = context.GetOp<InstKil>();
context.GetOp<InstKil>();
context.Discard();
}
public static void Pbk(EmitterContext context)
{
InstPbk op = context.GetOp<InstPbk>();
context.GetOp<InstPbk>();
EmitPbkPcntSsy(context);
}
public static void Pcnt(EmitterContext context)
{
InstPcnt op = context.GetOp<InstPcnt>();
context.GetOp<InstPcnt>();
EmitPbkPcntSsy(context);
}
public static void Ret(EmitterContext context)
{
InstRet op = context.GetOp<InstRet>();
context.GetOp<InstRet>();
if (context.IsNonMain)
{
@@ -220,14 +218,14 @@ namespace Ryujinx.Graphics.Shader.Instructions
public static void Ssy(EmitterContext context)
{
InstSsy op = context.GetOp<InstSsy>();
context.GetOp<InstSsy>();
EmitPbkPcntSsy(context);
}
public static void Sync(EmitterContext context)
{
InstSync op = context.GetOp<InstSync>();
context.GetOp<InstSync>();
EmitBrkContSync(context);
}
@@ -275,7 +273,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
private static void EmitBranch(EmitterContext context, ulong address)
{
InstOp op = context.CurrOp;
InstConditional opCond = new InstConditional(op.RawOpCode);
InstConditional opCond = new(op.RawOpCode);
// If we're branching to the next instruction, then the branch
// is useless and we can ignore it.
@@ -321,4 +319,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
}
}
}
}
}

View File

@@ -3,7 +3,6 @@ using Ryujinx.Graphics.Shader.IntermediateRepresentation;
using Ryujinx.Graphics.Shader.Translation;
using System;
using System.Runtime.CompilerServices;
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
namespace Ryujinx.Graphics.Shader.Instructions
@@ -111,7 +110,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
return new Operand[]
{
ConstF((float)Unsafe.As<ushort, Half>(ref low)),
ConstF((float)Unsafe.As<ushort, Half>(ref high))
ConstF((float)Unsafe.As<ushort, Half>(ref high)),
};
}
@@ -123,7 +122,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
return new Operand[]
{
ConstF((float)Unsafe.As<ushort, Half>(ref low)),
ConstF((float)Unsafe.As<ushort, Half>(ref high))
ConstF((float)Unsafe.As<ushort, Half>(ref high)),
};
}
@@ -139,56 +138,51 @@ namespace Ryujinx.Graphics.Shader.Instructions
public static Operand[] GetHalfUnpacked(EmitterContext context, Operand src, HalfSwizzle swizzle)
{
switch (swizzle)
return swizzle switch
{
case HalfSwizzle.F16:
return new Operand[]
{
HalfSwizzle.F16 => new Operand[]
{
context.UnpackHalf2x16Low (src),
context.UnpackHalf2x16High(src)
};
case HalfSwizzle.F32: return new Operand[] { src, src };
case HalfSwizzle.H0H0:
return new Operand[]
context.UnpackHalf2x16High(src),
},
HalfSwizzle.F32 => new Operand[] { src, src },
HalfSwizzle.H0H0 => new Operand[]
{
context.UnpackHalf2x16Low(src),
context.UnpackHalf2x16Low(src)
};
case HalfSwizzle.H1H1:
return new Operand[]
context.UnpackHalf2x16Low(src),
},
HalfSwizzle.H1H1 => new Operand[]
{
context.UnpackHalf2x16High(src),
context.UnpackHalf2x16High(src)
};
}
throw new ArgumentException($"Invalid swizzle \"{swizzle}\".");
context.UnpackHalf2x16High(src),
},
_ => throw new ArgumentException($"Invalid swizzle \"{swizzle}\"."),
};
}
public static Operand GetHalfPacked(EmitterContext context, OFmt swizzle, Operand[] results, int rd)
{
switch (swizzle)
{
case OFmt.F16: return context.PackHalf2x16(results[0], results[1]);
case OFmt.F16:
return context.PackHalf2x16(results[0], results[1]);
case OFmt.F32: return results[0];
case OFmt.F32:
return results[0];
case OFmt.MrgH0:
{
Operand h1 = GetHalfDest(context, rd, isHigh: true);
{
Operand h1 = GetHalfDest(context, rd, isHigh: true);
return context.PackHalf2x16(results[0], h1);
}
return context.PackHalf2x16(results[0], h1);
}
case OFmt.MrgH1:
{
Operand h0 = GetHalfDest(context, rd, isHigh: false);
{
Operand h0 = GetHalfDest(context, rd, isHigh: false);
return context.PackHalf2x16(h0, results[1]);
}
return context.PackHalf2x16(h0, results[1]);
}
}
throw new ArgumentException($"Invalid swizzle \"{swizzle}\".");
@@ -263,4 +257,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
return context.BitwiseAnd(src, Const(mask));
}
}
}
}

View File

@@ -510,7 +510,9 @@ namespace Ryujinx.Graphics.Shader.Instructions
aLow = context.BitwiseNot(aLow);
aHigh = context.BitwiseNot(aHigh);
#pragma warning disable IDE0059 // Remove unnecessary value assignment
aLow = AddWithCarry(context, aLow, Const(1), out Operand aLowCOut);
#pragma warning restore IDE0059
aHigh = context.IAdd(aHigh, aLowCOut);
}
@@ -696,4 +698,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
SetZnFlags(context, res, setCC: true, extended: extended);
}
}
}
}

View File

@@ -2,7 +2,6 @@ using Ryujinx.Graphics.Shader.Decoders;
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
using Ryujinx.Graphics.Shader.Translation;
using System;
using static Ryujinx.Graphics.Shader.Instructions.InstEmitAluHelper;
using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
@@ -220,7 +219,9 @@ namespace Ryujinx.Graphics.Shader.Instructions
else
{
res = context.ISubtract(srcA, srcB);
#pragma warning disable IDE0059 // Remove unnecessary value assignment
res = context.IAdd(res, context.BitwiseNot(GetCF()));
#pragma warning restore IDE0059
switch (cond)
{
@@ -287,17 +288,25 @@ namespace Ryujinx.Graphics.Shader.Instructions
IComp.Gt => Instruction.CompareGreaterU32,
IComp.Ne => Instruction.CompareNotEqual,
IComp.Ge => Instruction.CompareGreaterOrEqualU32,
_ => throw new InvalidOperationException($"Unexpected condition \"{cond}\".")
_ => throw new InvalidOperationException($"Unexpected condition \"{cond}\"."),
};
if (isSigned)
{
switch (cond)
{
case IComp.Lt: inst = Instruction.CompareLess; break;
case IComp.Le: inst = Instruction.CompareLessOrEqual; break;
case IComp.Gt: inst = Instruction.CompareGreater; break;
case IComp.Ge: inst = Instruction.CompareGreaterOrEqual; break;
case IComp.Lt:
inst = Instruction.CompareLess;
break;
case IComp.Le:
inst = Instruction.CompareLessOrEqual;
break;
case IComp.Gt:
inst = Instruction.CompareGreater;
break;
case IComp.Ge:
inst = Instruction.CompareGreaterOrEqual;
break;
}
}
@@ -307,4 +316,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
return res;
}
}
}
}

View File

@@ -1,7 +1,6 @@
using Ryujinx.Graphics.Shader.Decoders;
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
using Ryujinx.Graphics.Shader.Translation;
using static Ryujinx.Graphics.Shader.Instructions.InstEmitAluHelper;
using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
@@ -103,10 +102,10 @@ namespace Ryujinx.Graphics.Shader.Instructions
Operand res = logicOp switch
{
LogicOp.And => res = context.BitwiseAnd(srcA, srcB),
LogicOp.Or => res = context.BitwiseOr(srcA, srcB),
LogicOp.Xor => res = context.BitwiseExclusiveOr(srcA, srcB),
_ => srcB
LogicOp.And => context.BitwiseAnd(srcA, srcB),
LogicOp.Or => context.BitwiseOr(srcA, srcB),
LogicOp.Xor => context.BitwiseExclusiveOr(srcA, srcB),
_ => srcB,
};
EmitLopPredWrite(context, res, predOp, destPred);
@@ -164,4 +163,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
}
}
}
}
}

View File

@@ -68,4 +68,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
// TODO: X flags.
}
}
}
}

View File

@@ -2,7 +2,6 @@ using Ryujinx.Graphics.Shader.Decoders;
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
using Ryujinx.Graphics.Shader.Translation;
using System.Numerics;
using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
@@ -48,7 +47,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
AtomsSize.S32 => AtomSize.S32,
AtomsSize.U64 => AtomSize.U64,
AtomsSize.S64 => AtomSize.S64,
_ => AtomSize.U32
_ => AtomSize.U32,
};
Operand id = Const(context.Config.ResourceManager.SharedMemoryId);
@@ -85,7 +84,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
for (int index = 0; index < count; index++)
{
Register dest = new Register(op.Dest + index, RegisterType.Gpr);
Register dest = new(op.Dest + index, RegisterType.Gpr);
if (dest.IsRZ)
{
@@ -309,14 +308,14 @@ namespace Ryujinx.Graphics.Shader.Instructions
{
LsSize2.B64 => 2,
LsSize2.B128 => 4,
_ => 1
_ => 1,
};
Operand baseOffset = context.Copy(srcA);
for (int index = 0; index < count; index++)
{
Register dest = new Register(rd + index, RegisterType.Gpr);
Register dest = new(rd + index, RegisterType.Gpr);
if (dest.IsRZ)
{
@@ -354,7 +353,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
for (int index = 0; index < count; index++)
{
Register dest = new Register(rd + index, RegisterType.Gpr);
Register dest = new(rd + index, RegisterType.Gpr);
if (dest.IsRZ)
{
@@ -390,7 +389,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
{
LsSize2.B64 => 2,
LsSize2.B128 => 4,
_ => 1
_ => 1,
};
Operand baseOffset = context.Copy(srcA);
@@ -476,22 +475,18 @@ namespace Ryujinx.Graphics.Shader.Instructions
LsSize.S8 => StorageKind.GlobalMemoryS8,
LsSize.U16 => StorageKind.GlobalMemoryU16,
LsSize.S16 => StorageKind.GlobalMemoryS16,
_ => StorageKind.GlobalMemory
_ => StorageKind.GlobalMemory,
};
}
private static int GetVectorCount(LsSize size)
{
switch (size)
return size switch
{
case LsSize.B64:
return 2;
case LsSize.B128:
case LsSize.UB128:
return 4;
}
return 1;
LsSize.B64 => 2,
LsSize.B128 or LsSize.UB128 => 4,
_ => 1,
};
}
private static (Operand, Operand) Get40BitsAddress(
@@ -544,10 +539,18 @@ namespace Ryujinx.Graphics.Shader.Instructions
switch (size)
{
case LsSize.U8: value = ZeroExtendTo32(context, value, 8); break;
case LsSize.U16: value = ZeroExtendTo32(context, value, 16); break;
case LsSize.S8: value = SignExtendTo32(context, value, 8); break;
case LsSize.S16: value = SignExtendTo32(context, value, 16); break;
case LsSize.U8:
value = ZeroExtendTo32(context, value, 8);
break;
case LsSize.U16:
value = ZeroExtendTo32(context, value, 16);
break;
case LsSize.S8:
value = SignExtendTo32(context, value, 8);
break;
case LsSize.S16:
value = SignExtendTo32(context, value, 16);
break;
}
return value;
@@ -578,4 +581,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
return value;
}
}
}
}

View File

@@ -212,7 +212,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
int count = ccpr ? RegisterConsts.FlagsCount : RegisterConsts.PredsCount;
RegisterType type = ccpr ? RegisterType.Flag : RegisterType.Predicate;
int shift = (int)byteSel * 8;
for (int bit = 0; bit < count; bit++)
{
Operand flag = Register(bit, type);
@@ -228,4 +228,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
context.Copy(GetDest(rd), res);
}
}
}
}

View File

@@ -94,4 +94,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
context.Copy(GetDest(rd), srcB);
}
}
}
}

View File

@@ -7,9 +7,9 @@ namespace Ryujinx.Graphics.Shader.Instructions
{
public static void Nop(EmitterContext context)
{
InstNop op = context.GetOp<InstNop>();
context.GetOp<InstNop>();
// No operation.
}
}
}
}

View File

@@ -113,4 +113,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
context.Copy(dest, res);
}
}
}
}

View File

@@ -246,4 +246,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
context.Copy(GetDest(rd), res);
}
}
}
}

View File

@@ -4,7 +4,6 @@ using Ryujinx.Graphics.Shader.Translation;
using System;
using System.Collections.Generic;
using System.Numerics;
using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
@@ -221,7 +220,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
Operand destOperand = dest != RegisterConsts.RegisterZeroIndex ? Register(dest, RegisterType.Gpr) : null;
List<Operand> sourcesList = new List<Operand>();
List<Operand> sourcesList = new();
if (isBindless)
{
@@ -325,7 +324,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
return context.Copy(Register(srcA++, RegisterType.Gpr));
}
List<Operand> sourcesList = new List<Operand>();
List<Operand> sourcesList = new();
if (isBindless)
{
@@ -445,10 +444,18 @@ namespace Ryujinx.Graphics.Shader.Instructions
switch (size)
{
case SuSize.U8: context.Copy(dests[0], ZeroExtendTo32(context, dests[0], 8)); break;
case SuSize.U16: context.Copy(dests[0], ZeroExtendTo32(context, dests[0], 16)); break;
case SuSize.S8: context.Copy(dests[0], SignExtendTo32(context, dests[0], 8)); break;
case SuSize.S16: context.Copy(dests[0], SignExtendTo32(context, dests[0], 16)); break;
case SuSize.U8:
context.Copy(dests[0], ZeroExtendTo32(context, dests[0], 8));
break;
case SuSize.U16:
context.Copy(dests[0], ZeroExtendTo32(context, dests[0], 16));
break;
case SuSize.S8:
context.Copy(dests[0], SignExtendTo32(context, dests[0], 8));
break;
case SuSize.S16:
context.Copy(dests[0], SignExtendTo32(context, dests[0], 16));
break;
}
}
}
@@ -493,7 +500,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
return context.Copy(Register(srcB++, RegisterType.Gpr));
}
List<Operand> sourcesList = new List<Operand>();
List<Operand> sourcesList = new();
if (isBindless)
{
@@ -600,7 +607,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
return context.Copy(Register(srcB++, RegisterType.Gpr));
}
List<Operand> sourcesList = new List<Operand>();
List<Operand> sourcesList = new();
if (isBindless)
{
@@ -699,7 +706,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
SuatomSize.S64 => 3,
SuatomSize.Sd32 => 2,
SuatomSize.Sd64 => 3,
_ => 2
_ => 2,
};
}
@@ -715,7 +722,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
SuatomSize.S64 => TextureFormat.R32G32Uint,
SuatomSize.Sd32 => TextureFormat.R32Uint,
SuatomSize.Sd64 => TextureFormat.R32G32Uint,
_ => TextureFormat.R32Uint
_ => TextureFormat.R32Uint,
};
}
@@ -732,7 +739,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
SuatomOp.Or => TextureFlags.BitwiseOr,
SuatomOp.Xor => TextureFlags.BitwiseXor,
SuatomOp.Exch => TextureFlags.Swap,
_ => TextureFlags.Add
_ => TextureFlags.Add,
};
}
@@ -743,7 +750,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
SuSize.B64 => 2,
SuSize.B128 => 4,
SuSize.UB128 => 4,
_ => 1
_ => 1,
};
}
@@ -759,7 +766,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
SuSize.B64 => 3,
SuSize.B128 => 4,
SuSize.UB128 => 4,
_ => 2
_ => 2,
};
}
@@ -775,7 +782,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
SuSize.B64 => TextureFormat.R32G32Uint,
SuSize.B128 => TextureFormat.R32G32B32A32Uint,
SuSize.UB128 => TextureFormat.R32G32B32A32Uint,
_ => TextureFormat.R32Uint
_ => TextureFormat.R32Uint,
};
}
@@ -789,8 +796,8 @@ namespace Ryujinx.Graphics.Shader.Instructions
SuDim._2d => SamplerType.Texture2D,
SuDim._2dArray => SamplerType.Texture2D | SamplerType.Array,
SuDim._3d => SamplerType.Texture3D,
_ => SamplerType.None
_ => SamplerType.None,
};
}
}
}
}

View File

@@ -4,7 +4,6 @@ using Ryujinx.Graphics.Shader.Translation;
using System;
using System.Collections.Generic;
using System.Numerics;
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
namespace Ryujinx.Graphics.Shader.Instructions
@@ -14,7 +13,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
private static readonly int[,] _maskLut = new int[,]
{
{ 0b0001, 0b0010, 0b0100, 0b1000, 0b0011, 0b1001, 0b1010, 0b1100 },
{ 0b0111, 0b1011, 0b1101, 0b1110, 0b1111, 0b0000, 0b0000, 0b0000 }
{ 0b0111, 0b1011, 0b1101, 0b1110, 0b1111, 0b0000, 0b0000, 0b0000 },
};
public const bool Sample1DAs2D = true;
@@ -23,7 +22,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
{
Texs,
Tlds,
Tld4s
Tld4s,
}
public static void Tex(EmitterContext context)
@@ -207,7 +206,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
Operand arrayIndex = isArray ? Ra() : null;
List<Operand> sourcesList = new List<Operand>();
List<Operand> sourcesList = new();
if (isBindless)
{
@@ -353,7 +352,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
return;
}
List<Operand> sourcesList = new List<Operand>();
List<Operand> sourcesList = new();
Operand Ra()
{
@@ -722,7 +721,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
Operand arrayIndex = isArray ? Ra() : null;
List<Operand> sourcesList = new List<Operand>();
List<Operand> sourcesList = new();
SamplerType type = ConvertSamplerType(dimensions);
TextureFlags flags = TextureFlags.Gather;
@@ -864,7 +863,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
TextureFlags flags = TextureFlags.None;
List<Operand> sourcesList = new List<Operand>();
List<Operand> sourcesList = new();
if (isBindless)
{
@@ -996,7 +995,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
TextureFlags flags = TextureFlags.Derivatives;
List<Operand> sourcesList = new List<Operand>();
List<Operand> sourcesList = new();
if (isBindless)
{
@@ -1126,7 +1125,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
return context.Copy(Register(srcA++, RegisterType.Gpr));
}
List<Operand> sourcesList = new List<Operand>();
List<Operand> sourcesList = new();
if (isBindless)
{
@@ -1195,7 +1194,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
TexDim.Array3d => SamplerType.Texture3D | SamplerType.Array,
TexDim.Cube => SamplerType.TextureCube,
TexDim.ArrayCube => SamplerType.TextureCube | SamplerType.Array,
_ => throw new ArgumentException($"Invalid texture dimensions \"{dimensions}\".")
_ => throw new ArgumentException($"Invalid texture dimensions \"{dimensions}\"."),
};
}
@@ -1309,4 +1308,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
return TextureFlags.None;
}
}
}
}

View File

@@ -1,7 +1,6 @@
using Ryujinx.Graphics.Shader.Decoders;
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
using Ryujinx.Graphics.Shader.Translation;
using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
@@ -77,7 +76,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
{
VideoScale.Shr7 => 7,
VideoScale.Shr15 => 15,
_ => 0
_ => 0,
};
if (shift != 0)
@@ -115,4 +114,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
// TODO: CC.
}
}
}
}

View File

@@ -180,4 +180,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
context.Copy(Register(op.DestPredInv, RegisterType.Predicate), p1Res);
}
}
}
}

View File

@@ -1,7 +1,6 @@
using Ryujinx.Graphics.Shader.Decoders;
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
using Ryujinx.Graphics.Shader.Translation;
using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
@@ -39,7 +38,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
ShflMode.Up => context.ShuffleUp(srcA, srcB, srcC),
ShflMode.Down => context.ShuffleDown(srcA, srcB, srcC),
ShflMode.Bfly => context.ShuffleXor(srcA, srcB, srcC),
_ => (null, null)
_ => (null, null),
};
context.Copy(GetDest(op.Dest), res);
@@ -81,4 +80,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
}
}
}
}
}

View File

@@ -3,4 +3,4 @@ using Ryujinx.Graphics.Shader.Translation;
namespace Ryujinx.Graphics.Shader.Instructions
{
delegate void InstEmitter(EmitterContext context);
}
}

View File

@@ -1,6 +1,5 @@
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
using Ryujinx.Graphics.Shader.Translation;
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
namespace Ryujinx.Graphics.Shader.Instructions
@@ -9,27 +8,27 @@ namespace Ryujinx.Graphics.Shader.Instructions
{
private enum TruthTable : byte
{
False = 0x00, // false
True = 0xff, // true
In = 0xf0, // a
And2 = 0xc0, // a & b
Or2 = 0xfc, // a | b
Xor2 = 0x3c, // a ^ b
And3 = 0x80, // a & b & c
Or3 = 0xfe, // a | b | c
XorAnd = 0x60, // a & (b ^ c)
XorOr = 0xf6, // a | (b ^ c)
OrAnd = 0xe0, // a & (b | c)
AndOr = 0xf8, // a | (b & c)
Onehot = 0x16, // (a & !b & !c) | (!a & b & !c) | (!a & !b & c) - Only one value is true.
Majority = 0xe8, // Popcount(a, b, c) >= 2
Gamble = 0x81, // (a & b & c) | (!a & !b & !c) - All on or all off
False = 0x00, // false
True = 0xff, // true
In = 0xf0, // a
And2 = 0xc0, // a & b
Or2 = 0xfc, // a | b
Xor2 = 0x3c, // a ^ b
And3 = 0x80, // a & b & c
Or3 = 0xfe, // a | b | c
XorAnd = 0x60, // a & (b ^ c)
XorOr = 0xf6, // a | (b ^ c)
OrAnd = 0xe0, // a & (b | c)
AndOr = 0xf8, // a | (b & c)
Onehot = 0x16, // (a & !b & !c) | (!a & b & !c) | (!a & !b & c) - Only one value is true.
Majority = 0xe8, // Popcount(a, b, c) >= 2
Gamble = 0x81, // (a & b & c) | (!a & !b & !c) - All on or all off
InverseGamble = 0x7e, // Inverse of Gamble
Dot = 0x1a, // a ^ (c | (a & b))
Mux = 0xca, // a ? b : c
AndXor = 0x78, // a ^ (b & c)
OrXor = 0x1e, // a ^ (b | c)
Xor3 = 0x96, // a ^ b ^ c
Dot = 0x1a, // a ^ (c | (a & b))
Mux = 0xca, // a ? b : c
AndXor = 0x78, // a ^ (b & c)
OrXor = 0x1e, // a ^ (b | c)
Xor3 = 0x96, // a ^ b ^ c
}
public static Operand GetFromTruthTable(EmitterContext context, Operand srcA, Operand srcB, Operand srcC, int imm)
@@ -41,7 +40,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
Operand x = srcA;
Operand y = srcB;
Operand z = srcC;
if ((i & 0x01) != 0)
{
(x, y) = (y, x);
@@ -98,6 +97,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
{
return imm switch
{
#pragma warning disable IDE0055 // Disable formatting
TruthTable.False => Const(0),
TruthTable.True => Const(-1),
TruthTable.In => x,
@@ -118,7 +118,8 @@ namespace Ryujinx.Graphics.Shader.Instructions
TruthTable.AndXor => context.BitwiseExclusiveOr(x, context.BitwiseAnd(y, z)),
TruthTable.OrXor => context.BitwiseExclusiveOr(x, context.BitwiseOr(y, z)),
TruthTable.Xor3 => context.BitwiseExclusiveOr(x, context.BitwiseExclusiveOr(y, z)),
_ => null
_ => null,
#pragma warning restore IDE0055
};
}
@@ -138,4 +139,4 @@ namespace Ryujinx.Graphics.Shader.Instructions
return (TruthTable)result;
}
}
}
}

View File

@@ -83,9 +83,9 @@ namespace Ryujinx.Graphics.Shader.IntermediateRepresentation
case Instruction.Discard:
case Instruction.Return:
return true;
default:
return false;
}
return false;
}
}
}
}

View File

@@ -9,4 +9,4 @@ namespace Ryujinx.Graphics.Shader.IntermediateRepresentation
Comment = comment;
}
}
}
}

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