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43
.github/ISSUE_TEMPLATE/bug_report.md
vendored
43
.github/ISSUE_TEMPLATE/bug_report.md
vendored
@ -1,43 +0,0 @@
|
||||
---
|
||||
name: Bug Report
|
||||
about: Something doesn't work correctly in Ryujinx. Game-specific issues should be posted at https://github.com/Ryujinx/Ryujinx-Games-List instead, unless it is a provable regression.
|
||||
#assignees:
|
||||
---
|
||||
|
||||
## Bug Report
|
||||
|
||||
[ If any section does not apply, replace its contents with "N/A". ]</br>
|
||||
[ Lines between [ ] (square brackets) should be removed before posting. ]
|
||||
|
||||
### What's the issue you encountered?
|
||||
|
||||
[ Describe the issue in detail and what you were doing beforehand. ]</br>
|
||||
[ Did you make any changes related to Ryujinx itself? ]</br>
|
||||
[ If so, make sure to include details relating to what exactly you changed. ]
|
||||
|
||||
### How can the issue be reproduced?
|
||||
|
||||
[ Include a detailed step by step process for recreating your issue. ]
|
||||
|
||||
### Log file
|
||||
|
||||
[ Logs files can be found under ``Logs`` folder in Ryujinx program folder. ]</br>
|
||||
[ If you don't include a crash report in instances of crash related issues, we will ask you one to provide one. ]
|
||||
|
||||
### Environment?
|
||||
|
||||
- Ryujinx version: 1.0.X</br>
|
||||
[ Replace X's with the Ryujinx version at time of crash. ]
|
||||
- Game version: X.X.X</br>
|
||||
[ Replace X's with the game version at time of crash. ]
|
||||
- System Specs:
|
||||
- OS: *(e.g. Windows 10)*
|
||||
- CPU: *(e.g. i7-6700)*
|
||||
- GPU: *(e.g. NVIDIA RTX 2070)*
|
||||
- RAM: *(e.g. 16GiB)*
|
||||
- Applied Mods : [ Yes (Which ones) / No ]
|
||||
|
||||
### Additional context?
|
||||
|
||||
Additional info about your environment:</br>
|
||||
[ Any other information relevant to your issue. ]
|
75
.github/ISSUE_TEMPLATE/bug_report.yml
vendored
Normal file
75
.github/ISSUE_TEMPLATE/bug_report.yml
vendored
Normal file
@ -0,0 +1,75 @@
|
||||
name: Bug Report
|
||||
description: File a bug report
|
||||
body:
|
||||
- type: checkboxes
|
||||
attributes:
|
||||
label: Is there an existing issue for this?
|
||||
description: Please search to see if an issue already exists for the bug you encountered.
|
||||
options:
|
||||
- label: I have searched the existing issues
|
||||
required: true
|
||||
- type: textarea
|
||||
id: issue
|
||||
attributes:
|
||||
label: Description of Issue
|
||||
description: What's the issue you encountered?
|
||||
validations:
|
||||
required: true
|
||||
- type: textarea
|
||||
id: repro
|
||||
attributes:
|
||||
label: Reproduction Steps
|
||||
description: How can the issue be reproduced?
|
||||
validations:
|
||||
required: true
|
||||
- type: textarea
|
||||
id: log
|
||||
attributes:
|
||||
label: Log File
|
||||
description: A log file will help our developers to better diagnose and fix the issue.
|
||||
placeholder: Logs files can be found under "Logs" folder in Ryujinx program folder. You can drag and drop the log on to the text area
|
||||
validations:
|
||||
required: true
|
||||
- type: input
|
||||
id: os
|
||||
attributes:
|
||||
label: OS
|
||||
placeholder: "Example: Windows 10"
|
||||
validations:
|
||||
required: true
|
||||
- type: input
|
||||
id: ryujinx-version
|
||||
attributes:
|
||||
label: Ryujinx version
|
||||
placeholder: |
|
||||
- *(e.g. 1.0.470)*
|
||||
validations:
|
||||
required: true
|
||||
- type: input
|
||||
id: game-version
|
||||
attributes:
|
||||
label: Game version
|
||||
placeholder: |
|
||||
- *(e.g. 1.1.1)*
|
||||
validations:
|
||||
required: false
|
||||
- type: textarea
|
||||
id: environment
|
||||
attributes:
|
||||
label: Environment?
|
||||
value: |
|
||||
- ##### CPU: *(e.g. i7-6700)*
|
||||
- ##### GPU: *(e.g. NVIDIA RTX 2070)*
|
||||
- ##### RAM: *(e.g. 16GB)*
|
||||
- Applied Mods: [ Yes (Which ones) / No ]
|
||||
validations:
|
||||
required: true
|
||||
- type: textarea
|
||||
id: additional-context
|
||||
attributes:
|
||||
label: Additional context?
|
||||
description: |
|
||||
- Additional info about your environment:
|
||||
- Any other information relevant to your issue.
|
||||
validations:
|
||||
required: false
|
34
.github/ISSUE_TEMPLATE/feature_request.md
vendored
34
.github/ISSUE_TEMPLATE/feature_request.md
vendored
@ -1,34 +0,0 @@
|
||||
---
|
||||
name: Feature Request
|
||||
about: Suggest a new feature for Ryujinx.
|
||||
#assignees:
|
||||
---
|
||||
|
||||
## Feature Request
|
||||
|
||||
[ If any section does not apply, replace its contents with "N/A". ]</br>
|
||||
[ If you do not have the information needed for a section, replace its contents with "Unknown". ]</br>
|
||||
[ Lines between [ ] (square brackets) are to be removed before posting. ]</br>
|
||||
|
||||
[ Please search for existing [feature requests](https://github.com/Ryujinx/Ryujinx/issues) before you make your own request. ]</br>
|
||||
[ Duplicate requests will be marked as such and you will be referred to the original request. ]
|
||||
|
||||
### What feature are you suggesting?
|
||||
#### Overview:
|
||||
- [ Include the basic, high-level concepts for this feature here. ]
|
||||
|
||||
#### Smaller Details:
|
||||
- [ These may include specific methods of implementation etc. ]
|
||||
|
||||
#### Nature of Request:
|
||||
[ Remove all that do not apply to your request. ]
|
||||
- Addition
|
||||
- [ Ex: Addition of certain original features or features from other community projects. ]
|
||||
- [ If you are suggesting porting features or including features from other projects, include what license they are distributed under and what, if any libraries those project use. ]
|
||||
- Change
|
||||
- Removal
|
||||
- [Ex: Removal of certain features or implementation due to a specific issue/bug or because of low quality code, etc.]
|
||||
|
||||
### Why would this feature be useful?
|
||||
[ If this is a feature for an end-user, how does it benefit the end-user? ]</br>
|
||||
[ If this feature is for developers, what does it add to Ryujinx that did not already exist? ]
|
36
.github/ISSUE_TEMPLATE/feature_request.yml
vendored
Normal file
36
.github/ISSUE_TEMPLATE/feature_request.yml
vendored
Normal file
@ -0,0 +1,36 @@
|
||||
name: Feature Request
|
||||
description: Suggest a new feature for Ryujinx.
|
||||
body:
|
||||
- type: checkboxes
|
||||
attributes:
|
||||
label: Is there an existing issue for this?
|
||||
description: Please search to see if an issue already exists for the feature you are requesting.
|
||||
options:
|
||||
- label: I have searched the existing issues
|
||||
required: true
|
||||
- type: textarea
|
||||
id: overview
|
||||
attributes:
|
||||
label: Overview
|
||||
description: Include the basic, high-level concepts for this feature here.
|
||||
validations:
|
||||
required: true
|
||||
- type: textarea
|
||||
id: details
|
||||
attributes:
|
||||
label: Smaller Details
|
||||
description: These may include specific methods of implementation etc.
|
||||
validations:
|
||||
required: true
|
||||
- type: textarea
|
||||
id: request
|
||||
attributes:
|
||||
label: Nature of Request
|
||||
validations:
|
||||
required: true
|
||||
- type: textarea
|
||||
id: feature
|
||||
attributes:
|
||||
label: Why would this feature be useful?
|
||||
validations:
|
||||
required: true
|
@ -1,34 +0,0 @@
|
||||
---
|
||||
name: Missing CPU Instruction
|
||||
about: CPU Instruction is missing in Ryujinx.
|
||||
#assignees:
|
||||
---
|
||||
|
||||
## Missing CPU Instruction
|
||||
|
||||
[ If any section does not apply, replace its contents with "N/A". ]</br>
|
||||
[ If you do not have the information needed for a section, replace its contents with "Unknown". ]</br>
|
||||
[ Lines between [ ] (square brackets) are to be removed before posting. ]
|
||||
|
||||
[ Please search for existing [missing CPU instruction](https://github.com/Ryujinx/Ryujinx/issues) before you make your own issue. ]</br>
|
||||
[ See the following [issue](https://github.com/Ryujinx/Ryujinx/issues/1405) as an example ]</br>
|
||||
[ Duplicate issue will be marked as such and you will be referred to the original request. ]
|
||||
|
||||
### What CPU instruction is missing?
|
||||
|
||||
Requires the *INSTRUCTION* instruction.</br>
|
||||
[ Replace *INSTRUCTION* by the instruction name, e.g. VADDL.U16 ]
|
||||
|
||||
```
|
||||
*
|
||||
```
|
||||
[ Add the undefined instruction error message in the above code block ]
|
||||
|
||||
### Instruction name
|
||||
```
|
||||
*
|
||||
```
|
||||
[ Include the name from [armconverter.com](https://armconverter.com/?disasm) or [shell-storm.org](http://shell-storm.org/online/Online-Assembler-and-Disassembler/?arch=arm64&endianness=big&dis_with_raw=True&dis_with_ins=True) in the above code block ]
|
||||
|
||||
### Required by:
|
||||
[ Add our (games list database)[https://github.com/Ryujinx/Ryujinx-Games-List/issues] links of games who require this instruction ]
|
31
.github/ISSUE_TEMPLATE/missing_cpu_instruction.yml
vendored
Normal file
31
.github/ISSUE_TEMPLATE/missing_cpu_instruction.yml
vendored
Normal file
@ -0,0 +1,31 @@
|
||||
name: Missing CPU Instruction
|
||||
description: CPU Instruction is missing in Ryujinx.
|
||||
body:
|
||||
- type: checkboxes
|
||||
attributes:
|
||||
label: Is there an existing issue for this?
|
||||
description: Please search for existing missing CPU instruction
|
||||
options:
|
||||
- label: I have searched the existing issues
|
||||
required: true
|
||||
- type: textarea
|
||||
id: instruction
|
||||
attributes:
|
||||
label: CPU instruction
|
||||
description: What CPU instruction is missing?
|
||||
validations:
|
||||
required: true
|
||||
- type: textarea
|
||||
id: name
|
||||
attributes:
|
||||
label: Instruction name
|
||||
description: Include the name from [armconverter.com](https://armconverter.com/?disasm) or [shell-storm.org](http://shell-storm.org/online/Online-Assembler-and-Disassembler/?arch=arm64&endianness=big&dis_with_raw=True&dis_with_ins=True) in the above code block
|
||||
validations:
|
||||
required: true
|
||||
- type: textarea
|
||||
id: required
|
||||
attributes:
|
||||
label: Required by
|
||||
description: Add links to the [compatibility list page(s)](https://github.com/Ryujinx/Ryujinx-Games-List/issues) of the game(s) that require this instruction.
|
||||
validations:
|
||||
required: true
|
35
.github/ISSUE_TEMPLATE/missing_service_call.md
vendored
35
.github/ISSUE_TEMPLATE/missing_service_call.md
vendored
@ -1,35 +0,0 @@
|
||||
---
|
||||
name: Missing Service Call
|
||||
about: Service call is missing in Ryujinx.
|
||||
#assignees:
|
||||
---
|
||||
|
||||
## Missing Service Call
|
||||
|
||||
[ If any section does not apply, replace its contents with "N/A". ]</br>
|
||||
[ If you do not have the information needed for a section, replace its contents with "Unknown". ]</br>
|
||||
[ Lines between [ ] (square brackets) are to be removed before posting. ]
|
||||
|
||||
[ Please search for existing [missing service call](https://github.com/Ryujinx/Ryujinx/issues) before you make your own issue. ]</br>
|
||||
[ See the following [issue](https://github.com/Ryujinx/Ryujinx/issues/1431) as an example ]</br>
|
||||
[ Duplicate issue will be marked as such and you will be referred to the original request. ]
|
||||
|
||||
### What service call is missing?
|
||||
|
||||
*SERVICE* *INTERFACE*: *NUMBER* (*NAME*) is not implemented.</br>
|
||||
[ Replace *SERVICE* by the service name, e.g. appletAE ]</br>
|
||||
[ Replace *INTERFACE* by the interface name, e.g. IAllSystemAppletProxiesService ]</br>
|
||||
[ Replace *NUMBER* by the call number, e.g. 100 ]</br>
|
||||
[ Replace *NAME* by the call name, e.g. OpenSystemAppletProxy ]</br>
|
||||
[ e.g. appletAE IAllSystemAppletProxiesService: 100 (OpenSystemAppletProxy) ]
|
||||
|
||||
[ Add related links to the specific call from [Switchbrew](https://switchbrew.org/w/index.php?title=Services_API) and/or [SwIPC](https://reswitched.github.io/SwIPC/) ]
|
||||
|
||||
### Service description
|
||||
```
|
||||
*
|
||||
```
|
||||
[ Include the description/explanation from [Switchbrew](https://switchbrew.org/w/index.php?title=Services_API) and/or [SwIPC](https://reswitched.github.io/SwIPC/) in the above code block ]
|
||||
|
||||
### Required by:
|
||||
[ Add our (games list database)[https://github.com/Ryujinx/Ryujinx-Games-List/issues] links of games who require this call ]
|
31
.github/ISSUE_TEMPLATE/missing_service_call.yml
vendored
Normal file
31
.github/ISSUE_TEMPLATE/missing_service_call.yml
vendored
Normal file
@ -0,0 +1,31 @@
|
||||
name: Missing Service Call
|
||||
description: Service call is missing in Ryujinx.
|
||||
body:
|
||||
- type: checkboxes
|
||||
attributes:
|
||||
label: Is there an existing issue for this?
|
||||
description: Please search for an [existing missing service call issue](https://github.com/Ryujinx/Ryujinx/issues) first.
|
||||
options:
|
||||
- label: I have searched the existing issues
|
||||
required: true
|
||||
- type: textarea
|
||||
id: instruction
|
||||
attributes:
|
||||
label: Service Call
|
||||
description: What service call is missing?
|
||||
validations:
|
||||
required: true
|
||||
- type: textarea
|
||||
id: name
|
||||
attributes:
|
||||
label: Service description
|
||||
description: Include the description/explanation from [Switchbrew](https://switchbrew.org/w/index.php?title=Services_API) and/or [SwIPC](https://reswitched.github.io/SwIPC/) in the above code block
|
||||
validations:
|
||||
required: true
|
||||
- type: textarea
|
||||
id: required
|
||||
attributes:
|
||||
label: Required by
|
||||
description: Add links to the [compatibility list page(s)](https://github.com/Ryujinx/Ryujinx-Games-List/issues) of the game(s) that require this service.
|
||||
validations:
|
||||
required: true
|
@ -48,9 +48,21 @@ namespace ARMeilleure.CodeGen
|
||||
/// <returns>A delegate of type <typeparamref name="T"/> pointing to the mapped function</returns>
|
||||
public T Map<T>()
|
||||
{
|
||||
IntPtr codePtr = JitCache.Map(this);
|
||||
return MapWithPointer<T>(out _);
|
||||
}
|
||||
|
||||
return Marshal.GetDelegateForFunctionPointer<T>(codePtr);
|
||||
/// <summary>
|
||||
/// Maps the <see cref="CompiledFunction"/> onto the <see cref="JitCache"/> and returns a delegate of type
|
||||
/// <typeparamref name="T"/> pointing to the mapped function.
|
||||
/// </summary>
|
||||
/// <typeparam name="T">Type of delegate</typeparam>
|
||||
/// <param name="codePointer">Pointer to the function code in memory</param>
|
||||
/// <returns>A delegate of type <typeparamref name="T"/> pointing to the mapped function</returns>
|
||||
public T MapWithPointer<T>(out IntPtr codePointer)
|
||||
{
|
||||
codePointer = JitCache.Map(this);
|
||||
|
||||
return Marshal.GetDelegateForFunctionPointer<T>(codePointer);
|
||||
}
|
||||
}
|
||||
}
|
@ -191,7 +191,7 @@ namespace ARMeilleure.Instructions
|
||||
{
|
||||
TranslatedFunction function = Context.Translator.GetOrTranslate(address, GetContext().ExecutionMode);
|
||||
|
||||
return (ulong)function.FuncPtr.ToInt64();
|
||||
return (ulong)function.FuncPointer.ToInt64();
|
||||
}
|
||||
|
||||
public static void InvalidateCacheLine(ulong address)
|
||||
|
@ -745,9 +745,9 @@ namespace ARMeilleure.Translation.PTC
|
||||
bool highCq)
|
||||
{
|
||||
var cFunc = new CompiledFunction(code, unwindInfo, RelocInfo.Empty);
|
||||
var gFunc = cFunc.Map<GuestFunction>();
|
||||
var gFunc = cFunc.MapWithPointer<GuestFunction>(out IntPtr gFuncPointer);
|
||||
|
||||
return new TranslatedFunction(gFunc, callCounter, guestSize, highCq);
|
||||
return new TranslatedFunction(gFunc, gFuncPointer, callCounter, guestSize, highCq);
|
||||
}
|
||||
|
||||
private void UpdateInfo(InfoEntry infoEntry)
|
||||
|
@ -1,6 +1,5 @@
|
||||
using ARMeilleure.Common;
|
||||
using System;
|
||||
using System.Runtime.InteropServices;
|
||||
|
||||
namespace ARMeilleure.Translation
|
||||
{
|
||||
@ -8,18 +7,18 @@ namespace ARMeilleure.Translation
|
||||
{
|
||||
private readonly GuestFunction _func; // Ensure that this delegate will not be garbage collected.
|
||||
|
||||
public IntPtr FuncPointer { get; }
|
||||
public Counter<uint> CallCounter { get; }
|
||||
public ulong GuestSize { get; }
|
||||
public bool HighCq { get; }
|
||||
public IntPtr FuncPtr { get; }
|
||||
|
||||
public TranslatedFunction(GuestFunction func, Counter<uint> callCounter, ulong guestSize, bool highCq)
|
||||
public TranslatedFunction(GuestFunction func, IntPtr funcPointer, Counter<uint> callCounter, ulong guestSize, bool highCq)
|
||||
{
|
||||
_func = func;
|
||||
FuncPointer = funcPointer;
|
||||
CallCounter = callCounter;
|
||||
GuestSize = guestSize;
|
||||
HighCq = highCq;
|
||||
FuncPtr = Marshal.GetFunctionPointerForDelegate(func);
|
||||
}
|
||||
|
||||
public ulong Execute(State.ExecutionContext context)
|
||||
|
@ -211,7 +211,7 @@ namespace ARMeilleure.Translation
|
||||
|
||||
if (oldFunc != func)
|
||||
{
|
||||
JitCache.Unmap(func.FuncPtr);
|
||||
JitCache.Unmap(func.FuncPointer);
|
||||
func = oldFunc;
|
||||
}
|
||||
|
||||
@ -230,7 +230,7 @@ namespace ARMeilleure.Translation
|
||||
{
|
||||
if (FunctionTable.IsValid(guestAddress) && (Optimizations.AllowLcqInFunctionTable || func.HighCq))
|
||||
{
|
||||
Volatile.Write(ref FunctionTable.GetValue(guestAddress), (ulong)func.FuncPtr);
|
||||
Volatile.Write(ref FunctionTable.GetValue(guestAddress), (ulong)func.FuncPointer);
|
||||
}
|
||||
}
|
||||
|
||||
@ -292,11 +292,11 @@ namespace ARMeilleure.Translation
|
||||
_ptc.WriteCompiledFunction(address, funcSize, hash, highCq, compiledFunc);
|
||||
}
|
||||
|
||||
GuestFunction func = compiledFunc.Map<GuestFunction>();
|
||||
GuestFunction func = compiledFunc.MapWithPointer<GuestFunction>(out IntPtr funcPointer);
|
||||
|
||||
Allocators.ResetAll();
|
||||
|
||||
return new TranslatedFunction(func, counter, funcSize, highCq);
|
||||
return new TranslatedFunction(func, funcPointer, counter, funcSize, highCq);
|
||||
}
|
||||
|
||||
private void BackgroundTranslate()
|
||||
@ -537,7 +537,7 @@ namespace ARMeilleure.Translation
|
||||
|
||||
foreach (var func in functions)
|
||||
{
|
||||
JitCache.Unmap(func.FuncPtr);
|
||||
JitCache.Unmap(func.FuncPointer);
|
||||
|
||||
func.CallCounter?.Dispose();
|
||||
}
|
||||
@ -546,7 +546,7 @@ namespace ARMeilleure.Translation
|
||||
|
||||
while (_oldFuncs.TryDequeue(out var kv))
|
||||
{
|
||||
JitCache.Unmap(kv.Value.FuncPtr);
|
||||
JitCache.Unmap(kv.Value.FuncPointer);
|
||||
|
||||
kv.Value.CallCounter?.Dispose();
|
||||
}
|
||||
|
@ -36,7 +36,7 @@
|
||||
<PackageVersion Include="Ryujinx.GtkSharp" Version="3.24.24.59-ryujinx" />
|
||||
<PackageVersion Include="Ryujinx.SDL2-CS" Version="2.26.1-build23" />
|
||||
<PackageVersion Include="shaderc.net" Version="0.1.0" />
|
||||
<PackageVersion Include="SharpZipLib" Version="1.4.1" />
|
||||
<PackageVersion Include="SharpZipLib" Version="1.4.2" />
|
||||
<PackageVersion Include="Silk.NET.Vulkan" Version="2.16.0" />
|
||||
<PackageVersion Include="Silk.NET.Vulkan.Extensions.EXT" Version="2.16.0" />
|
||||
<PackageVersion Include="Silk.NET.Vulkan.Extensions.KHR" Version="2.16.0" />
|
||||
|
@ -241,7 +241,7 @@ namespace Ryujinx.Ava
|
||||
{
|
||||
DateTime currentTime = DateTime.Now;
|
||||
string filename = $"ryujinx_capture_{currentTime.Year}-{currentTime.Month:D2}-{currentTime.Day:D2}_{currentTime.Hour:D2}-{currentTime.Minute:D2}-{currentTime.Second:D2}.png";
|
||||
|
||||
|
||||
string directory = AppDataManager.Mode switch
|
||||
{
|
||||
AppDataManager.LaunchMode.Portable => Path.Combine(AppDataManager.BaseDirPath, "screenshots"),
|
||||
@ -678,7 +678,8 @@ namespace Ryujinx.Ava
|
||||
ConfigurationState.Instance.System.MemoryManagerMode,
|
||||
ConfigurationState.Instance.System.IgnoreMissingServices,
|
||||
ConfigurationState.Instance.Graphics.AspectRatio,
|
||||
ConfigurationState.Instance.System.AudioVolume);
|
||||
ConfigurationState.Instance.System.AudioVolume,
|
||||
ConfigurationState.Instance.System.UseHypervisor);
|
||||
|
||||
Device = new Switch(configuration);
|
||||
}
|
||||
@ -839,7 +840,7 @@ namespace Ryujinx.Ava
|
||||
{
|
||||
// Run a status update only when a frame is to be drawn. This prevents from updating the ui and wasting a render when no frame is queued.
|
||||
string dockedMode = ConfigurationState.Instance.System.EnableDockedMode ? LocaleManager.Instance[LocaleKeys.Docked] : LocaleManager.Instance[LocaleKeys.Handheld];
|
||||
|
||||
|
||||
if (GraphicsConfig.ResScale != 1)
|
||||
{
|
||||
dockedMode += $" ({GraphicsConfig.ResScale}x)";
|
||||
|
@ -7,6 +7,7 @@
|
||||
"SettingsTabSystemMemoryManagerModeSoftware": "Software",
|
||||
"SettingsTabSystemMemoryManagerModeHost": "Host (fast)",
|
||||
"SettingsTabSystemMemoryManagerModeHostUnchecked": "Host Unchecked (fastest, unsafe)",
|
||||
"SettingsTabSystemUseHypervisor": "Use Hypervisor",
|
||||
"MenuBarFile": "_File",
|
||||
"MenuBarFileOpenFromFile": "_Load Application From File",
|
||||
"MenuBarFileOpenUnpacked": "Load _Unpacked Game",
|
||||
@ -457,6 +458,7 @@
|
||||
"MemoryManagerSoftwareTooltip": "Use a software page table for address translation. Highest accuracy but slowest performance.",
|
||||
"MemoryManagerHostTooltip": "Directly map memory in the host address space. Much faster JIT compilation and execution.",
|
||||
"MemoryManagerUnsafeTooltip": "Directly map memory, but do not mask the address within the guest address space before access. Faster, but at the cost of safety. The guest application can access memory from anywhere in Ryujinx, so only run programs you trust with this mode.",
|
||||
"UseHypervisorTooltip": "Use Hypervisor instead of JIT. Greatly improves performance when available, but can be unstable in its current state.",
|
||||
"DRamTooltip": "Utilizes an alternative MemoryMode layout to mimic a Switch development model.\n\nThis is only useful for higher-resolution texture packs or 4k resolution mods. Does NOT improve performance.\n\nLeave OFF if unsure.",
|
||||
"IgnoreMissingServicesTooltip": "Ignores unimplemented Horizon OS services. This may help in bypassing crashes when booting certain games.\n\nLeave OFF if unsure.",
|
||||
"GraphicsBackendThreadingTooltip": "Executes graphics backend commands on a second thread.\n\nSpeeds up shader compilation, reduces stuttering, and improves performance on GPU drivers without multithreading support of their own. Slightly better performance on drivers with multithreading.\n\nSet to AUTO if unsure.",
|
||||
@ -507,7 +509,7 @@
|
||||
"SettingsTabNetwork": "Network",
|
||||
"SettingsTabNetworkConnection": "Network Connection",
|
||||
"SettingsTabCpuCache": "CPU Cache",
|
||||
"SettingsTabCpuMemory": "CPU Memory",
|
||||
"SettingsTabCpuMemory": "CPU Mode",
|
||||
"DialogUpdaterFlatpakNotSupportedMessage": "Please update Ryujinx via FlatHub.",
|
||||
"UpdaterDisabledWarningTitle": "Updater Disabled!",
|
||||
"GameListContextMenuOpenSdModsDirectory": "Open Atmosphere Mods Directory",
|
||||
|
@ -1,4 +1,4 @@
|
||||
<Project Sdk="Microsoft.NET.Sdk">
|
||||
<Project Sdk="Microsoft.NET.Sdk">
|
||||
<PropertyGroup>
|
||||
<TargetFramework>net7.0</TargetFramework>
|
||||
<RuntimeIdentifiers>win10-x64;osx-x64;linux-x64</RuntimeIdentifiers>
|
||||
@ -6,11 +6,16 @@
|
||||
<AllowUnsafeBlocks>true</AllowUnsafeBlocks>
|
||||
<Version>1.0.0-dirty</Version>
|
||||
<DefineConstants Condition=" '$(ExtraDefineConstants)' != '' ">$(DefineConstants);$(ExtraDefineConstants)</DefineConstants>
|
||||
<SigningCertificate Condition=" '$(SigningCertificate)' == '' ">-</SigningCertificate>
|
||||
<RootNamespace>Ryujinx.Ava</RootNamespace>
|
||||
<ApplicationIcon>Ryujinx.ico</ApplicationIcon>
|
||||
<TieredPGO>true</TieredPGO>
|
||||
</PropertyGroup>
|
||||
|
||||
<Target Name="PostBuild" AfterTargets="PostBuildEvent" Condition="$([MSBuild]::IsOSPlatform('OSX'))">
|
||||
<Exec Command="codesign --entitlements $(ProjectDir)..\distribution\macos\entitlements.xml -f --deep -s $(SigningCertificate) $(TargetDir)$(TargetName)" />
|
||||
</Target>
|
||||
|
||||
<PropertyGroup Condition="'$(RuntimeIdentifier)' != ''">
|
||||
<PublishSingleFile>true</PublishSingleFile>
|
||||
<PublishTrimmed>true</PublishTrimmed>
|
||||
|
@ -22,6 +22,7 @@ using System;
|
||||
using System.Collections.Generic;
|
||||
using System.Collections.ObjectModel;
|
||||
using System.Linq;
|
||||
using System.Runtime.InteropServices;
|
||||
using TimeZone = Ryujinx.Ava.UI.Models.TimeZone;
|
||||
|
||||
namespace Ryujinx.Ava.UI.ViewModels
|
||||
@ -59,6 +60,7 @@ namespace Ryujinx.Ava.UI.ViewModels
|
||||
OnPropertyChanged(nameof(IsCustomResolutionScaleActive));
|
||||
}
|
||||
}
|
||||
|
||||
public int GraphicsBackendMultithreadingIndex
|
||||
{
|
||||
get => _graphicsBackendMultithreadingIndex;
|
||||
@ -106,6 +108,8 @@ namespace Ryujinx.Ava.UI.ViewModels
|
||||
|
||||
public bool IsOpenGLAvailable => !OperatingSystem.IsMacOS();
|
||||
|
||||
public bool IsHypervisorAvailable => OperatingSystem.IsMacOS() && RuntimeInformation.ProcessArchitecture == Architecture.Arm64;
|
||||
|
||||
public bool DirectoryChanged
|
||||
{
|
||||
get => _directoryChanged;
|
||||
@ -117,10 +121,7 @@ namespace Ryujinx.Ava.UI.ViewModels
|
||||
}
|
||||
}
|
||||
|
||||
public bool IsMacOS
|
||||
{
|
||||
get => OperatingSystem.IsMacOS();
|
||||
}
|
||||
public bool IsMacOS => OperatingSystem.IsMacOS();
|
||||
|
||||
public bool EnableDiscordIntegration { get; set; }
|
||||
public bool CheckUpdatesOnStart { get; set; }
|
||||
@ -153,6 +154,7 @@ namespace Ryujinx.Ava.UI.ViewModels
|
||||
public bool EnableCustomTheme { get; set; }
|
||||
public bool IsCustomResolutionScaleActive => _resolutionScale == 4;
|
||||
public bool IsVulkanSelected => GraphicsBackendIndex == 0;
|
||||
public bool UseHypervisor { get; set; }
|
||||
|
||||
public string TimeZone { get; set; }
|
||||
public string ShaderDumpPath { get; set; }
|
||||
@ -349,6 +351,7 @@ namespace Ryujinx.Ava.UI.ViewModels
|
||||
// CPU
|
||||
EnablePptc = config.System.EnablePtc;
|
||||
MemoryMode = (int)config.System.MemoryManagerMode.Value;
|
||||
UseHypervisor = config.System.UseHypervisor;
|
||||
|
||||
// Graphics
|
||||
GraphicsBackendIndex = (int)config.Graphics.GraphicsBackend.Value;
|
||||
@ -369,7 +372,7 @@ namespace Ryujinx.Ava.UI.ViewModels
|
||||
|
||||
// Network
|
||||
EnableInternetAccess = config.System.EnableInternetAccess;
|
||||
|
||||
|
||||
// Logging
|
||||
EnableFileLog = config.Logger.EnableFileLog;
|
||||
EnableStub = config.Logger.EnableStub;
|
||||
@ -432,6 +435,7 @@ namespace Ryujinx.Ava.UI.ViewModels
|
||||
// CPU
|
||||
config.System.EnablePtc.Value = EnablePptc;
|
||||
config.System.MemoryManagerMode.Value = (MemoryManagerMode)MemoryMode;
|
||||
config.System.UseHypervisor.Value = UseHypervisor;
|
||||
|
||||
// Graphics
|
||||
config.Graphics.GraphicsBackend.Value = (GraphicsBackend)GraphicsBackendIndex;
|
||||
|
@ -1,4 +1,4 @@
|
||||
<UserControl
|
||||
<UserControl
|
||||
x:Class="Ryujinx.Ava.UI.Views.Settings.SettingsCPUView"
|
||||
xmlns="https://github.com/avaloniaui"
|
||||
xmlns:x="http://schemas.microsoft.com/winfx/2006/xaml"
|
||||
@ -65,8 +65,14 @@
|
||||
</ComboBoxItem>
|
||||
</ComboBox>
|
||||
</StackPanel>
|
||||
<CheckBox IsChecked="{Binding UseHypervisor}"
|
||||
IsVisible="{Binding IsHypervisorAvailable}"
|
||||
ToolTip.Tip="{locale:Locale UseHypervisorTooltip}">
|
||||
<TextBlock Text="{locale:Locale SettingsTabSystemUseHypervisor}"
|
||||
ToolTip.Tip="{locale:Locale UseHypervisorTooltip}" />
|
||||
</CheckBox>
|
||||
</StackPanel>
|
||||
</StackPanel>
|
||||
</Border>
|
||||
</ScrollViewer>
|
||||
</UserControl>
|
||||
</UserControl>
|
||||
|
27
Ryujinx.Cpu/AppleHv/Arm/ApFlags.cs
Normal file
27
Ryujinx.Cpu/AppleHv/Arm/ApFlags.cs
Normal file
@ -0,0 +1,27 @@
|
||||
namespace Ryujinx.Cpu.AppleHv.Arm
|
||||
{
|
||||
enum ApFlags : ulong
|
||||
{
|
||||
ApShift = 6,
|
||||
PxnShift = 53,
|
||||
UxnShift = 54,
|
||||
|
||||
UserExecuteKernelReadWriteExecute = (0UL << (int)ApShift),
|
||||
UserReadWriteExecuteKernelReadWrite = (1UL << (int)ApShift),
|
||||
UserExecuteKernelReadExecute = (2UL << (int)ApShift),
|
||||
UserReadExecuteKernelReadExecute = (3UL << (int)ApShift),
|
||||
|
||||
UserExecuteKernelReadWrite = (1UL << (int)PxnShift) | (0UL << (int)ApShift),
|
||||
UserExecuteKernelRead = (1UL << (int)PxnShift) | (2UL << (int)ApShift),
|
||||
UserReadExecuteKernelRead = (1UL << (int)PxnShift) | (3UL << (int)ApShift),
|
||||
|
||||
UserNoneKernelReadWriteExecute = (1UL << (int)UxnShift) | (0UL << (int)ApShift),
|
||||
UserReadWriteKernelReadWrite = (1UL << (int)UxnShift) | (1UL << (int)ApShift),
|
||||
UserNoneKernelReadExecute = (1UL << (int)UxnShift) | (2UL << (int)ApShift),
|
||||
UserReadKernelReadExecute = (1UL << (int)UxnShift) | (3UL << (int)ApShift),
|
||||
|
||||
UserNoneKernelReadWrite = (1UL << (int)PxnShift) | (1UL << (int)UxnShift) | (0UL << (int)ApShift),
|
||||
UserNoneKernelRead = (1UL << (int)PxnShift) | (1UL << (int)UxnShift) | (2UL << (int)ApShift),
|
||||
UserReadKernelRead = (1UL << (int)PxnShift) | (1UL << (int)UxnShift) | (3UL << (int)ApShift)
|
||||
}
|
||||
}
|
47
Ryujinx.Cpu/AppleHv/Arm/ExceptionClass.cs
Normal file
47
Ryujinx.Cpu/AppleHv/Arm/ExceptionClass.cs
Normal file
@ -0,0 +1,47 @@
|
||||
namespace Ryujinx.Cpu.AppleHv.Arm
|
||||
{
|
||||
enum ExceptionClass
|
||||
{
|
||||
Unknown = 0b000000,
|
||||
TrappedWfeWfiWfetWfit = 0b000001,
|
||||
TrappedMcrMrcCp15 = 0b000011,
|
||||
TrappedMcrrMrrcCp15 = 0b000100,
|
||||
TrappedMcrMrcCp14 = 0b000101,
|
||||
TrappedLdcStc = 0b000110,
|
||||
TrappedSveFpSimd = 0b000111,
|
||||
TrappedVmrs = 0b001000,
|
||||
TrappedPAuth = 0b001001,
|
||||
TrappedLd64bSt64bSt64bvSt64bv0 = 0b001010,
|
||||
TrappedMrrcCp14 = 0b001100,
|
||||
IllegalExecutionState = 0b001110,
|
||||
SvcAarch32 = 0b010001,
|
||||
HvcAarch32 = 0b010010,
|
||||
SmcAarch32 = 0b010011,
|
||||
SvcAarch64 = 0b010101,
|
||||
HvcAarch64 = 0b010110,
|
||||
SmcAarch64 = 0b010111,
|
||||
TrappedMsrMrsSystem = 0b011000,
|
||||
TrappedSve = 0b011001,
|
||||
TrappedEretEretaaEretab = 0b011010,
|
||||
PointerAuthenticationFailure = 0b011100,
|
||||
ImplementationDefinedEl3 = 0b011111,
|
||||
InstructionAbortLowerEl = 0b100000,
|
||||
InstructionAbortSameEl = 0b100001,
|
||||
PcAlignmentFault = 0b100010,
|
||||
DataAbortLowerEl = 0b100100,
|
||||
DataAbortSameEl = 0b100101,
|
||||
SpAlignmentFault = 0b100110,
|
||||
TrappedFpExceptionAarch32 = 0b101000,
|
||||
TrappedFpExceptionAarch64 = 0b101100,
|
||||
SErrorInterrupt = 0b101111,
|
||||
BreakpointLowerEl = 0b110000,
|
||||
BreakpointSameEl = 0b110001,
|
||||
SoftwareStepLowerEl = 0b110010,
|
||||
SoftwareStepSameEl = 0b110011,
|
||||
WatchpointLowerEl = 0b110100,
|
||||
WatchpointSameEl = 0b110101,
|
||||
BkptAarch32 = 0b111000,
|
||||
VectorCatchAarch32 = 0b111010,
|
||||
BrkAarch64 = 0b111100
|
||||
}
|
||||
}
|
17
Ryujinx.Cpu/AppleHv/DummyDiskCacheLoadState.cs
Normal file
17
Ryujinx.Cpu/AppleHv/DummyDiskCacheLoadState.cs
Normal file
@ -0,0 +1,17 @@
|
||||
using System;
|
||||
|
||||
namespace Ryujinx.Cpu.AppleHv
|
||||
{
|
||||
public class DummyDiskCacheLoadState : IDiskCacheLoadState
|
||||
{
|
||||
#pragma warning disable CS0067
|
||||
/// <inheritdoc/>
|
||||
public event Action<LoadState, int, int> StateChanged;
|
||||
#pragma warning restore CS0067
|
||||
|
||||
/// <inheritdoc/>
|
||||
public void Cancel()
|
||||
{
|
||||
}
|
||||
}
|
||||
}
|
129
Ryujinx.Cpu/AppleHv/HvAddressSpace.cs
Normal file
129
Ryujinx.Cpu/AppleHv/HvAddressSpace.cs
Normal file
@ -0,0 +1,129 @@
|
||||
using Ryujinx.Cpu.AppleHv.Arm;
|
||||
using Ryujinx.Memory;
|
||||
using System;
|
||||
|
||||
namespace Ryujinx.Cpu.AppleHv
|
||||
{
|
||||
class HvAddressSpace : IDisposable
|
||||
{
|
||||
private const ulong KernelRegionBase = unchecked((ulong)-(1L << 39));
|
||||
private const ulong KernelRegionCodeOffset = 0UL;
|
||||
private const ulong KernelRegionCodeSize = 0x2000UL;
|
||||
private const ulong KernelRegionTlbiEretOffset = KernelRegionCodeOffset + 0x1000UL;
|
||||
private const ulong KernelRegionEretOffset = KernelRegionTlbiEretOffset + 4UL;
|
||||
|
||||
public const ulong KernelRegionEretAddress = KernelRegionBase + KernelRegionEretOffset;
|
||||
public const ulong KernelRegionTlbiEretAddress = KernelRegionBase + KernelRegionTlbiEretOffset;
|
||||
|
||||
private const ulong AllocationGranule = 1UL << 14;
|
||||
|
||||
private readonly ulong _asBase;
|
||||
private readonly ulong _asSize;
|
||||
private readonly ulong _backingSize;
|
||||
|
||||
private readonly HvAddressSpaceRange _userRange;
|
||||
private readonly HvAddressSpaceRange _kernelRange;
|
||||
|
||||
private MemoryBlock _kernelCodeBlock;
|
||||
|
||||
public HvAddressSpace(MemoryBlock backingMemory, ulong asSize)
|
||||
{
|
||||
(_asBase, var ipaAllocator) = HvVm.CreateAddressSpace(backingMemory);
|
||||
_asSize = asSize;
|
||||
_backingSize = backingMemory.Size;
|
||||
|
||||
_userRange = new HvAddressSpaceRange(ipaAllocator);
|
||||
_kernelRange = new HvAddressSpaceRange(ipaAllocator);
|
||||
|
||||
_kernelCodeBlock = new MemoryBlock(AllocationGranule);
|
||||
|
||||
InitializeKernelCode(ipaAllocator);
|
||||
}
|
||||
|
||||
private void InitializeKernelCode(HvIpaAllocator ipaAllocator)
|
||||
{
|
||||
// Write exception handlers.
|
||||
for (ulong offset = 0; offset < 0x800; offset += 0x80)
|
||||
{
|
||||
// Offsets:
|
||||
// 0x0: Synchronous
|
||||
// 0x80: IRQ
|
||||
// 0x100: FIQ
|
||||
// 0x180: SError
|
||||
_kernelCodeBlock.Write(KernelRegionCodeOffset + offset, 0xD41FFFE2u); // HVC #0xFFFF
|
||||
_kernelCodeBlock.Write(KernelRegionCodeOffset + offset + 4, 0xD69F03E0u); // ERET
|
||||
}
|
||||
|
||||
_kernelCodeBlock.Write(KernelRegionTlbiEretOffset, 0xD508831Fu); // TLBI VMALLE1IS
|
||||
_kernelCodeBlock.Write(KernelRegionEretOffset, 0xD69F03E0u); // ERET
|
||||
|
||||
ulong kernelCodePa = ipaAllocator.Allocate(AllocationGranule);
|
||||
HvApi.hv_vm_map((ulong)_kernelCodeBlock.Pointer, kernelCodePa, AllocationGranule, hv_memory_flags_t.HV_MEMORY_READ | hv_memory_flags_t.HV_MEMORY_EXEC).ThrowOnError();
|
||||
|
||||
_kernelRange.Map(KernelRegionCodeOffset, kernelCodePa, KernelRegionCodeSize, ApFlags.UserNoneKernelReadExecute);
|
||||
}
|
||||
|
||||
public void InitializeMmu(ulong vcpu)
|
||||
{
|
||||
HvApi.hv_vcpu_set_sys_reg(vcpu, hv_sys_reg_t.HV_SYS_REG_VBAR_EL1, KernelRegionBase + KernelRegionCodeOffset);
|
||||
|
||||
HvApi.hv_vcpu_set_sys_reg(vcpu, hv_sys_reg_t.HV_SYS_REG_TTBR0_EL1, _userRange.GetIpaBase());
|
||||
HvApi.hv_vcpu_set_sys_reg(vcpu, hv_sys_reg_t.HV_SYS_REG_TTBR1_EL1, _kernelRange.GetIpaBase());
|
||||
HvApi.hv_vcpu_set_sys_reg(vcpu, hv_sys_reg_t.HV_SYS_REG_MAIR_EL1, 0xffUL);
|
||||
HvApi.hv_vcpu_set_sys_reg(vcpu, hv_sys_reg_t.HV_SYS_REG_TCR_EL1, 0x00000011B5193519UL);
|
||||
HvApi.hv_vcpu_set_sys_reg(vcpu, hv_sys_reg_t.HV_SYS_REG_SCTLR_EL1, 0x0000000034D5D925UL);
|
||||
}
|
||||
|
||||
public bool GetAndClearUserTlbInvalidationPending()
|
||||
{
|
||||
return _userRange.GetAndClearTlbInvalidationPending();
|
||||
}
|
||||
|
||||
public void MapUser(ulong va, ulong pa, ulong size, MemoryPermission permission)
|
||||
{
|
||||
pa += _asBase;
|
||||
|
||||
lock (_userRange)
|
||||
{
|
||||
_userRange.Map(va, pa, size, GetApFlags(permission));
|
||||
}
|
||||
}
|
||||
|
||||
public void UnmapUser(ulong va, ulong size)
|
||||
{
|
||||
lock (_userRange)
|
||||
{
|
||||
_userRange.Unmap(va, size);
|
||||
}
|
||||
}
|
||||
|
||||
public void ReprotectUser(ulong va, ulong size, MemoryPermission permission)
|
||||
{
|
||||
lock (_userRange)
|
||||
{
|
||||
_userRange.Reprotect(va, size, GetApFlags(permission));
|
||||
}
|
||||
}
|
||||
|
||||
private static ApFlags GetApFlags(MemoryPermission permission)
|
||||
{
|
||||
return permission switch
|
||||
{
|
||||
MemoryPermission.None => ApFlags.UserNoneKernelRead,
|
||||
MemoryPermission.Execute => ApFlags.UserExecuteKernelRead,
|
||||
MemoryPermission.Read => ApFlags.UserReadKernelRead,
|
||||
MemoryPermission.ReadAndWrite => ApFlags.UserReadWriteKernelReadWrite,
|
||||
MemoryPermission.ReadAndExecute => ApFlags.UserReadExecuteKernelRead,
|
||||
MemoryPermission.ReadWriteExecute => ApFlags.UserReadWriteExecuteKernelReadWrite,
|
||||
_ => throw new ArgumentException($"Permission \"{permission}\" is invalid.")
|
||||
};
|
||||
}
|
||||
|
||||
public void Dispose()
|
||||
{
|
||||
_userRange.Dispose();
|
||||
_kernelRange.Dispose();
|
||||
HvVm.DestroyAddressSpace(_asBase, _backingSize);
|
||||
}
|
||||
}
|
||||
}
|
370
Ryujinx.Cpu/AppleHv/HvAddressSpaceRange.cs
Normal file
370
Ryujinx.Cpu/AppleHv/HvAddressSpaceRange.cs
Normal file
@ -0,0 +1,370 @@
|
||||
using Ryujinx.Cpu.AppleHv.Arm;
|
||||
using System;
|
||||
using System.Diagnostics;
|
||||
using System.Runtime.InteropServices;
|
||||
using System.Threading;
|
||||
|
||||
namespace Ryujinx.Cpu.AppleHv
|
||||
{
|
||||
class HvAddressSpaceRange : IDisposable
|
||||
{
|
||||
private const ulong AllocationGranule = 1UL << 14;
|
||||
|
||||
private const ulong AttributesMask = (0x3ffUL << 2) | (0x3fffUL << 50);
|
||||
|
||||
private const ulong BaseAttributes = (1UL << 10) | (3UL << 8); // Access flag set, inner shareable.
|
||||
|
||||
private const int LevelBits = 9;
|
||||
private const int LevelCount = 1 << LevelBits;
|
||||
private const int LevelMask = LevelCount - 1;
|
||||
private const int PageBits = 12;
|
||||
private const int PageSize = 1 << PageBits;
|
||||
private const int PageMask = PageSize - 1;
|
||||
private const int AllLevelsMask = PageMask | (LevelMask << PageBits) | (LevelMask << (PageBits + LevelBits));
|
||||
|
||||
private class PtLevel
|
||||
{
|
||||
public ulong Address => Allocation.Ipa + Allocation.Offset;
|
||||
public int EntriesCount;
|
||||
public readonly HvMemoryBlockAllocation Allocation;
|
||||
public readonly PtLevel[] Next;
|
||||
|
||||
public PtLevel(HvMemoryBlockAllocator blockAllocator, int count, bool hasNext)
|
||||
{
|
||||
ulong size = (ulong)count * sizeof(ulong);
|
||||
Allocation = blockAllocator.Allocate(size, PageSize);
|
||||
|
||||
AsSpan().Fill(0UL);
|
||||
|
||||
if (hasNext)
|
||||
{
|
||||
Next = new PtLevel[count];
|
||||
}
|
||||
}
|
||||
|
||||
public unsafe Span<ulong> AsSpan()
|
||||
{
|
||||
return MemoryMarshal.Cast<byte, ulong>(Allocation.Memory.GetSpan(Allocation.Offset, (int)Allocation.Size));
|
||||
}
|
||||
}
|
||||
|
||||
private PtLevel _level0;
|
||||
|
||||
private int _tlbInvalidationPending;
|
||||
|
||||
private readonly HvIpaAllocator _ipaAllocator;
|
||||
private readonly HvMemoryBlockAllocator _blockAllocator;
|
||||
|
||||
public HvAddressSpaceRange(HvIpaAllocator ipaAllocator)
|
||||
{
|
||||
_ipaAllocator = ipaAllocator;
|
||||
_blockAllocator = new HvMemoryBlockAllocator(ipaAllocator, (int)AllocationGranule);
|
||||
}
|
||||
|
||||
public ulong GetIpaBase()
|
||||
{
|
||||
return EnsureLevel0().Address;
|
||||
}
|
||||
|
||||
public bool GetAndClearTlbInvalidationPending()
|
||||
{
|
||||
return Interlocked.Exchange(ref _tlbInvalidationPending, 0) != 0;
|
||||
}
|
||||
|
||||
public void Map(ulong va, ulong pa, ulong size, ApFlags accessPermission)
|
||||
{
|
||||
MapImpl(va, pa, size, (ulong)accessPermission | BaseAttributes);
|
||||
}
|
||||
|
||||
public void Unmap(ulong va, ulong size)
|
||||
{
|
||||
UnmapImpl(EnsureLevel0(), 0, va, size);
|
||||
Interlocked.Exchange(ref _tlbInvalidationPending, 1);
|
||||
}
|
||||
|
||||
public void Reprotect(ulong va, ulong size, ApFlags accessPermission)
|
||||
{
|
||||
UpdateAttributes(va, size, (ulong)accessPermission | BaseAttributes);
|
||||
}
|
||||
|
||||
private void MapImpl(ulong va, ulong pa, ulong size, ulong attr)
|
||||
{
|
||||
PtLevel level0 = EnsureLevel0();
|
||||
|
||||
ulong endVa = va + size;
|
||||
|
||||
while (va < endVa)
|
||||
{
|
||||
(ulong mapSize, int depth) = GetMapSizeAndDepth(va, pa, endVa);
|
||||
|
||||
PtLevel currentLevel = level0;
|
||||
|
||||
for (int i = 0; i < depth; i++)
|
||||
{
|
||||
int l = (int)(va >> (PageBits + (2 - i) * LevelBits)) & LevelMask;
|
||||
EnsureTable(currentLevel, l, i == 0);
|
||||
currentLevel = currentLevel.Next[l];
|
||||
}
|
||||
|
||||
(ulong blockSize, int blockShift) = GetBlockSizeAndShift(depth);
|
||||
|
||||
for (ulong i = 0; i < mapSize; i += blockSize)
|
||||
{
|
||||
if ((va >> blockShift) << blockShift != va ||
|
||||
(pa >> blockShift) << blockShift != pa)
|
||||
{
|
||||
Debug.Fail($"Block size 0x{blockSize:X} (log2: {blockShift}) is invalid for VA 0x{va:X} or PA 0x{pa:X}.");
|
||||
}
|
||||
|
||||
WriteBlock(currentLevel, (int)(va >> blockShift) & LevelMask, depth, pa, attr);
|
||||
|
||||
va += blockSize;
|
||||
pa += blockSize;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
private void UnmapImpl(PtLevel level, int depth, ulong va, ulong size)
|
||||
{
|
||||
ulong endVa = (va + size + PageMask) & ~((ulong)PageMask);
|
||||
va &= ~((ulong)PageMask);
|
||||
|
||||
(ulong blockSize, int blockShift) = GetBlockSizeAndShift(depth);
|
||||
|
||||
while (va < endVa)
|
||||
{
|
||||
ulong nextEntryVa = GetNextAddress(va, blockSize);
|
||||
ulong chunckSize = Math.Min(endVa - va, nextEntryVa - va);
|
||||
|
||||
int l = (int)(va >> (PageBits + (2 - depth) * LevelBits)) & LevelMask;
|
||||
|
||||
PtLevel nextTable = level.Next != null ? level.Next[l] : null;
|
||||
|
||||
if (nextTable != null)
|
||||
{
|
||||
// Entry is a table, visit it and update attributes as required.
|
||||
UnmapImpl(nextTable, depth + 1, va, chunckSize);
|
||||
}
|
||||
else if (chunckSize != blockSize)
|
||||
{
|
||||
// Entry is a block but is not aligned, we need to turn it into a table.
|
||||
ref ulong pte = ref level.AsSpan()[l];
|
||||
nextTable = CreateTable(pte, depth + 1);
|
||||
level.Next[l] = nextTable;
|
||||
|
||||
// Now that we have a table, we can handle it like the first case.
|
||||
UnmapImpl(nextTable, depth + 1, va, chunckSize);
|
||||
|
||||
// Update PTE to point to the new table.
|
||||
pte = (nextTable.Address & ~(ulong)PageMask) | 3UL;
|
||||
}
|
||||
|
||||
// If entry is a block, or if entry is a table but it is empty, we can remove it.
|
||||
if (nextTable == null || nextTable.EntriesCount == 0)
|
||||
{
|
||||
// Entry is a block and is fully aligned, so we can just set it to 0.
|
||||
if (nextTable != null)
|
||||
{
|
||||
nextTable.Allocation.Dispose();
|
||||
level.Next[l] = null;
|
||||
}
|
||||
|
||||
level.AsSpan()[l] = 0UL;
|
||||
level.EntriesCount--;
|
||||
ValidateEntriesCount(level.EntriesCount);
|
||||
}
|
||||
|
||||
va += chunckSize;
|
||||
}
|
||||
}
|
||||
|
||||
private void UpdateAttributes(ulong va, ulong size, ulong newAttr)
|
||||
{
|
||||
UpdateAttributes(EnsureLevel0(), 0, va, size, newAttr);
|
||||
|
||||
Interlocked.Exchange(ref _tlbInvalidationPending, 1);
|
||||
}
|
||||
|
||||
private void UpdateAttributes(PtLevel level, int depth, ulong va, ulong size, ulong newAttr)
|
||||
{
|
||||
ulong endVa = (va + size + PageSize - 1) & ~((ulong)PageSize - 1);
|
||||
va &= ~((ulong)PageSize - 1);
|
||||
|
||||
(ulong blockSize, int blockShift) = GetBlockSizeAndShift(depth);
|
||||
|
||||
while (va < endVa)
|
||||
{
|
||||
ulong nextEntryVa = GetNextAddress(va, blockSize);
|
||||
ulong chunckSize = Math.Min(endVa - va, nextEntryVa - va);
|
||||
|
||||
int l = (int)(va >> (PageBits + (2 - depth) * LevelBits)) & LevelMask;
|
||||
|
||||
ref ulong pte = ref level.AsSpan()[l];
|
||||
|
||||
// First check if the region is mapped.
|
||||
if ((pte & 3) != 0)
|
||||
{
|
||||
PtLevel nextTable = level.Next != null ? level.Next[l] : null;
|
||||
|
||||
if (nextTable != null)
|
||||
{
|
||||
// Entry is a table, visit it and update attributes as required.
|
||||
UpdateAttributes(nextTable, depth + 1, va, chunckSize, newAttr);
|
||||
}
|
||||
else if (chunckSize != blockSize)
|
||||
{
|
||||
// Entry is a block but is not aligned, we need to turn it into a table.
|
||||
nextTable = CreateTable(pte, depth + 1);
|
||||
level.Next[l] = nextTable;
|
||||
|
||||
// Now that we have a table, we can handle it like the first case.
|
||||
UpdateAttributes(nextTable, depth + 1, va, chunckSize, newAttr);
|
||||
|
||||
// Update PTE to point to the new table.
|
||||
pte = (nextTable.Address & ~(ulong)PageMask) | 3UL;
|
||||
}
|
||||
else
|
||||
{
|
||||
// Entry is a block and is fully aligned, so we can just update the attributes.
|
||||
// Update PTE with the new attributes.
|
||||
pte = (pte & ~AttributesMask) | newAttr;
|
||||
}
|
||||
}
|
||||
|
||||
va += chunckSize;
|
||||
}
|
||||
}
|
||||
|
||||
private PtLevel CreateTable(ulong pte, int depth)
|
||||
{
|
||||
pte &= ~3UL;
|
||||
pte |= (depth == 2 ? 3UL : 1UL);
|
||||
|
||||
PtLevel level = new PtLevel(_blockAllocator, LevelCount, depth < 2);
|
||||
Span<ulong> currentLevel = level.AsSpan();
|
||||
|
||||
(ulong blockSize, int blockShift) = GetBlockSizeAndShift(depth);
|
||||
|
||||
// Fill in the blocks.
|
||||
for (int i = 0; i < LevelCount; i++)
|
||||
{
|
||||
ulong offset = (ulong)i << blockShift;
|
||||
currentLevel[i] = pte + offset;
|
||||
}
|
||||
|
||||
level.EntriesCount = LevelCount;
|
||||
|
||||
return level;
|
||||
}
|
||||
|
||||
private static (ulong, int) GetBlockSizeAndShift(int depth)
|
||||
{
|
||||
int blockShift = PageBits + (2 - depth) * LevelBits;
|
||||
ulong blockSize = 1UL << blockShift;
|
||||
|
||||
return (blockSize, blockShift);
|
||||
}
|
||||
|
||||
private static (ulong, int) GetMapSizeAndDepth(ulong va, ulong pa, ulong endVa)
|
||||
{
|
||||
// Both virtual and physical addresses must be aligned to the block size.
|
||||
ulong combinedAddress = va | pa;
|
||||
|
||||
ulong l0Alignment = 1UL << (PageBits + LevelBits * 2);
|
||||
ulong l1Alignment = 1UL << (PageBits + LevelBits);
|
||||
|
||||
if ((combinedAddress & (l0Alignment - 1)) == 0 && AlignDown(endVa, l0Alignment) > va)
|
||||
{
|
||||
return (AlignDown(endVa, l0Alignment) - va, 0);
|
||||
}
|
||||
else if ((combinedAddress & (l1Alignment - 1)) == 0 && AlignDown(endVa, l1Alignment) > va)
|
||||
{
|
||||
ulong nextOrderVa = GetNextAddress(va, l0Alignment);
|
||||
|
||||
if (nextOrderVa <= endVa)
|
||||
{
|
||||
return (nextOrderVa - va, 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
return (AlignDown(endVa, l1Alignment) - va, 1);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
ulong nextOrderVa = GetNextAddress(va, l1Alignment);
|
||||
|
||||
if (nextOrderVa <= endVa)
|
||||
{
|
||||
return (nextOrderVa - va, 2);
|
||||
}
|
||||
else
|
||||
{
|
||||
return (endVa - va, 2);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
private static ulong AlignDown(ulong va, ulong alignment)
|
||||
{
|
||||
return va & ~(alignment - 1);
|
||||
}
|
||||
|
||||
private static ulong GetNextAddress(ulong va, ulong alignment)
|
||||
{
|
||||
return (va + alignment) & ~(alignment - 1);
|
||||
}
|
||||
|
||||
private PtLevel EnsureLevel0()
|
||||
{
|
||||
PtLevel level0 = _level0;
|
||||
|
||||
if (level0 == null)
|
||||
{
|
||||
level0 = new PtLevel(_blockAllocator, LevelCount, true);
|
||||
_level0 = level0;
|
||||
}
|
||||
|
||||
return level0;
|
||||
}
|
||||
|
||||
private void EnsureTable(PtLevel level, int index, bool hasNext)
|
||||
{
|
||||
Span<ulong> currentTable = level.AsSpan();
|
||||
|
||||
if ((currentTable[index] & 1) == 0)
|
||||
{
|
||||
PtLevel nextLevel = new PtLevel(_blockAllocator, LevelCount, hasNext);
|
||||
|
||||
currentTable[index] = (nextLevel.Address & ~(ulong)PageMask) | 3UL;
|
||||
level.Next[index] = nextLevel;
|
||||
level.EntriesCount++;
|
||||
ValidateEntriesCount(level.EntriesCount);
|
||||
}
|
||||
else if (level.Next[index] == null)
|
||||
{
|
||||
Debug.Fail($"Index {index} is block, expected a table.");
|
||||
}
|
||||
}
|
||||
|
||||
private void WriteBlock(PtLevel level, int index, int depth, ulong pa, ulong attr)
|
||||
{
|
||||
Span<ulong> currentTable = level.AsSpan();
|
||||
|
||||
currentTable[index] = (pa & ~((ulong)AllLevelsMask >> (depth * LevelBits))) | (depth == 2 ? 3UL : 1UL) | attr;
|
||||
|
||||
level.EntriesCount++;
|
||||
ValidateEntriesCount(level.EntriesCount);
|
||||
}
|
||||
|
||||
private static void ValidateEntriesCount(int count)
|
||||
{
|
||||
Debug.Assert(count >= 0 && count <= LevelCount, $"Entries count {count} is invalid.");
|
||||
}
|
||||
|
||||
public void Dispose()
|
||||
{
|
||||
_blockAllocator.Dispose();
|
||||
}
|
||||
}
|
||||
}
|
320
Ryujinx.Cpu/AppleHv/HvApi.cs
Normal file
320
Ryujinx.Cpu/AppleHv/HvApi.cs
Normal file
@ -0,0 +1,320 @@
|
||||
using ARMeilleure.State;
|
||||
using System;
|
||||
using System.Runtime.InteropServices;
|
||||
|
||||
namespace Ryujinx.Cpu.AppleHv
|
||||
{
|
||||
struct hv_vcpu_exit_exception_t
|
||||
{
|
||||
#pragma warning disable CS0649
|
||||
public ulong syndrome;
|
||||
public ulong virtual_address;
|
||||
public ulong physical_address;
|
||||
#pragma warning restore CS0649
|
||||
}
|
||||
|
||||
struct hv_vcpu_exit_t
|
||||
{
|
||||
#pragma warning disable CS0649
|
||||
public uint reason;
|
||||
public hv_vcpu_exit_exception_t exception;
|
||||
#pragma warning restore CS0649
|
||||
}
|
||||
|
||||
enum hv_reg_t : uint
|
||||
{
|
||||
HV_REG_X0,
|
||||
HV_REG_X1,
|
||||
HV_REG_X2,
|
||||
HV_REG_X3,
|
||||
HV_REG_X4,
|
||||
HV_REG_X5,
|
||||
HV_REG_X6,
|
||||
HV_REG_X7,
|
||||
HV_REG_X8,
|
||||
HV_REG_X9,
|
||||
HV_REG_X10,
|
||||
HV_REG_X11,
|
||||
HV_REG_X12,
|
||||
HV_REG_X13,
|
||||
HV_REG_X14,
|
||||
HV_REG_X15,
|
||||
HV_REG_X16,
|
||||
HV_REG_X17,
|
||||
HV_REG_X18,
|
||||
HV_REG_X19,
|
||||
HV_REG_X20,
|
||||
HV_REG_X21,
|
||||
HV_REG_X22,
|
||||
HV_REG_X23,
|
||||
HV_REG_X24,
|
||||
HV_REG_X25,
|
||||
HV_REG_X26,
|
||||
HV_REG_X27,
|
||||
HV_REG_X28,
|
||||
HV_REG_X29,
|
||||
HV_REG_FP = HV_REG_X29,
|
||||
HV_REG_X30,
|
||||
HV_REG_LR = HV_REG_X30,
|
||||
HV_REG_PC,
|
||||
HV_REG_FPCR,
|
||||
HV_REG_FPSR,
|
||||
HV_REG_CPSR,
|
||||
}
|
||||
|
||||
enum hv_simd_fp_reg_t : uint
|
||||
{
|
||||
HV_SIMD_FP_REG_Q0,
|
||||
HV_SIMD_FP_REG_Q1,
|
||||
HV_SIMD_FP_REG_Q2,
|
||||
HV_SIMD_FP_REG_Q3,
|
||||
HV_SIMD_FP_REG_Q4,
|
||||
HV_SIMD_FP_REG_Q5,
|
||||
HV_SIMD_FP_REG_Q6,
|
||||
HV_SIMD_FP_REG_Q7,
|
||||
HV_SIMD_FP_REG_Q8,
|
||||
HV_SIMD_FP_REG_Q9,
|
||||
HV_SIMD_FP_REG_Q10,
|
||||
HV_SIMD_FP_REG_Q11,
|
||||
HV_SIMD_FP_REG_Q12,
|
||||
HV_SIMD_FP_REG_Q13,
|
||||
HV_SIMD_FP_REG_Q14,
|
||||
HV_SIMD_FP_REG_Q15,
|
||||
HV_SIMD_FP_REG_Q16,
|
||||
HV_SIMD_FP_REG_Q17,
|
||||
HV_SIMD_FP_REG_Q18,
|
||||
HV_SIMD_FP_REG_Q19,
|
||||
HV_SIMD_FP_REG_Q20,
|
||||
HV_SIMD_FP_REG_Q21,
|
||||
HV_SIMD_FP_REG_Q22,
|
||||
HV_SIMD_FP_REG_Q23,
|
||||
HV_SIMD_FP_REG_Q24,
|
||||
HV_SIMD_FP_REG_Q25,
|
||||
HV_SIMD_FP_REG_Q26,
|
||||
HV_SIMD_FP_REG_Q27,
|
||||
HV_SIMD_FP_REG_Q28,
|
||||
HV_SIMD_FP_REG_Q29,
|
||||
HV_SIMD_FP_REG_Q30,
|
||||
HV_SIMD_FP_REG_Q31,
|
||||
}
|
||||
|
||||
enum hv_sys_reg_t : ushort
|
||||
{
|
||||
HV_SYS_REG_DBGBVR0_EL1 = 0x8004,
|
||||
HV_SYS_REG_DBGBCR0_EL1 = 0x8005,
|
||||
HV_SYS_REG_DBGWVR0_EL1 = 0x8006,
|
||||
HV_SYS_REG_DBGWCR0_EL1 = 0x8007,
|
||||
HV_SYS_REG_DBGBVR1_EL1 = 0x800c,
|
||||
HV_SYS_REG_DBGBCR1_EL1 = 0x800d,
|
||||
HV_SYS_REG_DBGWVR1_EL1 = 0x800e,
|
||||
HV_SYS_REG_DBGWCR1_EL1 = 0x800f,
|
||||
HV_SYS_REG_MDCCINT_EL1 = 0x8010,
|
||||
HV_SYS_REG_MDSCR_EL1 = 0x8012,
|
||||
HV_SYS_REG_DBGBVR2_EL1 = 0x8014,
|
||||
HV_SYS_REG_DBGBCR2_EL1 = 0x8015,
|
||||
HV_SYS_REG_DBGWVR2_EL1 = 0x8016,
|
||||
HV_SYS_REG_DBGWCR2_EL1 = 0x8017,
|
||||
HV_SYS_REG_DBGBVR3_EL1 = 0x801c,
|
||||
HV_SYS_REG_DBGBCR3_EL1 = 0x801d,
|
||||
HV_SYS_REG_DBGWVR3_EL1 = 0x801e,
|
||||
HV_SYS_REG_DBGWCR3_EL1 = 0x801f,
|
||||
HV_SYS_REG_DBGBVR4_EL1 = 0x8024,
|
||||
HV_SYS_REG_DBGBCR4_EL1 = 0x8025,
|
||||
HV_SYS_REG_DBGWVR4_EL1 = 0x8026,
|
||||
HV_SYS_REG_DBGWCR4_EL1 = 0x8027,
|
||||
HV_SYS_REG_DBGBVR5_EL1 = 0x802c,
|
||||
HV_SYS_REG_DBGBCR5_EL1 = 0x802d,
|
||||
HV_SYS_REG_DBGWVR5_EL1 = 0x802e,
|
||||
HV_SYS_REG_DBGWCR5_EL1 = 0x802f,
|
||||
HV_SYS_REG_DBGBVR6_EL1 = 0x8034,
|
||||
HV_SYS_REG_DBGBCR6_EL1 = 0x8035,
|
||||
HV_SYS_REG_DBGWVR6_EL1 = 0x8036,
|
||||
HV_SYS_REG_DBGWCR6_EL1 = 0x8037,
|
||||
HV_SYS_REG_DBGBVR7_EL1 = 0x803c,
|
||||
HV_SYS_REG_DBGBCR7_EL1 = 0x803d,
|
||||
HV_SYS_REG_DBGWVR7_EL1 = 0x803e,
|
||||
HV_SYS_REG_DBGWCR7_EL1 = 0x803f,
|
||||
HV_SYS_REG_DBGBVR8_EL1 = 0x8044,
|
||||
HV_SYS_REG_DBGBCR8_EL1 = 0x8045,
|
||||
HV_SYS_REG_DBGWVR8_EL1 = 0x8046,
|
||||
HV_SYS_REG_DBGWCR8_EL1 = 0x8047,
|
||||
HV_SYS_REG_DBGBVR9_EL1 = 0x804c,
|
||||
HV_SYS_REG_DBGBCR9_EL1 = 0x804d,
|
||||
HV_SYS_REG_DBGWVR9_EL1 = 0x804e,
|
||||
HV_SYS_REG_DBGWCR9_EL1 = 0x804f,
|
||||
HV_SYS_REG_DBGBVR10_EL1 = 0x8054,
|
||||
HV_SYS_REG_DBGBCR10_EL1 = 0x8055,
|
||||
HV_SYS_REG_DBGWVR10_EL1 = 0x8056,
|
||||
HV_SYS_REG_DBGWCR10_EL1 = 0x8057,
|
||||
HV_SYS_REG_DBGBVR11_EL1 = 0x805c,
|
||||
HV_SYS_REG_DBGBCR11_EL1 = 0x805d,
|
||||
HV_SYS_REG_DBGWVR11_EL1 = 0x805e,
|
||||
HV_SYS_REG_DBGWCR11_EL1 = 0x805f,
|
||||
HV_SYS_REG_DBGBVR12_EL1 = 0x8064,
|
||||
HV_SYS_REG_DBGBCR12_EL1 = 0x8065,
|
||||
HV_SYS_REG_DBGWVR12_EL1 = 0x8066,
|
||||
HV_SYS_REG_DBGWCR12_EL1 = 0x8067,
|
||||
HV_SYS_REG_DBGBVR13_EL1 = 0x806c,
|
||||
HV_SYS_REG_DBGBCR13_EL1 = 0x806d,
|
||||
HV_SYS_REG_DBGWVR13_EL1 = 0x806e,
|
||||
HV_SYS_REG_DBGWCR13_EL1 = 0x806f,
|
||||
HV_SYS_REG_DBGBVR14_EL1 = 0x8074,
|
||||
HV_SYS_REG_DBGBCR14_EL1 = 0x8075,
|
||||
HV_SYS_REG_DBGWVR14_EL1 = 0x8076,
|
||||
HV_SYS_REG_DBGWCR14_EL1 = 0x8077,
|
||||
HV_SYS_REG_DBGBVR15_EL1 = 0x807c,
|
||||
HV_SYS_REG_DBGBCR15_EL1 = 0x807d,
|
||||
HV_SYS_REG_DBGWVR15_EL1 = 0x807e,
|
||||
HV_SYS_REG_DBGWCR15_EL1 = 0x807f,
|
||||
HV_SYS_REG_MIDR_EL1 = 0xc000,
|
||||
HV_SYS_REG_MPIDR_EL1 = 0xc005,
|
||||
HV_SYS_REG_ID_AA64PFR0_EL1 = 0xc020,
|
||||
HV_SYS_REG_ID_AA64PFR1_EL1 = 0xc021,
|
||||
HV_SYS_REG_ID_AA64DFR0_EL1 = 0xc028,
|
||||
HV_SYS_REG_ID_AA64DFR1_EL1 = 0xc029,
|
||||
HV_SYS_REG_ID_AA64ISAR0_EL1 = 0xc030,
|
||||
HV_SYS_REG_ID_AA64ISAR1_EL1 = 0xc031,
|
||||
HV_SYS_REG_ID_AA64MMFR0_EL1 = 0xc038,
|
||||
HV_SYS_REG_ID_AA64MMFR1_EL1 = 0xc039,
|
||||
HV_SYS_REG_ID_AA64MMFR2_EL1 = 0xc03a,
|
||||
HV_SYS_REG_SCTLR_EL1 = 0xc080,
|
||||
HV_SYS_REG_CPACR_EL1 = 0xc082,
|
||||
HV_SYS_REG_TTBR0_EL1 = 0xc100,
|
||||
HV_SYS_REG_TTBR1_EL1 = 0xc101,
|
||||
HV_SYS_REG_TCR_EL1 = 0xc102,
|
||||
HV_SYS_REG_APIAKEYLO_EL1 = 0xc108,
|
||||
HV_SYS_REG_APIAKEYHI_EL1 = 0xc109,
|
||||
HV_SYS_REG_APIBKEYLO_EL1 = 0xc10a,
|
||||
HV_SYS_REG_APIBKEYHI_EL1 = 0xc10b,
|
||||
HV_SYS_REG_APDAKEYLO_EL1 = 0xc110,
|
||||
HV_SYS_REG_APDAKEYHI_EL1 = 0xc111,
|
||||
HV_SYS_REG_APDBKEYLO_EL1 = 0xc112,
|
||||
HV_SYS_REG_APDBKEYHI_EL1 = 0xc113,
|
||||
HV_SYS_REG_APGAKEYLO_EL1 = 0xc118,
|
||||
HV_SYS_REG_APGAKEYHI_EL1 = 0xc119,
|
||||
HV_SYS_REG_SPSR_EL1 = 0xc200,
|
||||
HV_SYS_REG_ELR_EL1 = 0xc201,
|
||||
HV_SYS_REG_SP_EL0 = 0xc208,
|
||||
HV_SYS_REG_AFSR0_EL1 = 0xc288,
|
||||
HV_SYS_REG_AFSR1_EL1 = 0xc289,
|
||||
HV_SYS_REG_ESR_EL1 = 0xc290,
|
||||
HV_SYS_REG_FAR_EL1 = 0xc300,
|
||||
HV_SYS_REG_PAR_EL1 = 0xc3a0,
|
||||
HV_SYS_REG_MAIR_EL1 = 0xc510,
|
||||
HV_SYS_REG_AMAIR_EL1 = 0xc518,
|
||||
HV_SYS_REG_VBAR_EL1 = 0xc600,
|
||||
HV_SYS_REG_CONTEXTIDR_EL1 = 0xc681,
|
||||
HV_SYS_REG_TPIDR_EL1 = 0xc684,
|
||||
HV_SYS_REG_CNTKCTL_EL1 = 0xc708,
|
||||
HV_SYS_REG_CSSELR_EL1 = 0xd000,
|
||||
HV_SYS_REG_TPIDR_EL0 = 0xde82,
|
||||
HV_SYS_REG_TPIDRRO_EL0 = 0xde83,
|
||||
HV_SYS_REG_CNTV_CTL_EL0 = 0xdf19,
|
||||
HV_SYS_REG_CNTV_CVAL_EL0 = 0xdf1a,
|
||||
HV_SYS_REG_SP_EL1 = 0xe208,
|
||||
}
|
||||
|
||||
enum hv_memory_flags_t : ulong
|
||||
{
|
||||
HV_MEMORY_READ = 1UL << 0,
|
||||
HV_MEMORY_WRITE = 1UL << 1,
|
||||
HV_MEMORY_EXEC = 1UL << 2
|
||||
}
|
||||
|
||||
enum hv_result_t : uint
|
||||
{
|
||||
HV_SUCCESS = 0,
|
||||
HV_ERROR = 0xfae94001,
|
||||
HV_BUSY = 0xfae94002,
|
||||
HV_BAD_ARGUMENT = 0xfae94003,
|
||||
HV_NO_RESOURCES = 0xfae94005,
|
||||
HV_NO_DEVICE = 0xfae94006,
|
||||
HV_DENIED = 0xfae94007,
|
||||
HV_UNSUPPORTED = 0xfae9400f
|
||||
}
|
||||
|
||||
enum hv_interrupt_type_t : uint
|
||||
{
|
||||
HV_INTERRUPT_TYPE_IRQ,
|
||||
HV_INTERRUPT_TYPE_FIQ
|
||||
}
|
||||
|
||||
struct hv_simd_fp_uchar16_t
|
||||
{
|
||||
public ulong Low;
|
||||
public ulong High;
|
||||
}
|
||||
|
||||
static class HvResultExtensions
|
||||
{
|
||||
public static void ThrowOnError(this hv_result_t result)
|
||||
{
|
||||
if (result != hv_result_t.HV_SUCCESS)
|
||||
{
|
||||
throw new Exception($"Unexpected result \"{result}\".");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static partial class HvApi
|
||||
{
|
||||
public const string LibraryName = "/System/Library/Frameworks/Hypervisor.framework/Hypervisor";
|
||||
|
||||
[LibraryImport(LibraryName, SetLastError = true)]
|
||||
public static partial hv_result_t hv_vm_get_max_vcpu_count(out uint max_vcpu_count);
|
||||
|
||||
[LibraryImport(LibraryName, SetLastError = true)]
|
||||
public static partial hv_result_t hv_vm_create(IntPtr config);
|
||||
|
||||
[LibraryImport(LibraryName, SetLastError = true)]
|
||||
public static partial hv_result_t hv_vm_destroy();
|
||||
|
||||
[LibraryImport(LibraryName, SetLastError = true)]
|
||||
public static partial hv_result_t hv_vm_map(ulong addr, ulong ipa, ulong size, hv_memory_flags_t flags);
|
||||
|
||||
[LibraryImport(LibraryName, SetLastError = true)]
|
||||
public static partial hv_result_t hv_vm_unmap(ulong ipa, ulong size);
|
||||
|
||||
[LibraryImport(LibraryName, SetLastError = true)]
|
||||
public static partial hv_result_t hv_vm_protect(ulong ipa, ulong size, hv_memory_flags_t flags);
|
||||
|
||||
[LibraryImport(LibraryName, SetLastError = true)]
|
||||
public unsafe static partial hv_result_t hv_vcpu_create(out ulong vcpu, ref hv_vcpu_exit_t* exit, IntPtr config);
|
||||
|
||||
[LibraryImport(LibraryName, SetLastError = true)]
|
||||
public unsafe static partial hv_result_t hv_vcpu_destroy(ulong vcpu);
|
||||
|
||||
[LibraryImport(LibraryName, SetLastError = true)]
|
||||
public static partial hv_result_t hv_vcpu_run(ulong vcpu);
|
||||
|
||||
[LibraryImport(LibraryName, SetLastError = true)]
|
||||
public static partial hv_result_t hv_vcpus_exit(ref ulong vcpus, uint vcpu_count);
|
||||
|
||||
[LibraryImport(LibraryName, SetLastError = true)]
|
||||
public static partial hv_result_t hv_vcpu_set_vtimer_mask(ulong vcpu, [MarshalAs(UnmanagedType.Bool)] bool vtimer_is_masked);
|
||||
|
||||
[LibraryImport(LibraryName, SetLastError = true)]
|
||||
public static partial hv_result_t hv_vcpu_get_reg(ulong vcpu, hv_reg_t reg, out ulong value);
|
||||
|
||||
[LibraryImport(LibraryName, SetLastError = true)]
|
||||
public static partial hv_result_t hv_vcpu_set_reg(ulong vcpu, hv_reg_t reg, ulong value);
|
||||
|
||||
[LibraryImport(LibraryName, SetLastError = true)]
|
||||
public static partial hv_result_t hv_vcpu_get_simd_fp_reg(ulong vcpu, hv_simd_fp_reg_t reg, out hv_simd_fp_uchar16_t value);
|
||||
|
||||
[LibraryImport(LibraryName, SetLastError = true)]
|
||||
public static partial hv_result_t hv_vcpu_set_simd_fp_reg(ulong vcpu, hv_simd_fp_reg_t reg, hv_simd_fp_uchar16_t value); // DO NOT USE DIRECTLY!
|
||||
|
||||
[LibraryImport(LibraryName, SetLastError = true)]
|
||||
public static partial hv_result_t hv_vcpu_get_sys_reg(ulong vcpu, hv_sys_reg_t reg, out ulong value);
|
||||
|
||||
[LibraryImport(LibraryName, SetLastError = true)]
|
||||
public static partial hv_result_t hv_vcpu_set_sys_reg(ulong vcpu, hv_sys_reg_t reg, ulong value);
|
||||
|
||||
[LibraryImport(LibraryName, SetLastError = true)]
|
||||
public static partial hv_result_t hv_vcpu_get_pending_interrupt(ulong vcpu, hv_interrupt_type_t type, [MarshalAs(UnmanagedType.Bool)] out bool pending);
|
||||
|
||||
[LibraryImport(LibraryName, SetLastError = true)]
|
||||
public static partial hv_result_t hv_vcpu_set_pending_interrupt(ulong vcpu, hv_interrupt_type_t type, [MarshalAs(UnmanagedType.Bool)] bool pending);
|
||||
}
|
||||
}
|
47
Ryujinx.Cpu/AppleHv/HvCpuContext.cs
Normal file
47
Ryujinx.Cpu/AppleHv/HvCpuContext.cs
Normal file
@ -0,0 +1,47 @@
|
||||
using ARMeilleure.Memory;
|
||||
using System;
|
||||
|
||||
namespace Ryujinx.Cpu.AppleHv
|
||||
{
|
||||
class HvCpuContext : ICpuContext
|
||||
{
|
||||
private readonly ITickSource _tickSource;
|
||||
private readonly HvMemoryManager _memoryManager;
|
||||
|
||||
public HvCpuContext(ITickSource tickSource, IMemoryManager memory, bool for64Bit)
|
||||
{
|
||||
_tickSource = tickSource;
|
||||
_memoryManager = (HvMemoryManager)memory;
|
||||
}
|
||||
|
||||
private void UnmapHandler(ulong address, ulong size)
|
||||
{
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public IExecutionContext CreateExecutionContext(ExceptionCallbacks exceptionCallbacks)
|
||||
{
|
||||
return new HvExecutionContext(_tickSource, exceptionCallbacks);
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public void Execute(IExecutionContext context, ulong address)
|
||||
{
|
||||
((HvExecutionContext)context).Execute(_memoryManager, address);
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public void InvalidateCacheRegion(ulong address, ulong size)
|
||||
{
|
||||
}
|
||||
|
||||
public IDiskCacheLoadState LoadDiskCache(string titleIdText, string displayVersion, bool enabled)
|
||||
{
|
||||
return new DummyDiskCacheLoadState();
|
||||
}
|
||||
|
||||
public void PrepareCodeRange(ulong address, ulong size)
|
||||
{
|
||||
}
|
||||
}
|
||||
}
|
20
Ryujinx.Cpu/AppleHv/HvEngine.cs
Normal file
20
Ryujinx.Cpu/AppleHv/HvEngine.cs
Normal file
@ -0,0 +1,20 @@
|
||||
using ARMeilleure.Memory;
|
||||
|
||||
namespace Ryujinx.Cpu.AppleHv
|
||||
{
|
||||
public class HvEngine : ICpuEngine
|
||||
{
|
||||
private readonly ITickSource _tickSource;
|
||||
|
||||
public HvEngine(ITickSource tickSource)
|
||||
{
|
||||
_tickSource = tickSource;
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public ICpuContext CreateCpuContext(IMemoryManager memoryManager, bool for64Bit)
|
||||
{
|
||||
return new HvCpuContext(_tickSource, memoryManager, for64Bit);
|
||||
}
|
||||
}
|
||||
}
|
284
Ryujinx.Cpu/AppleHv/HvExecutionContext.cs
Normal file
284
Ryujinx.Cpu/AppleHv/HvExecutionContext.cs
Normal file
@ -0,0 +1,284 @@
|
||||
using ARMeilleure.State;
|
||||
using Ryujinx.Cpu.AppleHv.Arm;
|
||||
using Ryujinx.Memory.Tracking;
|
||||
using System;
|
||||
|
||||
namespace Ryujinx.Cpu.AppleHv
|
||||
{
|
||||
class HvExecutionContext : IExecutionContext
|
||||
{
|
||||
/// <inheritdoc/>
|
||||
public ulong Pc => _impl.ElrEl1;
|
||||
|
||||
/// <inheritdoc/>
|
||||
public long TpidrEl0
|
||||
{
|
||||
get => _impl.TpidrEl0;
|
||||
set => _impl.TpidrEl0 = value;
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public long TpidrroEl0
|
||||
{
|
||||
get => _impl.TpidrroEl0;
|
||||
set => _impl.TpidrroEl0 = value;
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public uint Pstate
|
||||
{
|
||||
get => _impl.Pstate;
|
||||
set => _impl.Pstate = value;
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public uint Fpcr
|
||||
{
|
||||
get => _impl.Fpcr;
|
||||
set => _impl.Fpcr = value;
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public uint Fpsr
|
||||
{
|
||||
get => _impl.Fpsr;
|
||||
set => _impl.Fpsr = value;
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public bool IsAarch32
|
||||
{
|
||||
get => false;
|
||||
set
|
||||
{
|
||||
if (value)
|
||||
{
|
||||
throw new NotSupportedException();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public bool Running { get; private set; }
|
||||
|
||||
private readonly ICounter _counter;
|
||||
private readonly IHvExecutionContext _shadowContext;
|
||||
private IHvExecutionContext _impl;
|
||||
|
||||
private readonly ExceptionCallbacks _exceptionCallbacks;
|
||||
|
||||
public HvExecutionContext(ICounter counter, ExceptionCallbacks exceptionCallbacks)
|
||||
{
|
||||
_counter = counter;
|
||||
_shadowContext = new HvExecutionContextShadow();
|
||||
_impl = _shadowContext;
|
||||
_exceptionCallbacks = exceptionCallbacks;
|
||||
Running = true;
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public ulong GetX(int index) => _impl.GetX(index);
|
||||
|
||||
/// <inheritdoc/>
|
||||
public void SetX(int index, ulong value) => _impl.SetX(index, value);
|
||||
|
||||
/// <inheritdoc/>
|
||||
public V128 GetV(int index) => _impl.GetV(index);
|
||||
|
||||
/// <inheritdoc/>
|
||||
public void SetV(int index, V128 value) => _impl.SetV(index, value);
|
||||
|
||||
private void InterruptHandler()
|
||||
{
|
||||
_exceptionCallbacks.InterruptCallback?.Invoke(this);
|
||||
}
|
||||
|
||||
private void BreakHandler(ulong address, int imm)
|
||||
{
|
||||
_exceptionCallbacks.BreakCallback?.Invoke(this, address, imm);
|
||||
}
|
||||
|
||||
private void SupervisorCallHandler(ulong address, int imm)
|
||||
{
|
||||
_exceptionCallbacks.SupervisorCallback?.Invoke(this, address, imm);
|
||||
}
|
||||
|
||||
private void UndefinedHandler(ulong address, int opCode)
|
||||
{
|
||||
_exceptionCallbacks.UndefinedCallback?.Invoke(this, address, opCode);
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public void RequestInterrupt()
|
||||
{
|
||||
_impl.RequestInterrupt();
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public void StopRunning()
|
||||
{
|
||||
Running = false;
|
||||
RequestInterrupt();
|
||||
}
|
||||
|
||||
public unsafe void Execute(HvMemoryManager memoryManager, ulong address)
|
||||
{
|
||||
HvVcpu vcpu = HvVcpuPool.Instance.Create(memoryManager.AddressSpace, _shadowContext, SwapContext);
|
||||
|
||||
HvApi.hv_vcpu_set_reg(vcpu.Handle, hv_reg_t.HV_REG_PC, address).ThrowOnError();
|
||||
|
||||
while (Running)
|
||||
{
|
||||
HvApi.hv_vcpu_run(vcpu.Handle).ThrowOnError();
|
||||
|
||||
uint reason = vcpu.ExitInfo->reason;
|
||||
|
||||
if (reason == 1)
|
||||
{
|
||||
uint hvEsr = (uint)vcpu.ExitInfo->exception.syndrome;
|
||||
ExceptionClass hvEc = (ExceptionClass)(hvEsr >> 26);
|
||||
|
||||
if (hvEc != ExceptionClass.HvcAarch64)
|
||||
{
|
||||
throw new Exception($"Unhandled exception from guest kernel with ESR 0x{hvEsr:X} ({hvEc}).");
|
||||
}
|
||||
|
||||
address = SynchronousException(memoryManager, ref vcpu);
|
||||
HvApi.hv_vcpu_set_reg(vcpu.Handle, hv_reg_t.HV_REG_PC, address).ThrowOnError();
|
||||
}
|
||||
else if (reason == 0)
|
||||
{
|
||||
if (_impl.GetAndClearInterruptRequested())
|
||||
{
|
||||
ReturnToPool(vcpu);
|
||||
InterruptHandler();
|
||||
vcpu = RentFromPool(memoryManager.AddressSpace, vcpu);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
throw new Exception($"Unhandled exit reason {reason}.");
|
||||
}
|
||||
}
|
||||
|
||||
HvVcpuPool.Instance.Destroy(vcpu, SwapContext);
|
||||
}
|
||||
|
||||
private ulong SynchronousException(HvMemoryManager memoryManager, ref HvVcpu vcpu)
|
||||
{
|
||||
ulong vcpuHandle = vcpu.Handle;
|
||||
|
||||
HvApi.hv_vcpu_get_sys_reg(vcpuHandle, hv_sys_reg_t.HV_SYS_REG_ELR_EL1, out ulong elr).ThrowOnError();
|
||||
HvApi.hv_vcpu_get_sys_reg(vcpuHandle, hv_sys_reg_t.HV_SYS_REG_ESR_EL1, out ulong esr).ThrowOnError();
|
||||
|
||||
ExceptionClass ec = (ExceptionClass)((uint)esr >> 26);
|
||||
|
||||
switch (ec)
|
||||
{
|
||||
case ExceptionClass.DataAbortLowerEl:
|
||||
DataAbort(memoryManager.Tracking, vcpuHandle, (uint)esr);
|
||||
break;
|
||||
case ExceptionClass.TrappedMsrMrsSystem:
|
||||
InstructionTrap((uint)esr);
|
||||
HvApi.hv_vcpu_set_sys_reg(vcpuHandle, hv_sys_reg_t.HV_SYS_REG_ELR_EL1, elr + 4UL).ThrowOnError();
|
||||
break;
|
||||
case ExceptionClass.SvcAarch64:
|
||||
ReturnToPool(vcpu);
|
||||
ushort id = (ushort)esr;
|
||||
SupervisorCallHandler(elr - 4UL, id);
|
||||
vcpu = RentFromPool(memoryManager.AddressSpace, vcpu);
|
||||
break;
|
||||
default:
|
||||
throw new Exception($"Unhandled guest exception {ec}.");
|
||||
}
|
||||
|
||||
// Make sure we will continue running at EL0.
|
||||
if (memoryManager.AddressSpace.GetAndClearUserTlbInvalidationPending())
|
||||
{
|
||||
// TODO: Invalidate only the range that was modified?
|
||||
return HvAddressSpace.KernelRegionTlbiEretAddress;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HvAddressSpace.KernelRegionEretAddress;
|
||||
}
|
||||
}
|
||||
|
||||
private void DataAbort(MemoryTracking tracking, ulong vcpu, uint esr)
|
||||
{
|
||||
bool write = (esr & (1u << 6)) != 0;
|
||||
bool farValid = (esr & (1u << 10)) == 0;
|
||||
int accessSizeLog2 = (int)((esr >> 22) & 3);
|
||||
|
||||
if (farValid)
|
||||
{
|
||||
HvApi.hv_vcpu_get_sys_reg(vcpu, hv_sys_reg_t.HV_SYS_REG_FAR_EL1, out ulong far).ThrowOnError();
|
||||
|
||||
ulong size = 1UL << accessSizeLog2;
|
||||
|
||||
if (!tracking.VirtualMemoryEvent(far, size, write))
|
||||
{
|
||||
string rw = write ? "write" : "read";
|
||||
throw new Exception($"Unhandled invalid memory access at VA 0x{far:X} with size 0x{size:X} ({rw}).");
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
throw new Exception($"Unhandled invalid memory access at unknown VA with ESR 0x{esr:X}.");
|
||||
}
|
||||
}
|
||||
|
||||
private void InstructionTrap(uint esr)
|
||||
{
|
||||
bool read = (esr & 1) != 0;
|
||||
uint rt = (esr >> 5) & 0x1f;
|
||||
|
||||
if (read)
|
||||
{
|
||||
// Op0 Op2 Op1 CRn 00000 CRm
|
||||
switch ((esr >> 1) & 0x1ffe0f)
|
||||
{
|
||||
case 0b11_000_011_1110_00000_0000: // CNTFRQ_EL0
|
||||
WriteRt(rt, _counter.Frequency);
|
||||
break;
|
||||
case 0b11_001_011_1110_00000_0000: // CNTPCT_EL0
|
||||
WriteRt(rt, _counter.Counter);
|
||||
break;
|
||||
default:
|
||||
throw new Exception($"Unhandled system register read with ESR 0x{esr:X}");
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
throw new Exception($"Unhandled system register write with ESR 0x{esr:X}");
|
||||
}
|
||||
}
|
||||
|
||||
private void WriteRt(uint rt, ulong value)
|
||||
{
|
||||
if (rt < 31)
|
||||
{
|
||||
SetX((int)rt, value);
|
||||
}
|
||||
}
|
||||
|
||||
private void ReturnToPool(HvVcpu vcpu)
|
||||
{
|
||||
HvVcpuPool.Instance.Return(vcpu, SwapContext);
|
||||
}
|
||||
|
||||
private HvVcpu RentFromPool(HvAddressSpace addressSpace, HvVcpu vcpu)
|
||||
{
|
||||
return HvVcpuPool.Instance.Rent(addressSpace, _shadowContext, vcpu, SwapContext);
|
||||
}
|
||||
|
||||
private void SwapContext(IHvExecutionContext newContext)
|
||||
{
|
||||
_impl = newContext;
|
||||
}
|
||||
|
||||
public void Dispose()
|
||||
{
|
||||
}
|
||||
}
|
||||
}
|
59
Ryujinx.Cpu/AppleHv/HvExecutionContextShadow.cs
Normal file
59
Ryujinx.Cpu/AppleHv/HvExecutionContextShadow.cs
Normal file
@ -0,0 +1,59 @@
|
||||
using ARMeilleure.State;
|
||||
|
||||
namespace Ryujinx.Cpu.AppleHv
|
||||
{
|
||||
unsafe class HvExecutionContextShadow : IHvExecutionContext
|
||||
{
|
||||
public ulong Pc { get; set; }
|
||||
public ulong ElrEl1 { get; set; }
|
||||
public ulong EsrEl1 { get; set; }
|
||||
|
||||
public long TpidrEl0 { get; set; }
|
||||
public long TpidrroEl0 { get; set; }
|
||||
|
||||
public uint Pstate { get; set; }
|
||||
|
||||
public uint Fpcr { get; set; }
|
||||
public uint Fpsr { get; set; }
|
||||
|
||||
public bool IsAarch32 { get; set; }
|
||||
|
||||
private readonly ulong[] _x;
|
||||
private readonly V128[] _v;
|
||||
|
||||
public HvExecutionContextShadow()
|
||||
{
|
||||
_x = new ulong[32];
|
||||
_v = new V128[32];
|
||||
}
|
||||
|
||||
public ulong GetX(int index)
|
||||
{
|
||||
return _x[index];
|
||||
}
|
||||
|
||||
public void SetX(int index, ulong value)
|
||||
{
|
||||
_x[index] = value;
|
||||
}
|
||||
|
||||
public V128 GetV(int index)
|
||||
{
|
||||
return _v[index];
|
||||
}
|
||||
|
||||
public void SetV(int index, V128 value)
|
||||
{
|
||||
_v[index] = value;
|
||||
}
|
||||
|
||||
public void RequestInterrupt()
|
||||
{
|
||||
}
|
||||
|
||||
public bool GetAndClearInterruptRequested()
|
||||
{
|
||||
return false;
|
||||
}
|
||||
}
|
||||
}
|
196
Ryujinx.Cpu/AppleHv/HvExecutionContextVcpu.cs
Normal file
196
Ryujinx.Cpu/AppleHv/HvExecutionContextVcpu.cs
Normal file
@ -0,0 +1,196 @@
|
||||
using ARMeilleure.State;
|
||||
using Ryujinx.Memory;
|
||||
using System;
|
||||
using System.Runtime.InteropServices;
|
||||
using System.Threading;
|
||||
|
||||
namespace Ryujinx.Cpu.AppleHv
|
||||
{
|
||||
class HvExecutionContextVcpu : IHvExecutionContext
|
||||
{
|
||||
private static MemoryBlock _setSimdFpRegFuncMem;
|
||||
private delegate hv_result_t SetSimdFpReg(ulong vcpu, hv_simd_fp_reg_t reg, in V128 value, IntPtr funcPtr);
|
||||
private static SetSimdFpReg _setSimdFpReg;
|
||||
private static IntPtr _setSimdFpRegNativePtr;
|
||||
|
||||
static HvExecutionContextVcpu()
|
||||
{
|
||||
// .NET does not support passing vectors by value, so we need to pass a pointer and use a native
|
||||
// function to load the value into a vector register.
|
||||
_setSimdFpRegFuncMem = new MemoryBlock(MemoryBlock.GetPageSize());
|
||||
_setSimdFpRegFuncMem.Write(0, 0x3DC00040u); // LDR Q0, [X2]
|
||||
_setSimdFpRegFuncMem.Write(4, 0xD61F0060u); // BR X3
|
||||
_setSimdFpRegFuncMem.Reprotect(0, _setSimdFpRegFuncMem.Size, MemoryPermission.ReadAndExecute);
|
||||
|
||||
_setSimdFpReg = Marshal.GetDelegateForFunctionPointer<SetSimdFpReg>(_setSimdFpRegFuncMem.Pointer);
|
||||
|
||||
if (NativeLibrary.TryLoad(HvApi.LibraryName, out IntPtr hvLibHandle))
|
||||
{
|
||||
_setSimdFpRegNativePtr = NativeLibrary.GetExport(hvLibHandle, nameof(HvApi.hv_vcpu_set_simd_fp_reg));
|
||||
}
|
||||
}
|
||||
|
||||
public ulong Pc
|
||||
{
|
||||
get
|
||||
{
|
||||
HvApi.hv_vcpu_get_reg(_vcpu, hv_reg_t.HV_REG_PC, out ulong pc).ThrowOnError();
|
||||
return pc;
|
||||
}
|
||||
set
|
||||
{
|
||||
HvApi.hv_vcpu_set_reg(_vcpu, hv_reg_t.HV_REG_PC, value).ThrowOnError();
|
||||
}
|
||||
}
|
||||
|
||||
public ulong ElrEl1
|
||||
{
|
||||
get
|
||||
{
|
||||
HvApi.hv_vcpu_get_sys_reg(_vcpu, hv_sys_reg_t.HV_SYS_REG_ELR_EL1, out ulong elr).ThrowOnError();
|
||||
return elr;
|
||||
}
|
||||
set
|
||||
{
|
||||
HvApi.hv_vcpu_set_sys_reg(_vcpu, hv_sys_reg_t.HV_SYS_REG_ELR_EL1, value).ThrowOnError();
|
||||
}
|
||||
}
|
||||
|
||||
public ulong EsrEl1
|
||||
{
|
||||
get
|
||||
{
|
||||
HvApi.hv_vcpu_get_sys_reg(_vcpu, hv_sys_reg_t.HV_SYS_REG_ESR_EL1, out ulong esr).ThrowOnError();
|
||||
return esr;
|
||||
}
|
||||
set
|
||||
{
|
||||
HvApi.hv_vcpu_set_sys_reg(_vcpu, hv_sys_reg_t.HV_SYS_REG_ESR_EL1, value).ThrowOnError();
|
||||
}
|
||||
}
|
||||
|
||||
public long TpidrEl0
|
||||
{
|
||||
get
|
||||
{
|
||||
HvApi.hv_vcpu_get_sys_reg(_vcpu, hv_sys_reg_t.HV_SYS_REG_TPIDR_EL0, out ulong tpidrEl0).ThrowOnError();
|
||||
return (long)tpidrEl0;
|
||||
}
|
||||
set
|
||||
{
|
||||
HvApi.hv_vcpu_set_sys_reg(_vcpu, hv_sys_reg_t.HV_SYS_REG_TPIDR_EL0, (ulong)value).ThrowOnError();
|
||||
}
|
||||
}
|
||||
|
||||
public long TpidrroEl0
|
||||
{
|
||||
get
|
||||
{
|
||||
HvApi.hv_vcpu_get_sys_reg(_vcpu, hv_sys_reg_t.HV_SYS_REG_TPIDRRO_EL0, out ulong tpidrroEl0).ThrowOnError();
|
||||
return (long)tpidrroEl0;
|
||||
}
|
||||
set
|
||||
{
|
||||
HvApi.hv_vcpu_set_sys_reg(_vcpu, hv_sys_reg_t.HV_SYS_REG_TPIDRRO_EL0, (ulong)value).ThrowOnError();
|
||||
}
|
||||
}
|
||||
|
||||
public uint Pstate
|
||||
{
|
||||
get
|
||||
{
|
||||
HvApi.hv_vcpu_get_reg(_vcpu, hv_reg_t.HV_REG_CPSR, out ulong cpsr).ThrowOnError();
|
||||
return (uint)cpsr;
|
||||
}
|
||||
set
|
||||
{
|
||||
HvApi.hv_vcpu_set_reg(_vcpu, hv_reg_t.HV_REG_CPSR, (ulong)value).ThrowOnError();
|
||||
}
|
||||
}
|
||||
|
||||
public uint Fpcr
|
||||
{
|
||||
get
|
||||
{
|
||||
HvApi.hv_vcpu_get_reg(_vcpu, hv_reg_t.HV_REG_FPCR, out ulong fpcr).ThrowOnError();
|
||||
return (uint)fpcr;
|
||||
}
|
||||
set
|
||||
{
|
||||
HvApi.hv_vcpu_set_reg(_vcpu, hv_reg_t.HV_REG_FPCR, (ulong)value).ThrowOnError();
|
||||
}
|
||||
}
|
||||
|
||||
public uint Fpsr
|
||||
{
|
||||
get
|
||||
{
|
||||
HvApi.hv_vcpu_get_reg(_vcpu, hv_reg_t.HV_REG_FPSR, out ulong fpsr).ThrowOnError();
|
||||
return (uint)fpsr;
|
||||
}
|
||||
set
|
||||
{
|
||||
HvApi.hv_vcpu_set_reg(_vcpu, hv_reg_t.HV_REG_FPSR, (ulong)value).ThrowOnError();
|
||||
}
|
||||
}
|
||||
|
||||
private ulong _vcpu;
|
||||
private int _interruptRequested;
|
||||
|
||||
public HvExecutionContextVcpu(ulong vcpu)
|
||||
{
|
||||
_vcpu = vcpu;
|
||||
}
|
||||
|
||||
public ulong GetX(int index)
|
||||
{
|
||||
if (index == 31)
|
||||
{
|
||||
HvApi.hv_vcpu_get_sys_reg(_vcpu, hv_sys_reg_t.HV_SYS_REG_SP_EL0, out ulong value).ThrowOnError();
|
||||
return value;
|
||||
}
|
||||
else
|
||||
{
|
||||
HvApi.hv_vcpu_get_reg(_vcpu, hv_reg_t.HV_REG_X0 + (uint)index, out ulong value).ThrowOnError();
|
||||
return value;
|
||||
}
|
||||
}
|
||||
|
||||
public void SetX(int index, ulong value)
|
||||
{
|
||||
if (index == 31)
|
||||
{
|
||||
HvApi.hv_vcpu_set_sys_reg(_vcpu, hv_sys_reg_t.HV_SYS_REG_SP_EL0, value).ThrowOnError();
|
||||
}
|
||||
else
|
||||
{
|
||||
HvApi.hv_vcpu_set_reg(_vcpu, hv_reg_t.HV_REG_X0 + (uint)index, value).ThrowOnError();
|
||||
}
|
||||
}
|
||||
|
||||
public V128 GetV(int index)
|
||||
{
|
||||
HvApi.hv_vcpu_get_simd_fp_reg(_vcpu, hv_simd_fp_reg_t.HV_SIMD_FP_REG_Q0 + (uint)index, out hv_simd_fp_uchar16_t value).ThrowOnError();
|
||||
return new V128(value.Low, value.High);
|
||||
}
|
||||
|
||||
public void SetV(int index, V128 value)
|
||||
{
|
||||
_setSimdFpReg(_vcpu, hv_simd_fp_reg_t.HV_SIMD_FP_REG_Q0 + (uint)index, value, _setSimdFpRegNativePtr).ThrowOnError();
|
||||
}
|
||||
|
||||
public void RequestInterrupt()
|
||||
{
|
||||
if (Interlocked.Exchange(ref _interruptRequested, 1) == 0)
|
||||
{
|
||||
ulong vcpu = _vcpu;
|
||||
HvApi.hv_vcpus_exit(ref vcpu, 1);
|
||||
}
|
||||
}
|
||||
|
||||
public bool GetAndClearInterruptRequested()
|
||||
{
|
||||
return Interlocked.Exchange(ref _interruptRequested, 0) != 0;
|
||||
}
|
||||
}
|
||||
}
|
34
Ryujinx.Cpu/AppleHv/HvIpaAllocator.cs
Normal file
34
Ryujinx.Cpu/AppleHv/HvIpaAllocator.cs
Normal file
@ -0,0 +1,34 @@
|
||||
using System;
|
||||
|
||||
namespace Ryujinx.Cpu.AppleHv
|
||||
{
|
||||
class HvIpaAllocator
|
||||
{
|
||||
private const ulong AllocationGranule = 1UL << 14;
|
||||
private const ulong IpaRegionSize = 1UL << 35;
|
||||
|
||||
private readonly PrivateMemoryAllocator.Block _block;
|
||||
|
||||
public HvIpaAllocator()
|
||||
{
|
||||
_block = new PrivateMemoryAllocator.Block(null, IpaRegionSize);
|
||||
}
|
||||
|
||||
public ulong Allocate(ulong size, ulong alignment = AllocationGranule)
|
||||
{
|
||||
ulong offset = _block.Allocate(size, alignment);
|
||||
|
||||
if (offset == PrivateMemoryAllocator.InvalidOffset)
|
||||
{
|
||||
throw new InvalidOperationException($"No enough free IPA memory to allocate 0x{size:X} bytes with alignment 0x{alignment:X}.");
|
||||
}
|
||||
|
||||
return offset;
|
||||
}
|
||||
|
||||
public void Free(ulong offset, ulong size)
|
||||
{
|
||||
_block.Free(offset, size);
|
||||
}
|
||||
}
|
||||
}
|
34
Ryujinx.Cpu/AppleHv/HvMemoryBlockAllocation.cs
Normal file
34
Ryujinx.Cpu/AppleHv/HvMemoryBlockAllocation.cs
Normal file
@ -0,0 +1,34 @@
|
||||
using Ryujinx.Memory;
|
||||
using System;
|
||||
|
||||
namespace Ryujinx.Cpu.AppleHv
|
||||
{
|
||||
struct HvMemoryBlockAllocation : IDisposable
|
||||
{
|
||||
private readonly HvMemoryBlockAllocator _owner;
|
||||
private readonly HvMemoryBlockAllocator.Block _block;
|
||||
|
||||
public bool IsValid => _owner != null;
|
||||
public MemoryBlock Memory => _block.Memory;
|
||||
public ulong Ipa => _block.Ipa;
|
||||
public ulong Offset { get; }
|
||||
public ulong Size { get; }
|
||||
|
||||
public HvMemoryBlockAllocation(
|
||||
HvMemoryBlockAllocator owner,
|
||||
HvMemoryBlockAllocator.Block block,
|
||||
ulong offset,
|
||||
ulong size)
|
||||
{
|
||||
_owner = owner;
|
||||
_block = block;
|
||||
Offset = offset;
|
||||
Size = size;
|
||||
}
|
||||
|
||||
public void Dispose()
|
||||
{
|
||||
_owner.Free(_block, Offset, Size);
|
||||
}
|
||||
}
|
||||
}
|
59
Ryujinx.Cpu/AppleHv/HvMemoryBlockAllocator.cs
Normal file
59
Ryujinx.Cpu/AppleHv/HvMemoryBlockAllocator.cs
Normal file
@ -0,0 +1,59 @@
|
||||
using Ryujinx.Memory;
|
||||
using System.Collections.Generic;
|
||||
|
||||
namespace Ryujinx.Cpu.AppleHv
|
||||
{
|
||||
class HvMemoryBlockAllocator : PrivateMemoryAllocatorImpl<HvMemoryBlockAllocator.Block>
|
||||
{
|
||||
private const ulong InvalidOffset = ulong.MaxValue;
|
||||
|
||||
public class Block : PrivateMemoryAllocator.Block
|
||||
{
|
||||
private readonly HvIpaAllocator _ipaAllocator;
|
||||
public ulong Ipa { get; }
|
||||
|
||||
public Block(HvIpaAllocator ipaAllocator, MemoryBlock memory, ulong size) : base(memory, size)
|
||||
{
|
||||
_ipaAllocator = ipaAllocator;
|
||||
|
||||
lock (ipaAllocator)
|
||||
{
|
||||
Ipa = ipaAllocator.Allocate(size);
|
||||
}
|
||||
|
||||
HvApi.hv_vm_map((ulong)Memory.Pointer, Ipa, size, hv_memory_flags_t.HV_MEMORY_READ | hv_memory_flags_t.HV_MEMORY_WRITE).ThrowOnError();
|
||||
}
|
||||
|
||||
public override void Destroy()
|
||||
{
|
||||
HvApi.hv_vm_unmap(Ipa, Size).ThrowOnError();
|
||||
|
||||
lock (_ipaAllocator)
|
||||
{
|
||||
_ipaAllocator.Free(Ipa, Size);
|
||||
}
|
||||
|
||||
base.Destroy();
|
||||
}
|
||||
}
|
||||
|
||||
private readonly HvIpaAllocator _ipaAllocator;
|
||||
|
||||
public HvMemoryBlockAllocator(HvIpaAllocator ipaAllocator, int blockAlignment) : base(blockAlignment, MemoryAllocationFlags.None)
|
||||
{
|
||||
_ipaAllocator = ipaAllocator;
|
||||
}
|
||||
|
||||
public unsafe HvMemoryBlockAllocation Allocate(ulong size, ulong alignment)
|
||||
{
|
||||
var allocation = Allocate(size, alignment, CreateBlock);
|
||||
|
||||
return new HvMemoryBlockAllocation(this, allocation.Block, allocation.Offset, allocation.Size);
|
||||
}
|
||||
|
||||
private Block CreateBlock(MemoryBlock memory, ulong size)
|
||||
{
|
||||
return new Block(_ipaAllocator, memory, size);
|
||||
}
|
||||
}
|
||||
}
|
947
Ryujinx.Cpu/AppleHv/HvMemoryManager.cs
Normal file
947
Ryujinx.Cpu/AppleHv/HvMemoryManager.cs
Normal file
@ -0,0 +1,947 @@
|
||||
using ARMeilleure.Memory;
|
||||
using Ryujinx.Cpu.Tracking;
|
||||
using Ryujinx.Memory;
|
||||
using Ryujinx.Memory.Range;
|
||||
using Ryujinx.Memory.Tracking;
|
||||
using System;
|
||||
using System.Collections.Generic;
|
||||
using System.Linq;
|
||||
using System.Runtime.CompilerServices;
|
||||
using System.Runtime.InteropServices;
|
||||
using System.Threading;
|
||||
|
||||
namespace Ryujinx.Cpu.AppleHv
|
||||
{
|
||||
/// <summary>
|
||||
/// Represents a CPU memory manager which maps guest virtual memory directly onto the Hypervisor page table.
|
||||
/// </summary>
|
||||
public class HvMemoryManager : MemoryManagerBase, IMemoryManager, IVirtualMemoryManagerTracked, IWritableBlock
|
||||
{
|
||||
public const int PageBits = 12;
|
||||
public const int PageSize = 1 << PageBits;
|
||||
public const int PageMask = PageSize - 1;
|
||||
|
||||
public const int PageToPteShift = 5; // 32 pages (2 bits each) in one ulong page table entry.
|
||||
public const ulong BlockMappedMask = 0x5555555555555555; // First bit of each table entry set.
|
||||
|
||||
private enum HostMappedPtBits : ulong
|
||||
{
|
||||
Unmapped = 0,
|
||||
Mapped,
|
||||
WriteTracked,
|
||||
ReadWriteTracked,
|
||||
|
||||
MappedReplicated = 0x5555555555555555,
|
||||
WriteTrackedReplicated = 0xaaaaaaaaaaaaaaaa,
|
||||
ReadWriteTrackedReplicated = ulong.MaxValue
|
||||
}
|
||||
|
||||
private readonly InvalidAccessHandler _invalidAccessHandler;
|
||||
|
||||
private readonly ulong _addressSpaceSize;
|
||||
|
||||
private readonly HvAddressSpace _addressSpace;
|
||||
|
||||
internal HvAddressSpace AddressSpace => _addressSpace;
|
||||
|
||||
private readonly MemoryBlock _backingMemory;
|
||||
private readonly PageTable<ulong> _pageTable;
|
||||
|
||||
private readonly ulong[] _pageBitmap;
|
||||
|
||||
public bool Supports4KBPages => true;
|
||||
|
||||
public int AddressSpaceBits { get; }
|
||||
|
||||
public IntPtr PageTablePointer => IntPtr.Zero;
|
||||
|
||||
public MemoryManagerType Type => MemoryManagerType.SoftwarePageTable;
|
||||
|
||||
public MemoryTracking Tracking { get; }
|
||||
|
||||
public event Action<ulong, ulong> UnmapEvent;
|
||||
|
||||
/// <summary>
|
||||
/// Creates a new instance of the Hypervisor memory manager.
|
||||
/// </summary>
|
||||
/// <param name="backingMemory">Physical backing memory where virtual memory will be mapped to</param>
|
||||
/// <param name="addressSpaceSize">Size of the address space</param>
|
||||
/// <param name="invalidAccessHandler">Optional function to handle invalid memory accesses</param>
|
||||
public HvMemoryManager(MemoryBlock backingMemory, ulong addressSpaceSize, InvalidAccessHandler invalidAccessHandler = null)
|
||||
{
|
||||
_backingMemory = backingMemory;
|
||||
_pageTable = new PageTable<ulong>();
|
||||
_invalidAccessHandler = invalidAccessHandler;
|
||||
_addressSpaceSize = addressSpaceSize;
|
||||
|
||||
ulong asSize = PageSize;
|
||||
int asBits = PageBits;
|
||||
|
||||
while (asSize < addressSpaceSize)
|
||||
{
|
||||
asSize <<= 1;
|
||||
asBits++;
|
||||
}
|
||||
|
||||
_addressSpace = new HvAddressSpace(backingMemory, asSize);
|
||||
|
||||
AddressSpaceBits = asBits;
|
||||
|
||||
_pageBitmap = new ulong[1 << (AddressSpaceBits - (PageBits + PageToPteShift))];
|
||||
Tracking = new MemoryTracking(this, PageSize, invalidAccessHandler);
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// Checks if the virtual address is part of the addressable space.
|
||||
/// </summary>
|
||||
/// <param name="va">Virtual address</param>
|
||||
/// <returns>True if the virtual address is part of the addressable space</returns>
|
||||
private bool ValidateAddress(ulong va)
|
||||
{
|
||||
return va < _addressSpaceSize;
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// Checks if the combination of virtual address and size is part of the addressable space.
|
||||
/// </summary>
|
||||
/// <param name="va">Virtual address of the range</param>
|
||||
/// <param name="size">Size of the range in bytes</param>
|
||||
/// <returns>True if the combination of virtual address and size is part of the addressable space</returns>
|
||||
private bool ValidateAddressAndSize(ulong va, ulong size)
|
||||
{
|
||||
ulong endVa = va + size;
|
||||
return endVa >= va && endVa >= size && endVa <= _addressSpaceSize;
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// Ensures the combination of virtual address and size is part of the addressable space.
|
||||
/// </summary>
|
||||
/// <param name="va">Virtual address of the range</param>
|
||||
/// <param name="size">Size of the range in bytes</param>
|
||||
/// <exception cref="InvalidMemoryRegionException">Throw when the memory region specified outside the addressable space</exception>
|
||||
private void AssertValidAddressAndSize(ulong va, ulong size)
|
||||
{
|
||||
if (!ValidateAddressAndSize(va, size))
|
||||
{
|
||||
throw new InvalidMemoryRegionException($"va=0x{va:X16}, size=0x{size:X16}");
|
||||
}
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// Ensures the combination of virtual address and size is part of the addressable space and fully mapped.
|
||||
/// </summary>
|
||||
/// <param name="va">Virtual address of the range</param>
|
||||
/// <param name="size">Size of the range in bytes</param>
|
||||
private void AssertMapped(ulong va, ulong size)
|
||||
{
|
||||
if (!ValidateAddressAndSize(va, size) || !IsRangeMappedImpl(va, size))
|
||||
{
|
||||
throw new InvalidMemoryRegionException($"Not mapped: va=0x{va:X16}, size=0x{size:X16}");
|
||||
}
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public void Map(ulong va, ulong pa, ulong size, MemoryMapFlags flags)
|
||||
{
|
||||
AssertValidAddressAndSize(va, size);
|
||||
|
||||
PtMap(va, pa, size);
|
||||
_addressSpace.MapUser(va, pa, size, MemoryPermission.ReadWriteExecute);
|
||||
AddMapping(va, size);
|
||||
|
||||
Tracking.Map(va, size);
|
||||
}
|
||||
|
||||
private void PtMap(ulong va, ulong pa, ulong size)
|
||||
{
|
||||
while (size != 0)
|
||||
{
|
||||
_pageTable.Map(va, pa);
|
||||
|
||||
va += PageSize;
|
||||
pa += PageSize;
|
||||
size -= PageSize;
|
||||
}
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public void MapForeign(ulong va, nuint hostPointer, ulong size)
|
||||
{
|
||||
throw new NotSupportedException();
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public void Unmap(ulong va, ulong size)
|
||||
{
|
||||
AssertValidAddressAndSize(va, size);
|
||||
|
||||
UnmapEvent?.Invoke(va, size);
|
||||
Tracking.Unmap(va, size);
|
||||
|
||||
RemoveMapping(va, size);
|
||||
_addressSpace.UnmapUser(va, size);
|
||||
PtUnmap(va, size);
|
||||
}
|
||||
|
||||
private void PtUnmap(ulong va, ulong size)
|
||||
{
|
||||
while (size != 0)
|
||||
{
|
||||
_pageTable.Unmap(va);
|
||||
|
||||
va += PageSize;
|
||||
size -= PageSize;
|
||||
}
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public T Read<T>(ulong va) where T : unmanaged
|
||||
{
|
||||
return MemoryMarshal.Cast<byte, T>(GetSpan(va, Unsafe.SizeOf<T>()))[0];
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public T ReadTracked<T>(ulong va) where T : unmanaged
|
||||
{
|
||||
try
|
||||
{
|
||||
SignalMemoryTracking(va, (ulong)Unsafe.SizeOf<T>(), false);
|
||||
|
||||
return Read<T>(va);
|
||||
}
|
||||
catch (InvalidMemoryRegionException)
|
||||
{
|
||||
if (_invalidAccessHandler == null || !_invalidAccessHandler(va))
|
||||
{
|
||||
throw;
|
||||
}
|
||||
|
||||
return default;
|
||||
}
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public void Read(ulong va, Span<byte> data)
|
||||
{
|
||||
ReadImpl(va, data);
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public void Write<T>(ulong va, T value) where T : unmanaged
|
||||
{
|
||||
Write(va, MemoryMarshal.Cast<T, byte>(MemoryMarshal.CreateSpan(ref value, 1)));
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public void Write(ulong va, ReadOnlySpan<byte> data)
|
||||
{
|
||||
if (data.Length == 0)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
SignalMemoryTracking(va, (ulong)data.Length, true);
|
||||
|
||||
WriteImpl(va, data);
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public void WriteUntracked(ulong va, ReadOnlySpan<byte> data)
|
||||
{
|
||||
if (data.Length == 0)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
WriteImpl(va, data);
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public bool WriteWithRedundancyCheck(ulong va, ReadOnlySpan<byte> data)
|
||||
{
|
||||
if (data.Length == 0)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
SignalMemoryTracking(va, (ulong)data.Length, false);
|
||||
|
||||
if (IsContiguousAndMapped(va, data.Length))
|
||||
{
|
||||
var target = _backingMemory.GetSpan(GetPhysicalAddressInternal(va), data.Length);
|
||||
|
||||
bool changed = !data.SequenceEqual(target);
|
||||
|
||||
if (changed)
|
||||
{
|
||||
data.CopyTo(target);
|
||||
}
|
||||
|
||||
return changed;
|
||||
}
|
||||
else
|
||||
{
|
||||
WriteImpl(va, data);
|
||||
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
private void WriteImpl(ulong va, ReadOnlySpan<byte> data)
|
||||
{
|
||||
try
|
||||
{
|
||||
AssertValidAddressAndSize(va, (ulong)data.Length);
|
||||
|
||||
if (IsContiguousAndMapped(va, data.Length))
|
||||
{
|
||||
data.CopyTo(_backingMemory.GetSpan(GetPhysicalAddressInternal(va), data.Length));
|
||||
}
|
||||
else
|
||||
{
|
||||
int offset = 0, size;
|
||||
|
||||
if ((va & PageMask) != 0)
|
||||
{
|
||||
ulong pa = GetPhysicalAddressChecked(va);
|
||||
|
||||
size = Math.Min(data.Length, PageSize - (int)(va & PageMask));
|
||||
|
||||
data.Slice(0, size).CopyTo(_backingMemory.GetSpan(pa, size));
|
||||
|
||||
offset += size;
|
||||
}
|
||||
|
||||
for (; offset < data.Length; offset += size)
|
||||
{
|
||||
ulong pa = GetPhysicalAddressChecked(va + (ulong)offset);
|
||||
|
||||
size = Math.Min(data.Length - offset, PageSize);
|
||||
|
||||
data.Slice(offset, size).CopyTo(_backingMemory.GetSpan(pa, size));
|
||||
}
|
||||
}
|
||||
}
|
||||
catch (InvalidMemoryRegionException)
|
||||
{
|
||||
if (_invalidAccessHandler == null || !_invalidAccessHandler(va))
|
||||
{
|
||||
throw;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public ReadOnlySpan<byte> GetSpan(ulong va, int size, bool tracked = false)
|
||||
{
|
||||
if (size == 0)
|
||||
{
|
||||
return ReadOnlySpan<byte>.Empty;
|
||||
}
|
||||
|
||||
if (tracked)
|
||||
{
|
||||
SignalMemoryTracking(va, (ulong)size, false);
|
||||
}
|
||||
|
||||
if (IsContiguousAndMapped(va, size))
|
||||
{
|
||||
return _backingMemory.GetSpan(GetPhysicalAddressInternal(va), size);
|
||||
}
|
||||
else
|
||||
{
|
||||
Span<byte> data = new byte[size];
|
||||
|
||||
ReadImpl(va, data);
|
||||
|
||||
return data;
|
||||
}
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public WritableRegion GetWritableRegion(ulong va, int size, bool tracked = false)
|
||||
{
|
||||
if (size == 0)
|
||||
{
|
||||
return new WritableRegion(null, va, Memory<byte>.Empty);
|
||||
}
|
||||
|
||||
if (tracked)
|
||||
{
|
||||
SignalMemoryTracking(va, (ulong)size, true);
|
||||
}
|
||||
|
||||
if (IsContiguousAndMapped(va, size))
|
||||
{
|
||||
return new WritableRegion(null, va, _backingMemory.GetMemory(GetPhysicalAddressInternal(va), size));
|
||||
}
|
||||
else
|
||||
{
|
||||
Memory<byte> memory = new byte[size];
|
||||
|
||||
ReadImpl(va, memory.Span);
|
||||
|
||||
return new WritableRegion(this, va, memory);
|
||||
}
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public ref T GetRef<T>(ulong va) where T : unmanaged
|
||||
{
|
||||
if (!IsContiguous(va, Unsafe.SizeOf<T>()))
|
||||
{
|
||||
ThrowMemoryNotContiguous();
|
||||
}
|
||||
|
||||
SignalMemoryTracking(va, (ulong)Unsafe.SizeOf<T>(), true);
|
||||
|
||||
return ref _backingMemory.GetRef<T>(GetPhysicalAddressChecked(va));
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
[MethodImpl(MethodImplOptions.AggressiveInlining)]
|
||||
public bool IsMapped(ulong va)
|
||||
{
|
||||
return ValidateAddress(va) && IsMappedImpl(va);
|
||||
}
|
||||
|
||||
[MethodImpl(MethodImplOptions.AggressiveInlining)]
|
||||
private bool IsMappedImpl(ulong va)
|
||||
{
|
||||
ulong page = va >> PageBits;
|
||||
|
||||
int bit = (int)((page & 31) << 1);
|
||||
|
||||
int pageIndex = (int)(page >> PageToPteShift);
|
||||
ref ulong pageRef = ref _pageBitmap[pageIndex];
|
||||
|
||||
ulong pte = Volatile.Read(ref pageRef);
|
||||
|
||||
return ((pte >> bit) & 3) != 0;
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public bool IsRangeMapped(ulong va, ulong size)
|
||||
{
|
||||
AssertValidAddressAndSize(va, size);
|
||||
|
||||
return IsRangeMappedImpl(va, size);
|
||||
}
|
||||
|
||||
[MethodImpl(MethodImplOptions.AggressiveInlining)]
|
||||
private void GetPageBlockRange(ulong pageStart, ulong pageEnd, out ulong startMask, out ulong endMask, out int pageIndex, out int pageEndIndex)
|
||||
{
|
||||
startMask = ulong.MaxValue << ((int)(pageStart & 31) << 1);
|
||||
endMask = ulong.MaxValue >> (64 - ((int)(pageEnd & 31) << 1));
|
||||
|
||||
pageIndex = (int)(pageStart >> PageToPteShift);
|
||||
pageEndIndex = (int)((pageEnd - 1) >> PageToPteShift);
|
||||
}
|
||||
|
||||
private bool IsRangeMappedImpl(ulong va, ulong size)
|
||||
{
|
||||
int pages = GetPagesCount(va, size, out _);
|
||||
|
||||
if (pages == 1)
|
||||
{
|
||||
return IsMappedImpl(va);
|
||||
}
|
||||
|
||||
ulong pageStart = va >> PageBits;
|
||||
ulong pageEnd = pageStart + (ulong)pages;
|
||||
|
||||
GetPageBlockRange(pageStart, pageEnd, out ulong startMask, out ulong endMask, out int pageIndex, out int pageEndIndex);
|
||||
|
||||
// Check if either bit in each 2 bit page entry is set.
|
||||
// OR the block with itself shifted down by 1, and check the first bit of each entry.
|
||||
|
||||
ulong mask = BlockMappedMask & startMask;
|
||||
|
||||
while (pageIndex <= pageEndIndex)
|
||||
{
|
||||
if (pageIndex == pageEndIndex)
|
||||
{
|
||||
mask &= endMask;
|
||||
}
|
||||
|
||||
ref ulong pageRef = ref _pageBitmap[pageIndex++];
|
||||
ulong pte = Volatile.Read(ref pageRef);
|
||||
|
||||
pte |= pte >> 1;
|
||||
if ((pte & mask) != mask)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
mask = BlockMappedMask;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
private static void ThrowMemoryNotContiguous() => throw new MemoryNotContiguousException();
|
||||
|
||||
[MethodImpl(MethodImplOptions.AggressiveInlining)]
|
||||
private bool IsContiguousAndMapped(ulong va, int size) => IsContiguous(va, size) && IsMapped(va);
|
||||
|
||||
[MethodImpl(MethodImplOptions.AggressiveInlining)]
|
||||
private bool IsContiguous(ulong va, int size)
|
||||
{
|
||||
if (!ValidateAddress(va) || !ValidateAddressAndSize(va, (ulong)size))
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
int pages = GetPagesCount(va, (uint)size, out va);
|
||||
|
||||
for (int page = 0; page < pages - 1; page++)
|
||||
{
|
||||
if (!ValidateAddress(va + PageSize))
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
if (GetPhysicalAddressInternal(va) + PageSize != GetPhysicalAddressInternal(va + PageSize))
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
va += PageSize;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public IEnumerable<HostMemoryRange> GetHostRegions(ulong va, ulong size)
|
||||
{
|
||||
if (size == 0)
|
||||
{
|
||||
return Enumerable.Empty<HostMemoryRange>();
|
||||
}
|
||||
|
||||
var guestRegions = GetPhysicalRegionsImpl(va, size);
|
||||
if (guestRegions == null)
|
||||
{
|
||||
return null;
|
||||
}
|
||||
|
||||
var regions = new HostMemoryRange[guestRegions.Count];
|
||||
|
||||
for (int i = 0; i < regions.Length; i++)
|
||||
{
|
||||
var guestRegion = guestRegions[i];
|
||||
IntPtr pointer = _backingMemory.GetPointer(guestRegion.Address, guestRegion.Size);
|
||||
regions[i] = new HostMemoryRange((nuint)(ulong)pointer, guestRegion.Size);
|
||||
}
|
||||
|
||||
return regions;
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public IEnumerable<MemoryRange> GetPhysicalRegions(ulong va, ulong size)
|
||||
{
|
||||
if (size == 0)
|
||||
{
|
||||
return Enumerable.Empty<MemoryRange>();
|
||||
}
|
||||
|
||||
return GetPhysicalRegionsImpl(va, size);
|
||||
}
|
||||
|
||||
private List<MemoryRange> GetPhysicalRegionsImpl(ulong va, ulong size)
|
||||
{
|
||||
if (!ValidateAddress(va) || !ValidateAddressAndSize(va, size))
|
||||
{
|
||||
return null;
|
||||
}
|
||||
|
||||
int pages = GetPagesCount(va, (uint)size, out va);
|
||||
|
||||
var regions = new List<MemoryRange>();
|
||||
|
||||
ulong regionStart = GetPhysicalAddressInternal(va);
|
||||
ulong regionSize = PageSize;
|
||||
|
||||
for (int page = 0; page < pages - 1; page++)
|
||||
{
|
||||
if (!ValidateAddress(va + PageSize))
|
||||
{
|
||||
return null;
|
||||
}
|
||||
|
||||
ulong newPa = GetPhysicalAddressInternal(va + PageSize);
|
||||
|
||||
if (GetPhysicalAddressInternal(va) + PageSize != newPa)
|
||||
{
|
||||
regions.Add(new MemoryRange(regionStart, regionSize));
|
||||
regionStart = newPa;
|
||||
regionSize = 0;
|
||||
}
|
||||
|
||||
va += PageSize;
|
||||
regionSize += PageSize;
|
||||
}
|
||||
|
||||
regions.Add(new MemoryRange(regionStart, regionSize));
|
||||
|
||||
return regions;
|
||||
}
|
||||
|
||||
private void ReadImpl(ulong va, Span<byte> data)
|
||||
{
|
||||
if (data.Length == 0)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
try
|
||||
{
|
||||
AssertValidAddressAndSize(va, (ulong)data.Length);
|
||||
|
||||
int offset = 0, size;
|
||||
|
||||
if ((va & PageMask) != 0)
|
||||
{
|
||||
ulong pa = GetPhysicalAddressChecked(va);
|
||||
|
||||
size = Math.Min(data.Length, PageSize - (int)(va & PageMask));
|
||||
|
||||
_backingMemory.GetSpan(pa, size).CopyTo(data.Slice(0, size));
|
||||
|
||||
offset += size;
|
||||
}
|
||||
|
||||
for (; offset < data.Length; offset += size)
|
||||
{
|
||||
ulong pa = GetPhysicalAddressChecked(va + (ulong)offset);
|
||||
|
||||
size = Math.Min(data.Length - offset, PageSize);
|
||||
|
||||
_backingMemory.GetSpan(pa, size).CopyTo(data.Slice(offset, size));
|
||||
}
|
||||
}
|
||||
catch (InvalidMemoryRegionException)
|
||||
{
|
||||
if (_invalidAccessHandler == null || !_invalidAccessHandler(va))
|
||||
{
|
||||
throw;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
/// <remarks>
|
||||
/// This function also validates that the given range is both valid and mapped, and will throw if it is not.
|
||||
/// </remarks>
|
||||
public void SignalMemoryTracking(ulong va, ulong size, bool write, bool precise = false)
|
||||
{
|
||||
AssertValidAddressAndSize(va, size);
|
||||
|
||||
if (precise)
|
||||
{
|
||||
Tracking.VirtualMemoryEvent(va, size, write, precise: true);
|
||||
return;
|
||||
}
|
||||
|
||||
// Software table, used for managed memory tracking.
|
||||
|
||||
int pages = GetPagesCount(va, size, out _);
|
||||
ulong pageStart = va >> PageBits;
|
||||
|
||||
if (pages == 1)
|
||||
{
|
||||
ulong tag = (ulong)(write ? HostMappedPtBits.WriteTracked : HostMappedPtBits.ReadWriteTracked);
|
||||
|
||||
int bit = (int)((pageStart & 31) << 1);
|
||||
|
||||
int pageIndex = (int)(pageStart >> PageToPteShift);
|
||||
ref ulong pageRef = ref _pageBitmap[pageIndex];
|
||||
|
||||
ulong pte = Volatile.Read(ref pageRef);
|
||||
ulong state = ((pte >> bit) & 3);
|
||||
|
||||
if (state >= tag)
|
||||
{
|
||||
Tracking.VirtualMemoryEvent(va, size, write);
|
||||
return;
|
||||
}
|
||||
else if (state == 0)
|
||||
{
|
||||
ThrowInvalidMemoryRegionException($"Not mapped: va=0x{va:X16}, size=0x{size:X16}");
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
ulong pageEnd = pageStart + (ulong)pages;
|
||||
|
||||
GetPageBlockRange(pageStart, pageEnd, out ulong startMask, out ulong endMask, out int pageIndex, out int pageEndIndex);
|
||||
|
||||
ulong mask = startMask;
|
||||
|
||||
ulong anyTrackingTag = (ulong)HostMappedPtBits.WriteTrackedReplicated;
|
||||
|
||||
while (pageIndex <= pageEndIndex)
|
||||
{
|
||||
if (pageIndex == pageEndIndex)
|
||||
{
|
||||
mask &= endMask;
|
||||
}
|
||||
|
||||
ref ulong pageRef = ref _pageBitmap[pageIndex++];
|
||||
|
||||
ulong pte = Volatile.Read(ref pageRef);
|
||||
ulong mappedMask = mask & BlockMappedMask;
|
||||
|
||||
ulong mappedPte = pte | (pte >> 1);
|
||||
if ((mappedPte & mappedMask) != mappedMask)
|
||||
{
|
||||
ThrowInvalidMemoryRegionException($"Not mapped: va=0x{va:X16}, size=0x{size:X16}");
|
||||
}
|
||||
|
||||
pte &= mask;
|
||||
if ((pte & anyTrackingTag) != 0) // Search for any tracking.
|
||||
{
|
||||
// Writes trigger any tracking.
|
||||
// Only trigger tracking from reads if both bits are set on any page.
|
||||
if (write || (pte & (pte >> 1) & BlockMappedMask) != 0)
|
||||
{
|
||||
Tracking.VirtualMemoryEvent(va, size, write);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
mask = ulong.MaxValue;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// Computes the number of pages in a virtual address range.
|
||||
/// </summary>
|
||||
/// <param name="va">Virtual address of the range</param>
|
||||
/// <param name="size">Size of the range</param>
|
||||
/// <param name="startVa">The virtual address of the beginning of the first page</param>
|
||||
/// <remarks>This function does not differentiate between allocated and unallocated pages.</remarks>
|
||||
[MethodImpl(MethodImplOptions.AggressiveInlining)]
|
||||
private int GetPagesCount(ulong va, ulong size, out ulong startVa)
|
||||
{
|
||||
// WARNING: Always check if ulong does not overflow during the operations.
|
||||
startVa = va & ~(ulong)PageMask;
|
||||
ulong vaSpan = (va - startVa + size + PageMask) & ~(ulong)PageMask;
|
||||
|
||||
return (int)(vaSpan / PageSize);
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public void TrackingReprotect(ulong va, ulong size, MemoryPermission protection)
|
||||
{
|
||||
// Protection is inverted on software pages, since the default value is 0.
|
||||
protection = (~protection) & MemoryPermission.ReadAndWrite;
|
||||
|
||||
int pages = GetPagesCount(va, size, out va);
|
||||
ulong pageStart = va >> PageBits;
|
||||
|
||||
if (pages == 1)
|
||||
{
|
||||
ulong protTag = protection switch
|
||||
{
|
||||
MemoryPermission.None => (ulong)HostMappedPtBits.Mapped,
|
||||
MemoryPermission.Write => (ulong)HostMappedPtBits.WriteTracked,
|
||||
_ => (ulong)HostMappedPtBits.ReadWriteTracked,
|
||||
};
|
||||
|
||||
int bit = (int)((pageStart & 31) << 1);
|
||||
|
||||
ulong tagMask = 3UL << bit;
|
||||
ulong invTagMask = ~tagMask;
|
||||
|
||||
ulong tag = protTag << bit;
|
||||
|
||||
int pageIndex = (int)(pageStart >> PageToPteShift);
|
||||
ref ulong pageRef = ref _pageBitmap[pageIndex];
|
||||
|
||||
ulong pte;
|
||||
|
||||
do
|
||||
{
|
||||
pte = Volatile.Read(ref pageRef);
|
||||
}
|
||||
while ((pte & tagMask) != 0 && Interlocked.CompareExchange(ref pageRef, (pte & invTagMask) | tag, pte) != pte);
|
||||
}
|
||||
else
|
||||
{
|
||||
ulong pageEnd = pageStart + (ulong)pages;
|
||||
|
||||
GetPageBlockRange(pageStart, pageEnd, out ulong startMask, out ulong endMask, out int pageIndex, out int pageEndIndex);
|
||||
|
||||
ulong mask = startMask;
|
||||
|
||||
ulong protTag = protection switch
|
||||
{
|
||||
MemoryPermission.None => (ulong)HostMappedPtBits.MappedReplicated,
|
||||
MemoryPermission.Write => (ulong)HostMappedPtBits.WriteTrackedReplicated,
|
||||
_ => (ulong)HostMappedPtBits.ReadWriteTrackedReplicated,
|
||||
};
|
||||
|
||||
while (pageIndex <= pageEndIndex)
|
||||
{
|
||||
if (pageIndex == pageEndIndex)
|
||||
{
|
||||
mask &= endMask;
|
||||
}
|
||||
|
||||
ref ulong pageRef = ref _pageBitmap[pageIndex++];
|
||||
|
||||
ulong pte;
|
||||
ulong mappedMask;
|
||||
|
||||
// Change the protection of all 2 bit entries that are mapped.
|
||||
do
|
||||
{
|
||||
pte = Volatile.Read(ref pageRef);
|
||||
|
||||
mappedMask = pte | (pte >> 1);
|
||||
mappedMask |= (mappedMask & BlockMappedMask) << 1;
|
||||
mappedMask &= mask; // Only update mapped pages within the given range.
|
||||
}
|
||||
while (Interlocked.CompareExchange(ref pageRef, (pte & (~mappedMask)) | (protTag & mappedMask), pte) != pte);
|
||||
|
||||
mask = ulong.MaxValue;
|
||||
}
|
||||
}
|
||||
|
||||
protection = protection switch
|
||||
{
|
||||
MemoryPermission.None => MemoryPermission.ReadAndWrite,
|
||||
MemoryPermission.Write => MemoryPermission.Read,
|
||||
_ => MemoryPermission.None
|
||||
};
|
||||
|
||||
_addressSpace.ReprotectUser(va, size, protection);
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public CpuRegionHandle BeginTracking(ulong address, ulong size)
|
||||
{
|
||||
return new CpuRegionHandle(Tracking.BeginTracking(address, size));
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public CpuMultiRegionHandle BeginGranularTracking(ulong address, ulong size, IEnumerable<IRegionHandle> handles, ulong granularity)
|
||||
{
|
||||
return new CpuMultiRegionHandle(Tracking.BeginGranularTracking(address, size, handles, granularity));
|
||||
}
|
||||
|
||||
/// <inheritdoc/>
|
||||
public CpuSmartMultiRegionHandle BeginSmartGranularTracking(ulong address, ulong size, ulong granularity)
|
||||
{
|
||||
return new CpuSmartMultiRegionHandle(Tracking.BeginSmartGranularTracking(address, size, granularity));
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// Adds the given address mapping to the page table.
|
||||
/// </summary>
|
||||
/// <param name="va">Virtual memory address</param>
|
||||
/// <param name="size">Size to be mapped</param>
|
||||
private void AddMapping(ulong va, ulong size)
|
||||
{
|
||||
int pages = GetPagesCount(va, size, out _);
|
||||
ulong pageStart = va >> PageBits;
|
||||
ulong pageEnd = pageStart + (ulong)pages;
|
||||
|
||||
GetPageBlockRange(pageStart, pageEnd, out ulong startMask, out ulong endMask, out int pageIndex, out int pageEndIndex);
|
||||
|
||||
ulong mask = startMask;
|
||||
|
||||
while (pageIndex <= pageEndIndex)
|
||||
{
|
||||
if (pageIndex == pageEndIndex)
|
||||
{
|
||||
mask &= endMask;
|
||||
}
|
||||
|
||||
ref ulong pageRef = ref _pageBitmap[pageIndex++];
|
||||
|
||||
ulong pte;
|
||||
ulong mappedMask;
|
||||
|
||||
// Map all 2-bit entries that are unmapped.
|
||||
do
|
||||
{
|
||||
pte = Volatile.Read(ref pageRef);
|
||||
|
||||
mappedMask = pte | (pte >> 1);
|
||||
mappedMask |= (mappedMask & BlockMappedMask) << 1;
|
||||
mappedMask |= ~mask; // Treat everything outside the range as mapped, thus unchanged.
|
||||
}
|
||||
while (Interlocked.CompareExchange(ref pageRef, (pte & mappedMask) | (BlockMappedMask & (~mappedMask)), pte) != pte);
|
||||
|
||||
mask = ulong.MaxValue;
|
||||
}
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// Removes the given address mapping from the page table.
|
||||
/// </summary>
|
||||
/// <param name="va">Virtual memory address</param>
|
||||
/// <param name="size">Size to be unmapped</param>
|
||||
private void RemoveMapping(ulong va, ulong size)
|
||||
{
|
||||
int pages = GetPagesCount(va, size, out _);
|
||||
ulong pageStart = va >> PageBits;
|
||||
ulong pageEnd = pageStart + (ulong)pages;
|
||||
|
||||
GetPageBlockRange(pageStart, pageEnd, out ulong startMask, out ulong endMask, out int pageIndex, out int pageEndIndex);
|
||||
|
||||
startMask = ~startMask;
|
||||
endMask = ~endMask;
|
||||
|
||||
ulong mask = startMask;
|
||||
|
||||
while (pageIndex <= pageEndIndex)
|
||||
{
|
||||
if (pageIndex == pageEndIndex)
|
||||
{
|
||||
mask |= endMask;
|
||||
}
|
||||
|
||||
ref ulong pageRef = ref _pageBitmap[pageIndex++];
|
||||
ulong pte;
|
||||
|
||||
do
|
||||
{
|
||||
pte = Volatile.Read(ref pageRef);
|
||||
}
|
||||
while (Interlocked.CompareExchange(ref pageRef, pte & mask, pte) != pte);
|
||||
|
||||
mask = 0;
|
||||
}
|
||||
}
|
||||
|
||||
private ulong GetPhysicalAddressChecked(ulong va)
|
||||
{
|
||||
if (!IsMapped(va))
|
||||
{
|
||||
ThrowInvalidMemoryRegionException($"Not mapped: va=0x{va:X16}");
|
||||
}
|
||||
|
||||
return GetPhysicalAddressInternal(va);
|
||||
}
|
||||
|
||||
private ulong GetPhysicalAddressInternal(ulong va)
|
||||
{
|
||||
return _pageTable.Read(va) + (va & PageMask);
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// Disposes of resources used by the memory manager.
|
||||
/// </summary>
|
||||
protected override void Destroy()
|
||||
{
|
||||
_addressSpace.Dispose();
|
||||
}
|
||||
|
||||
private static void ThrowInvalidMemoryRegionException(string message) => throw new InvalidMemoryRegionException(message);
|
||||
}
|
||||
}
|
25
Ryujinx.Cpu/AppleHv/HvVcpu.cs
Normal file
25
Ryujinx.Cpu/AppleHv/HvVcpu.cs
Normal file
@ -0,0 +1,25 @@
|
||||
namespace Ryujinx.Cpu.AppleHv
|
||||
{
|
||||
unsafe class HvVcpu
|
||||
{
|
||||
public readonly ulong Handle;
|
||||
public readonly hv_vcpu_exit_t* ExitInfo;
|
||||
public readonly IHvExecutionContext ShadowContext;
|
||||
public readonly IHvExecutionContext NativeContext;
|
||||
public readonly bool IsEphemeral;
|
||||
|
||||
public HvVcpu(
|
||||
ulong handle,
|
||||
hv_vcpu_exit_t* exitInfo,
|
||||
IHvExecutionContext shadowContext,
|
||||
IHvExecutionContext nativeContext,
|
||||
bool isEphemeral)
|
||||
{
|
||||
Handle = handle;
|
||||
ExitInfo = exitInfo;
|
||||
ShadowContext = shadowContext;
|
||||
NativeContext = nativeContext;
|
||||
IsEphemeral = isEphemeral;
|
||||
}
|
||||
}
|
||||
}
|
103
Ryujinx.Cpu/AppleHv/HvVcpuPool.cs
Normal file
103
Ryujinx.Cpu/AppleHv/HvVcpuPool.cs
Normal file
@ -0,0 +1,103 @@
|
||||
using System;
|
||||
using System.Threading;
|
||||
|
||||
namespace Ryujinx.Cpu.AppleHv
|
||||
{
|
||||
class HvVcpuPool
|
||||
{
|
||||
// Since there's a limit on the number of VCPUs we can create,
|
||||
// and we assign one VCPU per guest thread, we need to ensure
|
||||
// there are enough VCPUs available for at least the maximum number of active guest threads.
|
||||
// To do that, we always destroy and re-create VCPUs that are above a given limit.
|
||||
// Those VCPUs are called "ephemeral" here because they are not kept for long.
|
||||
//
|
||||
// In the future, we might want to consider a smarter approach that only makes
|
||||
// VCPUs for threads that are not running frequently "ephemeral", but this is
|
||||
// complicated because VCPUs can only be destroyed by the same thread that created them.
|
||||
|
||||
private const int MaxActiveVcpus = 4;
|
||||
|
||||
public static readonly HvVcpuPool Instance = new HvVcpuPool();
|
||||
|
||||
private int _totalVcpus;
|
||||
private int _maxVcpus;
|
||||
|
||||
public HvVcpuPool()
|
||||
{
|
||||
HvApi.hv_vm_get_max_vcpu_count(out uint maxVcpuCount).ThrowOnError();
|
||||
_maxVcpus = (int)maxVcpuCount;
|
||||
}
|
||||
|
||||
public HvVcpu Create(HvAddressSpace addressSpace, IHvExecutionContext shadowContext, Action<IHvExecutionContext> swapContext)
|
||||
{
|
||||
HvVcpu vcpu = CreateNew(addressSpace, shadowContext);
|
||||
vcpu.NativeContext.Load(shadowContext);
|
||||
swapContext(vcpu.NativeContext);
|
||||
return vcpu;
|
||||
}
|
||||
|
||||
public void Destroy(HvVcpu vcpu, Action<IHvExecutionContext> swapContext)
|
||||
{
|
||||
vcpu.ShadowContext.Load(vcpu.NativeContext);
|
||||
swapContext(vcpu.ShadowContext);
|
||||
DestroyVcpu(vcpu);
|
||||
}
|
||||
|
||||
public void Return(HvVcpu vcpu, Action<IHvExecutionContext> swapContext)
|
||||
{
|
||||
if (vcpu.IsEphemeral)
|
||||
{
|
||||
Destroy(vcpu, swapContext);
|
||||
}
|
||||
}
|
||||
|
||||
public HvVcpu Rent(HvAddressSpace addressSpace, IHvExecutionContext shadowContext, HvVcpu vcpu, Action<IHvExecutionContext> swapContext)
|
||||
{
|
||||
if (vcpu.IsEphemeral)
|
||||
{
|
||||
return Create(addressSpace, shadowContext, swapContext);
|
||||
}
|
||||
else
|
||||
{
|
||||
return vcpu;
|
||||
}
|
||||
}
|
||||
|
||||
private unsafe HvVcpu CreateNew(HvAddressSpace addressSpace, IHvExecutionContext shadowContext)
|
||||
{
|
||||
int newCount = IncrementVcpuCount();
|
||||
bool isEphemeral = newCount > _maxVcpus - MaxActiveVcpus;
|
||||
|
||||
// Create VCPU.
|
||||
hv_vcpu_exit_t* exitInfo = null;
|
||||
HvApi.hv_vcpu_create(out ulong vcpuHandle, ref exitInfo, IntPtr.Zero).ThrowOnError();
|
||||
|
||||
// Enable FP and SIMD instructions.
|
||||
HvApi.hv_vcpu_set_sys_reg(vcpuHandle, hv_sys_reg_t.HV_SYS_REG_CPACR_EL1, 0b11 << 20).ThrowOnError();
|
||||
|
||||
addressSpace.InitializeMmu(vcpuHandle);
|
||||
|
||||
HvExecutionContextVcpu nativeContext = new HvExecutionContextVcpu(vcpuHandle);
|
||||
|
||||
HvVcpu vcpu = new HvVcpu(vcpuHandle, exitInfo, shadowContext, nativeContext, isEphemeral);
|
||||
|
||||
return vcpu;
|
||||
}
|
||||
|
||||
private void DestroyVcpu(HvVcpu vcpu)
|
||||
{
|
||||
HvApi.hv_vcpu_destroy(vcpu.Handle).ThrowOnError();
|
||||
DecrementVcpuCount();
|
||||
}
|
||||
|
||||
private int IncrementVcpuCount()
|
||||
{
|
||||
return Interlocked.Increment(ref _totalVcpus);
|
||||
}
|
||||
|
||||
private void DecrementVcpuCount()
|
||||
{
|
||||
Interlocked.Decrement(ref _totalVcpus);
|
||||
}
|
||||
}
|
||||
}
|
68
Ryujinx.Cpu/AppleHv/HvVm.cs
Normal file
68
Ryujinx.Cpu/AppleHv/HvVm.cs
Normal file
@ -0,0 +1,68 @@
|
||||
using Ryujinx.Memory;
|
||||
using System;
|
||||
|
||||
namespace Ryujinx.Cpu.AppleHv
|
||||
{
|
||||
static class HvVm
|
||||
{
|
||||
// This alignment allows us to use larger blocks on the page table.
|
||||
private const ulong AsIpaAlignment = 1UL << 30;
|
||||
|
||||
private static int _addressSpaces;
|
||||
private static HvIpaAllocator _ipaAllocator;
|
||||
private static object _lock = new object();
|
||||
|
||||
public static (ulong, HvIpaAllocator) CreateAddressSpace(MemoryBlock block)
|
||||
{
|
||||
HvIpaAllocator ipaAllocator;
|
||||
|
||||
lock (_lock)
|
||||
{
|
||||
if (++_addressSpaces == 1)
|
||||
{
|
||||
HvApi.hv_vm_create(IntPtr.Zero).ThrowOnError();
|
||||
_ipaAllocator = ipaAllocator = new HvIpaAllocator();
|
||||
}
|
||||
else
|
||||
{
|
||||
ipaAllocator = _ipaAllocator;
|
||||
}
|
||||
}
|
||||
|
||||
ulong baseAddress;
|
||||
|
||||
lock (ipaAllocator)
|
||||
{
|
||||
baseAddress = ipaAllocator.Allocate(block.Size, AsIpaAlignment);
|
||||
}
|
||||
|
||||
var rwx = hv_memory_flags_t.HV_MEMORY_READ | hv_memory_flags_t.HV_MEMORY_WRITE | hv_memory_flags_t.HV_MEMORY_EXEC;
|
||||
|
||||
HvApi.hv_vm_map((ulong)block.Pointer, baseAddress, block.Size, rwx).ThrowOnError();
|
||||
|
||||
return (baseAddress, ipaAllocator);
|
||||
}
|
||||
|
||||
public static void DestroyAddressSpace(ulong address, ulong size)
|
||||
{
|
||||
HvApi.hv_vm_unmap(address, size);
|
||||
|
||||
HvIpaAllocator ipaAllocator;
|
||||
|
||||
lock (_lock)
|
||||
{
|
||||
if (--_addressSpaces == 0)
|
||||
{
|
||||
HvApi.hv_vm_destroy().ThrowOnError();
|
||||
}
|
||||
|
||||
ipaAllocator = _ipaAllocator;
|
||||
}
|
||||
|
||||
lock (ipaAllocator)
|
||||
{
|
||||
ipaAllocator.Free(address, size);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
46
Ryujinx.Cpu/AppleHv/IHvExecutionContext.cs
Normal file
46
Ryujinx.Cpu/AppleHv/IHvExecutionContext.cs
Normal file
@ -0,0 +1,46 @@
|
||||
using ARMeilleure.State;
|
||||
|
||||
namespace Ryujinx.Cpu.AppleHv
|
||||
{
|
||||
public interface IHvExecutionContext
|
||||
{
|
||||
ulong Pc { get; set; }
|
||||
ulong ElrEl1 { get; set; }
|
||||
ulong EsrEl1 { get; set; }
|
||||
|
||||
long TpidrEl0 { get; set; }
|
||||
long TpidrroEl0 { get; set; }
|
||||
|
||||
uint Pstate { get; set; }
|
||||
|
||||
uint Fpcr { get; set; }
|
||||
uint Fpsr { get; set; }
|
||||
|
||||
ulong GetX(int index);
|
||||
void SetX(int index, ulong value);
|
||||
|
||||
V128 GetV(int index);
|
||||
void SetV(int index, V128 value);
|
||||
|
||||
public void Load(IHvExecutionContext context)
|
||||
{
|
||||
Pc = context.Pc;
|
||||
ElrEl1 = context.ElrEl1;
|
||||
EsrEl1 = context.EsrEl1;
|
||||
TpidrEl0 = context.TpidrEl0;
|
||||
TpidrroEl0 = context.TpidrroEl0;
|
||||
Pstate = context.Pstate;
|
||||
Fpcr = context.Fpcr;
|
||||
Fpsr = context.Fpsr;
|
||||
|
||||
for (int i = 0; i < 32; i++)
|
||||
{
|
||||
SetX(i, context.GetX(i));
|
||||
SetV(i, context.GetV(i));
|
||||
}
|
||||
}
|
||||
|
||||
void RequestInterrupt();
|
||||
bool GetAndClearInterruptRequested();
|
||||
}
|
||||
}
|
@ -22,7 +22,7 @@ namespace Ryujinx.Graphics.Gpu.Shader.DiskCache
|
||||
private const ushort FileFormatVersionMajor = 1;
|
||||
private const ushort FileFormatVersionMinor = 2;
|
||||
private const uint FileFormatVersionPacked = ((uint)FileFormatVersionMajor << 16) | FileFormatVersionMinor;
|
||||
private const uint CodeGenVersion = 4336;
|
||||
private const uint CodeGenVersion = 4369;
|
||||
|
||||
private const string SharedTocFileName = "shared.toc";
|
||||
private const string SharedDataFileName = "shared.data";
|
||||
|
@ -485,6 +485,16 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
|
||||
|
||||
AttributeType type = context.Config.GpuAccessor.QueryAttributeType(location);
|
||||
|
||||
return type.ToAggregateType();
|
||||
}
|
||||
else if (context.Config.Stage == ShaderStage.Fragment && isAsgDest &&
|
||||
operand.Value >= AttributeConsts.FragmentOutputColorBase &&
|
||||
operand.Value < AttributeConsts.FragmentOutputColorEnd)
|
||||
{
|
||||
int location = (operand.Value - AttributeConsts.FragmentOutputColorBase) / 16;
|
||||
|
||||
AttributeType type = context.Config.GpuAccessor.QueryFragmentOutputType(location);
|
||||
|
||||
return type.ToAggregateType();
|
||||
}
|
||||
}
|
||||
|
@ -4,6 +4,7 @@ using System;
|
||||
using System.Diagnostics;
|
||||
using System.Runtime.CompilerServices;
|
||||
using System.Runtime.Intrinsics;
|
||||
using System.Runtime.Intrinsics.Arm;
|
||||
using System.Runtime.Intrinsics.X86;
|
||||
|
||||
namespace Ryujinx.Graphics.Vic
|
||||
@ -17,10 +18,18 @@ namespace Ryujinx.Graphics.Vic
|
||||
int x2 = Math.Min(src.Width, x1 + targetRect.Width);
|
||||
int y2 = Math.Min(src.Height, y1 + targetRect.Height);
|
||||
|
||||
if (Sse41.IsSupported && ((x1 | x2) & 3) == 0)
|
||||
if (((x1 | x2) & 3) == 0)
|
||||
{
|
||||
BlendOneSse41(dst, src, ref slot, x1, y1, x2, y2);
|
||||
return;
|
||||
if (Sse41.IsSupported)
|
||||
{
|
||||
BlendOneSse41(dst, src, ref slot, x1, y1, x2, y2);
|
||||
return;
|
||||
}
|
||||
else if (AdvSimd.IsSupported)
|
||||
{
|
||||
BlendOneAdvSimd(dst, src, ref slot, x1, y1, x2, y2);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
for (int y = y1; y < y2; y++)
|
||||
@ -105,6 +114,84 @@ namespace Ryujinx.Graphics.Vic
|
||||
}
|
||||
}
|
||||
|
||||
private unsafe static void BlendOneAdvSimd(Surface dst, Surface src, ref SlotStruct slot, int x1, int y1, int x2, int y2)
|
||||
{
|
||||
Debug.Assert(((x1 | x2) & 3) == 0);
|
||||
|
||||
ref MatrixStruct mtx = ref slot.ColorMatrixStruct;
|
||||
|
||||
Vector128<int> col1 = Vector128.Create(mtx.MatrixCoeff00, mtx.MatrixCoeff10, mtx.MatrixCoeff20, 0);
|
||||
Vector128<int> col2 = Vector128.Create(mtx.MatrixCoeff01, mtx.MatrixCoeff11, mtx.MatrixCoeff21, 0);
|
||||
Vector128<int> col3 = Vector128.Create(mtx.MatrixCoeff02, mtx.MatrixCoeff12, mtx.MatrixCoeff22, 0);
|
||||
Vector128<int> col4 = Vector128.Create(mtx.MatrixCoeff03, mtx.MatrixCoeff13, mtx.MatrixCoeff23, 0);
|
||||
|
||||
Vector128<int> rShift = Vector128.Create(-mtx.MatrixRShift);
|
||||
Vector128<int> selMask = Vector128.Create(0, 0, 0, -1);
|
||||
Vector128<ushort> clMin = Vector128.Create((ushort)slot.SlotConfig.SoftClampLow);
|
||||
Vector128<ushort> clMax = Vector128.Create((ushort)slot.SlotConfig.SoftClampHigh);
|
||||
|
||||
fixed (Pixel* srcPtr = src.Data, dstPtr = dst.Data)
|
||||
{
|
||||
Pixel* ip = srcPtr;
|
||||
Pixel* op = dstPtr;
|
||||
|
||||
if (mtx.MatrixEnable)
|
||||
{
|
||||
for (int y = y1; y < y2; y++, ip += src.Width, op += dst.Width)
|
||||
{
|
||||
for (int x = x1; x < x2; x += 4)
|
||||
{
|
||||
Vector128<ushort> pixel12 = AdvSimd.LoadVector128((ushort*)(ip + (uint)x));
|
||||
Vector128<ushort> pixel34 = AdvSimd.LoadVector128((ushort*)(ip + (uint)x + 2));
|
||||
|
||||
Vector128<uint> pixel1 = AdvSimd.ZeroExtendWideningLower(pixel12.GetLower());
|
||||
Vector128<uint> pixel2 = AdvSimd.ZeroExtendWideningUpper(pixel12);
|
||||
Vector128<uint> pixel3 = AdvSimd.ZeroExtendWideningLower(pixel34.GetLower());
|
||||
Vector128<uint> pixel4 = AdvSimd.ZeroExtendWideningUpper(pixel34);
|
||||
|
||||
Vector128<int> t1 = MatrixMultiplyAdvSimd(pixel1.AsInt32(), col1, col2, col3, col4, rShift, selMask);
|
||||
Vector128<int> t2 = MatrixMultiplyAdvSimd(pixel2.AsInt32(), col1, col2, col3, col4, rShift, selMask);
|
||||
Vector128<int> t3 = MatrixMultiplyAdvSimd(pixel3.AsInt32(), col1, col2, col3, col4, rShift, selMask);
|
||||
Vector128<int> t4 = MatrixMultiplyAdvSimd(pixel4.AsInt32(), col1, col2, col3, col4, rShift, selMask);
|
||||
|
||||
Vector64<ushort> lower1 = AdvSimd.ExtractNarrowingSaturateUnsignedLower(t1);
|
||||
Vector64<ushort> lower3 = AdvSimd.ExtractNarrowingSaturateUnsignedLower(t3);
|
||||
|
||||
pixel12 = AdvSimd.ExtractNarrowingSaturateUnsignedUpper(lower1, t2);
|
||||
pixel34 = AdvSimd.ExtractNarrowingSaturateUnsignedUpper(lower3, t4);
|
||||
|
||||
pixel12 = AdvSimd.Min(pixel12, clMax);
|
||||
pixel34 = AdvSimd.Min(pixel34, clMax);
|
||||
pixel12 = AdvSimd.Max(pixel12, clMin);
|
||||
pixel34 = AdvSimd.Max(pixel34, clMin);
|
||||
|
||||
AdvSimd.Store((ushort*)(op + (uint)x + 0), pixel12);
|
||||
AdvSimd.Store((ushort*)(op + (uint)x + 2), pixel34);
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
for (int y = y1; y < y2; y++, ip += src.Width, op += dst.Width)
|
||||
{
|
||||
for (int x = x1; x < x2; x += 4)
|
||||
{
|
||||
Vector128<ushort> pixel12 = AdvSimd.LoadVector128((ushort*)(ip + (uint)x));
|
||||
Vector128<ushort> pixel34 = AdvSimd.LoadVector128((ushort*)(ip + (uint)x + 2));
|
||||
|
||||
pixel12 = AdvSimd.Min(pixel12, clMax);
|
||||
pixel34 = AdvSimd.Min(pixel34, clMax);
|
||||
pixel12 = AdvSimd.Max(pixel12, clMin);
|
||||
pixel34 = AdvSimd.Max(pixel34, clMin);
|
||||
|
||||
AdvSimd.Store((ushort*)(op + (uint)x + 0), pixel12);
|
||||
AdvSimd.Store((ushort*)(op + (uint)x + 2), pixel34);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
[MethodImpl(MethodImplOptions.AggressiveInlining)]
|
||||
private static void MatrixMultiply(ref MatrixStruct mtx, int x, int y, int z, out int r, out int g, out int b)
|
||||
{
|
||||
@ -159,5 +246,33 @@ namespace Ryujinx.Graphics.Vic
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
[MethodImpl(MethodImplOptions.AggressiveInlining)]
|
||||
private static Vector128<int> MatrixMultiplyAdvSimd(
|
||||
Vector128<int> pixel,
|
||||
Vector128<int> col1,
|
||||
Vector128<int> col2,
|
||||
Vector128<int> col3,
|
||||
Vector128<int> col4,
|
||||
Vector128<int> rShift,
|
||||
Vector128<int> selectMask)
|
||||
{
|
||||
Vector128<int> x = AdvSimd.DuplicateSelectedScalarToVector128(pixel, 0);
|
||||
Vector128<int> y = AdvSimd.DuplicateSelectedScalarToVector128(pixel, 1);
|
||||
Vector128<int> z = AdvSimd.DuplicateSelectedScalarToVector128(pixel, 2);
|
||||
|
||||
col1 = AdvSimd.Multiply(col1, x);
|
||||
col2 = AdvSimd.Multiply(col2, y);
|
||||
col3 = AdvSimd.Multiply(col3, z);
|
||||
|
||||
Vector128<int> res = AdvSimd.Add(col3, AdvSimd.Add(col1, col2));
|
||||
|
||||
res = AdvSimd.ShiftArithmetic(res, rShift);
|
||||
res = AdvSimd.Add(res, col4);
|
||||
res = AdvSimd.ShiftRightArithmetic(res, 8);
|
||||
res = AdvSimd.BitwiseSelect(selectMask, pixel, res);
|
||||
|
||||
return res;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -5,6 +5,7 @@ using Ryujinx.Graphics.Vic.Types;
|
||||
using System;
|
||||
using System.Runtime.CompilerServices;
|
||||
using System.Runtime.Intrinsics;
|
||||
using System.Runtime.Intrinsics.Arm;
|
||||
using System.Runtime.Intrinsics.X86;
|
||||
using static Ryujinx.Graphics.Vic.Image.SurfaceCommon;
|
||||
|
||||
@ -54,7 +55,7 @@ namespace Ryujinx.Graphics.Vic.Image
|
||||
(byte)4, (byte)6, (byte)7, (byte)5,
|
||||
(byte)8, (byte)10, (byte)11, (byte)9,
|
||||
(byte)12, (byte)14, (byte)15, (byte)13);
|
||||
Vector128<short> alphaMask = Vector128.Create(0xffUL << 48).AsInt16();
|
||||
Vector128<short> alphaMask = Vector128.Create(0xff << 24).AsInt16();
|
||||
|
||||
int yStrideGap = yStride - width;
|
||||
int uvStrideGap = uvStride - input.UvWidth;
|
||||
@ -95,6 +96,11 @@ namespace Ryujinx.Graphics.Vic.Image
|
||||
rgba2 = Ssse3.Shuffle(rgba2.AsByte(), shufMask).AsInt16();
|
||||
rgba3 = Ssse3.Shuffle(rgba3.AsByte(), shufMask).AsInt16();
|
||||
|
||||
rgba0 = Sse2.Or(rgba0, alphaMask);
|
||||
rgba1 = Sse2.Or(rgba1, alphaMask);
|
||||
rgba2 = Sse2.Or(rgba2, alphaMask);
|
||||
rgba3 = Sse2.Or(rgba3, alphaMask);
|
||||
|
||||
Vector128<short> rgba16_0 = Sse41.ConvertToVector128Int16(rgba0.AsByte());
|
||||
Vector128<short> rgba16_1 = Sse41.ConvertToVector128Int16(HighToLow(rgba0.AsByte()));
|
||||
Vector128<short> rgba16_2 = Sse41.ConvertToVector128Int16(rgba1.AsByte());
|
||||
@ -104,15 +110,6 @@ namespace Ryujinx.Graphics.Vic.Image
|
||||
Vector128<short> rgba16_6 = Sse41.ConvertToVector128Int16(rgba3.AsByte());
|
||||
Vector128<short> rgba16_7 = Sse41.ConvertToVector128Int16(HighToLow(rgba3.AsByte()));
|
||||
|
||||
rgba16_0 = Sse2.Or(rgba16_0, alphaMask);
|
||||
rgba16_1 = Sse2.Or(rgba16_1, alphaMask);
|
||||
rgba16_2 = Sse2.Or(rgba16_2, alphaMask);
|
||||
rgba16_3 = Sse2.Or(rgba16_3, alphaMask);
|
||||
rgba16_4 = Sse2.Or(rgba16_4, alphaMask);
|
||||
rgba16_5 = Sse2.Or(rgba16_5, alphaMask);
|
||||
rgba16_6 = Sse2.Or(rgba16_6, alphaMask);
|
||||
rgba16_7 = Sse2.Or(rgba16_7, alphaMask);
|
||||
|
||||
rgba16_0 = Sse2.ShiftLeftLogical(rgba16_0, 2);
|
||||
rgba16_1 = Sse2.ShiftLeftLogical(rgba16_1, 2);
|
||||
rgba16_2 = Sse2.ShiftLeftLogical(rgba16_2, 2);
|
||||
@ -149,6 +146,98 @@ namespace Ryujinx.Graphics.Vic.Image
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (AdvSimd.Arm64.IsSupported)
|
||||
{
|
||||
Vector128<int> alphaMask = Vector128.Create(0xffu << 24).AsInt32();
|
||||
|
||||
int yStrideGap = yStride - width;
|
||||
int uvStrideGap = uvStride - input.UvWidth;
|
||||
|
||||
int widthTrunc = width & ~0xf;
|
||||
|
||||
fixed (Pixel* dstPtr = output.Data)
|
||||
{
|
||||
Pixel* op = dstPtr;
|
||||
|
||||
fixed (byte* src0Ptr = input.Buffer0, src1Ptr = input.Buffer1)
|
||||
{
|
||||
byte* i0p = src0Ptr;
|
||||
|
||||
for (int y = 0; y < height; y++)
|
||||
{
|
||||
byte* i1p = src1Ptr + (y >> 1) * uvStride;
|
||||
|
||||
int x = 0;
|
||||
|
||||
for (; x < widthTrunc; x += 16, i0p += 16, i1p += 16)
|
||||
{
|
||||
Vector128<byte> ya = AdvSimd.LoadVector128(i0p);
|
||||
Vector128<byte> uv = AdvSimd.LoadVector128(i1p);
|
||||
|
||||
Vector128<short> ya0 = AdvSimd.ZeroExtendWideningLower(ya.GetLower()).AsInt16();
|
||||
Vector128<short> ya1 = AdvSimd.ZeroExtendWideningUpper(ya).AsInt16();
|
||||
|
||||
Vector128<short> uv0 = AdvSimd.Arm64.ZipLow(uv.AsInt16(), uv.AsInt16());
|
||||
Vector128<short> uv1 = AdvSimd.Arm64.ZipHigh(uv.AsInt16(), uv.AsInt16());
|
||||
|
||||
ya0 = AdvSimd.ShiftLeftLogical(ya0, 8);
|
||||
ya1 = AdvSimd.ShiftLeftLogical(ya1, 8);
|
||||
|
||||
Vector128<short> rgba0 = AdvSimd.Arm64.ZipLow(ya0, uv0);
|
||||
Vector128<short> rgba1 = AdvSimd.Arm64.ZipHigh(ya0, uv0);
|
||||
Vector128<short> rgba2 = AdvSimd.Arm64.ZipLow(ya1, uv1);
|
||||
Vector128<short> rgba3 = AdvSimd.Arm64.ZipHigh(ya1, uv1);
|
||||
|
||||
rgba0 = AdvSimd.ShiftRightLogicalAdd(alphaMask, rgba0.AsInt32(), 8).AsInt16();
|
||||
rgba1 = AdvSimd.ShiftRightLogicalAdd(alphaMask, rgba1.AsInt32(), 8).AsInt16();
|
||||
rgba2 = AdvSimd.ShiftRightLogicalAdd(alphaMask, rgba2.AsInt32(), 8).AsInt16();
|
||||
rgba3 = AdvSimd.ShiftRightLogicalAdd(alphaMask, rgba3.AsInt32(), 8).AsInt16();
|
||||
|
||||
Vector128<short> rgba16_0 = AdvSimd.ZeroExtendWideningLower(rgba0.AsByte().GetLower()).AsInt16();
|
||||
Vector128<short> rgba16_1 = AdvSimd.ZeroExtendWideningUpper(rgba0.AsByte()).AsInt16();
|
||||
Vector128<short> rgba16_2 = AdvSimd.ZeroExtendWideningLower(rgba1.AsByte().GetLower()).AsInt16();
|
||||
Vector128<short> rgba16_3 = AdvSimd.ZeroExtendWideningUpper(rgba1.AsByte()).AsInt16();
|
||||
Vector128<short> rgba16_4 = AdvSimd.ZeroExtendWideningLower(rgba2.AsByte().GetLower()).AsInt16();
|
||||
Vector128<short> rgba16_5 = AdvSimd.ZeroExtendWideningUpper(rgba2.AsByte()).AsInt16();
|
||||
Vector128<short> rgba16_6 = AdvSimd.ZeroExtendWideningLower(rgba3.AsByte().GetLower()).AsInt16();
|
||||
Vector128<short> rgba16_7 = AdvSimd.ZeroExtendWideningUpper(rgba3.AsByte()).AsInt16();
|
||||
|
||||
rgba16_0 = AdvSimd.ShiftLeftLogical(rgba16_0, 2);
|
||||
rgba16_1 = AdvSimd.ShiftLeftLogical(rgba16_1, 2);
|
||||
rgba16_2 = AdvSimd.ShiftLeftLogical(rgba16_2, 2);
|
||||
rgba16_3 = AdvSimd.ShiftLeftLogical(rgba16_3, 2);
|
||||
rgba16_4 = AdvSimd.ShiftLeftLogical(rgba16_4, 2);
|
||||
rgba16_5 = AdvSimd.ShiftLeftLogical(rgba16_5, 2);
|
||||
rgba16_6 = AdvSimd.ShiftLeftLogical(rgba16_6, 2);
|
||||
rgba16_7 = AdvSimd.ShiftLeftLogical(rgba16_7, 2);
|
||||
|
||||
AdvSimd.Store((short*)(op + (uint)x + 0), rgba16_0);
|
||||
AdvSimd.Store((short*)(op + (uint)x + 2), rgba16_1);
|
||||
AdvSimd.Store((short*)(op + (uint)x + 4), rgba16_2);
|
||||
AdvSimd.Store((short*)(op + (uint)x + 6), rgba16_3);
|
||||
AdvSimd.Store((short*)(op + (uint)x + 8), rgba16_4);
|
||||
AdvSimd.Store((short*)(op + (uint)x + 10), rgba16_5);
|
||||
AdvSimd.Store((short*)(op + (uint)x + 12), rgba16_6);
|
||||
AdvSimd.Store((short*)(op + (uint)x + 14), rgba16_7);
|
||||
}
|
||||
|
||||
for (; x < width; x++, i1p += (x & 1) * 2)
|
||||
{
|
||||
Pixel* px = op + (uint)x;
|
||||
|
||||
px->R = Upsample(*i0p++);
|
||||
px->G = Upsample(*i1p);
|
||||
px->B = Upsample(*(i1p + 1));
|
||||
px->A = 0x3ff;
|
||||
}
|
||||
|
||||
op += width;
|
||||
i0p += yStrideGap;
|
||||
i1p += uvStrideGap;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
for (int y = 0; y < height; y++)
|
||||
|
@ -3,6 +3,7 @@ using Ryujinx.Graphics.Texture;
|
||||
using Ryujinx.Graphics.Vic.Types;
|
||||
using System;
|
||||
using System.Runtime.Intrinsics;
|
||||
using System.Runtime.Intrinsics.Arm;
|
||||
using System.Runtime.Intrinsics.X86;
|
||||
using static Ryujinx.Graphics.Vic.Image.SurfaceCommon;
|
||||
|
||||
@ -93,6 +94,64 @@ namespace Ryujinx.Graphics.Vic.Image
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (AdvSimd.IsSupported)
|
||||
{
|
||||
int widthTrunc = width & ~7;
|
||||
int strideGap = stride - width * 4;
|
||||
|
||||
fixed (Pixel* srcPtr = input.Data)
|
||||
{
|
||||
Pixel* ip = srcPtr;
|
||||
|
||||
fixed (byte* dstPtr = dst)
|
||||
{
|
||||
byte* op = dstPtr;
|
||||
|
||||
for (int y = 0; y < height; y++, ip += input.Width)
|
||||
{
|
||||
int x = 0;
|
||||
|
||||
for (; x < widthTrunc; x += 8)
|
||||
{
|
||||
Vector128<ushort> pixel12 = AdvSimd.LoadVector128((ushort*)(ip + (uint)x));
|
||||
Vector128<ushort> pixel34 = AdvSimd.LoadVector128((ushort*)(ip + (uint)x + 2));
|
||||
Vector128<ushort> pixel56 = AdvSimd.LoadVector128((ushort*)(ip + (uint)x + 4));
|
||||
Vector128<ushort> pixel78 = AdvSimd.LoadVector128((ushort*)(ip + (uint)x + 6));
|
||||
|
||||
pixel12 = AdvSimd.ShiftRightLogical(pixel12, 2);
|
||||
pixel34 = AdvSimd.ShiftRightLogical(pixel34, 2);
|
||||
pixel56 = AdvSimd.ShiftRightLogical(pixel56, 2);
|
||||
pixel78 = AdvSimd.ShiftRightLogical(pixel78, 2);
|
||||
|
||||
Vector64<byte> lower12 = AdvSimd.ExtractNarrowingLower(pixel12.AsUInt16());
|
||||
Vector64<byte> lower56 = AdvSimd.ExtractNarrowingLower(pixel56.AsUInt16());
|
||||
|
||||
Vector128<byte> pixel1234 = AdvSimd.ExtractNarrowingUpper(lower12, pixel34.AsUInt16());
|
||||
Vector128<byte> pixel5678 = AdvSimd.ExtractNarrowingUpper(lower56, pixel78.AsUInt16());
|
||||
|
||||
AdvSimd.Store(op + 0x00, pixel1234);
|
||||
AdvSimd.Store(op + 0x10, pixel5678);
|
||||
|
||||
op += 0x20;
|
||||
}
|
||||
|
||||
for (; x < width; x++)
|
||||
{
|
||||
Pixel* px = ip + (uint)x;
|
||||
|
||||
*(op + 0) = Downsample(px->R);
|
||||
*(op + 1) = Downsample(px->G);
|
||||
*(op + 2) = Downsample(px->B);
|
||||
*(op + 3) = Downsample(px->A);
|
||||
|
||||
op += 4;
|
||||
}
|
||||
|
||||
op += strideGap;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
for (int y = 0; y < height; y++)
|
||||
@ -302,6 +361,87 @@ namespace Ryujinx.Graphics.Vic.Image
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (AdvSimd.IsSupported)
|
||||
{
|
||||
Vector128<ushort> mask = Vector128.Create(0xffffUL).AsUInt16();
|
||||
|
||||
int widthTrunc = width & ~0xf;
|
||||
int strideGap = yStride - width;
|
||||
|
||||
fixed (Pixel* srcPtr = input.Data)
|
||||
{
|
||||
Pixel* ip = srcPtr;
|
||||
|
||||
fixed (byte* dstPtr = dstY)
|
||||
{
|
||||
byte* op = dstPtr;
|
||||
|
||||
for (int y = 0; y < height; y++, ip += input.Width)
|
||||
{
|
||||
int x = 0;
|
||||
|
||||
for (; x < widthTrunc; x += 16)
|
||||
{
|
||||
byte* baseOffset = (byte*)(ip + (ulong)(uint)x);
|
||||
|
||||
Vector128<ushort> pixelp1 = AdvSimd.LoadVector128((ushort*)baseOffset);
|
||||
Vector128<ushort> pixelp2 = AdvSimd.LoadVector128((ushort*)(baseOffset + 0x10));
|
||||
Vector128<ushort> pixelp3 = AdvSimd.LoadVector128((ushort*)(baseOffset + 0x20));
|
||||
Vector128<ushort> pixelp4 = AdvSimd.LoadVector128((ushort*)(baseOffset + 0x30));
|
||||
Vector128<ushort> pixelp5 = AdvSimd.LoadVector128((ushort*)(baseOffset + 0x40));
|
||||
Vector128<ushort> pixelp6 = AdvSimd.LoadVector128((ushort*)(baseOffset + 0x50));
|
||||
Vector128<ushort> pixelp7 = AdvSimd.LoadVector128((ushort*)(baseOffset + 0x60));
|
||||
Vector128<ushort> pixelp8 = AdvSimd.LoadVector128((ushort*)(baseOffset + 0x70));
|
||||
|
||||
pixelp1 = AdvSimd.And(pixelp1, mask);
|
||||
pixelp2 = AdvSimd.And(pixelp2, mask);
|
||||
pixelp3 = AdvSimd.And(pixelp3, mask);
|
||||
pixelp4 = AdvSimd.And(pixelp4, mask);
|
||||
pixelp5 = AdvSimd.And(pixelp5, mask);
|
||||
pixelp6 = AdvSimd.And(pixelp6, mask);
|
||||
pixelp7 = AdvSimd.And(pixelp7, mask);
|
||||
pixelp8 = AdvSimd.And(pixelp8, mask);
|
||||
|
||||
Vector64<ushort> lowerp1 = AdvSimd.ExtractNarrowingLower(pixelp1.AsUInt32());
|
||||
Vector64<ushort> lowerp3 = AdvSimd.ExtractNarrowingLower(pixelp3.AsUInt32());
|
||||
Vector64<ushort> lowerp5 = AdvSimd.ExtractNarrowingLower(pixelp5.AsUInt32());
|
||||
Vector64<ushort> lowerp7 = AdvSimd.ExtractNarrowingLower(pixelp7.AsUInt32());
|
||||
|
||||
Vector128<ushort> pixelq1 = AdvSimd.ExtractNarrowingUpper(lowerp1, pixelp2.AsUInt32());
|
||||
Vector128<ushort> pixelq2 = AdvSimd.ExtractNarrowingUpper(lowerp3, pixelp4.AsUInt32());
|
||||
Vector128<ushort> pixelq3 = AdvSimd.ExtractNarrowingUpper(lowerp5, pixelp6.AsUInt32());
|
||||
Vector128<ushort> pixelq4 = AdvSimd.ExtractNarrowingUpper(lowerp7, pixelp8.AsUInt32());
|
||||
|
||||
Vector64<ushort> lowerq1 = AdvSimd.ExtractNarrowingLower(pixelq1.AsUInt32());
|
||||
Vector64<ushort> lowerq3 = AdvSimd.ExtractNarrowingLower(pixelq3.AsUInt32());
|
||||
|
||||
pixelq1 = AdvSimd.ExtractNarrowingUpper(lowerq1, pixelq2.AsUInt32());
|
||||
pixelq2 = AdvSimd.ExtractNarrowingUpper(lowerq3, pixelq4.AsUInt32());
|
||||
|
||||
pixelq1 = AdvSimd.ShiftRightLogical(pixelq1, 2);
|
||||
pixelq2 = AdvSimd.ShiftRightLogical(pixelq2, 2);
|
||||
|
||||
Vector64<byte> pixelLower = AdvSimd.ExtractNarrowingLower(pixelq1.AsUInt16());
|
||||
|
||||
Vector128<byte> pixel = AdvSimd.ExtractNarrowingUpper(pixelLower, pixelq2.AsUInt16());
|
||||
|
||||
AdvSimd.Store(op, pixel);
|
||||
|
||||
op += 0x10;
|
||||
}
|
||||
|
||||
for (; x < width; x++)
|
||||
{
|
||||
Pixel* px = ip + (uint)x;
|
||||
|
||||
*op++ = Downsample(px->R);
|
||||
}
|
||||
|
||||
op += strideGap;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
for (int y = 0; y < height; y++)
|
||||
@ -392,6 +532,69 @@ namespace Ryujinx.Graphics.Vic.Image
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (AdvSimd.Arm64.IsSupported)
|
||||
{
|
||||
int widthTrunc = uvWidth & ~7;
|
||||
int strideGap = uvStride - uvWidth * 2;
|
||||
|
||||
fixed (Pixel* srcPtr = input.Data)
|
||||
{
|
||||
Pixel* ip = srcPtr;
|
||||
|
||||
fixed (byte* dstPtr = dstUv)
|
||||
{
|
||||
byte* op = dstPtr;
|
||||
|
||||
for (int y = 0; y < uvHeight; y++, ip += input.Width * 2)
|
||||
{
|
||||
int x = 0;
|
||||
|
||||
for (; x < widthTrunc; x += 8)
|
||||
{
|
||||
byte* baseOffset = (byte*)ip + (ulong)(uint)x * 16;
|
||||
|
||||
Vector128<uint> pixel1 = AdvSimd.LoadAndReplicateToVector128((uint*)(baseOffset + 0x02));
|
||||
Vector128<uint> pixel2 = AdvSimd.LoadAndReplicateToVector128((uint*)(baseOffset + 0x12));
|
||||
Vector128<uint> pixel3 = AdvSimd.LoadAndReplicateToVector128((uint*)(baseOffset + 0x22));
|
||||
Vector128<uint> pixel4 = AdvSimd.LoadAndReplicateToVector128((uint*)(baseOffset + 0x32));
|
||||
Vector128<uint> pixel5 = AdvSimd.LoadAndReplicateToVector128((uint*)(baseOffset + 0x42));
|
||||
Vector128<uint> pixel6 = AdvSimd.LoadAndReplicateToVector128((uint*)(baseOffset + 0x52));
|
||||
Vector128<uint> pixel7 = AdvSimd.LoadAndReplicateToVector128((uint*)(baseOffset + 0x62));
|
||||
Vector128<uint> pixel8 = AdvSimd.LoadAndReplicateToVector128((uint*)(baseOffset + 0x72));
|
||||
|
||||
Vector128<uint> pixel12 = AdvSimd.Arm64.ZipLow(pixel1, pixel2);
|
||||
Vector128<uint> pixel34 = AdvSimd.Arm64.ZipLow(pixel3, pixel4);
|
||||
Vector128<uint> pixel56 = AdvSimd.Arm64.ZipLow(pixel5, pixel6);
|
||||
Vector128<uint> pixel78 = AdvSimd.Arm64.ZipLow(pixel7, pixel8);
|
||||
|
||||
Vector128<ulong> pixel1234 = AdvSimd.Arm64.ZipLow(pixel12.AsUInt64(), pixel34.AsUInt64());
|
||||
Vector128<ulong> pixel5678 = AdvSimd.Arm64.ZipLow(pixel56.AsUInt64(), pixel78.AsUInt64());
|
||||
|
||||
pixel1234 = AdvSimd.ShiftRightLogical(pixel1234, 2);
|
||||
pixel5678 = AdvSimd.ShiftRightLogical(pixel5678, 2);
|
||||
|
||||
Vector64<byte> pixelLower = AdvSimd.ExtractNarrowingLower(pixel1234.AsUInt16());
|
||||
|
||||
Vector128<byte> pixel = AdvSimd.ExtractNarrowingUpper(pixelLower, pixel5678.AsUInt16());
|
||||
|
||||
AdvSimd.Store(op, pixel);
|
||||
|
||||
op += 0x10;
|
||||
}
|
||||
|
||||
for (; x < uvWidth; x++)
|
||||
{
|
||||
Pixel* px = ip + (uint)(x << 1);
|
||||
|
||||
*op++ = Downsample(px->G);
|
||||
*op++ = Downsample(px->B);
|
||||
}
|
||||
|
||||
op += strideGap;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
for (int y = 0; y < uvHeight; y++)
|
||||
|
@ -1,5 +1,6 @@
|
||||
using System;
|
||||
using System.Diagnostics;
|
||||
using System.Linq;
|
||||
|
||||
namespace Ryujinx.Graphics.Vulkan
|
||||
{
|
||||
@ -16,6 +17,10 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
private bool _hasPendingQuery;
|
||||
private int _queryCount;
|
||||
|
||||
private int[] _queryCountHistory = new int[3];
|
||||
private int _queryCountHistoryIndex;
|
||||
private int _remainingQueries;
|
||||
|
||||
public void RegisterFlush(ulong drawCount)
|
||||
{
|
||||
_lastFlush = Stopwatch.GetTimestamp();
|
||||
@ -27,6 +32,9 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
public bool RegisterPendingQuery()
|
||||
{
|
||||
_hasPendingQuery = true;
|
||||
_remainingQueries--;
|
||||
|
||||
_queryCountHistory[_queryCountHistoryIndex]++;
|
||||
|
||||
// Interrupt render passes to flush queries, so that early results arrive sooner.
|
||||
if (++_queryCount == InitialQueryCountForFlush)
|
||||
@ -37,6 +45,21 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
return false;
|
||||
}
|
||||
|
||||
public int GetRemainingQueries()
|
||||
{
|
||||
if (_remainingQueries <= 0)
|
||||
{
|
||||
_remainingQueries = 16;
|
||||
}
|
||||
|
||||
if (_queryCount < InitialQueryCountForFlush)
|
||||
{
|
||||
return Math.Min(InitialQueryCountForFlush - _queryCount, _remainingQueries);
|
||||
}
|
||||
|
||||
return _remainingQueries;
|
||||
}
|
||||
|
||||
public bool ShouldFlushQuery()
|
||||
{
|
||||
return _hasPendingQuery;
|
||||
@ -69,5 +92,14 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
|
||||
return now > _lastFlush + flushTimeout;
|
||||
}
|
||||
|
||||
public void Present()
|
||||
{
|
||||
_queryCountHistoryIndex = (_queryCountHistoryIndex + 1) % 3;
|
||||
|
||||
_remainingQueries = _queryCountHistory.Max() + 10;
|
||||
|
||||
_queryCountHistory[_queryCountHistoryIndex] = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -14,6 +14,12 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
MemoryPropertyFlags.HostCoherentBit |
|
||||
MemoryPropertyFlags.HostCachedBit;
|
||||
|
||||
// Some drivers don't expose a "HostCached" memory type,
|
||||
// so we need those alternative flags for the allocation to succeed there.
|
||||
private const MemoryPropertyFlags DefaultBufferMemoryAltFlags =
|
||||
MemoryPropertyFlags.HostVisibleBit |
|
||||
MemoryPropertyFlags.HostCoherentBit;
|
||||
|
||||
private const MemoryPropertyFlags DeviceLocalBufferMemoryFlags =
|
||||
MemoryPropertyFlags.DeviceLocalBit;
|
||||
|
||||
@ -94,9 +100,21 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
gd.Api.CreateBuffer(_device, in bufferCreateInfo, null, out var buffer).ThrowOnError();
|
||||
gd.Api.GetBufferMemoryRequirements(_device, buffer, out var requirements);
|
||||
|
||||
var allocateFlags = deviceLocal ? DeviceLocalBufferMemoryFlags : DefaultBufferMemoryFlags;
|
||||
MemoryPropertyFlags allocateFlags;
|
||||
MemoryPropertyFlags allocateFlagsAlt;
|
||||
|
||||
var allocation = gd.MemoryAllocator.AllocateDeviceMemory(_physicalDevice, requirements, allocateFlags);
|
||||
if (deviceLocal)
|
||||
{
|
||||
allocateFlags = DeviceLocalBufferMemoryFlags;
|
||||
allocateFlagsAlt = DeviceLocalBufferMemoryFlags;
|
||||
}
|
||||
else
|
||||
{
|
||||
allocateFlags = DefaultBufferMemoryFlags;
|
||||
allocateFlagsAlt = DefaultBufferMemoryAltFlags;
|
||||
}
|
||||
|
||||
var allocation = gd.MemoryAllocator.AllocateDeviceMemory(_physicalDevice, requirements, allocateFlags, allocateFlagsAlt);
|
||||
|
||||
if (allocation.Memory.Handle == 0UL)
|
||||
{
|
||||
|
@ -23,7 +23,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
public int[] AttachmentIndices { get; }
|
||||
|
||||
public int AttachmentsCount { get; }
|
||||
public int MaxColorAttachmentIndex { get; }
|
||||
public int MaxColorAttachmentIndex => AttachmentIndices.Length > 0 ? AttachmentIndices[AttachmentIndices.Length - 1] : -1;
|
||||
public bool HasDepthStencil { get; }
|
||||
public int ColorAttachmentsCount => AttachmentsCount - (HasDepthStencil ? 1 : 0);
|
||||
|
||||
@ -38,7 +38,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
{
|
||||
_device = device;
|
||||
_attachments = new[] { view };
|
||||
_validColorAttachments = 1u;
|
||||
_validColorAttachments = isDepthStencil ? 0u : 1u;
|
||||
|
||||
Width = width;
|
||||
Height = height;
|
||||
@ -46,7 +46,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
|
||||
AttachmentSamples = new[] { samples };
|
||||
AttachmentFormats = new[] { format };
|
||||
AttachmentIndices = new[] { 0 };
|
||||
AttachmentIndices = isDepthStencil ? Array.Empty<int>() : new[] { 0 };
|
||||
|
||||
AttachmentsCount = 1;
|
||||
|
||||
@ -66,8 +66,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
|
||||
AttachmentSamples = new uint[count];
|
||||
AttachmentFormats = new VkFormat[count];
|
||||
AttachmentIndices = new int[count];
|
||||
MaxColorAttachmentIndex = colors.Length - 1;
|
||||
AttachmentIndices = new int[colorsCount];
|
||||
|
||||
uint width = uint.MaxValue;
|
||||
uint height = uint.MaxValue;
|
||||
|
@ -24,14 +24,16 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
public readonly bool SupportsGeometryShaderPassthrough;
|
||||
public readonly bool SupportsSubgroupSizeControl;
|
||||
public readonly bool SupportsShaderInt8;
|
||||
public readonly bool SupportsShaderStencilExport;
|
||||
public readonly bool SupportsConditionalRendering;
|
||||
public readonly bool SupportsExtendedDynamicState;
|
||||
public readonly bool SupportsMultiView;
|
||||
public readonly bool SupportsNullDescriptors;
|
||||
public readonly bool SupportsPreciseOcclusionQueries;
|
||||
public readonly bool SupportsPushDescriptors;
|
||||
public readonly bool SupportsTransformFeedback;
|
||||
public readonly bool SupportsTransformFeedbackQueries;
|
||||
public readonly bool SupportsPreciseOcclusionQueries;
|
||||
public readonly bool SupportsPipelineStatisticsQuery;
|
||||
public readonly bool SupportsGeometryShader;
|
||||
public readonly uint MinSubgroupSize;
|
||||
public readonly uint MaxSubgroupSize;
|
||||
@ -47,6 +49,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
bool supportsGeometryShaderPassthrough,
|
||||
bool supportsSubgroupSizeControl,
|
||||
bool supportsShaderInt8,
|
||||
bool supportsShaderStencilExport,
|
||||
bool supportsConditionalRendering,
|
||||
bool supportsExtendedDynamicState,
|
||||
bool supportsMultiView,
|
||||
@ -55,6 +58,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
bool supportsTransformFeedback,
|
||||
bool supportsTransformFeedbackQueries,
|
||||
bool supportsPreciseOcclusionQueries,
|
||||
bool supportsPipelineStatisticsQuery,
|
||||
bool supportsGeometryShader,
|
||||
uint minSubgroupSize,
|
||||
uint maxSubgroupSize,
|
||||
@ -69,6 +73,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
SupportsGeometryShaderPassthrough = supportsGeometryShaderPassthrough;
|
||||
SupportsSubgroupSizeControl = supportsSubgroupSizeControl;
|
||||
SupportsShaderInt8 = supportsShaderInt8;
|
||||
SupportsShaderStencilExport = supportsShaderStencilExport;
|
||||
SupportsConditionalRendering = supportsConditionalRendering;
|
||||
SupportsExtendedDynamicState = supportsExtendedDynamicState;
|
||||
SupportsMultiView = supportsMultiView;
|
||||
@ -77,6 +82,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
SupportsTransformFeedback = supportsTransformFeedback;
|
||||
SupportsTransformFeedbackQueries = supportsTransformFeedbackQueries;
|
||||
SupportsPreciseOcclusionQueries = supportsPreciseOcclusionQueries;
|
||||
SupportsPipelineStatisticsQuery = supportsPipelineStatisticsQuery;
|
||||
SupportsGeometryShader = supportsGeometryShader;
|
||||
MinSubgroupSize = minSubgroupSize;
|
||||
MaxSubgroupSize = maxSubgroupSize;
|
||||
|
@ -33,6 +33,8 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
private readonly IProgram _programConvertIndirectData;
|
||||
private readonly IProgram _programColorCopyToNonMs;
|
||||
private readonly IProgram _programColorDrawToMs;
|
||||
private readonly IProgram _programDepthBlit;
|
||||
private readonly IProgram _programStencilBlit;
|
||||
|
||||
public HelperShader(VulkanRenderer gd, Device device)
|
||||
{
|
||||
@ -42,13 +44,13 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
_samplerLinear = gd.CreateSampler(GAL.SamplerCreateInfo.Create(MinFilter.Linear, MagFilter.Linear));
|
||||
_samplerNearest = gd.CreateSampler(GAL.SamplerCreateInfo.Create(MinFilter.Nearest, MagFilter.Nearest));
|
||||
|
||||
var colorBlitVertexBindings = new ShaderBindings(
|
||||
var blitVertexBindings = new ShaderBindings(
|
||||
new[] { 1 },
|
||||
Array.Empty<int>(),
|
||||
Array.Empty<int>(),
|
||||
Array.Empty<int>());
|
||||
|
||||
var colorBlitFragmentBindings = new ShaderBindings(
|
||||
var blitFragmentBindings = new ShaderBindings(
|
||||
Array.Empty<int>(),
|
||||
Array.Empty<int>(),
|
||||
new[] { 0 },
|
||||
@ -56,14 +58,14 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
|
||||
_programColorBlit = gd.CreateProgramWithMinimalLayout(new[]
|
||||
{
|
||||
new ShaderSource(ShaderBinaries.ColorBlitVertexShaderSource, colorBlitVertexBindings, ShaderStage.Vertex, TargetLanguage.Spirv),
|
||||
new ShaderSource(ShaderBinaries.ColorBlitFragmentShaderSource, colorBlitFragmentBindings, ShaderStage.Fragment, TargetLanguage.Spirv),
|
||||
new ShaderSource(ShaderBinaries.ColorBlitVertexShaderSource, blitVertexBindings, ShaderStage.Vertex, TargetLanguage.Spirv),
|
||||
new ShaderSource(ShaderBinaries.ColorBlitFragmentShaderSource, blitFragmentBindings, ShaderStage.Fragment, TargetLanguage.Spirv),
|
||||
});
|
||||
|
||||
_programColorBlitClearAlpha = gd.CreateProgramWithMinimalLayout(new[]
|
||||
{
|
||||
new ShaderSource(ShaderBinaries.ColorBlitVertexShaderSource, colorBlitVertexBindings, ShaderStage.Vertex, TargetLanguage.Spirv),
|
||||
new ShaderSource(ShaderBinaries.ColorBlitClearAlphaFragmentShaderSource, colorBlitFragmentBindings, ShaderStage.Fragment, TargetLanguage.Spirv),
|
||||
new ShaderSource(ShaderBinaries.ColorBlitVertexShaderSource, blitVertexBindings, ShaderStage.Vertex, TargetLanguage.Spirv),
|
||||
new ShaderSource(ShaderBinaries.ColorBlitClearAlphaFragmentShaderSource, blitFragmentBindings, ShaderStage.Fragment, TargetLanguage.Spirv),
|
||||
});
|
||||
|
||||
var colorClearFragmentBindings = new ShaderBindings(
|
||||
@ -74,19 +76,19 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
|
||||
_programColorClearF = gd.CreateProgramWithMinimalLayout(new[]
|
||||
{
|
||||
new ShaderSource(ShaderBinaries.ColorClearVertexShaderSource, colorBlitVertexBindings, ShaderStage.Vertex, TargetLanguage.Spirv),
|
||||
new ShaderSource(ShaderBinaries.ColorClearVertexShaderSource, blitVertexBindings, ShaderStage.Vertex, TargetLanguage.Spirv),
|
||||
new ShaderSource(ShaderBinaries.ColorClearFFragmentShaderSource, colorClearFragmentBindings, ShaderStage.Fragment, TargetLanguage.Spirv),
|
||||
});
|
||||
|
||||
_programColorClearSI = gd.CreateProgramWithMinimalLayout(new[]
|
||||
{
|
||||
new ShaderSource(ShaderBinaries.ColorClearVertexShaderSource, colorBlitVertexBindings, ShaderStage.Vertex, TargetLanguage.Spirv),
|
||||
new ShaderSource(ShaderBinaries.ColorClearVertexShaderSource, blitVertexBindings, ShaderStage.Vertex, TargetLanguage.Spirv),
|
||||
new ShaderSource(ShaderBinaries.ColorClearSIFragmentShaderSource, colorClearFragmentBindings, ShaderStage.Fragment, TargetLanguage.Spirv),
|
||||
});
|
||||
|
||||
_programColorClearUI = gd.CreateProgramWithMinimalLayout(new[]
|
||||
{
|
||||
new ShaderSource(ShaderBinaries.ColorClearVertexShaderSource, colorBlitVertexBindings, ShaderStage.Vertex, TargetLanguage.Spirv),
|
||||
new ShaderSource(ShaderBinaries.ColorClearVertexShaderSource, blitVertexBindings, ShaderStage.Vertex, TargetLanguage.Spirv),
|
||||
new ShaderSource(ShaderBinaries.ColorClearUIFragmentShaderSource, colorClearFragmentBindings, ShaderStage.Fragment, TargetLanguage.Spirv),
|
||||
});
|
||||
|
||||
@ -151,6 +153,21 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
{
|
||||
new ShaderSource(ShaderBinaries.ConvertIndirectDataShaderSource, convertIndirectDataBindings, ShaderStage.Compute, TargetLanguage.Spirv),
|
||||
});
|
||||
|
||||
_programDepthBlit = gd.CreateProgramWithMinimalLayout(new[]
|
||||
{
|
||||
new ShaderSource(ShaderBinaries.ColorBlitVertexShaderSource, blitVertexBindings, ShaderStage.Vertex, TargetLanguage.Spirv),
|
||||
new ShaderSource(ShaderBinaries.DepthBlitFragmentShaderSource, blitFragmentBindings, ShaderStage.Fragment, TargetLanguage.Spirv),
|
||||
});
|
||||
|
||||
if (gd.Capabilities.SupportsShaderStencilExport)
|
||||
{
|
||||
_programStencilBlit = gd.CreateProgramWithMinimalLayout(new[]
|
||||
{
|
||||
new ShaderSource(ShaderBinaries.ColorBlitVertexShaderSource, blitVertexBindings, ShaderStage.Vertex, TargetLanguage.Spirv),
|
||||
new ShaderSource(ShaderBinaries.StencilBlitFragmentShaderSource, blitFragmentBindings, ShaderStage.Fragment, TargetLanguage.Spirv),
|
||||
});
|
||||
}
|
||||
}
|
||||
|
||||
public void Blit(
|
||||
@ -162,6 +179,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
VkFormat dstFormat,
|
||||
Extents2D srcRegion,
|
||||
Extents2D dstRegion,
|
||||
bool isDepthOrStencil,
|
||||
bool linearFilter,
|
||||
bool clearAlpha = false)
|
||||
{
|
||||
@ -169,10 +187,17 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
|
||||
using var cbs = gd.CommandBufferPool.Rent();
|
||||
|
||||
Blit(gd, cbs, src, dst, dstWidth, dstHeight, dstFormat, srcRegion, dstRegion, linearFilter, clearAlpha);
|
||||
if (isDepthOrStencil)
|
||||
{
|
||||
BlitDepthStencil(gd, cbs, src, dst, dstWidth, dstHeight, dstFormat, srcRegion, dstRegion);
|
||||
}
|
||||
else
|
||||
{
|
||||
BlitColor(gd, cbs, src, dst, dstWidth, dstHeight, dstFormat, srcRegion, dstRegion, linearFilter, clearAlpha);
|
||||
}
|
||||
}
|
||||
|
||||
public void Blit(
|
||||
public void BlitColor(
|
||||
VulkanRenderer gd,
|
||||
CommandBufferScoped cbs,
|
||||
TextureView src,
|
||||
@ -255,6 +280,173 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
gd.BufferManager.Delete(bufferHandle);
|
||||
}
|
||||
|
||||
private void BlitDepthStencil(
|
||||
VulkanRenderer gd,
|
||||
CommandBufferScoped cbs,
|
||||
TextureView src,
|
||||
Auto<DisposableImageView> dst,
|
||||
int dstWidth,
|
||||
int dstHeight,
|
||||
VkFormat dstFormat,
|
||||
Extents2D srcRegion,
|
||||
Extents2D dstRegion)
|
||||
{
|
||||
_pipeline.SetCommandBuffer(cbs);
|
||||
|
||||
const int RegionBufferSize = 16;
|
||||
|
||||
Span<float> region = stackalloc float[RegionBufferSize / sizeof(float)];
|
||||
|
||||
region[0] = (float)srcRegion.X1 / src.Width;
|
||||
region[1] = (float)srcRegion.X2 / src.Width;
|
||||
region[2] = (float)srcRegion.Y1 / src.Height;
|
||||
region[3] = (float)srcRegion.Y2 / src.Height;
|
||||
|
||||
if (dstRegion.X1 > dstRegion.X2)
|
||||
{
|
||||
(region[0], region[1]) = (region[1], region[0]);
|
||||
}
|
||||
|
||||
if (dstRegion.Y1 > dstRegion.Y2)
|
||||
{
|
||||
(region[2], region[3]) = (region[3], region[2]);
|
||||
}
|
||||
|
||||
var bufferHandle = gd.BufferManager.CreateWithHandle(gd, RegionBufferSize, false);
|
||||
|
||||
gd.BufferManager.SetData<float>(bufferHandle, 0, region);
|
||||
|
||||
_pipeline.SetUniformBuffers(stackalloc[] { new BufferAssignment(1, new BufferRange(bufferHandle, 0, RegionBufferSize)) });
|
||||
|
||||
Span<GAL.Viewport> viewports = stackalloc GAL.Viewport[1];
|
||||
|
||||
var rect = new Rectangle<float>(
|
||||
MathF.Min(dstRegion.X1, dstRegion.X2),
|
||||
MathF.Min(dstRegion.Y1, dstRegion.Y2),
|
||||
MathF.Abs(dstRegion.X2 - dstRegion.X1),
|
||||
MathF.Abs(dstRegion.Y2 - dstRegion.Y1));
|
||||
|
||||
viewports[0] = new GAL.Viewport(
|
||||
rect,
|
||||
ViewportSwizzle.PositiveX,
|
||||
ViewportSwizzle.PositiveY,
|
||||
ViewportSwizzle.PositiveZ,
|
||||
ViewportSwizzle.PositiveW,
|
||||
0f,
|
||||
1f);
|
||||
|
||||
Span<Rectangle<int>> scissors = stackalloc Rectangle<int>[1];
|
||||
|
||||
scissors[0] = new Rectangle<int>(0, 0, dstWidth, dstHeight);
|
||||
|
||||
_pipeline.SetRenderTarget(dst, (uint)dstWidth, (uint)dstHeight, true, dstFormat);
|
||||
_pipeline.SetScissors(scissors);
|
||||
_pipeline.SetViewports(viewports, false);
|
||||
_pipeline.SetPrimitiveTopology(GAL.PrimitiveTopology.TriangleStrip);
|
||||
|
||||
var aspectFlags = src.Info.Format.ConvertAspectFlags();
|
||||
|
||||
if (aspectFlags.HasFlag(ImageAspectFlags.DepthBit))
|
||||
{
|
||||
var depthTexture = CreateDepthOrStencilView(src, DepthStencilMode.Depth);
|
||||
|
||||
BlitDepthStencilDraw(depthTexture, isDepth: true);
|
||||
|
||||
if (depthTexture != src)
|
||||
{
|
||||
depthTexture.Release();
|
||||
}
|
||||
}
|
||||
|
||||
if (aspectFlags.HasFlag(ImageAspectFlags.StencilBit) && _programStencilBlit != null)
|
||||
{
|
||||
var stencilTexture = CreateDepthOrStencilView(src, DepthStencilMode.Stencil);
|
||||
|
||||
BlitDepthStencilDraw(stencilTexture, isDepth: false);
|
||||
|
||||
if (stencilTexture != src)
|
||||
{
|
||||
stencilTexture.Release();
|
||||
}
|
||||
}
|
||||
|
||||
_pipeline.Finish(gd, cbs);
|
||||
|
||||
gd.BufferManager.Delete(bufferHandle);
|
||||
}
|
||||
|
||||
private static TextureView CreateDepthOrStencilView(TextureView depthStencilTexture, DepthStencilMode depthStencilMode)
|
||||
{
|
||||
if (depthStencilTexture.Info.DepthStencilMode == depthStencilMode)
|
||||
{
|
||||
return depthStencilTexture;
|
||||
}
|
||||
|
||||
return (TextureView)depthStencilTexture.CreateView(new TextureCreateInfo(
|
||||
depthStencilTexture.Info.Width,
|
||||
depthStencilTexture.Info.Height,
|
||||
depthStencilTexture.Info.Depth,
|
||||
depthStencilTexture.Info.Levels,
|
||||
depthStencilTexture.Info.Samples,
|
||||
depthStencilTexture.Info.BlockWidth,
|
||||
depthStencilTexture.Info.BlockHeight,
|
||||
depthStencilTexture.Info.BytesPerPixel,
|
||||
depthStencilTexture.Info.Format,
|
||||
depthStencilMode,
|
||||
depthStencilTexture.Info.Target,
|
||||
SwizzleComponent.Red,
|
||||
SwizzleComponent.Green,
|
||||
SwizzleComponent.Blue,
|
||||
SwizzleComponent.Alpha), 0, 0);
|
||||
}
|
||||
|
||||
private void BlitDepthStencilDraw(TextureView src, bool isDepth)
|
||||
{
|
||||
_pipeline.SetTextureAndSampler(ShaderStage.Fragment, 0, src, _samplerNearest);
|
||||
|
||||
if (isDepth)
|
||||
{
|
||||
_pipeline.SetProgram(_programDepthBlit);
|
||||
_pipeline.SetDepthTest(new DepthTestDescriptor(true, true, GAL.CompareOp.Always));
|
||||
}
|
||||
else
|
||||
{
|
||||
_pipeline.SetProgram(_programStencilBlit);
|
||||
_pipeline.SetStencilTest(CreateStencilTestDescriptor(true));
|
||||
}
|
||||
|
||||
_pipeline.Draw(4, 1, 0, 0);
|
||||
|
||||
if (isDepth)
|
||||
{
|
||||
_pipeline.SetDepthTest(new DepthTestDescriptor(false, false, GAL.CompareOp.Always));
|
||||
}
|
||||
else
|
||||
{
|
||||
_pipeline.SetStencilTest(CreateStencilTestDescriptor(false));
|
||||
}
|
||||
}
|
||||
|
||||
private static StencilTestDescriptor CreateStencilTestDescriptor(bool enabled)
|
||||
{
|
||||
return new StencilTestDescriptor(
|
||||
enabled,
|
||||
GAL.CompareOp.Always,
|
||||
GAL.StencilOp.Replace,
|
||||
GAL.StencilOp.Replace,
|
||||
GAL.StencilOp.Replace,
|
||||
0,
|
||||
0xff,
|
||||
0xff,
|
||||
GAL.CompareOp.Always,
|
||||
GAL.StencilOp.Replace,
|
||||
GAL.StencilOp.Replace,
|
||||
GAL.StencilOp.Replace,
|
||||
0,
|
||||
0xff,
|
||||
0xff);
|
||||
}
|
||||
|
||||
public void Clear(
|
||||
VulkanRenderer gd,
|
||||
Auto<DisposableImageView> dst,
|
||||
@ -993,6 +1185,8 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
_programConvertIndirectData.Dispose();
|
||||
_programColorCopyToNonMs.Dispose();
|
||||
_programColorDrawToMs.Dispose();
|
||||
_programDepthBlit.Dispose();
|
||||
_programStencilBlit?.Dispose();
|
||||
_samplerNearest.Dispose();
|
||||
_samplerLinear.Dispose();
|
||||
_pipeline.Dispose();
|
||||
|
@ -27,7 +27,16 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
MemoryRequirements requirements,
|
||||
MemoryPropertyFlags flags = 0)
|
||||
{
|
||||
int memoryTypeIndex = FindSuitableMemoryTypeIndex(_api, physicalDevice, requirements.MemoryTypeBits, flags);
|
||||
return AllocateDeviceMemory(physicalDevice, requirements, flags, flags);
|
||||
}
|
||||
|
||||
public MemoryAllocation AllocateDeviceMemory(
|
||||
PhysicalDevice physicalDevice,
|
||||
MemoryRequirements requirements,
|
||||
MemoryPropertyFlags flags,
|
||||
MemoryPropertyFlags alternativeFlags)
|
||||
{
|
||||
int memoryTypeIndex = FindSuitableMemoryTypeIndex(_api, physicalDevice, requirements.MemoryTypeBits, flags, alternativeFlags);
|
||||
if (memoryTypeIndex < 0)
|
||||
{
|
||||
return default;
|
||||
@ -56,21 +65,35 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
return newBl.Allocate(size, alignment, map);
|
||||
}
|
||||
|
||||
private static int FindSuitableMemoryTypeIndex(Vk api, PhysicalDevice physicalDevice, uint memoryTypeBits, MemoryPropertyFlags flags)
|
||||
private static int FindSuitableMemoryTypeIndex(
|
||||
Vk api,
|
||||
PhysicalDevice physicalDevice,
|
||||
uint memoryTypeBits,
|
||||
MemoryPropertyFlags flags,
|
||||
MemoryPropertyFlags alternativeFlags)
|
||||
{
|
||||
int bestCandidateIndex = -1;
|
||||
|
||||
api.GetPhysicalDeviceMemoryProperties(physicalDevice, out var properties);
|
||||
|
||||
for (int i = 0; i < properties.MemoryTypeCount; i++)
|
||||
{
|
||||
var type = properties.MemoryTypes[i];
|
||||
|
||||
if ((memoryTypeBits & (1 << i)) != 0 && type.PropertyFlags.HasFlag(flags))
|
||||
if ((memoryTypeBits & (1 << i)) != 0)
|
||||
{
|
||||
return i;
|
||||
if (type.PropertyFlags.HasFlag(flags))
|
||||
{
|
||||
return i;
|
||||
}
|
||||
else if (type.PropertyFlags.HasFlag(alternativeFlags))
|
||||
{
|
||||
bestCandidateIndex = i;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
return bestCandidateIndex;
|
||||
}
|
||||
|
||||
public void Dispose()
|
||||
|
@ -22,7 +22,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
protected readonly Device Device;
|
||||
public readonly PipelineCache PipelineCache;
|
||||
|
||||
protected readonly AutoFlushCounter AutoFlush;
|
||||
public readonly AutoFlushCounter AutoFlush;
|
||||
|
||||
protected PipelineDynamicState DynamicState;
|
||||
private PipelineState _newState;
|
||||
@ -1344,8 +1344,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
var dstAttachmentFormats = _newState.Internal.AttachmentFormats.AsSpan();
|
||||
FramebufferParams.AttachmentFormats.CopyTo(dstAttachmentFormats);
|
||||
|
||||
int maxAttachmentIndex = FramebufferParams.MaxColorAttachmentIndex + (FramebufferParams.HasDepthStencil ? 1 : 0);
|
||||
for (int i = FramebufferParams.AttachmentFormats.Length; i <= maxAttachmentIndex; i++)
|
||||
for (int i = FramebufferParams.AttachmentFormats.Length; i < dstAttachmentFormats.Length; i++)
|
||||
{
|
||||
dstAttachmentFormats[i] = 0;
|
||||
}
|
||||
@ -1376,8 +1375,6 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
|
||||
for (int i = 0; i < FramebufferParams.AttachmentsCount; i++)
|
||||
{
|
||||
int bindIndex = FramebufferParams.AttachmentIndices[i];
|
||||
|
||||
attachmentDescs[i] = new AttachmentDescription(
|
||||
0,
|
||||
FramebufferParams.AttachmentFormats[i],
|
||||
|
@ -27,14 +27,11 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
|
||||
int attachmentCount = 0;
|
||||
int colorCount = 0;
|
||||
int maxColorAttachmentIndex = 0;
|
||||
|
||||
for (int i = 0; i < state.AttachmentEnable.Length; i++)
|
||||
{
|
||||
if (state.AttachmentEnable[i])
|
||||
{
|
||||
maxColorAttachmentIndex = i;
|
||||
|
||||
attachmentFormats[attachmentCount] = gd.FormatCapabilities.ConvertToVkFormat(state.AttachmentFormats[i]);
|
||||
|
||||
attachmentIndices[attachmentCount++] = i;
|
||||
@ -270,7 +267,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
|
||||
// NOTE: Viewports, Scissors are dynamic.
|
||||
|
||||
for (int i = 0; i < 8; i++)
|
||||
for (int i = 0; i < Constants.MaxRenderTargets; i++)
|
||||
{
|
||||
var blend = state.BlendDescriptors[i];
|
||||
|
||||
@ -293,21 +290,24 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
}
|
||||
}
|
||||
|
||||
int maxAttachmentIndex = 0;
|
||||
for (int i = 0; i < 8; i++)
|
||||
int attachmentCount = 0;
|
||||
int maxColorAttachmentIndex = -1;
|
||||
|
||||
for (int i = 0; i < Constants.MaxRenderTargets; i++)
|
||||
{
|
||||
if (state.AttachmentEnable[i])
|
||||
{
|
||||
pipeline.Internal.AttachmentFormats[maxAttachmentIndex++] = gd.FormatCapabilities.ConvertToVkFormat(state.AttachmentFormats[i]);
|
||||
pipeline.Internal.AttachmentFormats[attachmentCount++] = gd.FormatCapabilities.ConvertToVkFormat(state.AttachmentFormats[i]);
|
||||
maxColorAttachmentIndex = i;
|
||||
}
|
||||
}
|
||||
|
||||
if (state.DepthStencilEnable)
|
||||
{
|
||||
pipeline.Internal.AttachmentFormats[maxAttachmentIndex++] = gd.FormatCapabilities.ConvertToVkFormat(state.DepthStencilFormat);
|
||||
pipeline.Internal.AttachmentFormats[attachmentCount++] = gd.FormatCapabilities.ConvertToVkFormat(state.DepthStencilFormat);
|
||||
}
|
||||
|
||||
pipeline.ColorBlendAttachmentStateCount = 8;
|
||||
pipeline.ColorBlendAttachmentStateCount = (uint)(maxColorAttachmentIndex + 1);
|
||||
pipeline.VertexAttributeDescriptionsCount = (uint)Math.Min(Constants.MaxVertexAttributes, state.VertexAttribCount);
|
||||
|
||||
return pipeline;
|
||||
|
@ -14,7 +14,6 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
private CounterQueueEvent _activeConditionalRender;
|
||||
|
||||
private readonly List<BufferedQuery> _pendingQueryCopies;
|
||||
private readonly List<BufferedQuery> _pendingQueryResets;
|
||||
|
||||
private ulong _byteWeight;
|
||||
|
||||
@ -22,7 +21,6 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
{
|
||||
_activeQueries = new List<QueryPool>();
|
||||
_pendingQueryCopies = new();
|
||||
_pendingQueryResets = new List<BufferedQuery>();
|
||||
|
||||
CommandBuffer = (Cbs = gd.CommandBufferPool.Rent()).CommandBuffer;
|
||||
}
|
||||
@ -34,16 +32,6 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
query.PoolCopy(Cbs);
|
||||
}
|
||||
|
||||
lock (_pendingQueryResets)
|
||||
{
|
||||
foreach (var query in _pendingQueryResets)
|
||||
{
|
||||
query.PoolReset(CommandBuffer);
|
||||
}
|
||||
|
||||
_pendingQueryResets.Clear();
|
||||
}
|
||||
|
||||
_pendingQueryCopies.Clear();
|
||||
}
|
||||
|
||||
@ -238,10 +226,12 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
Gd.Api.CmdBeginQuery(CommandBuffer, queryPool, 0, Gd.Capabilities.SupportsPreciseOcclusionQueries ? QueryControlFlags.PreciseBit : 0);
|
||||
}
|
||||
|
||||
Gd.ResetCounterPool();
|
||||
|
||||
Restore();
|
||||
}
|
||||
|
||||
public void BeginQuery(BufferedQuery query, QueryPool pool, bool needsReset)
|
||||
public void BeginQuery(BufferedQuery query, QueryPool pool, bool needsReset, bool fromSamplePool)
|
||||
{
|
||||
if (needsReset)
|
||||
{
|
||||
@ -249,9 +239,11 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
|
||||
Gd.Api.CmdResetQueryPool(CommandBuffer, pool, 0, 1);
|
||||
|
||||
lock (_pendingQueryResets)
|
||||
if (fromSamplePool)
|
||||
{
|
||||
_pendingQueryResets.Remove(query); // Might be present on here.
|
||||
// Try reset some additional queries in advance.
|
||||
|
||||
Gd.ResetFutureCounters(CommandBuffer, AutoFlush.GetRemainingQueries());
|
||||
}
|
||||
}
|
||||
|
||||
@ -267,14 +259,6 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
_activeQueries.Remove(pool);
|
||||
}
|
||||
|
||||
public void ResetQuery(BufferedQuery query)
|
||||
{
|
||||
lock (_pendingQueryResets)
|
||||
{
|
||||
_pendingQueryResets.Add(query);
|
||||
}
|
||||
}
|
||||
|
||||
public void CopyQueryResults(BufferedQuery query)
|
||||
{
|
||||
_pendingQueryCopies.Add(query);
|
||||
|
@ -18,7 +18,6 @@ namespace Ryujinx.Graphics.Vulkan.Queries
|
||||
private readonly PipelineFull _pipeline;
|
||||
|
||||
private QueryPool _queryPool;
|
||||
private bool _isReset;
|
||||
|
||||
private readonly BufferHolder _buffer;
|
||||
private readonly IntPtr _bufferMap;
|
||||
@ -27,6 +26,7 @@ namespace Ryujinx.Graphics.Vulkan.Queries
|
||||
private bool _isSupported;
|
||||
|
||||
private long _defaultValue;
|
||||
private int? _resetSequence;
|
||||
|
||||
public unsafe BufferedQuery(VulkanRenderer gd, Device device, PipelineFull pipeline, CounterType type, bool result32Bit)
|
||||
{
|
||||
@ -67,8 +67,8 @@ namespace Ryujinx.Graphics.Vulkan.Queries
|
||||
return type switch
|
||||
{
|
||||
CounterType.SamplesPassed => true,
|
||||
CounterType.PrimitivesGenerated => gd.Capabilities.SupportsPipelineStatisticsQuery,
|
||||
CounterType.TransformFeedbackPrimitivesWritten => gd.Capabilities.SupportsTransformFeedbackQueries,
|
||||
CounterType.PrimitivesGenerated => gd.Capabilities.SupportsGeometryShader,
|
||||
_ => false
|
||||
};
|
||||
}
|
||||
@ -92,16 +92,17 @@ namespace Ryujinx.Graphics.Vulkan.Queries
|
||||
public void Reset()
|
||||
{
|
||||
End(false);
|
||||
Begin();
|
||||
Begin(null);
|
||||
}
|
||||
|
||||
public void Begin()
|
||||
public void Begin(int? resetSequence)
|
||||
{
|
||||
if (_isSupported)
|
||||
{
|
||||
_pipeline.BeginQuery(this, _queryPool, !_isReset);
|
||||
bool needsReset = resetSequence == null || _resetSequence == null || resetSequence.Value != _resetSequence.Value;
|
||||
_pipeline.BeginQuery(this, _queryPool, needsReset, _type == CounterType.SamplesPassed && resetSequence != null);
|
||||
}
|
||||
_isReset = false;
|
||||
_resetSequence = null;
|
||||
}
|
||||
|
||||
public unsafe void End(bool withResult)
|
||||
@ -162,13 +163,14 @@ namespace Ryujinx.Graphics.Vulkan.Queries
|
||||
return data;
|
||||
}
|
||||
|
||||
public void PoolReset(CommandBuffer cmd)
|
||||
public void PoolReset(CommandBuffer cmd, int resetSequence)
|
||||
{
|
||||
if (_isSupported)
|
||||
{
|
||||
_api.CmdResetQueryPool(cmd, _queryPool, 0, 1);
|
||||
}
|
||||
_isReset = true;
|
||||
|
||||
_resetSequence = resetSequence;
|
||||
}
|
||||
|
||||
public void PoolCopy(CommandBufferScoped cbs)
|
||||
|
@ -3,6 +3,7 @@ using Silk.NET.Vulkan;
|
||||
using System;
|
||||
using System.Collections.Generic;
|
||||
using System.Threading;
|
||||
using System.Linq;
|
||||
|
||||
namespace Ryujinx.Graphics.Vulkan.Queries
|
||||
{
|
||||
@ -32,6 +33,8 @@ namespace Ryujinx.Graphics.Vulkan.Queries
|
||||
|
||||
private Thread _consumerThread;
|
||||
|
||||
public int ResetSequence { get; private set; }
|
||||
|
||||
internal CounterQueue(VulkanRenderer gd, Device device, PipelineFull pipeline, CounterType type)
|
||||
{
|
||||
_gd = gd;
|
||||
@ -53,6 +56,24 @@ namespace Ryujinx.Graphics.Vulkan.Queries
|
||||
_consumerThread.Start();
|
||||
}
|
||||
|
||||
public void ResetCounterPool()
|
||||
{
|
||||
ResetSequence++;
|
||||
}
|
||||
|
||||
public void ResetFutureCounters(CommandBuffer cmd, int count)
|
||||
{
|
||||
// Pre-emptively reset queries to avoid render pass splitting.
|
||||
lock (_queryPool)
|
||||
{
|
||||
count = Math.Min(count, _queryPool.Count);
|
||||
for (int i = 0; i < count; i++)
|
||||
{
|
||||
_queryPool.ElementAt(i).PoolReset(cmd, ResetSequence);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
private void EventConsumer()
|
||||
{
|
||||
while (!Disposed)
|
||||
@ -106,7 +127,7 @@ namespace Ryujinx.Graphics.Vulkan.Queries
|
||||
{
|
||||
lock (_lock)
|
||||
{
|
||||
_pipeline.ResetQuery(query);
|
||||
// The query will be reset when it dequeues.
|
||||
_queryPool.Enqueue(query);
|
||||
}
|
||||
}
|
||||
|
@ -34,7 +34,7 @@ namespace Ryujinx.Graphics.Vulkan.Queries
|
||||
|
||||
DrawIndex = drawIndex;
|
||||
|
||||
_counter.Begin();
|
||||
_counter.Begin(_queue.ResetSequence);
|
||||
}
|
||||
|
||||
public Auto<DisposableBuffer> GetBuffer()
|
||||
|
@ -24,6 +24,19 @@ namespace Ryujinx.Graphics.Vulkan.Queries
|
||||
}
|
||||
}
|
||||
|
||||
public void ResetCounterPool()
|
||||
{
|
||||
foreach (var queue in _counterQueues)
|
||||
{
|
||||
queue.ResetCounterPool();
|
||||
}
|
||||
}
|
||||
|
||||
public void ResetFutureCounters(CommandBuffer cmd, int count)
|
||||
{
|
||||
_counterQueues[(int)CounterType.SamplesPassed].ResetFutureCounters(cmd, count);
|
||||
}
|
||||
|
||||
public CounterQueueEvent QueueReport(CounterType type, EventHandler<ulong> resultHandler, bool hostReserved)
|
||||
{
|
||||
return _counterQueues[(int)type].QueueReport(resultHandler, _pipeline.DrawCount, hostReserved);
|
||||
|
@ -0,0 +1,10 @@
|
||||
#version 450 core
|
||||
|
||||
layout (binding = 0, set = 2) uniform sampler2D texDepth;
|
||||
|
||||
layout (location = 0) in vec2 tex_coord;
|
||||
|
||||
void main()
|
||||
{
|
||||
gl_FragDepth = texture(texDepth, tex_coord).r;
|
||||
}
|
@ -1459,5 +1459,95 @@ namespace Ryujinx.Graphics.Vulkan.Shaders
|
||||
0x3B, 0x01, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0xF9, 0x00, 0x02, 0x00, 0xE3, 0x00, 0x00, 0x00,
|
||||
0xF8, 0x00, 0x02, 0x00, 0xE5, 0x00, 0x00, 0x00, 0xFD, 0x00, 0x01, 0x00, 0x38, 0x00, 0x01, 0x00,
|
||||
};
|
||||
|
||||
public static readonly byte[] DepthBlitFragmentShaderSource = new byte[]
|
||||
{
|
||||
0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0B, 0x00, 0x08, 0x00, 0x17, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x06, 0x00,
|
||||
0x01, 0x00, 0x00, 0x00, 0x47, 0x4C, 0x53, 0x4C, 0x2E, 0x73, 0x74, 0x64, 0x2E, 0x34, 0x35, 0x30,
|
||||
0x00, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
|
||||
0x0F, 0x00, 0x07, 0x00, 0x04, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x6D, 0x61, 0x69, 0x6E,
|
||||
0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x10, 0x00, 0x03, 0x00,
|
||||
0x04, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x10, 0x00, 0x03, 0x00, 0x04, 0x00, 0x00, 0x00,
|
||||
0x0C, 0x00, 0x00, 0x00, 0x03, 0x00, 0x03, 0x00, 0x02, 0x00, 0x00, 0x00, 0xC2, 0x01, 0x00, 0x00,
|
||||
0x05, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x6D, 0x61, 0x69, 0x6E, 0x00, 0x00, 0x00, 0x00,
|
||||
0x05, 0x00, 0x06, 0x00, 0x08, 0x00, 0x00, 0x00, 0x67, 0x6C, 0x5F, 0x46, 0x72, 0x61, 0x67, 0x44,
|
||||
0x65, 0x70, 0x74, 0x68, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x05, 0x00, 0x0C, 0x00, 0x00, 0x00,
|
||||
0x74, 0x65, 0x78, 0x44, 0x65, 0x70, 0x74, 0x68, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x05, 0x00,
|
||||
0x10, 0x00, 0x00, 0x00, 0x74, 0x65, 0x78, 0x5F, 0x63, 0x6F, 0x6F, 0x72, 0x64, 0x00, 0x00, 0x00,
|
||||
0x47, 0x00, 0x04, 0x00, 0x08, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00,
|
||||
0x47, 0x00, 0x04, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00,
|
||||
0x47, 0x00, 0x04, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x47, 0x00, 0x04, 0x00, 0x10, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x13, 0x00, 0x02, 0x00, 0x02, 0x00, 0x00, 0x00, 0x21, 0x00, 0x03, 0x00, 0x03, 0x00, 0x00, 0x00,
|
||||
0x02, 0x00, 0x00, 0x00, 0x16, 0x00, 0x03, 0x00, 0x06, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00,
|
||||
0x20, 0x00, 0x04, 0x00, 0x07, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00,
|
||||
0x3B, 0x00, 0x04, 0x00, 0x07, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00,
|
||||
0x19, 0x00, 0x09, 0x00, 0x09, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x1B, 0x00, 0x03, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00,
|
||||
0x20, 0x00, 0x04, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00,
|
||||
0x3B, 0x00, 0x04, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x17, 0x00, 0x04, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00,
|
||||
0x20, 0x00, 0x04, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00,
|
||||
0x3B, 0x00, 0x04, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
|
||||
0x17, 0x00, 0x04, 0x00, 0x12, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00,
|
||||
0x36, 0x00, 0x05, 0x00, 0x02, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x03, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x02, 0x00, 0x05, 0x00, 0x00, 0x00, 0x3D, 0x00, 0x04, 0x00,
|
||||
0x0A, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x3D, 0x00, 0x04, 0x00,
|
||||
0x0E, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x57, 0x00, 0x05, 0x00,
|
||||
0x12, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00,
|
||||
0x51, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x03, 0x00, 0x08, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00,
|
||||
0xFD, 0x00, 0x01, 0x00, 0x38, 0x00, 0x01, 0x00,
|
||||
};
|
||||
|
||||
public static readonly byte[] StencilBlitFragmentShaderSource = new byte[]
|
||||
{
|
||||
0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0B, 0x00, 0x08, 0x00, 0x18, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00,
|
||||
0x95, 0x13, 0x00, 0x00, 0x0A, 0x00, 0x09, 0x00, 0x53, 0x50, 0x56, 0x5F, 0x45, 0x58, 0x54, 0x5F,
|
||||
0x73, 0x68, 0x61, 0x64, 0x65, 0x72, 0x5F, 0x73, 0x74, 0x65, 0x6E, 0x63, 0x69, 0x6C, 0x5F, 0x65,
|
||||
0x78, 0x70, 0x6F, 0x72, 0x74, 0x00, 0x00, 0x00, 0x0B, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00,
|
||||
0x47, 0x4C, 0x53, 0x4C, 0x2E, 0x73, 0x74, 0x64, 0x2E, 0x34, 0x35, 0x30, 0x00, 0x00, 0x00, 0x00,
|
||||
0x0E, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x07, 0x00,
|
||||
0x04, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x6D, 0x61, 0x69, 0x6E, 0x00, 0x00, 0x00, 0x00,
|
||||
0x08, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x10, 0x00, 0x03, 0x00, 0x04, 0x00, 0x00, 0x00,
|
||||
0x07, 0x00, 0x00, 0x00, 0x10, 0x00, 0x03, 0x00, 0x04, 0x00, 0x00, 0x00, 0xA3, 0x13, 0x00, 0x00,
|
||||
0x03, 0x00, 0x03, 0x00, 0x02, 0x00, 0x00, 0x00, 0xC2, 0x01, 0x00, 0x00, 0x04, 0x00, 0x09, 0x00,
|
||||
0x47, 0x4C, 0x5F, 0x41, 0x52, 0x42, 0x5F, 0x73, 0x68, 0x61, 0x64, 0x65, 0x72, 0x5F, 0x73, 0x74,
|
||||
0x65, 0x6E, 0x63, 0x69, 0x6C, 0x5F, 0x65, 0x78, 0x70, 0x6F, 0x72, 0x74, 0x00, 0x00, 0x00, 0x00,
|
||||
0x05, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x6D, 0x61, 0x69, 0x6E, 0x00, 0x00, 0x00, 0x00,
|
||||
0x05, 0x00, 0x08, 0x00, 0x08, 0x00, 0x00, 0x00, 0x67, 0x6C, 0x5F, 0x46, 0x72, 0x61, 0x67, 0x53,
|
||||
0x74, 0x65, 0x6E, 0x63, 0x69, 0x6C, 0x52, 0x65, 0x66, 0x41, 0x52, 0x42, 0x00, 0x00, 0x00, 0x00,
|
||||
0x05, 0x00, 0x05, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x74, 0x65, 0x78, 0x53, 0x74, 0x65, 0x6E, 0x63,
|
||||
0x69, 0x6C, 0x00, 0x00, 0x05, 0x00, 0x05, 0x00, 0x11, 0x00, 0x00, 0x00, 0x74, 0x65, 0x78, 0x5F,
|
||||
0x63, 0x6F, 0x6F, 0x72, 0x64, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x08, 0x00, 0x00, 0x00,
|
||||
0x0B, 0x00, 0x00, 0x00, 0x96, 0x13, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x0C, 0x00, 0x00, 0x00,
|
||||
0x22, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x0C, 0x00, 0x00, 0x00,
|
||||
0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x11, 0x00, 0x00, 0x00,
|
||||
0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 0x00, 0x02, 0x00, 0x02, 0x00, 0x00, 0x00,
|
||||
0x21, 0x00, 0x03, 0x00, 0x03, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x15, 0x00, 0x04, 0x00,
|
||||
0x06, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x20, 0x00, 0x04, 0x00,
|
||||
0x07, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x3B, 0x00, 0x04, 0x00,
|
||||
0x07, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x19, 0x00, 0x09, 0x00,
|
||||
0x09, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x1B, 0x00, 0x03, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x20, 0x00, 0x04, 0x00,
|
||||
0x0B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x3B, 0x00, 0x04, 0x00,
|
||||
0x0B, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0x00, 0x03, 0x00,
|
||||
0x0E, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x17, 0x00, 0x04, 0x00, 0x0F, 0x00, 0x00, 0x00,
|
||||
0x0E, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x20, 0x00, 0x04, 0x00, 0x10, 0x00, 0x00, 0x00,
|
||||
0x01, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x3B, 0x00, 0x04, 0x00, 0x10, 0x00, 0x00, 0x00,
|
||||
0x11, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x17, 0x00, 0x04, 0x00, 0x13, 0x00, 0x00, 0x00,
|
||||
0x06, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x36, 0x00, 0x05, 0x00, 0x02, 0x00, 0x00, 0x00,
|
||||
0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x02, 0x00,
|
||||
0x05, 0x00, 0x00, 0x00, 0x3D, 0x00, 0x04, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00,
|
||||
0x0C, 0x00, 0x00, 0x00, 0x3D, 0x00, 0x04, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00,
|
||||
0x11, 0x00, 0x00, 0x00, 0x57, 0x00, 0x05, 0x00, 0x13, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00,
|
||||
0x0D, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x51, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00,
|
||||
0x17, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3E, 0x00, 0x03, 0x00,
|
||||
0x08, 0x00, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0xFD, 0x00, 0x01, 0x00, 0x38, 0x00, 0x01, 0x00,
|
||||
};
|
||||
}
|
||||
}
|
@ -0,0 +1,12 @@
|
||||
#version 450 core
|
||||
|
||||
#extension GL_ARB_shader_stencil_export : require
|
||||
|
||||
layout (binding = 0, set = 2) uniform isampler2D texStencil;
|
||||
|
||||
layout (location = 0) in vec2 tex_coord;
|
||||
|
||||
void main()
|
||||
{
|
||||
gl_FragStencilRefARB = texture(texStencil, tex_coord).r;
|
||||
}
|
@ -362,21 +362,16 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
levels,
|
||||
linearFilter);
|
||||
|
||||
return;
|
||||
}
|
||||
else if (srcFormat == GAL.Format.D32FloatS8Uint && srcFormat == dstFormat && SupportsBlitFromD32FS8ToD32FAndS8())
|
||||
{
|
||||
BlitDepthStencilWithBuffer(_gd, cbs, src, dst, srcRegion, dstRegion);
|
||||
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
bool isDepthOrStencil = dst.Info.Format.IsDepthOrStencil();
|
||||
|
||||
if (VulkanConfiguration.UseSlowSafeBlitOnAmd &&
|
||||
(_gd.Vendor == Vendor.Amd || _gd.IsMoltenVk) &&
|
||||
src.Info.Target == Target.Texture2D &&
|
||||
dst.Info.Target == Target.Texture2D &&
|
||||
!dst.Info.Format.IsDepthOrStencil())
|
||||
dst.Info.Target == Target.Texture2D)
|
||||
{
|
||||
_gd.HelperShader.Blit(
|
||||
_gd,
|
||||
@ -387,6 +382,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
dst.VkFormat,
|
||||
srcRegion,
|
||||
dstRegion,
|
||||
isDepthOrStencil,
|
||||
linearFilter);
|
||||
|
||||
return;
|
||||
@ -395,7 +391,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
Auto<DisposableImage> srcImage;
|
||||
Auto<DisposableImage> dstImage;
|
||||
|
||||
if (dst.Info.Format.IsDepthOrStencil())
|
||||
if (isDepthOrStencil)
|
||||
{
|
||||
srcImage = src.Storage.CreateAliasedColorForDepthStorageUnsafe(srcFormat).GetImage();
|
||||
dstImage = dst.Storage.CreateAliasedColorForDepthStorageUnsafe(dstFormat).GetImage();
|
||||
@ -426,189 +422,6 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
ImageAspectFlags.ColorBit);
|
||||
}
|
||||
|
||||
private static void BlitDepthStencilWithBuffer(
|
||||
VulkanRenderer gd,
|
||||
CommandBufferScoped cbs,
|
||||
TextureView src,
|
||||
TextureView dst,
|
||||
Extents2D srcRegion,
|
||||
Extents2D dstRegion)
|
||||
{
|
||||
int drBaseX = Math.Min(dstRegion.X1, dstRegion.X2);
|
||||
int drBaseY = Math.Min(dstRegion.Y1, dstRegion.Y2);
|
||||
int drWidth = Math.Abs(dstRegion.X2 - dstRegion.X1);
|
||||
int drHeight = Math.Abs(dstRegion.Y2 - dstRegion.Y1);
|
||||
|
||||
var drOriginZero = new Extents2D(
|
||||
dstRegion.X1 - drBaseX,
|
||||
dstRegion.Y1 - drBaseY,
|
||||
dstRegion.X2 - drBaseX,
|
||||
dstRegion.Y2 - drBaseY);
|
||||
|
||||
var d32SrcStorageInfo = TextureStorage.NewCreateInfoWith(ref src._info, GAL.Format.D32Float, 4);
|
||||
var d32DstStorageInfo = TextureStorage.NewCreateInfoWith(ref dst._info, GAL.Format.D32Float, 4, drWidth, drHeight);
|
||||
var s8SrcStorageInfo = TextureStorage.NewCreateInfoWith(ref src._info, GAL.Format.S8Uint, 1);
|
||||
var s8DstStorageInfo = TextureStorage.NewCreateInfoWith(ref dst._info, GAL.Format.S8Uint, 1, drWidth, drHeight);
|
||||
|
||||
using var d32SrcStorage = gd.CreateTextureStorage(d32SrcStorageInfo, src.Storage.ScaleFactor);
|
||||
using var d32DstStorage = gd.CreateTextureStorage(d32DstStorageInfo, dst.Storage.ScaleFactor);
|
||||
using var s8SrcStorage = gd.CreateTextureStorage(s8SrcStorageInfo, src.Storage.ScaleFactor);
|
||||
using var s8DstStorage = gd.CreateTextureStorage(s8DstStorageInfo, dst.Storage.ScaleFactor);
|
||||
|
||||
void SlowBlit(TextureStorage srcTemp, TextureStorage dstTemp, ImageAspectFlags aspectFlags)
|
||||
{
|
||||
int levels = Math.Min(src.Info.Levels, dst.Info.Levels);
|
||||
|
||||
int srcSize = 0;
|
||||
int dstSize = 0;
|
||||
|
||||
for (int l = 0; l < levels; l++)
|
||||
{
|
||||
srcSize += srcTemp.Info.GetMipSize2D(l);
|
||||
dstSize += dstTemp.Info.GetMipSize2D(l);
|
||||
}
|
||||
|
||||
using var srcTempBuffer = gd.BufferManager.Create(gd, srcSize, deviceLocal: true);
|
||||
using var dstTempBuffer = gd.BufferManager.Create(gd, dstSize, deviceLocal: true);
|
||||
|
||||
src.Storage.CopyFromOrToBuffer(
|
||||
cbs.CommandBuffer,
|
||||
srcTempBuffer.GetBuffer().Get(cbs, 0, srcSize).Value,
|
||||
src.GetImage().Get(cbs).Value,
|
||||
srcSize,
|
||||
to: true,
|
||||
0,
|
||||
0,
|
||||
src.FirstLayer,
|
||||
src.FirstLevel,
|
||||
1,
|
||||
levels,
|
||||
true,
|
||||
aspectFlags,
|
||||
false);
|
||||
|
||||
BufferHolder.InsertBufferBarrier(
|
||||
gd,
|
||||
cbs.CommandBuffer,
|
||||
srcTempBuffer.GetBuffer().Get(cbs, 0, srcSize).Value,
|
||||
AccessFlags.TransferWriteBit,
|
||||
AccessFlags.TransferReadBit,
|
||||
PipelineStageFlags.TransferBit,
|
||||
PipelineStageFlags.TransferBit,
|
||||
0,
|
||||
srcSize);
|
||||
|
||||
srcTemp.CopyFromOrToBuffer(
|
||||
cbs.CommandBuffer,
|
||||
srcTempBuffer.GetBuffer().Get(cbs, 0, srcSize).Value,
|
||||
srcTemp.GetImage().Get(cbs).Value,
|
||||
srcSize,
|
||||
to: false,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
levels,
|
||||
true,
|
||||
aspectFlags,
|
||||
false);
|
||||
|
||||
InsertImageBarrier(
|
||||
gd.Api,
|
||||
cbs.CommandBuffer,
|
||||
srcTemp.GetImage().Get(cbs).Value,
|
||||
AccessFlags.TransferWriteBit,
|
||||
AccessFlags.TransferReadBit,
|
||||
PipelineStageFlags.TransferBit,
|
||||
PipelineStageFlags.TransferBit,
|
||||
aspectFlags,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
levels);
|
||||
|
||||
TextureCopy.Blit(
|
||||
gd.Api,
|
||||
cbs.CommandBuffer,
|
||||
srcTemp.GetImage().Get(cbs).Value,
|
||||
dstTemp.GetImage().Get(cbs).Value,
|
||||
srcTemp.Info,
|
||||
dstTemp.Info,
|
||||
srcRegion,
|
||||
drOriginZero,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
levels,
|
||||
false,
|
||||
aspectFlags,
|
||||
aspectFlags);
|
||||
|
||||
InsertImageBarrier(
|
||||
gd.Api,
|
||||
cbs.CommandBuffer,
|
||||
dstTemp.GetImage().Get(cbs).Value,
|
||||
AccessFlags.TransferWriteBit,
|
||||
AccessFlags.TransferReadBit,
|
||||
PipelineStageFlags.TransferBit,
|
||||
PipelineStageFlags.TransferBit,
|
||||
aspectFlags,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
levels);
|
||||
|
||||
dstTemp.CopyFromOrToBuffer(
|
||||
cbs.CommandBuffer,
|
||||
dstTempBuffer.GetBuffer().Get(cbs, 0, dstSize).Value,
|
||||
dstTemp.GetImage().Get(cbs).Value,
|
||||
dstSize,
|
||||
to: true,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
levels,
|
||||
true,
|
||||
aspectFlags,
|
||||
false);
|
||||
|
||||
BufferHolder.InsertBufferBarrier(
|
||||
gd,
|
||||
cbs.CommandBuffer,
|
||||
dstTempBuffer.GetBuffer().Get(cbs, 0, dstSize).Value,
|
||||
AccessFlags.TransferWriteBit,
|
||||
AccessFlags.TransferReadBit,
|
||||
PipelineStageFlags.TransferBit,
|
||||
PipelineStageFlags.TransferBit,
|
||||
0,
|
||||
dstSize);
|
||||
|
||||
dst.Storage.CopyFromOrToBuffer(
|
||||
cbs.CommandBuffer,
|
||||
dstTempBuffer.GetBuffer().Get(cbs, 0, dstSize).Value,
|
||||
dst.GetImage().Get(cbs).Value,
|
||||
dstSize,
|
||||
to: false,
|
||||
drBaseX,
|
||||
drBaseY,
|
||||
dst.FirstLayer,
|
||||
dst.FirstLevel,
|
||||
1,
|
||||
levels,
|
||||
true,
|
||||
aspectFlags,
|
||||
false);
|
||||
}
|
||||
|
||||
SlowBlit(d32SrcStorage, d32DstStorage, ImageAspectFlags.DepthBit);
|
||||
SlowBlit(s8SrcStorage, s8DstStorage, ImageAspectFlags.StencilBit);
|
||||
}
|
||||
|
||||
public static unsafe void InsertImageBarrier(
|
||||
Vk api,
|
||||
CommandBuffer commandBuffer,
|
||||
@ -649,13 +462,6 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
memoryBarrier);
|
||||
}
|
||||
|
||||
private bool SupportsBlitFromD32FS8ToD32FAndS8()
|
||||
{
|
||||
var formatFeatureFlags = FormatFeatureFlags.BlitSrcBit | FormatFeatureFlags.BlitDstBit;
|
||||
return _gd.FormatCapabilities.OptimalFormatSupports(formatFeatureFlags, GAL.Format.D32Float) &&
|
||||
_gd.FormatCapabilities.OptimalFormatSupports(formatFeatureFlags, GAL.Format.S8Uint);
|
||||
}
|
||||
|
||||
public TextureView GetView(GAL.Format format)
|
||||
{
|
||||
if (format == Info.Format)
|
||||
|
@ -9,6 +9,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
Intel,
|
||||
Nvidia,
|
||||
ARM,
|
||||
Broadcom,
|
||||
Qualcomm,
|
||||
Apple,
|
||||
Unknown
|
||||
@ -28,6 +29,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
0x106B => Vendor.Apple,
|
||||
0x10DE => Vendor.Nvidia,
|
||||
0x13B5 => Vendor.ARM,
|
||||
0x14E4 => Vendor.Broadcom,
|
||||
0x8086 => Vendor.Intel,
|
||||
0x5143 => Vendor.Qualcomm,
|
||||
_ => Vendor.Unknown
|
||||
@ -43,6 +45,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
0x106B => "Apple",
|
||||
0x10DE => "NVIDIA",
|
||||
0x13B5 => "ARM",
|
||||
0x14E4 => "Broadcom",
|
||||
0x1AE0 => "Google",
|
||||
0x5143 => "Qualcomm",
|
||||
0x8086 => "Intel",
|
||||
|
@ -29,6 +29,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
"VK_EXT_fragment_shader_interlock",
|
||||
"VK_EXT_index_type_uint8",
|
||||
"VK_EXT_robustness2",
|
||||
"VK_EXT_shader_stencil_export",
|
||||
"VK_KHR_shader_float16_int8",
|
||||
"VK_EXT_shader_subgroup_ballot",
|
||||
"VK_EXT_subgroup_size_control",
|
||||
@ -162,7 +163,6 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
if (messageSeverity.HasFlag(DebugUtilsMessageSeverityFlagsEXT.ErrorBitExt))
|
||||
{
|
||||
Logger.Error?.Print(LogClass.Gpu, msg);
|
||||
//throw new Exception(msg);
|
||||
}
|
||||
else if (messageSeverity.HasFlag(DebugUtilsMessageSeverityFlagsEXT.WarningBitExt))
|
||||
{
|
||||
@ -379,14 +379,34 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
SType = StructureType.PhysicalDeviceFeatures2
|
||||
};
|
||||
|
||||
PhysicalDeviceCustomBorderColorFeaturesEXT featuresCustomBorderColorSupported = new PhysicalDeviceCustomBorderColorFeaturesEXT()
|
||||
PhysicalDeviceVulkan11Features supportedFeaturesVk11 = new PhysicalDeviceVulkan11Features()
|
||||
{
|
||||
SType = StructureType.PhysicalDeviceCustomBorderColorFeaturesExt
|
||||
SType = StructureType.PhysicalDeviceVulkan11Features,
|
||||
PNext = features2.PNext
|
||||
};
|
||||
|
||||
features2.PNext = &supportedFeaturesVk11;
|
||||
|
||||
PhysicalDeviceCustomBorderColorFeaturesEXT supportedFeaturesCustomBorderColor = new PhysicalDeviceCustomBorderColorFeaturesEXT()
|
||||
{
|
||||
SType = StructureType.PhysicalDeviceCustomBorderColorFeaturesExt,
|
||||
PNext = features2.PNext
|
||||
};
|
||||
|
||||
if (supportedExtensions.Contains("VK_EXT_custom_border_color"))
|
||||
{
|
||||
features2.PNext = &featuresCustomBorderColorSupported;
|
||||
features2.PNext = &supportedFeaturesCustomBorderColor;
|
||||
}
|
||||
|
||||
PhysicalDeviceTransformFeedbackFeaturesEXT supportedFeaturesTransformFeedback = new PhysicalDeviceTransformFeedbackFeaturesEXT()
|
||||
{
|
||||
SType = StructureType.PhysicalDeviceTransformFeedbackFeaturesExt,
|
||||
PNext = features2.PNext
|
||||
};
|
||||
|
||||
if (supportedExtensions.Contains(ExtTransformFeedback.ExtensionName))
|
||||
{
|
||||
features2.PNext = &supportedFeaturesTransformFeedback;
|
||||
}
|
||||
|
||||
PhysicalDeviceRobustness2FeaturesEXT supportedFeaturesRobustness2 = new PhysicalDeviceRobustness2FeaturesEXT()
|
||||
@ -408,42 +428,49 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
var features = new PhysicalDeviceFeatures()
|
||||
{
|
||||
DepthBiasClamp = true,
|
||||
DepthClamp = true,
|
||||
DualSrcBlend = true,
|
||||
DepthClamp = supportedFeatures.DepthClamp,
|
||||
DualSrcBlend = supportedFeatures.DualSrcBlend,
|
||||
FragmentStoresAndAtomics = true,
|
||||
GeometryShader = supportedFeatures.GeometryShader,
|
||||
ImageCubeArray = true,
|
||||
IndependentBlend = true,
|
||||
LogicOp = supportedFeatures.LogicOp,
|
||||
MultiViewport = true,
|
||||
OcclusionQueryPrecise = supportedFeatures.OcclusionQueryPrecise,
|
||||
MultiViewport = supportedFeatures.MultiViewport,
|
||||
PipelineStatisticsQuery = supportedFeatures.PipelineStatisticsQuery,
|
||||
SamplerAnisotropy = true,
|
||||
ShaderClipDistance = true,
|
||||
ShaderFloat64 = supportedFeatures.ShaderFloat64,
|
||||
ShaderImageGatherExtended = true,
|
||||
ShaderImageGatherExtended = supportedFeatures.ShaderImageGatherExtended,
|
||||
ShaderStorageImageMultisample = supportedFeatures.ShaderStorageImageMultisample,
|
||||
// ShaderStorageImageReadWithoutFormat = true,
|
||||
// ShaderStorageImageWriteWithoutFormat = true,
|
||||
TessellationShader = true,
|
||||
TessellationShader = supportedFeatures.TessellationShader,
|
||||
VertexPipelineStoresAndAtomics = true,
|
||||
RobustBufferAccess = useRobustBufferAccess
|
||||
};
|
||||
|
||||
void* pExtendedFeatures = null;
|
||||
|
||||
var featuresTransformFeedback = new PhysicalDeviceTransformFeedbackFeaturesEXT()
|
||||
{
|
||||
SType = StructureType.PhysicalDeviceTransformFeedbackFeaturesExt,
|
||||
PNext = pExtendedFeatures,
|
||||
TransformFeedback = true
|
||||
};
|
||||
PhysicalDeviceTransformFeedbackFeaturesEXT featuresTransformFeedback;
|
||||
|
||||
pExtendedFeatures = &featuresTransformFeedback;
|
||||
if (supportedExtensions.Contains(ExtTransformFeedback.ExtensionName))
|
||||
{
|
||||
featuresTransformFeedback = new PhysicalDeviceTransformFeedbackFeaturesEXT()
|
||||
{
|
||||
SType = StructureType.PhysicalDeviceTransformFeedbackFeaturesExt,
|
||||
PNext = pExtendedFeatures,
|
||||
TransformFeedback = supportedFeaturesTransformFeedback.TransformFeedback
|
||||
};
|
||||
|
||||
pExtendedFeatures = &featuresTransformFeedback;
|
||||
}
|
||||
|
||||
PhysicalDeviceRobustness2FeaturesEXT featuresRobustness2;
|
||||
|
||||
if (supportedExtensions.Contains("VK_EXT_robustness2"))
|
||||
{
|
||||
var featuresRobustness2 = new PhysicalDeviceRobustness2FeaturesEXT()
|
||||
featuresRobustness2 = new PhysicalDeviceRobustness2FeaturesEXT()
|
||||
{
|
||||
SType = StructureType.PhysicalDeviceRobustness2FeaturesExt,
|
||||
PNext = pExtendedFeatures,
|
||||
@ -466,7 +493,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
{
|
||||
SType = StructureType.PhysicalDeviceVulkan11Features,
|
||||
PNext = pExtendedFeatures,
|
||||
ShaderDrawParameters = true
|
||||
ShaderDrawParameters = supportedFeaturesVk11.ShaderDrawParameters
|
||||
};
|
||||
|
||||
pExtendedFeatures = &featuresVk11;
|
||||
@ -527,8 +554,8 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
PhysicalDeviceCustomBorderColorFeaturesEXT featuresCustomBorderColor;
|
||||
|
||||
if (supportedExtensions.Contains("VK_EXT_custom_border_color") &&
|
||||
featuresCustomBorderColorSupported.CustomBorderColors &&
|
||||
featuresCustomBorderColorSupported.CustomBorderColorWithoutFormat)
|
||||
supportedFeaturesCustomBorderColor.CustomBorderColors &&
|
||||
supportedFeaturesCustomBorderColor.CustomBorderColorWithoutFormat)
|
||||
{
|
||||
featuresCustomBorderColor = new PhysicalDeviceCustomBorderColorFeaturesEXT()
|
||||
{
|
||||
|
@ -263,6 +263,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
supportedExtensions.Contains("VK_NV_geometry_shader_passthrough"),
|
||||
supportedExtensions.Contains("VK_EXT_subgroup_size_control"),
|
||||
featuresShaderInt8.ShaderInt8,
|
||||
supportedExtensions.Contains("VK_EXT_shader_stencil_export"),
|
||||
supportedExtensions.Contains(ExtConditionalRendering.ExtensionName),
|
||||
supportedExtensions.Contains(ExtExtendedDynamicState.ExtensionName),
|
||||
features2.Features.MultiViewport,
|
||||
@ -271,6 +272,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
supportsTransformFeedback,
|
||||
propertiesTransformFeedback.TransformFeedbackQueries,
|
||||
features2.Features.OcclusionQueryPrecise,
|
||||
supportedFeatures.PipelineStatisticsQuery,
|
||||
supportedFeatures.GeometryShader,
|
||||
propertiesSubgroupSizeControl.MinSubgroupSize,
|
||||
propertiesSubgroupSizeControl.MaxSubgroupSize,
|
||||
@ -589,9 +591,13 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
|
||||
Vendor = VendorUtils.FromId(properties.VendorID);
|
||||
|
||||
IsAmdWindows = Vendor == Vendor.Amd && RuntimeInformation.IsOSPlatform(OSPlatform.Windows);
|
||||
IsIntelWindows = Vendor == Vendor.Intel && RuntimeInformation.IsOSPlatform(OSPlatform.Windows);
|
||||
IsTBDR = IsMoltenVk || Vendor == Vendor.Qualcomm || Vendor == Vendor.ARM || Vendor == Vendor.ImgTec;
|
||||
IsAmdWindows = Vendor == Vendor.Amd && OperatingSystem.IsWindows();
|
||||
IsIntelWindows = Vendor == Vendor.Intel && OperatingSystem.IsWindows();
|
||||
IsTBDR = IsMoltenVk ||
|
||||
Vendor == Vendor.Qualcomm ||
|
||||
Vendor == Vendor.ARM ||
|
||||
Vendor == Vendor.Broadcom ||
|
||||
Vendor == Vendor.ImgTec;
|
||||
|
||||
GpuVendor = vendorName;
|
||||
GpuRenderer = Marshal.PtrToStringAnsi((IntPtr)properties.DeviceName);
|
||||
@ -679,6 +685,16 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
_counters.Update();
|
||||
}
|
||||
|
||||
public void ResetCounterPool()
|
||||
{
|
||||
_counters.ResetCounterPool();
|
||||
}
|
||||
|
||||
public void ResetFutureCounters(CommandBuffer cmd, int count)
|
||||
{
|
||||
_counters?.ResetFutureCounters(cmd, count);
|
||||
}
|
||||
|
||||
public void BackgroundContextAction(Action action, bool alwaysBackground = false)
|
||||
{
|
||||
action();
|
||||
|
@ -120,7 +120,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
ImageSharingMode = SharingMode.Exclusive,
|
||||
ImageArrayLayers = 1,
|
||||
PreTransform = capabilities.CurrentTransform,
|
||||
CompositeAlpha = CompositeAlphaFlagsKHR.OpaqueBitKhr,
|
||||
CompositeAlpha = ChooseCompositeAlpha(capabilities.SupportedCompositeAlpha),
|
||||
PresentMode = ChooseSwapPresentMode(presentModes, _vsyncEnabled),
|
||||
Clipped = true
|
||||
};
|
||||
@ -188,6 +188,22 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
return availableFormats[0];
|
||||
}
|
||||
|
||||
private static CompositeAlphaFlagsKHR ChooseCompositeAlpha(CompositeAlphaFlagsKHR supportedFlags)
|
||||
{
|
||||
if (supportedFlags.HasFlag(CompositeAlphaFlagsKHR.OpaqueBitKhr))
|
||||
{
|
||||
return CompositeAlphaFlagsKHR.OpaqueBitKhr;
|
||||
}
|
||||
else if (supportedFlags.HasFlag(CompositeAlphaFlagsKHR.PreMultipliedBitKhr))
|
||||
{
|
||||
return CompositeAlphaFlagsKHR.PreMultipliedBitKhr;
|
||||
}
|
||||
else
|
||||
{
|
||||
return CompositeAlphaFlagsKHR.InheritBitKhr;
|
||||
}
|
||||
}
|
||||
|
||||
private static PresentModeKHR ChooseSwapPresentMode(PresentModeKHR[] availablePresentModes, bool vsyncEnabled)
|
||||
{
|
||||
if (!vsyncEnabled && availablePresentModes.Contains(PresentModeKHR.ImmediateKhr))
|
||||
@ -198,10 +214,6 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
{
|
||||
return PresentModeKHR.MailboxKhr;
|
||||
}
|
||||
else if (availablePresentModes.Contains(PresentModeKHR.FifoKhr))
|
||||
{
|
||||
return PresentModeKHR.FifoKhr;
|
||||
}
|
||||
else
|
||||
{
|
||||
return PresentModeKHR.FifoKhr;
|
||||
@ -225,6 +237,8 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
|
||||
public unsafe override void Present(ITexture texture, ImageCrop crop, Action swapBuffersCallback)
|
||||
{
|
||||
_gd.PipelineInternal.AutoFlush.Present();
|
||||
|
||||
uint nextImage = 0;
|
||||
|
||||
while (true)
|
||||
@ -321,7 +335,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
int dstY0 = crop.FlipY ? dstPaddingY : _height - dstPaddingY;
|
||||
int dstY1 = crop.FlipY ? _height - dstPaddingY : dstPaddingY;
|
||||
|
||||
_gd.HelperShader.Blit(
|
||||
_gd.HelperShader.BlitColor(
|
||||
_gd,
|
||||
cbs,
|
||||
view,
|
||||
|
@ -148,6 +148,11 @@ namespace Ryujinx.HLE
|
||||
/// </summary>
|
||||
public float AudioVolume { get; set; }
|
||||
|
||||
/// <summary>
|
||||
/// Use Hypervisor over JIT if available.
|
||||
/// </summary>
|
||||
internal readonly bool UseHypervisor;
|
||||
|
||||
/// <summary>
|
||||
/// An action called when HLE force a refresh of output after docked mode changed.
|
||||
/// </summary>
|
||||
@ -175,7 +180,8 @@ namespace Ryujinx.HLE
|
||||
MemoryManagerMode memoryManagerMode,
|
||||
bool ignoreMissingServices,
|
||||
AspectRatio aspectRatio,
|
||||
float audioVolume)
|
||||
float audioVolume,
|
||||
bool useHypervisor)
|
||||
{
|
||||
VirtualFileSystem = virtualFileSystem;
|
||||
LibHacHorizonManager = libHacHorizonManager;
|
||||
@ -200,6 +206,7 @@ namespace Ryujinx.HLE
|
||||
IgnoreMissingServices = ignoreMissingServices;
|
||||
AspectRatio = aspectRatio;
|
||||
AudioVolume = audioVolume;
|
||||
UseHypervisor = useHypervisor;
|
||||
}
|
||||
}
|
||||
}
|
@ -1,17 +1,19 @@
|
||||
using Ryujinx.Common.Configuration;
|
||||
using Ryujinx.Cpu;
|
||||
using Ryujinx.Cpu.AppleHv;
|
||||
using Ryujinx.Cpu.Jit;
|
||||
using Ryujinx.Graphics.Gpu;
|
||||
using Ryujinx.HLE.HOS.Kernel;
|
||||
using Ryujinx.HLE.HOS.Kernel.Process;
|
||||
using Ryujinx.Memory;
|
||||
using System;
|
||||
using System.Runtime.InteropServices;
|
||||
|
||||
namespace Ryujinx.HLE.HOS
|
||||
{
|
||||
class ArmProcessContextFactory : IProcessContextFactory
|
||||
{
|
||||
private readonly ICpuEngine _cpuEngine;
|
||||
private readonly ITickSource _tickSource;
|
||||
private readonly GpuContext _gpu;
|
||||
private readonly string _titleIdText;
|
||||
private readonly string _displayVersion;
|
||||
@ -22,7 +24,7 @@ namespace Ryujinx.HLE.HOS
|
||||
public IDiskCacheLoadState DiskCacheLoadState { get; private set; }
|
||||
|
||||
public ArmProcessContextFactory(
|
||||
ICpuEngine cpuEngine,
|
||||
ITickSource tickSource,
|
||||
GpuContext gpu,
|
||||
string titleIdText,
|
||||
string displayVersion,
|
||||
@ -30,7 +32,7 @@ namespace Ryujinx.HLE.HOS
|
||||
ulong codeAddress,
|
||||
ulong codeSize)
|
||||
{
|
||||
_cpuEngine = cpuEngine;
|
||||
_tickSource = tickSource;
|
||||
_gpu = gpu;
|
||||
_titleIdText = titleIdText;
|
||||
_displayVersion = displayVersion;
|
||||
@ -41,31 +43,42 @@ namespace Ryujinx.HLE.HOS
|
||||
|
||||
public IProcessContext Create(KernelContext context, ulong pid, ulong addressSpaceSize, InvalidAccessHandler invalidAccessHandler, bool for64Bit)
|
||||
{
|
||||
MemoryManagerMode mode = context.Device.Configuration.MemoryManagerMode;
|
||||
|
||||
if (!MemoryBlock.SupportsFlags(MemoryAllocationFlags.ViewCompatible))
|
||||
{
|
||||
mode = MemoryManagerMode.SoftwarePageTable;
|
||||
}
|
||||
|
||||
IArmProcessContext processContext;
|
||||
|
||||
switch (mode)
|
||||
if (OperatingSystem.IsMacOS() && RuntimeInformation.ProcessArchitecture == Architecture.Arm64 && for64Bit && context.Device.Configuration.UseHypervisor)
|
||||
{
|
||||
case MemoryManagerMode.SoftwarePageTable:
|
||||
var memoryManager = new MemoryManager(context.Memory, addressSpaceSize, invalidAccessHandler);
|
||||
processContext = new ArmProcessContext<MemoryManager>(pid, _cpuEngine, _gpu, memoryManager, for64Bit);
|
||||
break;
|
||||
var cpuEngine = new HvEngine(_tickSource);
|
||||
var memoryManager = new HvMemoryManager(context.Memory, addressSpaceSize, invalidAccessHandler);
|
||||
processContext = new ArmProcessContext<HvMemoryManager>(pid, cpuEngine, _gpu, memoryManager, for64Bit);
|
||||
}
|
||||
else
|
||||
{
|
||||
MemoryManagerMode mode = context.Device.Configuration.MemoryManagerMode;
|
||||
|
||||
case MemoryManagerMode.HostMapped:
|
||||
case MemoryManagerMode.HostMappedUnsafe:
|
||||
bool unsafeMode = mode == MemoryManagerMode.HostMappedUnsafe;
|
||||
var memoryManagerHostMapped = new MemoryManagerHostMapped(context.Memory, addressSpaceSize, unsafeMode, invalidAccessHandler);
|
||||
processContext = new ArmProcessContext<MemoryManagerHostMapped>(pid, _cpuEngine, _gpu, memoryManagerHostMapped, for64Bit);
|
||||
break;
|
||||
if (!MemoryBlock.SupportsFlags(MemoryAllocationFlags.ViewCompatible))
|
||||
{
|
||||
mode = MemoryManagerMode.SoftwarePageTable;
|
||||
}
|
||||
|
||||
default:
|
||||
throw new ArgumentOutOfRangeException();
|
||||
var cpuEngine = new JitEngine(_tickSource);
|
||||
|
||||
switch (mode)
|
||||
{
|
||||
case MemoryManagerMode.SoftwarePageTable:
|
||||
var memoryManager = new MemoryManager(context.Memory, addressSpaceSize, invalidAccessHandler);
|
||||
processContext = new ArmProcessContext<MemoryManager>(pid, cpuEngine, _gpu, memoryManager, for64Bit);
|
||||
break;
|
||||
|
||||
case MemoryManagerMode.HostMapped:
|
||||
case MemoryManagerMode.HostMappedUnsafe:
|
||||
bool unsafeMode = mode == MemoryManagerMode.HostMappedUnsafe;
|
||||
var memoryManagerHostMapped = new MemoryManagerHostMapped(context.Memory, addressSpaceSize, unsafeMode, invalidAccessHandler);
|
||||
processContext = new ArmProcessContext<MemoryManagerHostMapped>(pid, cpuEngine, _gpu, memoryManagerHostMapped, for64Bit);
|
||||
break;
|
||||
|
||||
default:
|
||||
throw new ArgumentOutOfRangeException();
|
||||
}
|
||||
}
|
||||
|
||||
DiskCacheLoadState = processContext.Initialize(_titleIdText, _displayVersion, _diskCacheEnabled, _codeAddress, _codeSize);
|
||||
|
@ -12,7 +12,6 @@ using Ryujinx.Audio.Renderer.Device;
|
||||
using Ryujinx.Audio.Renderer.Server;
|
||||
using Ryujinx.Common.Utilities;
|
||||
using Ryujinx.Cpu;
|
||||
using Ryujinx.Cpu.Jit;
|
||||
using Ryujinx.HLE.FileSystem;
|
||||
using Ryujinx.HLE.HOS.Kernel;
|
||||
using Ryujinx.HLE.HOS.Kernel.Memory;
|
||||
@ -61,7 +60,6 @@ namespace Ryujinx.HLE.HOS
|
||||
internal Switch Device { get; private set; }
|
||||
|
||||
internal ITickSource TickSource { get; }
|
||||
internal ICpuEngine CpuEngine { get; }
|
||||
|
||||
internal SurfaceFlinger SurfaceFlinger { get; private set; }
|
||||
internal AudioManager AudioManager { get; private set; }
|
||||
@ -130,7 +128,6 @@ namespace Ryujinx.HLE.HOS
|
||||
public Horizon(Switch device)
|
||||
{
|
||||
TickSource = new TickSource(KernelConstants.CounterFrequency);
|
||||
CpuEngine = new JitEngine(TickSource);
|
||||
|
||||
KernelContext = new KernelContext(
|
||||
TickSource,
|
||||
|
@ -129,7 +129,7 @@ namespace Ryujinx.HLE.HOS
|
||||
KProcess process = new KProcess(context);
|
||||
|
||||
var processContextFactory = new ArmProcessContextFactory(
|
||||
context.Device.System.CpuEngine,
|
||||
context.Device.System.TickSource,
|
||||
context.Device.Gpu,
|
||||
string.Empty,
|
||||
string.Empty,
|
||||
@ -308,7 +308,7 @@ namespace Ryujinx.HLE.HOS
|
||||
}
|
||||
|
||||
var processContextFactory = new ArmProcessContextFactory(
|
||||
context.Device.System.CpuEngine,
|
||||
context.Device.System.TickSource,
|
||||
context.Device.Gpu,
|
||||
programInfo.TitleIdText,
|
||||
programInfo.DisplayVersion,
|
||||
|
@ -137,7 +137,7 @@ namespace Ryujinx.HLE.HOS.Services.Account.Acc
|
||||
|
||||
return resultCode;
|
||||
}
|
||||
|
||||
|
||||
[CommandHipc(110)]
|
||||
// StoreSaveDataThumbnail(nn::account::Uid, buffer<bytes, 5>)
|
||||
public ResultCode StoreSaveDataThumbnail(ServiceCtx context)
|
||||
@ -153,10 +153,17 @@ namespace Ryujinx.HLE.HOS.Services.Account.Acc
|
||||
}
|
||||
|
||||
[CommandHipc(130)] // 5.0.0+
|
||||
// LoadOpenContext(nn::account::Uid)
|
||||
// LoadOpenContext(nn::account::Uid) -> object<nn::account::baas::IManagerForApplication>
|
||||
public ResultCode LoadOpenContext(ServiceCtx context)
|
||||
{
|
||||
Logger.Stub?.PrintStub(LogClass.ServiceAcc);
|
||||
ResultCode resultCode = _applicationServiceServer.CheckUserId(context, out UserId userId);
|
||||
|
||||
if (resultCode != ResultCode.Success)
|
||||
{
|
||||
return resultCode;
|
||||
}
|
||||
|
||||
MakeObject(context, new IManagerForApplication(userId));
|
||||
|
||||
return ResultCode.Success;
|
||||
}
|
||||
|
@ -129,6 +129,9 @@ namespace Ryujinx.Headless.SDL2
|
||||
[Option("audio-volume", Required = false, Default = 1.0f, HelpText ="The audio level (0 to 1).")]
|
||||
public float AudioVolume { get; set; }
|
||||
|
||||
[Option("use-hypervisor", Required = false, Default = true, HelpText = "Uses Hypervisor over JIT if available.")]
|
||||
public bool UseHypervisor { get; set; }
|
||||
|
||||
// Logging
|
||||
|
||||
[Option("disable-file-logging", Required = false, Default = false, HelpText = "Disables logging to a file on disk.")]
|
||||
|
@ -548,7 +548,8 @@ namespace Ryujinx.Headless.SDL2
|
||||
options.MemoryManagerMode,
|
||||
options.IgnoreMissingServices,
|
||||
options.AspectRatio,
|
||||
options.AudioVolume);
|
||||
options.AudioVolume,
|
||||
options.UseHypervisor);
|
||||
|
||||
return new Switch(configuration);
|
||||
}
|
||||
|
@ -14,7 +14,7 @@ namespace Ryujinx.Ui.Common.Configuration
|
||||
/// <summary>
|
||||
/// The current version of the file format
|
||||
/// </summary>
|
||||
public const int CurrentVersion = 42;
|
||||
public const int CurrentVersion = 43;
|
||||
|
||||
/// <summary>
|
||||
/// Version of the configuration file format
|
||||
@ -330,6 +330,11 @@ namespace Ryujinx.Ui.Common.Configuration
|
||||
/// </summary>
|
||||
public string PreferredGpu { get; set; }
|
||||
|
||||
/// <summary>
|
||||
/// Uses Hypervisor over JIT if available
|
||||
/// </summary>
|
||||
public bool UseHypervisor { get; set; }
|
||||
|
||||
/// <summary>
|
||||
/// Loads a configuration file from disk
|
||||
/// </summary>
|
||||
|
@ -301,6 +301,11 @@ namespace Ryujinx.Ui.Common.Configuration
|
||||
/// </summary>
|
||||
public ReactiveObject<bool> IgnoreMissingServices { get; private set; }
|
||||
|
||||
/// <summary>
|
||||
/// Uses Hypervisor over JIT if available
|
||||
/// </summary>
|
||||
public ReactiveObject<bool> UseHypervisor { get; private set; }
|
||||
|
||||
public SystemSection()
|
||||
{
|
||||
Language = new ReactiveObject<Language>();
|
||||
@ -327,6 +332,8 @@ namespace Ryujinx.Ui.Common.Configuration
|
||||
IgnoreMissingServices.Event += static (sender, e) => LogValueChange(sender, e, nameof(IgnoreMissingServices));
|
||||
AudioVolume = new ReactiveObject<float>();
|
||||
AudioVolume.Event += static (sender, e) => LogValueChange(sender, e, nameof(AudioVolume));
|
||||
UseHypervisor = new ReactiveObject<bool>();
|
||||
UseHypervisor.Event += static (sender, e) => LogValueChange(sender, e, nameof(UseHypervisor));
|
||||
}
|
||||
}
|
||||
|
||||
@ -566,6 +573,7 @@ namespace Ryujinx.Ui.Common.Configuration
|
||||
MemoryManagerMode = System.MemoryManagerMode,
|
||||
ExpandRam = System.ExpandRam,
|
||||
IgnoreMissingServices = System.IgnoreMissingServices,
|
||||
UseHypervisor = System.UseHypervisor,
|
||||
GuiColumns = new GuiColumns
|
||||
{
|
||||
FavColumn = Ui.GuiColumns.FavColumn,
|
||||
@ -652,6 +660,7 @@ namespace Ryujinx.Ui.Common.Configuration
|
||||
System.MemoryManagerMode.Value = MemoryManagerMode.HostMappedUnsafe;
|
||||
System.ExpandRam.Value = false;
|
||||
System.IgnoreMissingServices.Value = false;
|
||||
System.UseHypervisor.Value = true;
|
||||
Ui.GuiColumns.FavColumn.Value = true;
|
||||
Ui.GuiColumns.IconColumn.Value = true;
|
||||
Ui.GuiColumns.AppColumn.Value = true;
|
||||
@ -1192,6 +1201,13 @@ namespace Ryujinx.Ui.Common.Configuration
|
||||
configurationFileFormat.EnableMacroHLE = true;
|
||||
}
|
||||
|
||||
if (configurationFileFormat.Version < 43)
|
||||
{
|
||||
Ryujinx.Common.Logging.Logger.Warning?.Print(LogClass.Application, $"Outdated configuration version {configurationFileFormat.Version}, migrating to version 43.");
|
||||
|
||||
configurationFileFormat.UseHypervisor = true;
|
||||
}
|
||||
|
||||
Logger.EnableFileLog.Value = configurationFileFormat.EnableFileLog;
|
||||
Graphics.ResScale.Value = configurationFileFormat.ResScale;
|
||||
Graphics.ResScaleCustom.Value = configurationFileFormat.ResScaleCustom;
|
||||
@ -1233,6 +1249,7 @@ namespace Ryujinx.Ui.Common.Configuration
|
||||
System.MemoryManagerMode.Value = configurationFileFormat.MemoryManagerMode;
|
||||
System.ExpandRam.Value = configurationFileFormat.ExpandRam;
|
||||
System.IgnoreMissingServices.Value = configurationFileFormat.IgnoreMissingServices;
|
||||
System.UseHypervisor.Value = configurationFileFormat.UseHypervisor;
|
||||
Ui.GuiColumns.FavColumn.Value = configurationFileFormat.GuiColumns.FavColumn;
|
||||
Ui.GuiColumns.IconColumn.Value = configurationFileFormat.GuiColumns.IconColumn;
|
||||
Ui.GuiColumns.AppColumn.Value = configurationFileFormat.GuiColumns.AppColumn;
|
||||
@ -1292,4 +1309,4 @@ namespace Ryujinx.Ui.Common.Configuration
|
||||
Instance = new ConfigurationState();
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
@ -577,7 +577,8 @@ namespace Ryujinx.Ui
|
||||
ConfigurationState.Instance.System.MemoryManagerMode,
|
||||
ConfigurationState.Instance.System.IgnoreMissingServices,
|
||||
ConfigurationState.Instance.Graphics.AspectRatio,
|
||||
ConfigurationState.Instance.System.AudioVolume);
|
||||
ConfigurationState.Instance.System.AudioVolume,
|
||||
ConfigurationState.Instance.System.UseHypervisor);
|
||||
|
||||
_emulationContext = new HLE.Switch(configuration);
|
||||
}
|
||||
|
Reference in New Issue
Block a user