Fix audio renderer compressor effect (#5742)

* Delete DecibelToLinearExtended and fix Log10 function

* Fix CopyBuffer and ClearBuffer

* Change effect states from class to struct + formatting

* Formatting

* Make UpdateLowPassFilter readonly

* More compressor fixes

.editorconfig

@@ -1,8 +1,7 @@
 # Remove the line below if you want to inherit .editorconfig settings from higher directories
 root = true
 
-# C# files
-[*.cs]
+[*]
 
 #### Core EditorConfig Options ####
 
@@ -12,8 +11,18 @@ indent_style = space
 tab_width = 4
 
 # New line preferences
-end_of_line = crlf
-insert_final_newline = false
+end_of_line = lf
+insert_final_newline = true
+
+# JSON files
+[*.json]
+
+# Indentation and spacing
+indent_size = 2
+tab_width = 2
+
+# C# files
+[*.cs]
 
 #### .NET Coding Conventions ####
 
@@ -59,7 +68,7 @@ dotnet_style_prefer_simplified_interpolation = true:suggestion
 dotnet_style_readonly_field = true:suggestion
 
 # Parameter preferences
-dotnet_code_quality_unused_parameters = all:suggestion
+dotnet_code_quality_unused_parameters = all:silent
 
 #### C# Coding Conventions ####
 
@@ -85,7 +94,7 @@ csharp_style_expression_bodied_properties = true:silent
 # Pattern matching preferences
 csharp_style_pattern_matching_over_as_with_null_check = true:suggestion
 csharp_style_pattern_matching_over_is_with_cast_check = true:suggestion
-csharp_style_prefer_switch_expression = true:suggestion
+csharp_style_prefer_switch_expression = false:silent
 
 # Null-checking preferences
 csharp_style_conditional_delegate_call = true:suggestion
@@ -94,6 +103,7 @@ csharp_style_conditional_delegate_call = true:suggestion
 csharp_prefer_static_local_function = true:suggestion
 csharp_preferred_modifier_order = public,private,protected,internal,static,extern,new,virtual,abstract,sealed,override,readonly,unsafe,volatile,async:silent
 csharp_style_prefer_readonly_struct = true
+csharp_style_prefer_method_group_conversion = true
 
 # Code-block preferences
 csharp_prefer_braces = true:silent
@@ -109,6 +119,7 @@ csharp_style_prefer_range_operator = true:suggestion
 csharp_style_throw_expression = true:suggestion
 csharp_style_unused_value_assignment_preference = discard_variable:suggestion
 csharp_style_unused_value_expression_statement_preference = discard_variable:silent
+csharp_style_implicit_object_creation_when_type_is_apparent = true
 
 # 'using' directive preferences
 csharp_using_directive_placement = outside_namespace:silent
@@ -140,7 +151,6 @@ csharp_space_after_dot = false
 csharp_space_after_keywords_in_control_flow_statements = true
 csharp_space_after_semicolon_in_for_statement = true
 csharp_space_around_binary_operators = before_and_after
-csharp_space_around_declaration_statements = false
 csharp_space_before_colon_in_inheritance_clause = true
 csharp_space_before_comma = false
 csharp_space_before_dot = false
@@ -158,23 +168,31 @@ csharp_space_between_square_brackets = false
 
 # Wrapping preferences
 csharp_preserve_single_line_blocks = true
-csharp_preserve_single_line_statements = true
+csharp_preserve_single_line_statements = false
 
 #### Naming styles ####
 
 # Naming rules
 
-dotnet_naming_rule.interface_should_be_begins_with_i.severity = suggestion
-dotnet_naming_rule.interface_should_be_begins_with_i.symbols = interface
-dotnet_naming_rule.interface_should_be_begins_with_i.style = begins_with_i
+dotnet_naming_rule.interfaces_should_be_prefixed_with_I.severity = suggestion
+dotnet_naming_rule.interfaces_should_be_prefixed_with_I.symbols = interface
+dotnet_naming_rule.interfaces_should_be_prefixed_with_I.style = IPascalCase
 
 dotnet_naming_rule.types_should_be_pascal_case.severity = suggestion
 dotnet_naming_rule.types_should_be_pascal_case.symbols = types
-dotnet_naming_rule.types_should_be_pascal_case.style = pascal_case
+dotnet_naming_rule.types_should_be_pascal_case.style = PascalCase
 
 dotnet_naming_rule.non_field_members_should_be_pascal_case.severity = suggestion
 dotnet_naming_rule.non_field_members_should_be_pascal_case.symbols = non_field_members
-dotnet_naming_rule.non_field_members_should_be_pascal_case.style = pascal_case
+dotnet_naming_rule.non_field_members_should_be_pascal_case.style = PascalCase
+
+dotnet_naming_rule.private_static_readonly_fields_should_be_camel_case_and_prefixed_with__.symbols = private_static_readonly_fields
+dotnet_naming_rule.private_static_readonly_fields_should_be_camel_case_and_prefixed_with__.severity = suggestion
+dotnet_naming_rule.private_static_readonly_fields_should_be_camel_case_and_prefixed_with__.style = _camelCase
+
+dotnet_naming_rule.local_constants_should_be_pascal_case.symbols = local_constants
+dotnet_naming_rule.local_constants_should_be_pascal_case.severity = suggestion
+dotnet_naming_rule.local_constants_should_be_pascal_case.style = PascalCase
 
 # Symbol specifications
 
@@ -190,14 +208,39 @@ dotnet_naming_symbols.non_field_members.applicable_kinds = property, event, meth
 dotnet_naming_symbols.non_field_members.applicable_accessibilities = public, internal, private, protected, protected_internal, private_protected
 dotnet_naming_symbols.non_field_members.required_modifiers =
 
+dotnet_naming_symbols.private_static_readonly_fields.applicable_kinds = field
+dotnet_naming_symbols.private_static_readonly_fields.applicable_accessibilities = private
+dotnet_naming_symbols.private_static_readonly_fields.required_modifiers = static, readonly
+
+dotnet_naming_symbols.local_constants.applicable_kinds = local
+dotnet_naming_symbols.local_constants.applicable_accessibilities = local
+dotnet_naming_symbols.local_constants.required_modifiers = const
+
 # Naming styles
 
-dotnet_naming_style.pascal_case.required_prefix =
-dotnet_naming_style.pascal_case.required_suffix =
-dotnet_naming_style.pascal_case.word_separator =
-dotnet_naming_style.pascal_case.capitalization = pascal_case
+dotnet_naming_style._camelCase.required_prefix = _
+dotnet_naming_style._camelCase.required_suffix =
+dotnet_naming_style._camelCase.word_separator =
+dotnet_naming_style._camelCase.capitalization = camel_case
 
-dotnet_naming_style.begins_with_i.required_prefix = I
-dotnet_naming_style.begins_with_i.required_suffix =
-dotnet_naming_style.begins_with_i.word_separator =
-dotnet_naming_style.begins_with_i.capitalization = pascal_case
+dotnet_naming_style.PascalCase.required_prefix =
+dotnet_naming_style.PascalCase.required_suffix =
+dotnet_naming_style.PascalCase.word_separator =
+dotnet_naming_style.PascalCase.capitalization = pascal_case
+
+dotnet_naming_style.IPascalCase.required_prefix = I
+dotnet_naming_style.IPascalCase.required_suffix =
+dotnet_naming_style.IPascalCase.word_separator =
+dotnet_naming_style.IPascalCase.capitalization = pascal_case
+
+[src/Ryujinx.HLE/HOS/Services/**.cs]
+# Disable "mark members as static" rule for services
+dotnet_diagnostic.CA1822.severity = none
+
+[src/Ryujinx.Ava/UI/ViewModels/**.cs]
+# Disable "mark members as static" rule for ViewModels
+dotnet_diagnostic.CA1822.severity = none
+
+[src/Ryujinx.Tests/Cpu/*.cs]
+# Disable naming rules for CPU tests
+dotnet_diagnostic.IDE1006.severity = none

.github/ISSUE_TEMPLATE/missing_shader_instruction.yml

@@ -0,0 +1,19 @@
+name: Missing Shader Instruction
+description: Shader Instruction is missing in Ryujinx.
+title: "[GPU]"
+labels: [gpu, not-implemented]
+body:
+  - type: textarea
+    id: instruction
+    attributes:
+      label: Shader instruction
+      description: What shader instruction is missing?
+    validations:
+      required: true
+  - type: textarea
+    id: required
+    attributes:
+      label: Required by
+      description: Add links to the [compatibility list page(s)](https://github.com/Ryujinx/Ryujinx-Games-List/issues) of the game(s) that require this instruction.
+    validations:
+      required: true

.github/csc.json

@@ -0,0 +1,18 @@
+{
+    "problemMatcher": [
+        {
+            "owner": "csc",
+            "pattern": [
+                {
+                    "regexp": "^((?:\\\\|/)(?:[^\\\\/:]+(?:\\\\|/))+[^\\\\/]+)\\((\\d+),(\\d+)\\):\\s+([a-zA-Z]+)\\s+([^:]+):\\s+([^[]+)\\s+\\[",
+                    "file": 1,
+                    "line": 2,
+                    "column": 3,
+                    "severity": 4,
+                    "code": 5,
+                    "message": 6
+                }
+            ]
+        }
+    ]
+}

.github/labeler.yml

@@ -0,0 +1,33 @@
+audio: 'src/Ryujinx.Audio*/**'
+
+cpu:
+  - 'src/ARMeilleure/**'
+  - 'src/Ryujinx.Cpu/**'
+  - 'src/Ryujinx.Memory/**'
+
+gpu:
+  - 'src/Ryujinx.Graphics.*/**'
+  - 'src/Spv.Generator/**'
+  - 'src/Ryujinx.ShaderTools/**'
+
+'graphics-backend:opengl': 'src/Ryujinx.Graphics.OpenGL/**'
+'graphics-backend:vulkan':
+  - 'src/Ryujinx.Graphics.Vulkan/**'
+  - 'src/Spv.Generator/**'
+
+gui:
+  - 'src/Ryujinx/**'
+  - 'src/Ryujinx.Ui.Common/**'
+  - 'src/Ryujinx.Ui.LocaleGenerator/**'
+  - 'src/Ryujinx.Ava/**'
+
+horizon:
+  - 'src/Ryujinx.HLE/**'
+  - 'src/Ryujinx.Horizon*/**'
+
+kernel: 'src/Ryujinx.HLE/HOS/Kernel/**'
+
+infra:
+  - '.github/**'
+  - 'distribution/**'
+  - 'Directory.Packages.props'

.github/reviewers.yml

@@ -0,0 +1,32 @@
+audio:
+  - marysaka
+
+cpu:
+  - gdkchan
+  - riperiperi
+  - marysaka
+  - LDj3SNuD
+
+gpu:
+  - gdkchan
+  - riperiperi
+  - marysaka
+
+gui:
+  - Ack77
+  - emmauss
+  - TSRBerry
+  - marysaka
+
+horizon:
+  - gdkchan
+  - Ack77
+  - marysaka
+  - TSRBerry
+
+infra:
+  - marysaka
+  - TSRBerry
+
+default:
+  - '@developers'

.github/workflows/build.yml

@@ -1,22 +1,7 @@
 name: Build job
 
 on:
-  workflow_dispatch:
-    inputs: {}
-  #push:
-  #  branches: [ master ]
-  #  paths-ignore:
-  #    - '.github/*'
-  #    - '.github/ISSUE_TEMPLATE/**'
-  #    - '*.yml'
-  #    - 'README.md'
-  pull_request:
-    branches: [ master ]
-    paths-ignore:
-      - '.github/*'
-      - '.github/ISSUE_TEMPLATE/**'
-      - '*.yml'
-      - 'README.md'
+  workflow_call:
 
 env:
   POWERSHELL_TELEMETRY_OPTOUT: 1
@@ -27,7 +12,7 @@ jobs:
   build:
     name: ${{ matrix.OS_NAME }} (${{ matrix.configuration }})
     runs-on: ${{ matrix.os }}
-    timeout-minutes: 35
+    timeout-minutes: 45
     strategy:
       matrix:
         os: [ubuntu-latest, macOS-latest, windows-latest]
@@ -50,11 +35,14 @@ jobs:
 
       fail-fast: false
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
 
       - uses: actions/setup-dotnet@v3
         with:
           global-json-file: global.json
+          
+      - name: Overwrite csc problem matcher
+        run: echo "::add-matcher::.github/csc.json"
 
       - name: Get git short hash
         id: git_short_hash
@@ -65,7 +53,11 @@ jobs:
         run: dotnet build -c "${{ matrix.configuration }}" -p:Version="${{ env.RYUJINX_BASE_VERSION }}" -p:SourceRevisionId="${{ steps.git_short_hash.outputs.result }}" -p:ExtraDefineConstants=DISABLE_UPDATER
 
       - name: Test
-        run: dotnet test --no-build -c "${{ matrix.configuration }}"
+        uses: TSRBerry/unstable-commands@v1
+        with:
+          commands: dotnet test --no-build -c "${{ matrix.configuration }}"
+          timeout-minutes: 10
+          retry-codes: 139
 
       - name: Publish Ryujinx
         run: dotnet publish -c "${{ matrix.configuration }}" -r "${{ matrix.DOTNET_RUNTIME_IDENTIFIER }}" -o ./publish -p:Version="${{ env.RYUJINX_BASE_VERSION }}" -p:DebugType=embedded -p:SourceRevisionId="${{ steps.git_short_hash.outputs.result }}" -p:ExtraDefineConstants=DISABLE_UPDATER src/Ryujinx --self-contained true
@@ -110,13 +102,13 @@ jobs:
   build_macos:
     name: macOS Universal (${{ matrix.configuration }})
     runs-on: ubuntu-latest
-    timeout-minutes: 35
+    timeout-minutes: 45
     strategy:
       matrix:
         configuration: [ Debug, Release ]
 
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
 
       - uses: actions/setup-dotnet@v3
         with:
@@ -143,13 +135,24 @@ jobs:
         id: git_short_hash
         run: echo "result=$(git rev-parse --short "${{ github.sha }}")" >> $GITHUB_OUTPUT
 
-      - name: Publish macOS
+      - name: Publish macOS Ryujinx.Ava
         run: |
-          ./distribution/macos/create_macos_build.sh . publish_tmp publish_ava ./distribution/macos/entitlements.xml "${{ env.RYUJINX_BASE_VERSION }}" "${{ steps.git_short_hash.outputs.result }}" "${{ matrix.configuration }}" "-p:ExtraDefineConstants=DISABLE_UPDATER"
+          ./distribution/macos/create_macos_build_ava.sh . publish_tmp_ava publish_ava ./distribution/macos/entitlements.xml "${{ env.RYUJINX_BASE_VERSION }}" "${{ steps.git_short_hash.outputs.result }}" "${{ matrix.configuration }}" "-p:ExtraDefineConstants=DISABLE_UPDATER"
+
+      - name: Publish macOS Ryujinx.Headless.SDL2
+        run: |
+          ./distribution/macos/create_macos_build_headless.sh . publish_tmp_headless publish_headless ./distribution/macos/entitlements.xml "${{ env.RYUJINX_BASE_VERSION }}" "${{ steps.git_short_hash.outputs.result }}" "${{ matrix.configuration }}" "-p:ExtraDefineConstants=DISABLE_UPDATER"
 
       - name: Upload Ryujinx.Ava artifact
         uses: actions/upload-artifact@v3
         with:
           name: ava-ryujinx-${{ matrix.configuration }}-${{ env.RYUJINX_BASE_VERSION }}+${{ steps.git_short_hash.outputs.result }}-macos_universal
           path: "publish_ava/*.tar.gz"
+        if: github.event_name == 'pull_request'
+
+      - name: Upload Ryujinx.Headless.SDL2 artifact
+        uses: actions/upload-artifact@v3
+        with:
+          name: sdl2-ryujinx-headless-${{ matrix.configuration }}-${{ env.RYUJINX_BASE_VERSION }}+${{ steps.git_short_hash.outputs.result }}-macos_universal
+          path: "publish_headless/*.tar.gz"
         if: github.event_name == 'pull_request'

.github/workflows/checks.yml

@@ -0,0 +1,74 @@
+name: Perform checks
+
+on:
+  pull_request:
+    branches: [ master ]
+    paths:
+      - '**'
+      - '!.github/**'
+      - '!*.yml'
+      - '!*.config'
+      - '!README.md'
+      - '.github/workflows/*.yml'
+
+permissions:
+  pull-requests: write
+  checks: write
+
+concurrency:
+  group: pr-checks-${{ github.event.number }}
+  cancel-in-progress: true
+
+jobs:
+  format:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v4
+        with:
+          fetch-depth: 0
+
+      - uses: actions/setup-dotnet@v3
+        with:
+          global-json-file: global.json
+
+      - name: Overwrite csc problem matcher
+        run: echo "::add-matcher::.github/csc.json"
+
+      - run: dotnet restore
+
+      - name: Print dotnet format version
+        run: dotnet format --version
+
+      - name: Run dotnet format whitespace
+        run: |
+          dotnet format whitespace --verify-no-changes --report ./whitespace-report.json -v d
+
+      # For some unknown reason this step sometimes fails with exit code 139 (segfault?),
+      # so in that case we'll try again (3 tries max).
+      - name: Run dotnet format style
+        uses: TSRBerry/unstable-commands@v1
+        with:
+          commands: dotnet format style --severity info --verify-no-changes --report ./style-report.json -v d
+          timeout-minutes: 5
+          retry-codes: 139
+
+      # For some unknown reason this step sometimes fails with exit code 139 (segfault?),
+      # so in that case we'll try again (3 tries max).
+      - name: Run dotnet format analyzers
+        uses: TSRBerry/unstable-commands@v1
+        with:
+          commands: dotnet format analyzers --severity info --verify-no-changes --report ./analyzers-report.json -v d
+          timeout-minutes: 5
+          retry-codes: 139
+
+      - name: Upload report
+        if: failure()
+        uses: actions/upload-artifact@v3
+        with:
+          name: dotnet-format
+          path: ./*-report.json
+
+  pr_build:
+    uses: ./.github/workflows/build.yml
+    needs: format
+    secrets: inherit

.github/workflows/flatpak.yml

@@ -12,7 +12,7 @@ concurrency: flatpak-release
 
 jobs:
   release:
-    timeout-minutes: 35
+    timeout-minutes: ${{ fromJSON(vars.JOB_TIMEOUT) }}
     runs-on: ubuntu-latest
 
     env:
@@ -24,7 +24,7 @@ jobs:
       RYUJINX_VERSION: "${{ inputs.ryujinx_version }}"
 
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
         with:
           path: Ryujinx
 
@@ -38,7 +38,7 @@ jobs:
         run: |
           echo "git_hash=$(git rev-parse HEAD)" >> $GITHUB_OUTPUT
 
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
         with:
           repository: flathub/org.ryujinx.Ryujinx
           token: ${{ secrets.RYUJINX_BOT_PAT }}

.github/workflows/nightly_pr_comment.yml

@@ -1,13 +1,15 @@
 name: Comment PR artifacts links
+
 on:
   workflow_run:
-    workflows: ['Build job']
+    workflows: ['Perform checks']
     types: [completed]
+
 jobs:
   pr_comment:
     if: github.event.workflow_run.event == 'pull_request' && github.event.workflow_run.conclusion == 'success'
     runs-on: ubuntu-latest
-    timeout-minutes: 35
+    timeout-minutes: ${{ fromJSON(vars.JOB_TIMEOUT) }}
     steps:
       - uses: actions/github-script@v6
         with:

.github/workflows/pr_triage.yml

@@ -0,0 +1,47 @@
+name: "Pull Request Triage"
+on:
+  pull_request_target:
+    types: [opened, ready_for_review]
+
+jobs:
+  triage:
+    permissions:
+      contents: read
+      pull-requests: write
+
+    runs-on: ubuntu-latest
+
+    steps:
+      # Grab sources to get latest labeler.yml
+      - name: Fetch sources
+        uses: actions/checkout@v4
+        with:
+           # Ensure we pin the source origin as pull_request_target run under forks.
+           fetch-depth: 0
+           repository: Ryujinx/Ryujinx
+           ref: master
+
+      - name: Checkout Ryujinx-Mako
+        uses: actions/checkout@v4
+        with:
+            repository: Ryujinx/Ryujinx-Mako
+            ref: master
+            path: '.ryujinx-mako'
+
+      - name: Setup Ryujinx-Mako
+        uses: ./.ryujinx-mako/.github/actions/setup-mako
+
+      - name: Update labels based on changes
+        uses: actions/labeler@v4
+        with:
+          sync-labels: true
+          dot: true
+
+      - name: Assign reviewers
+        run: |
+            poetry -n -C .ryujinx-mako run ryujinx-mako update-reviewers ${{ github.repository }} ${{ github.event.pull_request.number }} .github/reviewers.yml
+        shell: bash
+        env:
+            MAKO_APP_ID: ${{ secrets.MAKO_APP_ID }}
+            MAKO_PRIVATE_KEY: ${{ secrets.MAKO_PRIVATE_KEY }}
+            MAKO_INSTALLATION_ID: ${{ secrets.MAKO_INSTALLATION_ID }}

.github/workflows/release.yml

@@ -6,9 +6,10 @@ on:
   push:
     branches: [ master ]
     paths-ignore:
-      - '.github/*'
-      - '.github/ISSUE_TEMPLATE/**'
+      - '.github/**'
       - '*.yml'
+      - '*.json'
+      - '*.config'
       - 'README.md'
 
 concurrency: release
@@ -33,7 +34,7 @@ jobs:
         shell: bash
 
       - name: Create tag
-        uses: actions/github-script@v5
+        uses: actions/github-script@v6
         with:
           script: |
             github.rest.git.createRef({
@@ -46,7 +47,7 @@ jobs:
   release:
     name: Release ${{ matrix.OS_NAME }}
     runs-on: ${{ matrix.os }}
-    timeout-minutes: 35
+    timeout-minutes: ${{ fromJSON(vars.JOB_TIMEOUT) }}
     strategy:
       matrix:
         os: [ ubuntu-latest, windows-latest ]
@@ -61,11 +62,14 @@ jobs:
             DOTNET_RUNTIME_IDENTIFIER: win10-x64
             RELEASE_ZIP_OS_NAME: win_x64
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
 
       - uses: actions/setup-dotnet@v3
         with:
           global-json-file: global.json
+          
+      - name: Overwrite csc problem matcher
+        run: echo "::add-matcher::.github/csc.json"
 
       - name: Get version info
         id: version_info
@@ -144,9 +148,9 @@ jobs:
   macos_release:
     name: Release MacOS universal
     runs-on: ubuntu-latest
-    timeout-minutes: 35
+    timeout-minutes: ${{ fromJSON(vars.JOB_TIMEOUT) }}
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
 
       - uses: actions/setup-dotnet@v3
         with:
@@ -184,15 +188,19 @@ jobs:
           sed -r --in-place 's/\%\%RYUJINX_TARGET_RELEASE_CHANNEL_REPO\%\%/${{ env.RYUJINX_TARGET_RELEASE_CHANNEL_REPO }}/g;' src/Ryujinx.Common/ReleaseInformation.cs
         shell: bash
 
-      - name: Publish macOS
+      - name: Publish macOS Ryujinx.Ava
         run: |
-          ./distribution/macos/create_macos_build.sh . publish_tmp publish_ava ./distribution/macos/entitlements.xml "${{ steps.version_info.outputs.build_version }}" "${{ steps.version_info.outputs.git_short_hash }}" Release
+          ./distribution/macos/create_macos_build_ava.sh . publish_tmp_ava publish_ava ./distribution/macos/entitlements.xml "${{ steps.version_info.outputs.build_version }}" "${{ steps.version_info.outputs.git_short_hash }}" Release
+          
+      - name: Publish macOS Ryujinx.Headless.SDL2
+        run: |
+          ./distribution/macos/create_macos_build_headless.sh . publish_tmp_headless publish_headless ./distribution/macos/entitlements.xml "${{ steps.version_info.outputs.build_version }}" "${{ steps.version_info.outputs.git_short_hash }}" Release
 
       - name: Pushing new release
         uses: ncipollo/release-action@v1
         with:
           name: ${{ steps.version_info.outputs.build_version }}
-          artifacts: "publish_ava/*.tar.gz"
+          artifacts: "publish_ava/*.tar.gz, publish_headless/*.tar.gz"
           tag: ${{ steps.version_info.outputs.build_version }}
           body: "For more information about this release please check out the official [Changelog](https://github.com/Ryujinx/Ryujinx/wiki/Changelog)."
           omitBodyDuringUpdate: true

CONTRIBUTING.md

@@ -0,0 +1,147 @@
+# Contribution to Ryujinx
+
+You can contribute to Ryujinx with PRs, testing of PRs and issues. Contributing code and other implementations is greatly appreciated alongside simply filing issues for problems you encounter.
+Please read the entire document before continuing as it can potentially save everyone involved a significant amount of time.
+
+# Quick Links
+
+* [Code Style Documentation](docs/coding-guidelines/coding-style.md)
+* [Pull Request Guidelines](docs/workflow/pr-guide.md)
+
+## Reporting Issues
+
+We always welcome bug reports, feature proposals and overall feedback. Here are a few tips on how you can make reporting your issue as effective as possible.
+
+### Identify Where to Report
+
+The Ryujinx codebase is distributed across multiple repositories in the [Ryujinx organization](https://github.com/Ryujinx). Depending on the feedback you might want to file the issue on a different repo. Here are a few common repos:
+
+* [Ryujinx/Ryujinx](https://github.com/Ryujinx/Ryujinx) Ryujinx core project files.
+* [Ryujinx/Ryujinx-Games-List](https://github.com/Ryujinx/Ryujinx-Games-List) Ryujinx game compatibility list.
+* [Ryujinx/Ryujinx-Website](https://github.com/Ryujinx/Ryujinx-Website) Ryujinx website source code.
+* [Ryujinx/Ryujinx-Ldn-Website](https://github.com/Ryujinx/Ryujinx-Ldn-Website) Ryujinx LDN website source code.
+
+### Finding Existing Issues
+
+Before filing a new issue, please search our [open issues](https://github.com/Ryujinx/Ryujinx/issues) to check if it already exists.
+
+If you do find an existing issue, please include your own feedback in the discussion. Do consider upvoting (👍 reaction) the original post, as this helps us prioritize popular issues in our backlog.
+
+### Writing a Good Feature Request
+
+Please review any feature requests already opened to both check it has not already been suggested, and to familiarize yourself with the format. When ready to submit a proposal, please use the [Feature Request issue template](https://github.com/Ryujinx/Ryujinx/issues/new?assignees=&labels=&projects=&template=feature_request.yml&title=%5BFeature+Request%5D).
+
+### Writing a Good Bug Report
+
+Good bug reports make it easier for maintainers to verify and root cause the underlying problem. The better a bug report, the faster the problem will be resolved. 
+Ideally, a bug report should contain the following information:
+
+* A high-level description of the problem.
+* A _minimal reproduction_, i.e. the smallest time commitment/configuration required to reproduce the wrong behavior. This can be in the form of a small homebrew application, or by providing a save file and reproduction steps for a specific game.
+* A description of the _expected behavior_, contrasted with the _actual behavior_ observed.
+* Information on the environment: OS/distro, CPU, GPU (including driver), RAM etc.
+* A Ryujinx log file of the run instance where the issue occurred. Log files can be found in `[Executable Folder]/Logs` and are named chronologically.
+* Additional information, e.g. is it a regression from previous versions? Are there any known workarounds?
+
+When ready to submit a bug report, please use the [Bug Report issue template](https://github.com/Ryujinx/Ryujinx/issues/new?assignees=&labels=bug&projects=&template=bug_report.yml&title=%5BBug%5D).
+
+## Contributing Changes
+
+Project maintainers will merge changes that both improve the project and meet our standards for code quality.
+
+The [Pull Request Guide](docs/workflow/pr-guide.md) and [License](https://github.com/Ryujinx/Ryujinx/blob/master/LICENSE.txt) docs define additional guidance.
+
+### DOs and DON'Ts
+
+Please do:
+
+* **DO** follow our [coding style](docs/coding-guidelines/coding-style.md) (C# code-specific).
+* **DO** give priority to the current style of the project or file you're changing even if it diverges from the general guidelines.
+* **DO** keep the discussions focused. When a new or related topic comes up
+  it's often better to create new issue than to side track the discussion.
+* **DO** clearly state on an issue that you are going to take on implementing it.
+* **DO** blog and tweet (or whatever) about your contributions, frequently!
+
+Please do not:
+
+* **DON'T** make PRs for style changes.
+* **DON'T** surprise us with big pull requests. Instead, file an issue and talk with us on Discord to start
+  a discussion so we can agree on a direction before you invest a large amount
+  of time.
+* **DON'T** commit code that you didn't write. If you find code that you think is a good fit to add to Ryujinx, file an issue or talk to us on Discord to start a discussion before proceeding.
+* **DON'T** submit PRs that alter licensing related files or headers. If you believe there's a problem with them, file an issue and we'll be happy to discuss it.
+
+### Suggested Workflow
+
+We use and recommend the following workflow:
+
+1. Create or find an issue for your work.
+    - You can skip this step for trivial changes.
+    - Get agreement from the team and the community that your proposed change is a good one if it is of significant size or changes core functionality.
+    - Clearly state that you are going to take on implementing it, if that's the case. You can request that the issue be assigned to you. Note: The issue filer and the implementer don't have to be the same person.
+2. Create a personal fork of the repository on GitHub (if you don't already have one).
+3. In your fork, create a branch off of main (`git checkout -b mybranch`).
+    - Branches are useful since they isolate your changes from incoming changes from upstream. They also enable you to create multiple PRs from the same fork.
+4. Make and commit your changes to your branch.
+    - [Build Instructions](https://github.com/Ryujinx/Ryujinx#building) explains how to build and test.
+    - Commit messages should be clear statements of action and intent.
+6. Build the repository with your changes.
+    - Make sure that the builds are clean.
+    - Make sure that `dotnet format` has been run and any corrections tested and committed.
+7. Create a pull request (PR) against the Ryujinx/Ryujinx repository's **main** branch.
+    - State in the description what issue or improvement your change is addressing.
+    - Check if all the Continuous Integration checks are passing. Refer to [Actions](https://github.com/Ryujinx/Ryujinx/actions) to check for outstanding errors.
+8. Wait for feedback or approval of your changes from the [core development team](https://github.com/orgs/Ryujinx/teams/developers)
+    - Details about the pull request [review procedure](docs/workflow/ci/pr-guide.md).
+9. When the team members have signed off, and all checks are green, your PR will be merged.
+    - The next official build will automatically include your change.
+    - You can delete the branch you used for making the change.
+
+### Good First Issues
+
+The team marks the most straightforward issues as [good first issues](https://github.com/Ryujinx/Ryujinx/issues?q=is%3Aopen+is%3Aissue+label%3A%22good+first+issue%22). This set of issues is the place to start if you are interested in contributing but new to the codebase.
+
+### Commit Messages
+
+Please format commit messages as follows (based on [A Note About Git Commit Messages](http://tbaggery.com/2008/04/19/a-note-about-git-commit-messages.html)):
+
+```
+Summarize change in 50 characters or less
+
+Provide more detail after the first line. Leave one blank line below the
+summary and wrap all lines at 72 characters or less.
+
+If the change fixes an issue, leave another blank line after the final
+paragraph and indicate which issue is fixed in the specific format
+below.
+
+Fix #42
+```
+
+Also do your best to factor commits appropriately, not too large with unrelated things in the same commit, and not too small with the same small change applied N times in N different commits.
+
+### PR - CI Process
+
+The [Ryujinx continuous integration](https://github.com/Ryujinx/Ryujinx/actions) (CI) system will automatically perform the required builds and run tests (including the ones you are expected to run) for PRs. Builds and test runs must be clean or have bugs properly filed against flaky/unexpected failures that are unrelated to your change.
+
+If the CI build fails for any reason, the PR actions tab should be consulted for further information on the failure. There are a few usual suspects for such a failure:
+* `dotnet format` has not been run on the PR and has outstanding stylistic issues.
+* There is an error within the PR that fails a test or errors the compiler.
+* Random failure of the workflow can occasionally result in a CI failure. In this scenario a maintainer will manually restart the job.
+
+### PR Feedback
+
+Ryujinx team and community members will provide feedback on your change. Community feedback is highly valued. You may see the absence of team feedback if the community has already provided good review feedback.
+
+Two Ryujinx team members must review and approve every PR prior to merge. They will often reply with "LGTM, see nit". That means that the PR will be merged once the feedback is resolved. "LGTM" == "looks good to me".
+
+There are lots of thoughts and [approaches](https://github.com/antlr/antlr4-cpp/blob/master/CONTRIBUTING.md#emoji) for how to efficiently discuss changes. It is best to be clear and explicit with your feedback. Please be patient with people who might not understand the finer details about your approach to feedback.
+
+#### Copying Changes from Other Projects
+
+Ryujinx uses some implementations and frameworks from other projects. The following rules must be followed for PRs that include changes from another project:
+
+- The license of the file is [permissive](https://en.wikipedia.org/wiki/Permissive_free_software_licence).
+- The license of the file is left in-tact.
+- The contribution is correctly attributed in the [3rd party notices](https://github.com/Ryujinx/Ryujinx/blob/master/distribution/legal/THIRDPARTY.md) file in the repository, as needed.
+

Directory.Packages.props

@@ -3,25 +3,25 @@
     <ManagePackageVersionsCentrally>true</ManagePackageVersionsCentrally>
   </PropertyGroup>
   <ItemGroup>
-    <PackageVersion Include="Avalonia" Version="0.10.19" />
-    <PackageVersion Include="Avalonia.Controls.DataGrid" Version="0.10.19" />
-    <PackageVersion Include="Avalonia.Desktop" Version="0.10.19" />
-    <PackageVersion Include="Avalonia.Diagnostics" Version="0.10.19" />
-    <PackageVersion Include="Avalonia.Markup.Xaml.Loader" Version="0.10.19" />
-    <PackageVersion Include="Avalonia.Svg" Version="0.10.18" />
-    <PackageVersion Include="Avalonia.Svg.Skia" Version="0.10.18" />
+    <PackageVersion Include="Avalonia" Version="11.0.4" />
+    <PackageVersion Include="Avalonia.Controls.DataGrid" Version="11.0.4" />
+    <PackageVersion Include="Avalonia.Desktop" Version="11.0.4" />
+    <PackageVersion Include="Avalonia.Diagnostics" Version="11.0.4" />
+    <PackageVersion Include="Avalonia.Markup.Xaml.Loader" Version="11.0.4" />
+    <PackageVersion Include="Avalonia.Svg" Version="11.0.0.2" />
+    <PackageVersion Include="Avalonia.Svg.Skia" Version="11.0.0.2" />
     <PackageVersion Include="CommandLineParser" Version="2.9.1" />
     <PackageVersion Include="Concentus" Version="1.1.7" />
-    <PackageVersion Include="DiscordRichPresence" Version="1.1.3.18" />
-    <PackageVersion Include="DynamicData" Version="7.13.8" />
-    <PackageVersion Include="FluentAvaloniaUI" Version="1.4.5" />
+    <PackageVersion Include="DiscordRichPresence" Version="1.2.1.24" />
+    <PackageVersion Include="DynamicData" Version="7.14.2" />
+    <PackageVersion Include="FluentAvaloniaUI" Version="2.0.4" />
     <PackageVersion Include="GtkSharp.Dependencies" Version="1.1.1" />
     <PackageVersion Include="GtkSharp.Dependencies.osx" Version="0.0.5" />
-    <PackageVersion Include="jp2masa.Avalonia.Flexbox" Version="0.2.0" />
+    <PackageVersion Include="jp2masa.Avalonia.Flexbox" Version="0.3.0-beta.4" />
     <PackageVersion Include="LibHac" Version="0.18.0" />
     <PackageVersion Include="Microsoft.CodeAnalysis.Analyzers" Version="3.3.4" />
-    <PackageVersion Include="Microsoft.CodeAnalysis.CSharp" Version="4.5.0" />
-    <PackageVersion Include="Microsoft.NET.Test.Sdk" Version="17.5.0" />
+    <PackageVersion Include="Microsoft.CodeAnalysis.CSharp" Version="4.6.0" />
+    <PackageVersion Include="Microsoft.NET.Test.Sdk" Version="17.7.2" />
     <PackageVersion Include="Microsoft.IO.RecyclableMemoryStream" Version="2.3.2" />
     <PackageVersion Include="MsgPack.Cli" Version="1.0.1" />
     <PackageVersion Include="NUnit" Version="3.13.3" />
@@ -34,7 +34,7 @@
     <PackageVersion Include="Ryujinx.Graphics.Nvdec.Dependencies" Version="5.0.1-build13" />
     <PackageVersion Include="Ryujinx.Graphics.Vulkan.Dependencies.MoltenVK" Version="1.2.0" />
     <PackageVersion Include="Ryujinx.GtkSharp" Version="3.24.24.59-ryujinx" />
-    <PackageVersion Include="Ryujinx.SDL2-CS" Version="2.26.3-build25" />
+    <PackageVersion Include="Ryujinx.SDL2-CS" Version="2.28.1-build28" />
     <PackageVersion Include="shaderc.net" Version="0.1.0" />
     <PackageVersion Include="SharpZipLib" Version="1.4.2" />
     <PackageVersion Include="Silk.NET.Vulkan" Version="2.16.0" />
@@ -44,10 +44,9 @@
     <PackageVersion Include="SixLabors.ImageSharp.Drawing" Version="1.0.0-beta11" />
     <PackageVersion Include="SPB" Version="0.0.4-build28" />
     <PackageVersion Include="System.Drawing.Common" Version="7.0.0" />
-    <PackageVersion Include="System.IdentityModel.Tokens.Jwt" Version="6.30.1" />
+    <PackageVersion Include="System.IdentityModel.Tokens.Jwt" Version="7.0.0" />
     <PackageVersion Include="System.IO.Hashing" Version="7.0.0" />
-    <PackageVersion Include="System.Management" Version="7.0.1" />
+    <PackageVersion Include="System.Management" Version="7.0.2" />
     <PackageVersion Include="UnicornEngine.Unicorn" Version="2.0.2-rc1-fb78016" />
-    <PackageVersion Include="XamlNameReferenceGenerator" Version="1.6.1" />
   </ItemGroup>
-</Project>
+</Project>

distribution/linux/Ryujinx.sh

@@ -11,4 +11,10 @@ if [ -f "$SCRIPT_DIR/Ryujinx.Headless.SDL2" ]; then
     RYUJINX_BIN="Ryujinx.Headless.SDL2"
 fi
 
-env DOTNET_EnableAlternateStackCheck=1 "$SCRIPT_DIR/$RYUJINX_BIN" "$@"
+COMMAND="env DOTNET_EnableAlternateStackCheck=1"
+
+if command -v gamemoderun > /dev/null 2>&1; then
+    COMMAND="$COMMAND gamemoderun"
+fi
+
+$COMMAND "$SCRIPT_DIR/$RYUJINX_BIN" "$@"

distribution/macos/Info.plist

@@ -39,10 +39,120 @@
     <key>CSResourcesFileMapped</key>
     <true/>
     <key>NSHumanReadableCopyright</key>
-    <string>Copyright © 2018 - 2022 Ryujinx Team and Contributors.</string>
+    <string>Copyright © 2018 - 2023 Ryujinx Team and Contributors.</string>
     <key>LSApplicationCategoryType</key>
     <string>public.app-category.games</string>
     <key>LSMinimumSystemVersion</key>
     <string>11.0</string>
+    <key>UTExportedTypeDeclarations</key>
+    <array>
+      <dict>
+        <key>UTTypeDescription</key>
+        <string>Extensible Application Markup Language</string>
+        <key>UTTypeConformsTo</key>
+        <array>
+          <string>public.xml</string>
+        </array>
+        <key>UTTypeIdentifier</key>
+        <string>com.ryujinx.xaml</string>
+        <key>UTTypeTagSpecification</key>
+        <dict>
+          <key>public.filename-extension</key>
+          <array>
+            <string>xaml</string>
+          </array>
+        </dict>
+      </dict>
+      <dict>
+        <key>UTTypeDescription</key>
+        <string>Nintendo Submission Package</string>
+        <key>UTTypeConformsTo</key>
+        <array>
+          <string>public.data</string>
+        </array>
+        <key>UTTypeIdentifier</key>
+        <string>com.ryujinx.nsp</string>
+        <key>UTTypeTagSpecification</key>
+        <dict>
+          <key>public.filename-extension</key>
+          <array>
+            <string>nsp</string>
+          </array>
+        </dict>
+      </dict>
+      <dict>
+        <key>UTTypeDescription</key>
+        <string>Nintendo Switch Cartridge</string>
+        <key>UTTypeConformsTo</key>
+        <array>
+          <string>public.data</string>
+        </array>
+        <key>UTTypeIdentifier</key>
+        <string>com.ryujinx.xci</string>
+        <key>UTTypeTagSpecification</key>
+        <dict>
+          <key>public.filename-extension</key>
+          <array>
+            <string>xci</string>
+          </array>
+        </dict>
+      </dict>
+      <dict>
+        <key>UTTypeDescription</key>
+        <string>Nintendo Content Archive</string>
+        <key>UTTypeConformsTo</key>
+        <array>
+          <string>public.data</string>
+        </array>
+        <key>UTTypeIdentifier</key>
+        <string>com.ryujinx.nca</string>
+        <key>UTTypeTagSpecification</key>
+        <dict>
+          <key>public.filename-extension</key>
+          <array>
+            <string>nca</string>
+          </array>
+        </dict>
+      </dict>
+      <dict>
+        <key>UTTypeDescription</key>
+        <string>Nintendo Relocatable Object</string>
+        <key>UTTypeConformsTo</key>
+        <array>
+          <string>public.data</string>
+        </array>
+        <key>UTTypeIdentifier</key>
+        <string>com.ryujinx.nro</string>
+        <key>UTTypeTagSpecification</key>
+        <dict>
+          <key>public.filename-extension</key>
+          <array>
+            <string>nro</string>
+          </array>
+        </dict>
+      </dict>
+      <dict>
+        <key>UTTypeDescription</key>
+        <string>Nintendo Shared Object</string>
+        <key>UTTypeConformsTo</key>
+        <array>
+          <string>public.data</string>
+        </array>
+        <key>UTTypeIdentifier</key>
+        <string>com.ryujinx.nso</string>
+        <key>UTTypeTagSpecification</key>
+        <dict>
+          <key>public.filename-extension</key>
+          <array>
+            <string>nso</string>
+          </array>
+        </dict>
+      </dict>
+    </array>
+    <key>LSEnvironment</key>
+    <dict>
+        <key>DOTNET_DefaultStackSize</key>
+        <string>200000</string>
+    </dict>
 </dict>
-</plist>
+</plist>

distribution/macos/create_macos_build_ava.sh

@@ -35,12 +35,12 @@ EXECUTABLE_SUB_PATH=Contents/MacOS/Ryujinx
 rm -rf "$TEMP_DIRECTORY"
 mkdir -p "$TEMP_DIRECTORY"
 
-DOTNET_COMMON_ARGS="-p:DebugType=embedded -p:Version=$VERSION -p:SourceRevisionId=$SOURCE_REVISION_ID --self-contained true $EXTRA_ARGS"
+DOTNET_COMMON_ARGS=(-p:DebugType=embedded -p:Version="$VERSION" -p:SourceRevisionId="$SOURCE_REVISION_ID" --self-contained true $EXTRA_ARGS)
 
 dotnet restore
-dotnet build -c $CONFIGURATION src/Ryujinx.Ava
-dotnet publish -c $CONFIGURATION -r osx-arm64 -o "$TEMP_DIRECTORY/publish_arm64" $DOTNET_COMMON_ARGS src/Ryujinx.Ava
-dotnet publish -c $CONFIGURATION -r osx-x64 -o "$TEMP_DIRECTORY/publish_x64" $DOTNET_COMMON_ARGS src/Ryujinx.Ava
+dotnet build -c "$CONFIGURATION" src/Ryujinx.Ava
+dotnet publish -c "$CONFIGURATION" -r osx-arm64 -o "$TEMP_DIRECTORY/publish_arm64" "${DOTNET_COMMON_ARGS[@]}" src/Ryujinx.Ava
+dotnet publish -c "$CONFIGURATION" -r osx-x64 -o "$TEMP_DIRECTORY/publish_x64" "${DOTNET_COMMON_ARGS[@]}" src/Ryujinx.Ava
 
 # Get rid of the support library for ARMeilleure for x64 (that's only for arm64)
 rm -rf "$TEMP_DIRECTORY/publish_x64/libarmeilleure-jitsupport.dylib"
@@ -104,10 +104,10 @@ fi
 
 echo "Creating archive"
 pushd "$OUTPUT_DIRECTORY"
-tar --exclude "Ryujinx.app/Contents/MacOS/Ryujinx" -cvf $RELEASE_TAR_FILE_NAME Ryujinx.app 1> /dev/null
-python3 "$BASE_DIR/distribution/misc/add_tar_exec.py" $RELEASE_TAR_FILE_NAME "Ryujinx.app/Contents/MacOS/Ryujinx" "Ryujinx.app/Contents/MacOS/Ryujinx"
-gzip -9 < $RELEASE_TAR_FILE_NAME > $RELEASE_TAR_FILE_NAME.gz
-rm $RELEASE_TAR_FILE_NAME
+tar --exclude "Ryujinx.app/Contents/MacOS/Ryujinx" -cvf "$RELEASE_TAR_FILE_NAME" Ryujinx.app 1> /dev/null
+python3 "$BASE_DIR/distribution/misc/add_tar_exec.py" "$RELEASE_TAR_FILE_NAME" "Ryujinx.app/Contents/MacOS/Ryujinx" "Ryujinx.app/Contents/MacOS/Ryujinx"
+gzip -9 < "$RELEASE_TAR_FILE_NAME" > "$RELEASE_TAR_FILE_NAME.gz"
+rm "$RELEASE_TAR_FILE_NAME"
 popd
 
 echo "Done"

distribution/macos/create_macos_build_headless.sh

@@ -0,0 +1,111 @@
+#!/bin/bash
+
+set -e
+
+if [ "$#" -lt 7 ]; then
+    echo "usage <BASE_DIR> <TEMP_DIRECTORY> <OUTPUT_DIRECTORY> <ENTITLEMENTS_FILE_PATH> <VERSION> <SOURCE_REVISION_ID> <CONFIGURATION> <EXTRA_ARGS>"
+    exit 1
+fi
+
+mkdir -p "$1"
+mkdir -p "$2"
+mkdir -p "$3"
+
+BASE_DIR=$(readlink -f "$1")
+TEMP_DIRECTORY=$(readlink -f "$2")
+OUTPUT_DIRECTORY=$(readlink -f "$3")
+ENTITLEMENTS_FILE_PATH=$(readlink -f "$4")
+VERSION=$5
+SOURCE_REVISION_ID=$6
+CONFIGURATION=$7
+EXTRA_ARGS=$8
+
+if [ "$VERSION" == "1.1.0" ];
+then
+  RELEASE_TAR_FILE_NAME=sdl2-ryujinx-headless-$CONFIGURATION-$VERSION+$SOURCE_REVISION_ID-macos_universal.tar
+else
+  RELEASE_TAR_FILE_NAME=sdl2-ryujinx-headless-$VERSION-macos_universal.tar
+fi
+
+ARM64_OUTPUT="$TEMP_DIRECTORY/publish_arm64"
+X64_OUTPUT="$TEMP_DIRECTORY/publish_x64"
+UNIVERSAL_OUTPUT="$OUTPUT_DIRECTORY/publish"
+EXECUTABLE_SUB_PATH=Ryujinx.Headless.SDL2
+
+rm -rf "$TEMP_DIRECTORY"
+mkdir -p "$TEMP_DIRECTORY"
+
+DOTNET_COMMON_ARGS=(-p:DebugType=embedded -p:Version="$VERSION" -p:SourceRevisionId="$SOURCE_REVISION_ID" --self-contained true $EXTRA_ARGS)
+
+dotnet restore
+dotnet build -c "$CONFIGURATION" src/Ryujinx.Headless.SDL2
+dotnet publish -c "$CONFIGURATION" -r osx-arm64 -o "$TEMP_DIRECTORY/publish_arm64" "${DOTNET_COMMON_ARGS[@]}" src/Ryujinx.Headless.SDL2
+dotnet publish -c "$CONFIGURATION" -r osx-x64 -o "$TEMP_DIRECTORY/publish_x64" "${DOTNET_COMMON_ARGS[@]}" src/Ryujinx.Headless.SDL2
+
+# Get rid of the support library for ARMeilleure for x64 (that's only for arm64)
+rm -rf "$TEMP_DIRECTORY/publish_x64/libarmeilleure-jitsupport.dylib"
+
+# Get rid of libsoundio from arm64 builds as we don't have a arm64 variant
+# TODO: remove this once done
+rm -rf "$TEMP_DIRECTORY/publish_arm64/libsoundio.dylib"
+
+rm -rf "$OUTPUT_DIRECTORY"
+mkdir -p "$OUTPUT_DIRECTORY"
+
+# Let's copy one of the two different outputs and remove the executable
+cp -R "$ARM64_OUTPUT/" "$UNIVERSAL_OUTPUT"
+rm "$UNIVERSAL_OUTPUT/$EXECUTABLE_SUB_PATH"
+
+# Make it libraries universal
+python3 "$BASE_DIR/distribution/macos/construct_universal_dylib.py" "$ARM64_OUTPUT" "$X64_OUTPUT" "$UNIVERSAL_OUTPUT" "**/*.dylib"
+
+if ! [ -x "$(command -v lipo)" ];
+then
+    if ! [ -x "$(command -v llvm-lipo-14)" ];
+    then
+        LIPO=llvm-lipo
+    else
+        LIPO=llvm-lipo-14
+    fi
+else
+    LIPO=lipo
+fi
+
+# Make the executable universal
+$LIPO "$ARM64_OUTPUT/$EXECUTABLE_SUB_PATH" "$X64_OUTPUT/$EXECUTABLE_SUB_PATH" -output "$UNIVERSAL_OUTPUT/$EXECUTABLE_SUB_PATH" -create
+
+# Now sign it
+if ! [ -x "$(command -v codesign)" ];
+then
+    if ! [ -x "$(command -v rcodesign)" ];
+    then
+        echo "Cannot find rcodesign on your system, please install rcodesign."
+        exit 1
+    fi
+
+    # NOTE: Currently require https://github.com/indygreg/apple-platform-rs/pull/44 to work on other OSes.
+    # cargo install --git "https://github.com/marysaka/apple-platform-rs" --branch "fix/adhoc-app-bundle" apple-codesign --bin "rcodesign"
+    echo "Using rcodesign for ad-hoc signing"
+    for FILE in "$UNIVERSAL_OUTPUT"/*; do
+        if [[ $(file "$FILE") == *"Mach-O"* ]]; then
+            rcodesign sign --entitlements-xml-path "$ENTITLEMENTS_FILE_PATH" "$FILE"
+        fi
+    done  
+else
+    echo "Using codesign for ad-hoc signing"
+    for FILE in "$UNIVERSAL_OUTPUT"/*; do
+        if [[ $(file "$FILE") == *"Mach-O"* ]]; then
+            codesign --entitlements "$ENTITLEMENTS_FILE_PATH" -f --deep -s - "$FILE"
+        fi
+    done    
+fi
+
+echo "Creating archive"
+pushd "$OUTPUT_DIRECTORY"
+tar --exclude "publish/Ryujinx.Headless.SDL2" -cvf "$RELEASE_TAR_FILE_NAME" publish 1> /dev/null
+python3 "$BASE_DIR/distribution/misc/add_tar_exec.py" "$RELEASE_TAR_FILE_NAME" "publish/Ryujinx.Headless.SDL2" "publish/Ryujinx.Headless.SDL2"
+gzip -9 < "$RELEASE_TAR_FILE_NAME" > "$RELEASE_TAR_FILE_NAME.gz"
+rm "$RELEASE_TAR_FILE_NAME"
+popd
+
+echo "Done"

distribution/macos/updater.sh

@@ -5,7 +5,7 @@ set -e
 INSTALL_DIRECTORY=$1
 NEW_APP_DIRECTORY=$2
 APP_PID=$3
-APP_ARGUMENTS="${@:4}"
+APP_ARGUMENTS=("${@:4}")
 
 error_handler() {
     local lineno="$1"
@@ -25,14 +25,27 @@ error_handler() {
     exit 1
 }
 
-# Wait for Ryujinx to exit
-# NOTE: in case no fds are open, lsof could be returning with a process still living.
-# We wait 1s and assume the process stopped after that
-lsof -p $APP_PID +r 1 &>/dev/null
-sleep 1
-
 trap 'error_handler ${LINENO}' ERR
 
+# Wait for Ryujinx to exit.
+# If the main process is still acitve, we wait for 1 second and check it again.
+# After the fifth time checking, this script exits with status 1.
+
+attempt=0
+while true; do
+    if lsof -p "$APP_PID" +r 1 &>/dev/null || ps -p "$APP_PID" &>/dev/null; then
+        if [ "$attempt" -eq 4 ]; then
+            exit 1
+        fi
+        sleep 1
+    else
+        break
+    fi
+    (( attempt++ ))
+done
+
+sleep 1
+
 # Now replace and reopen.
 rm -rf "$INSTALL_DIRECTORY"
 mv "$NEW_APP_DIRECTORY" "$INSTALL_DIRECTORY"
@@ -40,5 +53,5 @@ mv "$NEW_APP_DIRECTORY" "$INSTALL_DIRECTORY"
 if [ "$#" -le 3 ]; then
     open -a "$INSTALL_DIRECTORY"
 else
-    open -a "$INSTALL_DIRECTORY" --args "$APP_ARGUMENTS"
-fi
+    open -a "$INSTALL_DIRECTORY" --args "${APP_ARGUMENTS[@]}"
+fi

docs/README.md

@@ -0,0 +1,40 @@
+# Documents Index
+
+This repo includes several documents that explain both high-level and low-level concepts about Ryujinx and its functions. These are very useful for contributors, to get context that can be very difficult to acquire from just reading code.
+
+Intro to Ryujinx
+==================
+
+Ryujinx is an open-source Nintendo Switch emulator, created by gdkchan, written in C#. 
+* The CPU emulator, ARMeilleure, emulates an ARMv8 CPU and currently has support for most 64-bit ARMv8 and some of the ARMv7 (and older) instructions.
+* The GPU emulator emulates the Switch's Maxwell GPU using either the OpenGL (version 4.5 minimum), Vulkan, or Metal (via MoltenVK) APIs through a custom build of OpenTK or Silk.NET respectively.
+* Audio output is entirely supported via C# wrappers for SDL2, with OpenAL & libsoundio as fallbacks.
+
+Getting Started
+===============
+
+- [Installing the .NET SDK](https://dotnet.microsoft.com/download)
+- [Official .NET Docs](https://docs.microsoft.com/dotnet/core/)
+
+Contributing (Building, testing, benchmarking, profiling, etc.)
+===============
+
+If you want to contribute a code change to this repo, start here.
+
+- [Contributor Guide](../CONTRIBUTING.md)
+
+Coding Guidelines
+=================
+
+- [C# coding style](coding-guidelines/coding-style.md)
+- [Service Implementation Guidelines - WIP](https://gist.github.com/gdkchan/84ba88cd50efbe58d1babfaa7cd7c455)
+
+Project Docs
+=================
+
+To be added. Many project files will contain basic XML docs for key functions and classes in the meantime.
+
+Other Information
+=================
+
+- N/A

docs/coding-guidelines/coding-style.md

@@ -0,0 +1,116 @@
+# C# Coding Style
+
+The general rule we follow is "use Visual Studio defaults". 
+Using an IDE that supports the `.editorconfig` standard will make this much simpler.
+
+1. We use [Allman style](http://en.wikipedia.org/wiki/Indent_style#Allman_style) braces, where each brace begins on a new line. A single line statement block can go without braces but the block must be properly indented on its own line and must not be nested in other statement blocks that use braces (See rule 18 for more details). One exception is that a `using` statement is permitted to be nested within another `using` statement by starting on the following line at the same indentation level, even if the nested `using` contains a controlled block.
+2. We use four spaces of indentation (no tabs).
+3. We use `_camelCase` for internal and private fields and use `readonly` where possible. Prefix internal and private instance fields with `_`, static fields with `s_` and thread static fields with `t_`. When used on static fields, `readonly` should come after `static` (e.g. `static readonly` not `readonly static`).  Public fields should be used sparingly and should use PascalCasing with no prefix when used.
+4. We avoid `this.` unless absolutely necessary.
+5. We always specify the visibility, even if it's the default (e.g.
+   `private string _foo` not `string _foo`). Visibility should be the first modifier (e.g.
+   `public abstract` not `abstract public`).
+6. Namespace imports should be specified at the top of the file, *outside* of `namespace` declarations.
+7. Avoid more than one empty line at any time. For example, do not have two
+   blank lines between members of a type.
+8. Avoid spurious free spaces.
+   For example avoid `if (someVar == 0)...`, where the dots mark the spurious free spaces.
+   Consider enabling "View White Space (Ctrl+R, Ctrl+W)" or "Edit -> Advanced -> View White Space" if using Visual Studio to aid detection.
+9. If a file happens to differ in style from these guidelines (e.g. private members are named `m_member`
+   rather than `_member`), the existing style in that file takes precedence.
+10. We only use `var` when the type is explicitly named on the right-hand side, typically due to either `new` or an explicit cast, e.g. `var stream = new FileStream(...)` not `var stream = OpenStandardInput()`.
+    - Similarly, target-typed `new()` can only be used when the type is explicitly named on the left-hand side, in a variable definition statement or a field definition statement. e.g. `FileStream stream = new(...);`, but not `stream = new(...);` (where the type was specified on a previous line).
+11. We use language keywords instead of BCL types (e.g. `int, string, float` instead of `Int32, String, Single`, etc) for both type references as well as method calls (e.g. `int.Parse` instead of `Int32.Parse`). See issue [#13976](https://github.com/dotnet/runtime/issues/13976) for examples.
+12. We use PascalCasing to name all our constant local variables and fields. The only exception is for interop code where the constant value should exactly match the name and value of the code you are calling via interop.
+13. We use PascalCasing for all method names, including local functions.
+14. We use ```nameof(...)``` instead of ```"..."``` whenever possible and relevant.
+15. Fields should be specified at the top within type declarations.
+16. When including non-ASCII characters in the source code use Unicode escape sequences (\uXXXX) instead of literal characters. Literal non-ASCII characters occasionally get garbled by a tool or editor.
+17. When using labels (for goto), indent the label one less than the current indentation.
+18. When using a single-statement if, we follow these conventions:
+    - Never use single-line form (for example: `if (source == null) throw new ArgumentNullException("source");`)
+    - Using braces is always accepted, and required if any block of an `if`/`else if`/.../`else` compound statement uses braces or if a single statement body spans multiple lines.
+    - Braces may be omitted only if the body of *every* block associated with an `if`/`else if`/.../`else` compound statement is placed on a single line.
+19. Make all internal and private types static or sealed unless derivation from them is required.  As with any implementation detail, they can be changed if/when derivation is required in the future.
+20. XML docs should be used when writing interfaces or when a class/method is deemed sufficient in scope or complexity.
+21. So-called [Magic Numbers](https://en.wikipedia.org/wiki/Magic_number_(programming)) should be defined as named constants before use (for example `for (int i = 56; i < 68; i++)` could read `for (int i = _currentAge; i < _retireAge; i++)`). 
+    This may be ignored for trivial or syntactically common statements.
+
+An [EditorConfig](https://editorconfig.org "EditorConfig homepage") file (`.editorconfig`) has been provided at the root of the runtime repository, enabling C# auto-formatting conforming to the above guidelines.
+
+### Example File:
+
+``ShaderCache.cs:``
+
+```C#
+using Ryujinx.Common.Configuration;
+using Ryujinx.Common.Logging;
+using Ryujinx.Graphics.GAL;
+using Ryujinx.Graphics.Gpu.Engine.Threed;
+using Ryujinx.Graphics.Gpu.Engine.Types;
+using Ryujinx.Graphics.Gpu.Image;
+using Ryujinx.Graphics.Gpu.Memory;
+using Ryujinx.Graphics.Gpu.Shader.DiskCache;
+using Ryujinx.Graphics.Shader;
+using Ryujinx.Graphics.Shader.Translation;
+using System;
+using System.Collections.Generic;
+using System.IO;
+using System.Threading;
+
+namespace Ryujinx.Graphics.Gpu.Shader
+{
+    /// <summary>
+    /// Memory cache of shader code.
+    /// </summary>
+    class ShaderCache : IDisposable
+    {
+        /// <summary>
+        /// Default flags used on the shader translation process.
+        /// </summary>
+        public const TranslationFlags DefaultFlags = TranslationFlags.DebugMode;
+
+        private readonly struct TranslatedShader
+        {
+            public readonly CachedShaderStage Shader;
+            public readonly ShaderProgram Program;
+
+            public TranslatedShader(CachedShaderStage shader, ShaderProgram program)
+            {
+                Shader = shader;
+                Program = program;
+            }
+        }
+        ...
+
+        /// <summary>
+        /// Processes the queue of shaders that must save their binaries to the disk cache.
+        /// </summary>
+        public void ProcessShaderCacheQueue()
+        {
+            // Check to see if the binaries for previously compiled shaders are ready, and save them out.
+
+            while (_programsToSaveQueue.TryPeek(out ProgramToSave programToSave))
+            {
+                ProgramLinkStatus result = programToSave.HostProgram.CheckProgramLink(false);
+
+                if (result != ProgramLinkStatus.Incomplete)
+                {
+                    if (result == ProgramLinkStatus.Success)
+                    {
+                        _cacheWriter.AddShader(programToSave.CachedProgram, programToSave.BinaryCode ?? programToSave.HostProgram.GetBinary());
+                    }
+
+                    _programsToSaveQueue.Dequeue();
+                }
+                else
+                {
+                    break;
+                }
+            }
+        }
+    }
+}
+```
+
+For other languages, our current best guidance is consistency. When editing files, keep new code and changes consistent with the style in the files. For new files, it should conform to the style for that component. If there is a completely new component, anything that is reasonably broadly accepted is fine.

docs/workflow/pr-guide.md

@@ -0,0 +1,56 @@
+# Pull Request Guide
+
+## Contributing Rules
+
+All contributions to Ryujinx/Ryujinx repository are made via pull requests (PRs) rather than through direct commits. The pull requests are reviewed and merged by the maintainers after a review and at least two approvals from the core development team.
+
+To merge pull requests, you must have write permissions in the repository.
+
+## Quick Code Review Rules
+
+* Do not mix unrelated changes in one pull request. For example, a code style change should never be mixed with a bug fix.
+* All changes should follow the existing code style. You can read more about our code style at [docs/coding-guidelines](../coding-guidelines/coding-style.md).
+* Adding external dependencies is to be avoided unless not doing so would introduce _significant_ complexity. Any dependency addition should be justified and discussed before merge.
+* Use Draft pull requests for changes you are still working on but want early CI loop feedback. When you think your changes are ready for review, [change the status](https://help.github.com/en/github/collaborating-with-issues-and-pull-requests/changing-the-stage-of-a-pull-request) of your pull request.
+* Rebase your changes when required or directly requested. Changes should always be commited on top of the upstream branch, not the other way around.
+* If you are asked to make changes during the review process do them as a new commit.
+* Only resolve GitHub conversations with reviewers once they have been addressed with a commit, or via a mutual agreement.
+
+## Pull Request Ownership
+
+Every pull request will have automatically have labels and reviewers assigned. The label not only indicates the code segment which the change touches but also the area reviewers to be assigned.
+
+If during the code review process a merge conflict occurs, the PR author is responsible for its resolution. Help will be provided if necessary although GitHub makes this easier by allowing simple conflict resolution using the [conflict-editor](https://help.github.com/en/github/collaborating-with-issues-and-pull-requests/resolving-a-merge-conflict-on-github).
+
+## Pull Request Builds
+
+When submitting a PR to the `Ryujinx/Ryujinx` repository, various builds will run validating many areas to ensure we keep developer productivity and product quality high. These various workflows can be tracked in the [Actions](https://github.com/Ryujinx/Ryujinx/actions) tab of the repository. If the job continues to completion, the build artifacts will be uploaded and posted as a comment in the PR discussion.
+
+## Review Turnaround Times
+
+Ryujinx is a project that is maintained by volunteers on a completely free-time basis. As such we cannot guarantee any particular timeframe for pull request review and approval. Weeks to months are common for larger (>500 line) PRs but there are some additional best practises to avoid review purgatory.
+
+* Make the reviewers life easier wherever possible. Make use of descriptive commit names, code comments and XML docs where applicable.
+* If there is disagreement on feedback then always lean on the side of the development team and community over any personal opinion.
+* We're human. We miss things. We forget things. If there has been radio silence on your changes for a substantial period of time then do not hesitate to reach out directly either with something simple like "bump" on GitHub or a directly on Discord.
+
+To re-iterate, make the review as easy for us as possible, respond promptly and be comfortable to interact directly with us for anything else.
+
+## Merging Pull Requests
+
+Anyone with write access can merge a pull request manually when the following conditions have been met:
+
+* The PR has been approved by two reviewers and any other objections are addressed.
+    * You can request follow up reviews from the original reviewers if they requested changes.
+* The PR successfully builds and passes all tests in the Continuous Integration (CI) system. In case of failures, refer to the [Actions](https://github.com/Ryujinx/Ryujinx/actions) tab of your PR.
+
+Typically, PRs are merged as one commit (squash merges). It creates a simpler history than a Merge Commit. "Special circumstances" are rare, and typically mean that there are a series of cleanly separated changes that will be too hard to understand if squashed together, or for some reason we want to preserve the ability to dissect them.
+
+## Blocking Pull Request Merging
+
+If for whatever reason you would like to move your pull request back to an in-progress status to avoid merging it in the current form, you can turn the PR into a draft PR by selecting the option under the reviewers section. Alternatively, you can do that by adding [WIP] prefix to the pull request title.
+
+## Old Pull Request Policy
+
+From time to time we will review older PRs and check them for relevance. If we find the PR is inactive or no longer applies, we will close it. As the PR owner, you can simply reopen it if you feel your closed PR needs our attention.
+

src/ARMeilleure/Allocators.cs

@@ -23,10 +23,7 @@ namespace ARMeilleure
         [MethodImpl(MethodImplOptions.AggressiveInlining)]
         private static ArenaAllocator GetAllocator(ref ArenaAllocator alloc, uint pageSize, uint pageCount)
         {
-            if (alloc == null)
-            {
-                alloc = new ArenaAllocator(pageSize, pageCount);
-            }
+            alloc ??= new ArenaAllocator(pageSize, pageCount);
 
             return alloc;
         }

src/ARMeilleure/CodeGen/Arm64/Arm64Optimizer.cs

@@ -221,7 +221,7 @@ namespace ARMeilleure.CodeGen.Arm64
                         2 => Multiplier.x4,
                         3 => Multiplier.x8,
                         4 => Multiplier.x16,
-                        _ => Multiplier.x1
+                        _ => Multiplier.x1,
                     };
 
                     baseOp = indexOnSrc2 ? src1 : src2;

src/ARMeilleure/CodeGen/Arm64/ArmCondition.cs

@@ -5,22 +5,22 @@ namespace ARMeilleure.CodeGen.Arm64
 {
     enum ArmCondition
     {
-        Eq   = 0,
-        Ne   = 1,
+        Eq = 0,
+        Ne = 1,
         GeUn = 2,
         LtUn = 3,
-        Mi   = 4,
-        Pl   = 5,
-        Vs   = 6,
-        Vc   = 7,
+        Mi = 4,
+        Pl = 5,
+        Vs = 6,
+        Vc = 7,
         GtUn = 8,
         LeUn = 9,
-        Ge   = 10,
-        Lt   = 11,
-        Gt   = 12,
-        Le   = 13,
-        Al   = 14,
-        Nv   = 15
+        Ge = 10,
+        Lt = 11,
+        Gt = 12,
+        Le = 13,
+        Al = 14,
+        Nv = 15,
     }
 
     static class ComparisonArm64Extensions
@@ -29,6 +29,7 @@ namespace ARMeilleure.CodeGen.Arm64
         {
             return comp switch
             {
+#pragma warning disable IDE0055 // Disable formatting
                 Comparison.Equal            => ArmCondition.Eq,
                 Comparison.NotEqual         => ArmCondition.Ne,
                 Comparison.Greater          => ArmCondition.Gt,
@@ -39,8 +40,9 @@ namespace ARMeilleure.CodeGen.Arm64
                 Comparison.Less             => ArmCondition.Lt,
                 Comparison.GreaterOrEqualUI => ArmCondition.GeUn,
                 Comparison.LessUI           => ArmCondition.LtUn,
+#pragma warning restore IDE0055
 
-                _ => throw new ArgumentException(null, nameof(comp))
+                _ => throw new ArgumentException(null, nameof(comp)),
             };
         }
     }

src/ARMeilleure/CodeGen/Arm64/ArmExtensionType.cs

@@ -9,6 +9,6 @@ namespace ARMeilleure.CodeGen.Arm64
         Sxtb = 4,
         Sxth = 5,
         Sxtw = 6,
-        Sxtx = 7
+        Sxtx = 7,
     }
 }

src/ARMeilleure/CodeGen/Arm64/ArmShiftType.cs

@@ -6,6 +6,6 @@ namespace ARMeilleure.CodeGen.Arm64
         Lsl = 0,
         Lsr = 1,
         Asr = 2,
-        Ror = 3
+        Ror = 3,
     }
-}
+}

src/ARMeilleure/CodeGen/Arm64/Assembler.cs

@@ -188,7 +188,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
             uint rmode = topHalf ? 1u << 19 : 0u;
             uint ftype = rd.Type == OperandType.FP64 || rn.Type == OperandType.FP64 ? 1u << 22 : 0u;
-            uint sf    = rd.Type == OperandType.I64  || rn.Type == OperandType.I64  ? SfFlag   : 0u;
+            uint sf = rd.Type == OperandType.I64 || rn.Type == OperandType.I64 ? SfFlag : 0u;
 
             WriteUInt32(0x1e260000u | (opcode << 16) | rmode | ftype | sf | EncodeReg(rd) | (EncodeReg(rn) << 5));
         }
@@ -992,7 +992,7 @@ namespace ARMeilleure.CodeGen.Arm64
                 {
                     OperandType.FP32 => 0,
                     OperandType.FP64 => 1,
-                    _ => 2
+                    _ => 2,
                 };
 
                 instruction = vecInst | ((uint)opc << 30);
@@ -1124,10 +1124,11 @@ namespace ARMeilleure.CodeGen.Arm64
                 OperandType.FP32 => 2,
                 OperandType.FP64 => 3,
                 OperandType.V128 => 4,
-                _ => throw new ArgumentException($"Invalid type {type}.")
+                _ => throw new ArgumentException($"Invalid type {type}."),
             };
         }
 
+#pragma warning disable IDE0051 // Remove unused private member
         private void WriteInt16(short value)
         {
             WriteUInt16((ushort)value);
@@ -1142,6 +1143,7 @@ namespace ARMeilleure.CodeGen.Arm64
         {
             _stream.WriteByte(value);
         }
+#pragma warning restore IDE0051
 
         private void WriteUInt16(ushort value)
         {

src/ARMeilleure/CodeGen/Arm64/CallingConvention.cs

@@ -93,4 +93,4 @@ namespace ARMeilleure.CodeGen.Arm64
             return 0;
         }
     }
-}
+}

src/ARMeilleure/CodeGen/Arm64/CodeGenCommon.cs

@@ -88,4 +88,4 @@ namespace ARMeilleure.CodeGen.Arm64
             return true;
         }
     }
-}
+}

src/ARMeilleure/CodeGen/Arm64/CodeGenContext.cs

@@ -14,7 +14,7 @@ namespace ARMeilleure.CodeGen.Arm64
         private const int CbnzInstLength = 4;
         private const int LdrLitInstLength = 4;
 
-        private Stream _stream;
+        private readonly Stream _stream;
 
         public int StreamOffset => (int)_stream.Length;
 
@@ -32,7 +32,7 @@ namespace ARMeilleure.CodeGen.Arm64
         private readonly Dictionary<BasicBlock, long> _visitedBlocks;
         private readonly Dictionary<BasicBlock, List<(ArmCondition Condition, long BranchPos)>> _pendingBranches;
 
-        private struct ConstantPoolEntry
+        private readonly struct ConstantPoolEntry
         {
             public readonly int Offset;
             public readonly Symbol Symbol;
@@ -58,7 +58,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private readonly bool _relocatable;
 
-        public CodeGenContext(AllocationResult allocResult, int maxCallArgs, int blocksCount, bool relocatable)
+        public CodeGenContext(AllocationResult allocResult, int maxCallArgs, bool relocatable)
         {
             _stream = MemoryStreamManager.Shared.GetStream();
 
@@ -93,10 +93,10 @@ namespace ARMeilleure.CodeGen.Arm64
 
             if (_pendingBranches.TryGetValue(block, out var list))
             {
-                foreach (var tuple in list)
+                foreach ((ArmCondition condition, long branchPos) in list)
                 {
-                    _stream.Seek(tuple.BranchPos, SeekOrigin.Begin);
-                    WriteBranch(tuple.Condition, target);
+                    _stream.Seek(branchPos, SeekOrigin.Begin);
+                    WriteBranch(condition, target);
                 }
 
                 _stream.Seek(target, SeekOrigin.Begin);
@@ -284,4 +284,4 @@ namespace ARMeilleure.CodeGen.Arm64
             _stream.WriteByte((byte)(value >> 56));
         }
     }
-}
+}

src/ARMeilleure/CodeGen/Arm64/CodeGenerator.cs

@@ -10,7 +10,6 @@ using System;
 using System.Collections.Generic;
 using System.Diagnostics;
 using System.Numerics;
-
 using static ARMeilleure.IntermediateRepresentation.Operand;
 using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
 
@@ -31,15 +30,16 @@ namespace ARMeilleure.CodeGen.Arm64
         {
             Byte,
             Hword,
-            Auto
+            Auto,
         }
 
-        private static Action<CodeGenContext, Operation>[] _instTable;
+        private static readonly Action<CodeGenContext, Operation>[] _instTable;
 
         static CodeGenerator()
         {
             _instTable = new Action<CodeGenContext, Operation>[EnumUtils.GetCount(typeof(Instruction))];
 
+#pragma warning disable IDE0055 // Disable formatting
             Add(Instruction.Add,                     GenerateAdd);
             Add(Instruction.BitwiseAnd,              GenerateBitwiseAnd);
             Add(Instruction.BitwiseExclusiveOr,      GenerateBitwiseExclusiveOr);
@@ -48,7 +48,7 @@ namespace ARMeilleure.CodeGen.Arm64
             Add(Instruction.BranchIf,                GenerateBranchIf);
             Add(Instruction.ByteSwap,                GenerateByteSwap);
             Add(Instruction.Call,                    GenerateCall);
-            //Add(Instruction.Clobber,                 GenerateClobber);
+            // Add(Instruction.Clobber,                 GenerateClobber);
             Add(Instruction.Compare,                 GenerateCompare);
             Add(Instruction.CompareAndSwap,          GenerateCompareAndSwap);
             Add(Instruction.CompareAndSwap16,        GenerateCompareAndSwap16);
@@ -100,6 +100,7 @@ namespace ARMeilleure.CodeGen.Arm64
             Add(Instruction.ZeroExtend16,            GenerateZeroExtend16);
             Add(Instruction.ZeroExtend32,            GenerateZeroExtend32);
             Add(Instruction.ZeroExtend8,             GenerateZeroExtend8);
+#pragma warning restore IDE0055
 
             static void Add(Instruction inst, Action<CodeGenContext, Operation> func)
             {
@@ -131,7 +132,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
             StackAllocator stackAlloc = new();
 
-            PreAllocator.RunPass(cctx, stackAlloc, out int maxCallArgs);
+            PreAllocator.RunPass(cctx, out int maxCallArgs);
 
             Logger.EndPass(PassName.PreAllocation, cfg);
 
@@ -168,11 +169,9 @@ namespace ARMeilleure.CodeGen.Arm64
 
             Logger.StartPass(PassName.CodeGeneration);
 
-            //Console.Error.WriteLine(IRDumper.GetDump(cfg));
-
             bool relocatable = (cctx.Options & CompilerOptions.Relocatable) != 0;
 
-            CodeGenContext context = new(allocResult, maxCallArgs, cfg.Blocks.Count, relocatable);
+            CodeGenContext context = new(allocResult, maxCallArgs, relocatable);
 
             UnwindInfo unwindInfo = WritePrologue(context);
 
@@ -294,7 +293,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateBitwiseNot(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             ValidateUnOp(dest, source);
@@ -332,7 +331,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateByteSwap(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             ValidateUnOp(dest, source);
@@ -366,15 +365,15 @@ namespace ARMeilleure.CodeGen.Arm64
         {
             if (operation.SourcesCount == 5) // CompareAndSwap128 has 5 sources, compared to CompareAndSwap64/32's 3.
             {
-                Operand actualLow    = operation.GetDestination(0);
-                Operand actualHigh   = operation.GetDestination(1);
-                Operand temp0        = operation.GetDestination(2);
-                Operand temp1        = operation.GetDestination(3);
-                Operand address      = operation.GetSource(0);
-                Operand expectedLow  = operation.GetSource(1);
+                Operand actualLow = operation.GetDestination(0);
+                Operand actualHigh = operation.GetDestination(1);
+                Operand temp0 = operation.GetDestination(2);
+                Operand temp1 = operation.GetDestination(3);
+                Operand address = operation.GetSource(0);
+                Operand expectedLow = operation.GetSource(1);
                 Operand expectedHigh = operation.GetSource(2);
-                Operand desiredLow   = operation.GetSource(3);
-                Operand desiredHigh  = operation.GetSource(4);
+                Operand desiredLow = operation.GetSource(3);
+                Operand desiredHigh = operation.GetSource(4);
 
                 GenerateAtomicDcas(
                     context,
@@ -390,11 +389,11 @@ namespace ARMeilleure.CodeGen.Arm64
             }
             else
             {
-                Operand actual   = operation.GetDestination(0);
-                Operand result   = operation.GetDestination(1);
-                Operand address  = operation.GetSource(0);
+                Operand actual = operation.GetDestination(0);
+                Operand result = operation.GetDestination(1);
+                Operand address = operation.GetSource(0);
                 Operand expected = operation.GetSource(1);
-                Operand desired  = operation.GetSource(2);
+                Operand desired = operation.GetSource(2);
 
                 GenerateAtomicCas(context, address, expected, desired, actual, result, AccessSize.Auto);
             }
@@ -402,22 +401,22 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateCompareAndSwap16(CodeGenContext context, Operation operation)
         {
-            Operand actual   = operation.GetDestination(0);
-            Operand result   = operation.GetDestination(1);
-            Operand address  = operation.GetSource(0);
+            Operand actual = operation.GetDestination(0);
+            Operand result = operation.GetDestination(1);
+            Operand address = operation.GetSource(0);
             Operand expected = operation.GetSource(1);
-            Operand desired  = operation.GetSource(2);
+            Operand desired = operation.GetSource(2);
 
             GenerateAtomicCas(context, address, expected, desired, actual, result, AccessSize.Hword);
         }
 
         private static void GenerateCompareAndSwap8(CodeGenContext context, Operation operation)
         {
-            Operand actual   = operation.GetDestination(0);
-            Operand result   = operation.GetDestination(1);
-            Operand address  = operation.GetSource(0);
+            Operand actual = operation.GetDestination(0);
+            Operand result = operation.GetDestination(1);
+            Operand address = operation.GetSource(0);
             Operand expected = operation.GetSource(1);
-            Operand desired  = operation.GetSource(2);
+            Operand desired = operation.GetSource(2);
 
             GenerateAtomicCas(context, address, expected, desired, actual, result, AccessSize.Byte);
         }
@@ -446,13 +445,13 @@ namespace ARMeilleure.CodeGen.Arm64
             Debug.Assert(dest.Type.IsInteger());
             Debug.Assert(src1.Type == OperandType.I32);
 
-            context.Assembler.Cmp (src1, Const(src1.Type, 0));
+            context.Assembler.Cmp(src1, Const(src1.Type, 0));
             context.Assembler.Csel(dest, src2, src3, ArmCondition.Ne);
         }
 
         private static void GenerateConvertI64ToI32(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type == OperandType.I32 && source.Type == OperandType.I64);
@@ -462,7 +461,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateConvertToFP(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type == OperandType.FP32 || dest.Type == OperandType.FP64);
@@ -481,7 +480,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateConvertToFPUI(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type == OperandType.FP32 || dest.Type == OperandType.FP64);
@@ -493,7 +492,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateCopy(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             EnsureSameType(dest, source);
@@ -525,7 +524,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateCountLeadingZeros(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             EnsureSameType(dest, source);
@@ -537,9 +536,9 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateDivide(CodeGenContext context, Operation operation)
         {
-            Operand dest     = operation.Destination;
+            Operand dest = operation.Destination;
             Operand dividend = operation.GetSource(0);
-            Operand divisor  = operation.GetSource(1);
+            Operand divisor = operation.GetSource(1);
 
             ValidateBinOp(dest, dividend, divisor);
 
@@ -555,9 +554,9 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateDivideUI(CodeGenContext context, Operation operation)
         {
-            Operand dest     = operation.Destination;
+            Operand dest = operation.Destination;
             Operand dividend = operation.GetSource(0);
-            Operand divisor  = operation.GetSource(1);
+            Operand divisor = operation.GetSource(1);
 
             ValidateBinOp(dest, dividend, divisor);
 
@@ -566,7 +565,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateLoad(CodeGenContext context, Operation operation)
         {
-            Operand value   = operation.Destination;
+            Operand value = operation.Destination;
             Operand address = operation.GetSource(0);
 
             context.Assembler.Ldr(value, address);
@@ -574,7 +573,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateLoad16(CodeGenContext context, Operation operation)
         {
-            Operand value   = operation.Destination;
+            Operand value = operation.Destination;
             Operand address = operation.GetSource(0);
 
             Debug.Assert(value.Type.IsInteger());
@@ -584,7 +583,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateLoad8(CodeGenContext context, Operation operation)
         {
-            Operand value   = operation.Destination;
+            Operand value = operation.Destination;
             Operand address = operation.GetSource(0);
 
             Debug.Assert(value.Type.IsInteger());
@@ -643,7 +642,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateNegate(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             ValidateUnOp(dest, source);
@@ -730,7 +729,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateSignExtend16(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -740,7 +739,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateSignExtend32(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -750,7 +749,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateSignExtend8(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -760,7 +759,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateFill(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand offset = operation.GetSource(0);
 
             Debug.Assert(offset.Kind == OperandKind.Constant);
@@ -801,7 +800,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateStackAlloc(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand offset = operation.GetSource(0);
 
             Debug.Assert(offset.Kind == OperandKind.Constant);
@@ -813,7 +812,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateStore(CodeGenContext context, Operation operation)
         {
-            Operand value   = operation.GetSource(1);
+            Operand value = operation.GetSource(1);
             Operand address = operation.GetSource(0);
 
             context.Assembler.Str(value, address);
@@ -821,7 +820,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateStore16(CodeGenContext context, Operation operation)
         {
-            Operand value   = operation.GetSource(1);
+            Operand value = operation.GetSource(1);
             Operand address = operation.GetSource(0);
 
             Debug.Assert(value.Type.IsInteger());
@@ -831,7 +830,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateStore8(CodeGenContext context, Operation operation)
         {
-            Operand value   = operation.GetSource(1);
+            Operand value = operation.GetSource(1);
             Operand address = operation.GetSource(0);
 
             Debug.Assert(value.Type.IsInteger());
@@ -878,7 +877,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateVectorCreateScalar(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             if (dest != default)
@@ -1024,7 +1023,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateVectorZeroUpper64(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type == OperandType.V128 && source.Type == OperandType.V128);
@@ -1034,7 +1033,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateVectorZeroUpper96(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type == OperandType.V128 && source.Type == OperandType.V128);
@@ -1044,7 +1043,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateZeroExtend16(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -1054,7 +1053,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateZeroExtend32(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -1070,7 +1069,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateZeroExtend8(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -1080,7 +1079,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static UnwindInfo WritePrologue(CodeGenContext context)
         {
-            List<UnwindPushEntry> pushEntries = new List<UnwindPushEntry>();
+            List<UnwindPushEntry> pushEntries = new();
 
             Operand rsp = Register(SpRegister);
 
@@ -1570,11 +1569,13 @@ namespace ARMeilleure.CodeGen.Arm64
             Debug.Assert(op1.Type == op3.Type);
         }
 
+#pragma warning disable IDE0051 // Remove unused private member
         private static void EnsureSameType(Operand op1, Operand op2, Operand op3, Operand op4)
         {
             Debug.Assert(op1.Type == op2.Type);
             Debug.Assert(op1.Type == op3.Type);
             Debug.Assert(op1.Type == op4.Type);
         }
+#pragma warning restore IDE0051
     }
-}
+}

src/ARMeilleure/CodeGen/Arm64/CodeGeneratorIntrinsic.cs

@@ -179,6 +179,35 @@ namespace ARMeilleure.CodeGen.Arm64
                         (uint)operation.GetSource(2).AsInt32());
                     break;
 
+                case IntrinsicType.Vector128Unary:
+                    GenerateVectorUnary(
+                        context,
+                        1,
+                        0,
+                        info.Inst,
+                        operation.Destination,
+                        operation.GetSource(0));
+                    break;
+                case IntrinsicType.Vector128Binary:
+                    GenerateVectorBinary(
+                        context,
+                        1,
+                        0,
+                        info.Inst,
+                        operation.Destination,
+                        operation.GetSource(0),
+                        operation.GetSource(1));
+                    break;
+                case IntrinsicType.Vector128BinaryRd:
+                    GenerateVectorUnary(
+                        context,
+                        1,
+                        0,
+                        info.Inst,
+                        operation.Destination,
+                        operation.GetSource(1));
+                    break;
+
                 case IntrinsicType.VectorUnary:
                     GenerateVectorUnary(
                         context,
@@ -659,4 +688,4 @@ namespace ARMeilleure.CodeGen.Arm64
             context.Assembler.WriteInstruction(instruction, rd, rn);
         }
     }
-}
+}

src/ARMeilleure/CodeGen/Arm64/HardwareCapabilities.cs

@@ -1,7 +1,4 @@
 using System;
-using System.Linq;
-using System.Reflection;
-using System.Runtime.CompilerServices;
 using System.Runtime.InteropServices;
 using System.Runtime.Intrinsics.Arm;
 using System.Runtime.Versioning;
@@ -35,7 +32,7 @@ namespace ARMeilleure.CodeGen.Arm64
             }
         }
 
-#region Linux
+        #region Linux
 
         private const ulong AT_HWCAP = 16;
         private const ulong AT_HWCAP2 = 26;
@@ -46,88 +43,88 @@ namespace ARMeilleure.CodeGen.Arm64
         [Flags]
         public enum LinuxFeatureFlagsHwCap : ulong
         {
-            Fp        = 1 << 0,
-            Asimd     = 1 << 1,
-            Evtstrm   = 1 << 2,
-            Aes       = 1 << 3,
-            Pmull     = 1 << 4,
-            Sha1      = 1 << 5,
-            Sha2      = 1 << 6,
-            Crc32     = 1 << 7,
-            Atomics   = 1 << 8,
-            FpHp      = 1 << 9,
-            AsimdHp   = 1 << 10,
-            CpuId     = 1 << 11,
-            AsimdRdm  = 1 << 12,
-            Jscvt     = 1 << 13,
-            Fcma      = 1 << 14,
-            Lrcpc     = 1 << 15,
-            DcpOp     = 1 << 16,
-            Sha3      = 1 << 17,
-            Sm3       = 1 << 18,
-            Sm4       = 1 << 19,
-            AsimdDp   = 1 << 20,
-            Sha512    = 1 << 21,
-            Sve       = 1 << 22,
-            AsimdFhm  = 1 << 23,
-            Dit       = 1 << 24,
-            Uscat     = 1 << 25,
-            Ilrcpc    = 1 << 26,
-            FlagM     = 1 << 27,
-            Ssbs      = 1 << 28,
-            Sb        = 1 << 29,
-            Paca      = 1 << 30,
-            Pacg      = 1UL << 31
+            Fp = 1 << 0,
+            Asimd = 1 << 1,
+            Evtstrm = 1 << 2,
+            Aes = 1 << 3,
+            Pmull = 1 << 4,
+            Sha1 = 1 << 5,
+            Sha2 = 1 << 6,
+            Crc32 = 1 << 7,
+            Atomics = 1 << 8,
+            FpHp = 1 << 9,
+            AsimdHp = 1 << 10,
+            CpuId = 1 << 11,
+            AsimdRdm = 1 << 12,
+            Jscvt = 1 << 13,
+            Fcma = 1 << 14,
+            Lrcpc = 1 << 15,
+            DcpOp = 1 << 16,
+            Sha3 = 1 << 17,
+            Sm3 = 1 << 18,
+            Sm4 = 1 << 19,
+            AsimdDp = 1 << 20,
+            Sha512 = 1 << 21,
+            Sve = 1 << 22,
+            AsimdFhm = 1 << 23,
+            Dit = 1 << 24,
+            Uscat = 1 << 25,
+            Ilrcpc = 1 << 26,
+            FlagM = 1 << 27,
+            Ssbs = 1 << 28,
+            Sb = 1 << 29,
+            Paca = 1 << 30,
+            Pacg = 1UL << 31,
         }
 
         [Flags]
         public enum LinuxFeatureFlagsHwCap2 : ulong
         {
-            Dcpodp      = 1 << 0,
-            Sve2        = 1 << 1,
-            SveAes      = 1 << 2,
-            SvePmull    = 1 << 3,
-            SveBitperm  = 1 << 4,
-            SveSha3     = 1 << 5,
-            SveSm4      = 1 << 6,
-            FlagM2      = 1 << 7,
-            Frint       = 1 << 8,
-            SveI8mm     = 1 << 9,
-            SveF32mm    = 1 << 10,
-            SveF64mm    = 1 << 11,
-            SveBf16     = 1 << 12,
-            I8mm        = 1 << 13,
-            Bf16        = 1 << 14,
-            Dgh         = 1 << 15,
-            Rng         = 1 << 16,
-            Bti         = 1 << 17,
-            Mte         = 1 << 18,
-            Ecv         = 1 << 19,
-            Afp         = 1 << 20,
-            Rpres       = 1 << 21,
-            Mte3        = 1 << 22,
-            Sme         = 1 << 23,
-            Sme_i16i64  = 1 << 24,
-            Sme_f64f64  = 1 << 25,
-            Sme_i8i32   = 1 << 26,
-            Sme_f16f32  = 1 << 27,
-            Sme_b16f32  = 1 << 28,
-            Sme_f32f32  = 1 << 29,
-            Sme_fa64    = 1 << 30,
-            Wfxt        = 1UL << 31,
-            Ebf16       = 1UL << 32,
-            Sve_Ebf16   = 1UL << 33,
-            Cssc        = 1UL << 34,
-            Rprfm       = 1UL << 35,
-            Sve2p1      = 1UL << 36
+            Dcpodp = 1 << 0,
+            Sve2 = 1 << 1,
+            SveAes = 1 << 2,
+            SvePmull = 1 << 3,
+            SveBitperm = 1 << 4,
+            SveSha3 = 1 << 5,
+            SveSm4 = 1 << 6,
+            FlagM2 = 1 << 7,
+            Frint = 1 << 8,
+            SveI8mm = 1 << 9,
+            SveF32mm = 1 << 10,
+            SveF64mm = 1 << 11,
+            SveBf16 = 1 << 12,
+            I8mm = 1 << 13,
+            Bf16 = 1 << 14,
+            Dgh = 1 << 15,
+            Rng = 1 << 16,
+            Bti = 1 << 17,
+            Mte = 1 << 18,
+            Ecv = 1 << 19,
+            Afp = 1 << 20,
+            Rpres = 1 << 21,
+            Mte3 = 1 << 22,
+            Sme = 1 << 23,
+            Sme_i16i64 = 1 << 24,
+            Sme_f64f64 = 1 << 25,
+            Sme_i8i32 = 1 << 26,
+            Sme_f16f32 = 1 << 27,
+            Sme_b16f32 = 1 << 28,
+            Sme_f32f32 = 1 << 29,
+            Sme_fa64 = 1 << 30,
+            Wfxt = 1UL << 31,
+            Ebf16 = 1UL << 32,
+            Sve_Ebf16 = 1UL << 33,
+            Cssc = 1UL << 34,
+            Rprfm = 1UL << 35,
+            Sve2p1 = 1UL << 36,
         }
 
         public static LinuxFeatureFlagsHwCap LinuxFeatureInfoHwCap { get; } = 0;
         public static LinuxFeatureFlagsHwCap2 LinuxFeatureInfoHwCap2 { get; } = 0;
 
-#endregion
+        #endregion
 
-#region macOS
+        #region macOS
 
         [LibraryImport("libSystem.dylib", SetLastError = true)]
         private static unsafe partial int sysctlbyname([MarshalAs(UnmanagedType.LPStr)] string name, out int oldValue, ref ulong oldSize, IntPtr newValue, ulong newValueSize);
@@ -143,7 +140,7 @@ namespace ARMeilleure.CodeGen.Arm64
             return false;
         }
 
-        private static string[] _sysctlNames = new string[]
+        private static readonly string[] _sysctlNames = new string[]
         {
             "hw.optional.floatingpoint",
             "hw.optional.AdvSIMD",
@@ -153,26 +150,26 @@ namespace ARMeilleure.CodeGen.Arm64
             "hw.optional.arm.FEAT_LSE",
             "hw.optional.armv8_crc32",
             "hw.optional.arm.FEAT_SHA1",
-            "hw.optional.arm.FEAT_SHA256"
+            "hw.optional.arm.FEAT_SHA256",
         };
 
         [Flags]
         public enum MacOsFeatureFlags
         {
-            Fp      = 1 << 0,
+            Fp = 1 << 0,
             AdvSimd = 1 << 1,
-            Fp16    = 1 << 2,
-            Aes     = 1 << 3,
-            Pmull   = 1 << 4,
-            Lse     = 1 << 5,
-            Crc32   = 1 << 6,
-            Sha1    = 1 << 7,
-            Sha256  = 1 << 8
+            Fp16 = 1 << 2,
+            Aes = 1 << 3,
+            Pmull = 1 << 4,
+            Lse = 1 << 5,
+            Crc32 = 1 << 6,
+            Sha1 = 1 << 7,
+            Sha256 = 1 << 8,
         }
 
         public static MacOsFeatureFlags MacOsFeatureInfo { get; } = 0;
 
-#endregion
+        #endregion
 
         public static bool SupportsAdvSimd => LinuxFeatureInfoHwCap.HasFlag(LinuxFeatureFlagsHwCap.Asimd) || MacOsFeatureInfo.HasFlag(MacOsFeatureFlags.AdvSimd);
         public static bool SupportsAes => LinuxFeatureInfoHwCap.HasFlag(LinuxFeatureFlagsHwCap.Aes) || MacOsFeatureInfo.HasFlag(MacOsFeatureFlags.Aes);

src/ARMeilleure/CodeGen/Arm64/IntrinsicInfo.cs

@@ -1,8 +1,8 @@
 namespace ARMeilleure.CodeGen.Arm64
 {
-    struct IntrinsicInfo
+    readonly struct IntrinsicInfo
     {
-        public uint          Inst { get; }
+        public uint Inst { get; }
         public IntrinsicType Type { get; }
 
         public IntrinsicInfo(uint inst, IntrinsicType type)
@@ -11,4 +11,4 @@ namespace ARMeilleure.CodeGen.Arm64
             Type = type;
         }
     }
-}
+}

src/ARMeilleure/CodeGen/Arm64/IntrinsicTable.cs

@@ -5,12 +5,13 @@ namespace ARMeilleure.CodeGen.Arm64
 {
     static class IntrinsicTable
     {
-        private static IntrinsicInfo[] _intrinTable;
+        private static readonly IntrinsicInfo[] _intrinTable;
 
         static IntrinsicTable()
         {
             _intrinTable = new IntrinsicInfo[EnumUtils.GetCount(typeof(Intrinsic))];
 
+#pragma warning disable IDE0055 // Disable formatting
             Add(Intrinsic.Arm64AbsS,          new IntrinsicInfo(0x5e20b800u, IntrinsicType.ScalarUnary));
             Add(Intrinsic.Arm64AbsV,          new IntrinsicInfo(0x0e20b800u, IntrinsicType.VectorUnary));
             Add(Intrinsic.Arm64AddhnV,        new IntrinsicInfo(0x0e204000u, IntrinsicType.VectorTernaryRd));
@@ -19,8 +20,8 @@ namespace ARMeilleure.CodeGen.Arm64
             Add(Intrinsic.Arm64AddvV,         new IntrinsicInfo(0x0e31b800u, IntrinsicType.VectorUnary));
             Add(Intrinsic.Arm64AddS,          new IntrinsicInfo(0x5e208400u, IntrinsicType.ScalarBinary));
             Add(Intrinsic.Arm64AddV,          new IntrinsicInfo(0x0e208400u, IntrinsicType.VectorBinary));
-            Add(Intrinsic.Arm64AesdV,         new IntrinsicInfo(0x4e285800u, IntrinsicType.Vector128Unary));
-            Add(Intrinsic.Arm64AeseV,         new IntrinsicInfo(0x4e284800u, IntrinsicType.Vector128Unary));
+            Add(Intrinsic.Arm64AesdV,         new IntrinsicInfo(0x4e285800u, IntrinsicType.Vector128BinaryRd));
+            Add(Intrinsic.Arm64AeseV,         new IntrinsicInfo(0x4e284800u, IntrinsicType.Vector128BinaryRd));
             Add(Intrinsic.Arm64AesimcV,       new IntrinsicInfo(0x4e287800u, IntrinsicType.Vector128Unary));
             Add(Intrinsic.Arm64AesmcV,        new IntrinsicInfo(0x4e286800u, IntrinsicType.Vector128Unary));
             Add(Intrinsic.Arm64AndV,          new IntrinsicInfo(0x0e201c00u, IntrinsicType.VectorBinaryBitwise));
@@ -448,6 +449,7 @@ namespace ARMeilleure.CodeGen.Arm64
             Add(Intrinsic.Arm64XtnV,          new IntrinsicInfo(0x0e212800u, IntrinsicType.VectorUnary));
             Add(Intrinsic.Arm64Zip1V,         new IntrinsicInfo(0x0e003800u, IntrinsicType.VectorBinary));
             Add(Intrinsic.Arm64Zip2V,         new IntrinsicInfo(0x0e007800u, IntrinsicType.VectorBinary));
+#pragma warning restore IDE0055
         }
 
         private static void Add(Intrinsic intrin, IntrinsicInfo info)
@@ -460,4 +462,4 @@ namespace ARMeilleure.CodeGen.Arm64
             return _intrinTable[(int)intrin];
         }
     }
-}
+}

src/ARMeilleure/CodeGen/Arm64/IntrinsicType.cs

@@ -23,6 +23,10 @@ namespace ARMeilleure.CodeGen.Arm64
         ScalarTernaryShlRd,
         ScalarTernaryShrRd,
 
+        Vector128Unary,
+        Vector128Binary,
+        Vector128BinaryRd,
+
         VectorUnary,
         VectorUnaryBitwise,
         VectorUnaryByElem,
@@ -50,10 +54,7 @@ namespace ARMeilleure.CodeGen.Arm64
         VectorTernaryShlRd,
         VectorTernaryShrRd,
 
-        Vector128Unary,
-        Vector128Binary,
-
         GetRegister,
-        SetRegister
+        SetRegister,
     }
-}
+}

src/ARMeilleure/CodeGen/Arm64/PreAllocator.cs

@@ -1,4 +1,3 @@
-using ARMeilleure.CodeGen.RegisterAllocators;
 using ARMeilleure.IntermediateRepresentation;
 using ARMeilleure.Translation;
 using System;
@@ -31,7 +30,7 @@ namespace ARMeilleure.CodeGen.Arm64
             }
         }
 
-        public static void RunPass(CompilerContext cctx, StackAllocator stackAlloc, out int maxCallArgs)
+        public static void RunPass(CompilerContext cctx, out int maxCallArgs)
         {
             maxCallArgs = -1;
 
@@ -41,7 +40,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
             for (BasicBlock block = cctx.Cfg.Blocks.First; block != null; block = block.ListNext)
             {
-                ConstantDict constants = new ConstantDict();
+                ConstantDict constants = new();
 
                 Operation nextNode;
 
@@ -92,7 +91,7 @@ namespace ARMeilleure.CodeGen.Arm64
                             InsertReturnCopy(block.Operations, node);
                             break;
                         case Instruction.Tailcall:
-                            InsertTailcallCopies(constants, block.Operations, stackAlloc, node, node);
+                            InsertTailcallCopies(constants, block.Operations, node, node);
                             break;
                     }
                 }
@@ -138,10 +137,7 @@ namespace ARMeilleure.CodeGen.Arm64
                     {
                         src2 = node.GetSource(1);
 
-                        Operand temp = src1;
-
-                        src1 = src2;
-                        src2 = temp;
+                        (src2, src1) = (src1, src2);
 
                         node.SetSource(0, src1);
                         node.SetSource(1, src2);
@@ -265,9 +261,9 @@ namespace ARMeilleure.CodeGen.Arm64
 
             Operand dest = operation.Destination;
 
-            List<Operand> sources = new List<Operand>
+            List<Operand> sources = new()
             {
-                operation.GetSource(0)
+                operation.GetSource(0),
             };
 
             int argsCount = operation.SourcesCount - 1;
@@ -302,10 +298,10 @@ namespace ARMeilleure.CodeGen.Arm64
                 if (source.Type == OperandType.V128 && passOnReg)
                 {
                     // V128 is a struct, we pass each half on a GPR if possible.
-                    Operand argReg  = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64);
+                    Operand argReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64);
                     Operand argReg2 = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64);
 
-                    nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg,  source, Const(0)));
+                    nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg, source, Const(0)));
                     nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg2, source, Const(1)));
 
                     continue;
@@ -339,7 +335,7 @@ namespace ARMeilleure.CodeGen.Arm64
             {
                 if (dest.Type == OperandType.V128)
                 {
-                    Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(),     OperandType.I64);
+                    Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(), OperandType.I64);
                     Operand retHReg = Gpr(CallingConvention.GetIntReturnRegisterHigh(), OperandType.I64);
 
                     node = nodes.AddAfter(node, Operation(Instruction.VectorCreateScalar, dest, retLReg));
@@ -364,16 +360,14 @@ namespace ARMeilleure.CodeGen.Arm64
             operation.SetSources(sources.ToArray());
         }
 
-        private static void InsertTailcallCopies(
-            ConstantDict constants,
+        private static void InsertTailcallCopies(ConstantDict constants,
             IntrusiveList<Operation> nodes,
-            StackAllocator stackAlloc,
             Operation node,
             Operation operation)
         {
-            List<Operand> sources = new List<Operand>
+            List<Operand> sources = new()
             {
-                operation.GetSource(0)
+                operation.GetSource(0),
             };
 
             int argsCount = operation.SourcesCount - 1;
@@ -403,7 +397,7 @@ namespace ARMeilleure.CodeGen.Arm64
                 if (source.Type == OperandType.V128 && passOnReg)
                 {
                     // V128 is a struct, we pass each half on a GPR if possible.
-                    Operand argReg  = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64);
+                    Operand argReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64);
                     Operand argReg2 = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64);
 
                     nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg, source, Const(0)));
@@ -519,7 +513,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
             if (source.Type == OperandType.V128)
             {
-                Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(),     OperandType.I64);
+                Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(), OperandType.I64);
                 Operand retHReg = Gpr(CallingConvention.GetIntReturnRegisterHigh(), OperandType.I64);
 
                 nodes.AddBefore(node, Operation(Instruction.VectorExtract, retLReg, source, Const(0)));
@@ -746,6 +740,7 @@ namespace ARMeilleure.CodeGen.Arm64
                    info.Type == IntrinsicType.ScalarTernaryFPRdByElem ||
                    info.Type == IntrinsicType.ScalarTernaryShlRd ||
                    info.Type == IntrinsicType.ScalarTernaryShrRd ||
+                   info.Type == IntrinsicType.Vector128BinaryRd ||
                    info.Type == IntrinsicType.VectorBinaryRd ||
                    info.Type == IntrinsicType.VectorInsertByElem ||
                    info.Type == IntrinsicType.VectorTernaryRd ||

src/ARMeilleure/CodeGen/CompiledFunction.cs

@@ -35,9 +35,9 @@ namespace ARMeilleure.CodeGen
         /// <param name="relocInfo">Relocation info</param>
         internal CompiledFunction(byte[] code, UnwindInfo unwindInfo, RelocInfo relocInfo)
         {
-            Code       = code;
+            Code = code;
             UnwindInfo = unwindInfo;
-            RelocInfo  = relocInfo;
+            RelocInfo = relocInfo;
         }
 
         /// <summary>
@@ -65,4 +65,4 @@ namespace ARMeilleure.CodeGen
             return Marshal.GetDelegateForFunctionPointer<T>(codePointer);
         }
     }
-}
+}

src/ARMeilleure/CodeGen/Linking/RelocEntry.cs

@@ -35,4 +35,4 @@ namespace ARMeilleure.CodeGen.Linking
             return $"({nameof(Position)} = {Position}, {nameof(Symbol)} = {Symbol})";
         }
     }
-}
+}

src/ARMeilleure/CodeGen/Linking/RelocInfo.cs

@@ -29,4 +29,4 @@ namespace ARMeilleure.CodeGen.Linking
             _entries = entries;
         }
     }
-}
+}

src/ARMeilleure/CodeGen/Linking/SymbolType.cs

@@ -23,6 +23,6 @@
         /// <summary>
         /// Refers to a special symbol which is handled by <see cref="Translation.PTC.Ptc.PatchCode"/>.
         /// </summary>
-        Special
+        Special,
     }
 }

src/ARMeilleure/CodeGen/Optimizations/ConstantFolding.cs

@@ -164,7 +164,7 @@ namespace ARMeilleure.CodeGen.Optimizations
                     }
                     break;
 
-                 case Instruction.Multiply:
+                case Instruction.Multiply:
                     if (type == OperandType.I32)
                     {
                         EvaluateBinaryI32(operation, (x, y) => x * y);
@@ -343,4 +343,4 @@ namespace ARMeilleure.CodeGen.Optimizations
             operation.TurnIntoCopy(Const(op(x, y)));
         }
     }
-}
+}

src/ARMeilleure/CodeGen/Optimizations/Optimizer.cs

@@ -182,7 +182,7 @@ namespace ARMeilleure.CodeGen.Optimizations
         private static void PropagateCopy(ref Span<Operation> buffer, Operation copyOp)
         {
             // Propagate copy source operand to all uses of the destination operand.
-            Operand dest   = copyOp.Destination;
+            Operand dest = copyOp.Destination;
             Operand source = copyOp.GetSource(0);
 
             Span<Operation> uses = dest.GetUses(ref buffer);
@@ -249,4 +249,4 @@ namespace ARMeilleure.CodeGen.Optimizations
             return operation.Destination.Type == operation.GetSource(0).Type;
         }
     }
-}
+}

src/ARMeilleure/CodeGen/Optimizations/Simplification.cs

@@ -171,13 +171,12 @@ namespace ARMeilleure.CodeGen.Optimizations
 
         private static ulong AllOnes(OperandType type)
         {
-            switch (type)
+            return type switch
             {
-                case OperandType.I32: return ~0U;
-                case OperandType.I64: return ~0UL;
-            }
-
-            throw new ArgumentException("Invalid operand type \"" + type + "\".");
+                OperandType.I32 => ~0U,
+                OperandType.I64 => ~0UL,
+                _ => throw new ArgumentException("Invalid operand type \"" + type + "\"."),
+            };
         }
     }
-}
+}

src/ARMeilleure/CodeGen/RegisterAllocators/AllocationResult.cs

@@ -4,7 +4,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
     {
         public int IntUsedRegisters { get; }
         public int VecUsedRegisters { get; }
-        public int SpillRegionSize  { get; }
+        public int SpillRegionSize { get; }
 
         public AllocationResult(
             int intUsedRegisters,
@@ -13,7 +13,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
         {
             IntUsedRegisters = intUsedRegisters;
             VecUsedRegisters = vecUsedRegisters;
-            SpillRegionSize  = spillRegionSize;
+            SpillRegionSize = spillRegionSize;
         }
     }
-}
+}

src/ARMeilleure/CodeGen/RegisterAllocators/CopyResolver.cs

@@ -1,7 +1,6 @@
 using ARMeilleure.IntermediateRepresentation;
 using System;
 using System.Collections.Generic;
-
 using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
 using static ARMeilleure.IntermediateRepresentation.Operation.Factory;
 
@@ -13,16 +12,16 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
         {
             private readonly struct Copy
             {
-                public Register Dest   { get; }
+                public Register Dest { get; }
                 public Register Source { get; }
 
                 public OperandType Type { get; }
 
                 public Copy(Register dest, Register source, OperandType type)
                 {
-                    Dest   = dest;
+                    Dest = dest;
                     Source = source;
-                    Type   = type;
+                    Type = type;
                 }
             }
 
@@ -42,19 +41,19 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
 
             public void Sequence(List<Operation> sequence)
             {
-                Dictionary<Register, Register> locations = new Dictionary<Register, Register>();
-                Dictionary<Register, Register> sources   = new Dictionary<Register, Register>();
+                Dictionary<Register, Register> locations = new();
+                Dictionary<Register, Register> sources = new();
 
-                Dictionary<Register, OperandType> types = new Dictionary<Register, OperandType>();
+                Dictionary<Register, OperandType> types = new();
 
-                Queue<Register> pendingQueue = new Queue<Register>();
-                Queue<Register> readyQueue   = new Queue<Register>();
+                Queue<Register> pendingQueue = new();
+                Queue<Register> readyQueue = new();
 
                 foreach (Copy copy in _copies)
                 {
                     locations[copy.Source] = copy.Source;
-                    sources[copy.Dest]     = copy.Source;
-                    types[copy.Dest]       = copy.Type;
+                    sources[copy.Dest] = copy.Source;
+                    types[copy.Dest] = copy.Type;
 
                     pendingQueue.Enqueue(copy.Dest);
                 }
@@ -91,7 +90,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
                         }
                     }
 
-                    copyDest   = current;
+                    copyDest = current;
                     origSource = sources[copyDest];
                     copySource = locations[origSource];
 
@@ -186,10 +185,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
 
         private void AddSplitFill(LiveInterval left, LiveInterval right, OperandType type)
         {
-            if (_fillQueue == null)
-            {
-                _fillQueue = new Queue<Operation>();
-            }
+            _fillQueue ??= new Queue<Operation>();
 
             Operand register = GetRegister(right.Register, type);
             Operand offset = Const(left.SpillOffset);
@@ -201,10 +197,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
 
         private void AddSplitSpill(LiveInterval left, LiveInterval right, OperandType type)
         {
-            if (_spillQueue == null)
-            {
-                _spillQueue = new Queue<Operation>();
-            }
+            _spillQueue ??= new Queue<Operation>();
 
             Operand offset = Const(right.SpillOffset);
             Operand register = GetRegister(left.Register, type);
@@ -216,10 +209,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
 
         private void AddSplitCopy(LiveInterval left, LiveInterval right, OperandType type)
         {
-            if (_parallelCopy == null)
-            {
-                _parallelCopy = new ParallelCopy();
-            }
+            _parallelCopy ??= new ParallelCopy();
 
             _parallelCopy.AddCopy(right.Register, left.Register, type);
 
@@ -228,7 +218,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
 
         public Operation[] Sequence()
         {
-            List<Operation> sequence = new List<Operation>();
+            List<Operation> sequence = new();
 
             if (_spillQueue != null)
             {
@@ -256,4 +246,4 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
             return Register(reg.Index, reg.Type, type);
         }
     }
-}
+}

src/ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs

@@ -20,7 +20,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
 
             public BlockInfo(bool hasCall, int intFixedRegisters, int vecFixedRegisters)
             {
-                HasCall           = hasCall;
+                HasCall = hasCall;
                 IntFixedRegisters = intFixedRegisters;
                 VecFixedRegisters = vecFixedRegisters;
             }
@@ -39,7 +39,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
             private int _first;
             private int _last;
 
-            public bool IsBlockLocal => _first == _last;
+            public readonly bool IsBlockLocal => _first == _last;
 
             public LocalInfo(OperandType type, int uses, int blkIndex)
             {
@@ -53,7 +53,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
                 SpillOffset = default;
 
                 _first = -1;
-                _last  = -1;
+                _last = -1;
 
                 SetBlockIndex(blkIndex);
             }
@@ -348,17 +348,17 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
                                 if (dest.Type.IsInteger())
                                 {
                                     intLocalFreeRegisters &= ~(1 << selectedReg);
-                                    intUsedRegisters      |=   1 << selectedReg;
+                                    intUsedRegisters |= 1 << selectedReg;
                                 }
                                 else
                                 {
                                     vecLocalFreeRegisters &= ~(1 << selectedReg);
-                                    vecUsedRegisters      |=   1 << selectedReg;
+                                    vecUsedRegisters |= 1 << selectedReg;
                                 }
                             }
                             else
                             {
-                                info.Register    = default;
+                                info.Register = default;
                                 info.SpillOffset = Const(stackAlloc.Allocate(dest.Type.GetSizeInBytes()));
                             }
                         }
@@ -382,7 +382,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
                                     : GetSpillTemp(dest, vecSpillTempRegisters, ref vecLocalAsg);
 
                                 info.Sequence = sequence;
-                                info.Temp     = temp;
+                                info.Temp = temp;
                             }
 
                             dest = temp;
@@ -408,7 +408,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
         private static int SelectSpillTemps(int mask0, int mask1)
         {
             int selection = 0;
-            int count     = 0;
+            int count = 0;
 
             while (count < MaxIROperands && mask0 != 0)
             {
@@ -451,4 +451,4 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
             return local.AssignmentsCount + local.UsesCount;
         }
     }
-}
+}

src/ARMeilleure/CodeGen/RegisterAllocators/IRegisterAllocator.cs

@@ -9,4 +9,4 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
             StackAllocator stackAlloc,
             RegisterMasks regMasks);
     }
-}
+}

src/ARMeilleure/CodeGen/RegisterAllocators/LinearScanAllocator.cs

@@ -14,7 +14,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
     // http://www.christianwimmer.at/Publications/Wimmer04a/Wimmer04a.pdf
     class LinearScanAllocator : IRegisterAllocator
     {
-        private const int InstructionGap     = 2;
+        private const int InstructionGap = 2;
         private const int InstructionGapMask = InstructionGap - 1;
 
         private HashSet<int> _blockEdges;
@@ -33,7 +33,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
 
             public StackAllocator StackAlloc { get; }
 
-            public BitMap Active   { get; }
+            public BitMap Active { get; }
             public BitMap Inactive { get; }
 
             public int IntUsedRegisters { get; set; }
@@ -47,9 +47,9 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
             public AllocationContext(StackAllocator stackAlloc, RegisterMasks masks, int intervalsCount)
             {
                 StackAlloc = stackAlloc;
-                Masks      = masks;
+                Masks = masks;
 
-                Active   = new BitMap(Allocators.Default, intervalsCount);
+                Active = new BitMap(Allocators.Default, intervalsCount);
                 Inactive = new BitMap(Allocators.Default, intervalsCount);
 
                 PopulateFreePositions(RegisterType.Integer, out _intFreePositions, out _intFreePositionsCount);
@@ -443,7 +443,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
 
                 if (highest < current)
                 {
-                    highest  = current;
+                    highest = current;
                     selected = index;
 
                     if (current == int.MaxValue)
@@ -485,9 +485,9 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
 
         private void SplitAndSpillOverlappingInterval(
             AllocationContext context,
-            LiveInterval      current,
-            LiveInterval      interval,
-            int               registersCount)
+            LiveInterval current,
+            LiveInterval interval,
+            int registersCount)
         {
             // If there's a next use after the start of the current interval,
             // we need to split the spilled interval twice, and re-insert it
@@ -530,8 +530,8 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
         private void InsertInterval(LiveInterval interval, int registersCount)
         {
             Debug.Assert(interval.UsesCount != 0, "Trying to insert a interval without uses.");
-            Debug.Assert(!interval.IsEmpty,       "Trying to insert a empty interval.");
-            Debug.Assert(!interval.IsSpilled,     "Trying to insert a spilled interval.");
+            Debug.Assert(!interval.IsEmpty, "Trying to insert a empty interval.");
+            Debug.Assert(!interval.IsSpilled, "Trying to insert a spilled interval.");
 
             int startIndex = registersCount * 2;
 
@@ -545,9 +545,9 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
             _intervals.Insert(insertIndex, interval);
         }
 
-        private void Spill(AllocationContext context, LiveInterval interval)
+        private static void Spill(AllocationContext context, LiveInterval interval)
         {
-            Debug.Assert(!interval.IsFixed,       "Trying to spill a fixed interval.");
+            Debug.Assert(!interval.IsFixed, "Trying to spill a fixed interval.");
             Debug.Assert(interval.UsesCount == 0, "Trying to spill a interval with uses.");
 
             // We first check if any of the siblings were spilled, if so we can reuse
@@ -561,7 +561,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
 
         private void InsertSplitCopies()
         {
-            Dictionary<int, CopyResolver> copyResolvers = new Dictionary<int, CopyResolver>();
+            Dictionary<int, CopyResolver> copyResolvers = new();
 
             CopyResolver GetCopyResolver(int position)
             {
@@ -668,18 +668,15 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
                             continue;
                         }
 
-                        int lEnd   = _blockRanges[block.Index].End - 1;
+                        int lEnd = _blockRanges[block.Index].End - 1;
                         int rStart = _blockRanges[succIndex].Start;
 
-                        LiveInterval left  = interval.GetSplitChild(lEnd);
+                        LiveInterval left = interval.GetSplitChild(lEnd);
                         LiveInterval right = interval.GetSplitChild(rStart);
 
                         if (left != default && right != default && left != right)
                         {
-                            if (copyResolver == null)
-                            {
-                                copyResolver = new CopyResolver();
-                            }
+                            copyResolver ??= new CopyResolver();
 
                             copyResolver.AddSplit(left, right);
                         }
@@ -856,14 +853,14 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
 
             int mapSize = _intervals.Count;
 
-            BitMap[] blkLiveGen  = new BitMap[cfg.Blocks.Count];
+            BitMap[] blkLiveGen = new BitMap[cfg.Blocks.Count];
             BitMap[] blkLiveKill = new BitMap[cfg.Blocks.Count];
 
             // Compute local live sets.
             for (BasicBlock block = cfg.Blocks.First; block != null; block = block.ListNext)
             {
-                BitMap liveGen  = new BitMap(Allocators.Default, mapSize);
-                BitMap liveKill = new BitMap(Allocators.Default, mapSize);
+                BitMap liveGen = new(Allocators.Default, mapSize);
+                BitMap liveKill = new(Allocators.Default, mapSize);
 
                 for (Operation node = block.Operations.First; node != default; node = node.ListNext)
                 {
@@ -910,17 +907,17 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
                     }
                 }
 
-                blkLiveGen [block.Index] = liveGen;
+                blkLiveGen[block.Index] = liveGen;
                 blkLiveKill[block.Index] = liveKill;
             }
 
             // Compute global live sets.
-            BitMap[] blkLiveIn  = new BitMap[cfg.Blocks.Count];
+            BitMap[] blkLiveIn = new BitMap[cfg.Blocks.Count];
             BitMap[] blkLiveOut = new BitMap[cfg.Blocks.Count];
 
             for (int index = 0; index < cfg.Blocks.Count; index++)
             {
-                blkLiveIn [index] = new BitMap(Allocators.Default, mapSize);
+                blkLiveIn[index] = new BitMap(Allocators.Default, mapSize);
                 blkLiveOut[index] = new BitMap(Allocators.Default, mapSize);
             }
 
@@ -945,9 +942,9 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
 
                     BitMap liveIn = blkLiveIn[block.Index];
 
-                    liveIn.Set  (liveOut);
+                    liveIn.Set(liveOut);
                     liveIn.Clear(blkLiveKill[block.Index]);
-                    liveIn.Set  (blkLiveGen [block.Index]);
+                    liveIn.Set(blkLiveGen[block.Index]);
                 }
             }
             while (modified);
@@ -969,7 +966,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
                 int instCount = Math.Max(block.Operations.Count, 1);
 
                 int blockStart = operationPos - instCount * InstructionGap;
-                int blockEnd   = operationPos;
+                int blockEnd = operationPos;
 
                 _blockRanges[block.Index] = new LiveRange(blockStart, blockEnd);
 
@@ -1061,7 +1058,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
             {
                 int regIndex = BitOperations.TrailingZeroCount(mask);
 
-                Register callerSavedReg = new Register(regIndex, regType);
+                Register callerSavedReg = new(regIndex, regType);
 
                 LiveInterval interval = _intervals[GetRegisterId(callerSavedReg)];
 
@@ -1098,4 +1095,4 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
                    kind == OperandKind.Register;
         }
     }
-}
+}

src/ARMeilleure/CodeGen/RegisterAllocators/LiveInterval.cs

@@ -240,8 +240,10 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
 
         public LiveInterval Split(int position)
         {
-            LiveInterval result = new(Local, Parent);
-            result.End = End;
+            LiveInterval result = new(Local, Parent)
+            {
+                End = End,
+            };
 
             LiveRange prev = PrevRange;
             LiveRange curr = CurrRange;
@@ -393,4 +395,4 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
             return string.Join(", ", GetRanges());
         }
     }
-}
+}

src/ARMeilleure/CodeGen/RegisterAllocators/LiveIntervalList.cs

@@ -8,8 +8,8 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
         private int _count;
         private int _capacity;
 
-        public int Count => _count;
-        public Span<LiveInterval> Span => new(_items, _count);
+        public readonly int Count => _count;
+        public readonly Span<LiveInterval> Span => new(_items, _count);
 
         public void Add(LiveInterval interval)
         {
@@ -37,4 +37,4 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
             _count++;
         }
     }
-}
+}

src/ARMeilleure/CodeGen/RegisterAllocators/LiveRange.cs

@@ -71,4 +71,4 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
             return $"[{Start}, {End})";
         }
     }
-}
+}

src/ARMeilleure/CodeGen/RegisterAllocators/RegisterMasks.cs

@@ -5,8 +5,8 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
 {
     readonly struct RegisterMasks
     {
-        public int IntAvailableRegisters   { get; }
-        public int VecAvailableRegisters   { get; }
+        public int IntAvailableRegisters { get; }
+        public int VecAvailableRegisters { get; }
         public int IntCallerSavedRegisters { get; }
         public int VecCallerSavedRegisters { get; }
         public int IntCalleeSavedRegisters { get; }
@@ -22,13 +22,13 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
             int vecCalleeSavedRegisters,
             int registersCount)
         {
-            IntAvailableRegisters   = intAvailableRegisters;
-            VecAvailableRegisters   = vecAvailableRegisters;
+            IntAvailableRegisters = intAvailableRegisters;
+            VecAvailableRegisters = vecAvailableRegisters;
             IntCallerSavedRegisters = intCallerSavedRegisters;
             VecCallerSavedRegisters = vecCallerSavedRegisters;
             IntCalleeSavedRegisters = intCalleeSavedRegisters;
             VecCalleeSavedRegisters = vecCalleeSavedRegisters;
-            RegistersCount          = registersCount;
+            RegistersCount = registersCount;
         }
 
         public int GetAvailableRegisters(RegisterType type)
@@ -47,4 +47,4 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
             }
         }
     }
-}
+}

src/ARMeilleure/CodeGen/RegisterAllocators/StackAllocator.cs

@@ -22,4 +22,4 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
             return offset;
         }
     }
-}
+}

src/ARMeilleure/CodeGen/RegisterAllocators/UseList.cs

@@ -6,15 +6,15 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
     {
         private int* _items;
         private int _capacity;
-        private int _count;
 
-        public int Count => _count;
-        public int FirstUse => _count > 0 ? _items[_count - 1] : LiveInterval.NotFound;
-        public Span<int> Span => new(_items, _count);
+        public int Count { get; private set; }
+
+        public readonly int FirstUse => Count > 0 ? _items[Count - 1] : LiveInterval.NotFound;
+        public readonly Span<int> Span => new(_items, Count);
 
         public void Add(int position)
         {
-            if (_count + 1 > _capacity)
+            if (Count + 1 > _capacity)
             {
                 var oldSpan = Span;
 
@@ -28,7 +28,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
 
             // Use positions are usually inserted in descending order, so inserting in descending order is faster,
             // since the number of half exchanges is reduced.
-            int i = _count - 1;
+            int i = Count - 1;
 
             while (i >= 0 && _items[i] < position)
             {
@@ -36,19 +36,19 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
             }
 
             _items[i + 1] = position;
-            _count++;
+            Count++;
         }
 
-        public int NextUse(int position)
+        public readonly int NextUse(int position)
         {
             int index = NextUseIndex(position);
 
             return index != LiveInterval.NotFound ? _items[index] : LiveInterval.NotFound;
         }
 
-        public int NextUseIndex(int position)
+        public readonly int NextUseIndex(int position)
         {
-            int i = _count - 1;
+            int i = Count - 1;
 
             if (i == -1 || position > _items[0])
             {
@@ -69,16 +69,18 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
 
             // Since the list is in descending order, the new split list takes the front of the list and the current
             // list takes the back of the list.
-            UseList result = new();
-            result._count = index + 1;
-            result._capacity = result._count;
+            UseList result = new()
+            {
+                Count = index + 1,
+            };
+            result._capacity = result.Count;
             result._items = _items;
 
-            _count = _count - result._count;
-            _capacity = _count;
-            _items = _items + result._count;
+            Count -= result.Count;
+            _capacity = Count;
+            _items += result.Count;
 
             return result;
         }
     }
-}
+}

src/ARMeilleure/CodeGen/Unwinding/UnwindInfo.cs

@@ -13,4 +13,4 @@ namespace ARMeilleure.CodeGen.Unwinding
             PrologSize = prologSize;
         }
     }
-}
+}

src/ARMeilleure/CodeGen/Unwinding/UnwindPseudoOp.cs

@@ -2,10 +2,10 @@ namespace ARMeilleure.CodeGen.Unwinding
 {
     enum UnwindPseudoOp
     {
-        PushReg    = 0,
-        SetFrame   = 1,
+        PushReg = 0,
+        SetFrame = 1,
         AllocStack = 2,
-        SaveReg    = 3,
-        SaveXmm128 = 4
+        SaveReg = 3,
+        SaveXmm128 = 4,
     }
-}
+}

src/ARMeilleure/CodeGen/Unwinding/UnwindPushEntry.cs

@@ -17,4 +17,4 @@ namespace ARMeilleure.CodeGen.Unwinding
             StackOffsetOrAllocSize = stackOffsetOrAllocSize;
         }
     }
-}
+}

src/ARMeilleure/CodeGen/X86/Assembler.cs

@@ -15,7 +15,7 @@ namespace ARMeilleure.CodeGen.X86
 
         private const int OpModRMBits = 24;
 
-        private const byte RexPrefix  = 0x40;
+        private const byte RexPrefix = 0x40;
         private const byte RexWPrefix = 0x48;
         private const byte LockPrefix = 0xf0;
 
@@ -799,7 +799,7 @@ namespace ARMeilleure.CodeGen.X86
                             {
                                 JumpIndex = _jumps.Count - 1,
                                 Position = (int)_stream.Position,
-                                Symbol = source.Symbol
+                                Symbol = source.Symbol,
                             });
                         }
 
@@ -959,7 +959,7 @@ namespace ARMeilleure.CodeGen.X86
                 }
             }
 
-            bool needsSibByte      = false;
+            bool needsSibByte = false;
             bool needsDisplacement = false;
 
             int sib = 0;
@@ -971,7 +971,7 @@ namespace ARMeilleure.CodeGen.X86
 
                 X86Register baseRegLow = (X86Register)(baseReg.Index & 0b111);
 
-                needsSibByte      = memOp.Index != default  || baseRegLow == X86Register.Rsp;
+                needsSibByte = memOp.Index != default || baseRegLow == X86Register.Rsp;
                 needsDisplacement = memOp.Displacement != 0 || baseRegLow == X86Register.Rbp;
 
                 if (needsDisplacement)
@@ -1049,7 +1049,7 @@ namespace ARMeilleure.CodeGen.X86
                     InstructionFlags.Prefix66 => 1,
                     InstructionFlags.PrefixF3 => 2,
                     InstructionFlags.PrefixF2 => 3,
-                    _ => 0
+                    _ => 0,
                 };
 
                 if (src1 != default)
@@ -1081,11 +1081,19 @@ namespace ARMeilleure.CodeGen.X86
 
                     switch (opCodeHigh)
                     {
-                        case 0xf:   vexByte1 |= 1; break;
-                        case 0xf38: vexByte1 |= 2; break;
-                        case 0xf3a: vexByte1 |= 3; break;
+                        case 0xf:
+                            vexByte1 |= 1;
+                            break;
+                        case 0xf38:
+                            vexByte1 |= 2;
+                            break;
+                        case 0xf3a:
+                            vexByte1 |= 3;
+                            break;
 
-                        default: Debug.Assert(false, $"Failed to VEX encode opcode 0x{opCode:X}."); break;
+                        default:
+                            Debug.Assert(false, $"Failed to VEX encode opcode 0x{opCode:X}.");
+                            break;
                     }
 
                     vexByte2 |= (rexPrefix & 8) << 4;
@@ -1191,11 +1199,19 @@ namespace ARMeilleure.CodeGen.X86
 
             switch ((ushort)(opCode >> 8))
             {
-                case 0xf00: mm = 0b01; break;
-                case 0xf38: mm = 0b10; break;
-                case 0xf3a: mm = 0b11; break;
+                case 0xf00:
+                    mm = 0b01;
+                    break;
+                case 0xf38:
+                    mm = 0b10;
+                    break;
+                case 0xf3a:
+                    mm = 0b11;
+                    break;
 
-                default: Debug.Fail($"Failed to EVEX encode opcode 0x{opCode:X}."); break;
+                default:
+                    Debug.Fail($"Failed to EVEX encode opcode 0x{opCode:X}.");
+                    break;
             }
 
             WriteByte(
@@ -1217,7 +1233,7 @@ namespace ARMeilleure.CodeGen.X86
                 InstructionFlags.Prefix66 => 0b01,
                 InstructionFlags.PrefixF3 => 0b10,
                 InstructionFlags.PrefixF2 => 0b11,
-                _ => 0
+                _ => 0,
             };
             WriteByte(
                 (byte)(
@@ -1233,11 +1249,19 @@ namespace ARMeilleure.CodeGen.X86
             byte ll = 0b00;
             switch (registerWidth)
             {
-                case 128: ll = 0b00; break;
-                case 256: ll = 0b01; break;
-                case 512: ll = 0b10; break;
+                case 128:
+                    ll = 0b00;
+                    break;
+                case 256:
+                    ll = 0b01;
+                    break;
+                case 512:
+                    ll = 0b10;
+                    break;
 
-                default: Debug.Fail($"Invalid EVEX vector register width {registerWidth}."); break;
+                default:
+                    Debug.Fail($"Invalid EVEX vector register width {registerWidth}.");
+                    break;
             }
             // Embedded broadcast in the case of a memory operand
             bool bcast = broadcast;
@@ -1315,10 +1339,7 @@ namespace ARMeilleure.CodeGen.X86
                     ref Jump jump = ref jumps[i];
 
                     // If jump target not resolved yet, resolve it.
-                    if (jump.JumpTarget == null)
-                    {
-                        jump.JumpTarget = _labels[jump.JumpLabel];
-                    }
+                    jump.JumpTarget ??= _labels[jump.JumpLabel];
 
                     long jumpTarget = jump.JumpTarget.Value;
                     long offset = jumpTarget - jump.JumpPosition;
@@ -1556,4 +1577,4 @@ namespace ARMeilleure.CodeGen.X86
             _stream.WriteByte((byte)(value >> 56));
         }
     }
-}
+}

src/ARMeilleure/CodeGen/X86/AssemblerTable.cs

@@ -1,4 +1,5 @@
 using System;
+using System.Diagnostics.CodeAnalysis;
 
 namespace ARMeilleure.CodeGen.X86
 {
@@ -12,47 +13,48 @@ namespace ARMeilleure.CodeGen.X86
         private const int BadOp = 0;
 
         [Flags]
+        [SuppressMessage("Design", "CA1069: Enums values should not be duplicated")]
         private enum InstructionFlags
         {
-            None     = 0,
-            RegOnly  = 1 << 0,
-            Reg8Src  = 1 << 1,
+            None = 0,
+            RegOnly = 1 << 0,
+            Reg8Src = 1 << 1,
             Reg8Dest = 1 << 2,
-            RexW     = 1 << 3,
-            Vex      = 1 << 4,
-            Evex     = 1 << 5,
+            RexW = 1 << 3,
+            Vex = 1 << 4,
+            Evex = 1 << 5,
 
-            PrefixBit  = 16,
+            PrefixBit = 16,
             PrefixMask = 7 << PrefixBit,
-            Prefix66   = 1 << PrefixBit,
-            PrefixF3   = 2 << PrefixBit,
-            PrefixF2   = 4 << PrefixBit
+            Prefix66 = 1 << PrefixBit,
+            PrefixF3 = 2 << PrefixBit,
+            PrefixF2 = 4 << PrefixBit,
         }
 
         private readonly struct InstructionInfo
         {
-            public int OpRMR     { get; }
-            public int OpRMImm8  { get; }
+            public int OpRMR { get; }
+            public int OpRMImm8 { get; }
             public int OpRMImm32 { get; }
-            public int OpRImm64  { get; }
-            public int OpRRM     { get; }
+            public int OpRImm64 { get; }
+            public int OpRRM { get; }
 
             public InstructionFlags Flags { get; }
 
             public InstructionInfo(
-                int              opRMR,
-                int              opRMImm8,
-                int              opRMImm32,
-                int              opRImm64,
-                int              opRRM,
+                int opRMR,
+                int opRMImm8,
+                int opRMImm32,
+                int opRImm64,
+                int opRRM,
                 InstructionFlags flags)
             {
-                OpRMR     = opRMR;
-                OpRMImm8  = opRMImm8;
+                OpRMR = opRMR;
+                OpRMImm8 = opRMImm8;
                 OpRMImm32 = opRMImm32;
-                OpRImm64  = opRImm64;
-                OpRRM     = opRRM;
-                Flags     = flags;
+                OpRImm64 = opRImm64;
+                OpRRM = opRRM;
+                Flags = flags;
             }
         }
 
@@ -62,6 +64,7 @@ namespace ARMeilleure.CodeGen.X86
         {
             _instTable = new InstructionInfo[(int)X86Instruction.Count];
 
+#pragma warning disable IDE0055 // Disable formatting
             //  Name                                             RM/R        RM/I8       RM/I32      R/I64       R/RM        Flags
             Add(X86Instruction.Add,           new InstructionInfo(0x00000001, 0x00000083, 0x00000081, BadOp,      0x00000003, InstructionFlags.None));
             Add(X86Instruction.Addpd,         new InstructionInfo(BadOp,      BadOp,      BadOp,      BadOp,      0x00000f58, InstructionFlags.Vex | InstructionFlags.Prefix66));
@@ -285,6 +288,7 @@ namespace ARMeilleure.CodeGen.X86
             Add(X86Instruction.Xor,           new InstructionInfo(0x00000031, 0x06000083, 0x06000081, BadOp,      0x00000033, InstructionFlags.None));
             Add(X86Instruction.Xorpd,         new InstructionInfo(BadOp,      BadOp,      BadOp,      BadOp,      0x00000f57, InstructionFlags.Vex | InstructionFlags.Prefix66));
             Add(X86Instruction.Xorps,         new InstructionInfo(BadOp,      BadOp,      BadOp,      BadOp,      0x00000f57, InstructionFlags.Vex));
+#pragma warning restore IDE0055
 
             static void Add(X86Instruction inst, in InstructionInfo info)
             {

src/ARMeilleure/CodeGen/X86/CallConvName.cs

@@ -3,6 +3,6 @@ namespace ARMeilleure.CodeGen.X86
     enum CallConvName
     {
         SystemV,
-        Windows
+        Windows,
     }
-}
+}

src/ARMeilleure/CodeGen/X86/CallingConvention.cs

@@ -20,6 +20,7 @@ namespace ARMeilleure.CodeGen.X86
         {
             if (GetCurrentCallConv() == CallConvName.Windows)
             {
+#pragma warning disable IDE0055 // Disable formatting
                 return (1 << (int)X86Register.Rax) |
                        (1 << (int)X86Register.Rcx) |
                        (1 << (int)X86Register.Rdx) |
@@ -39,6 +40,7 @@ namespace ARMeilleure.CodeGen.X86
                        (1 << (int)X86Register.R9)  |
                        (1 << (int)X86Register.R10) |
                        (1 << (int)X86Register.R11);
+#pragma warning restore IDE0055
             }
         }
 
@@ -90,22 +92,32 @@ namespace ARMeilleure.CodeGen.X86
             {
                 switch (index)
                 {
-                    case 0: return X86Register.Rcx;
-                    case 1: return X86Register.Rdx;
-                    case 2: return X86Register.R8;
-                    case 3: return X86Register.R9;
+                    case 0:
+                        return X86Register.Rcx;
+                    case 1:
+                        return X86Register.Rdx;
+                    case 2:
+                        return X86Register.R8;
+                    case 3:
+                        return X86Register.R9;
                 }
             }
             else /* if (GetCurrentCallConv() == CallConvName.SystemV) */
             {
                 switch (index)
                 {
-                    case 0: return X86Register.Rdi;
-                    case 1: return X86Register.Rsi;
-                    case 2: return X86Register.Rdx;
-                    case 3: return X86Register.Rcx;
-                    case 4: return X86Register.R8;
-                    case 5: return X86Register.R9;
+                    case 0:
+                        return X86Register.Rdi;
+                    case 1:
+                        return X86Register.Rsi;
+                    case 2:
+                        return X86Register.Rdx;
+                    case 3:
+                        return X86Register.Rcx;
+                    case 4:
+                        return X86Register.R8;
+                    case 5:
+                        return X86Register.R9;
                 }
             }
 
@@ -155,4 +167,4 @@ namespace ARMeilleure.CodeGen.X86
                 : CallConvName.SystemV;
         }
     }
-}
+}

src/ARMeilleure/CodeGen/X86/CodeGenContext.cs

@@ -30,7 +30,7 @@ namespace ARMeilleure.CodeGen.X86
             Assembler = new Assembler(_stream, relocatable);
 
             CallArgsRegionSize = GetCallArgsRegionSize(allocResult, maxCallArgs, out int xmmSaveRegionSize);
-            XmmSaveRegionSize  = xmmSaveRegionSize;
+            XmmSaveRegionSize = xmmSaveRegionSize;
         }
 
         private static int GetCallArgsRegionSize(AllocationResult allocResult, int maxCallArgs, out int xmmSaveRegionSize)
@@ -102,4 +102,4 @@ namespace ARMeilleure.CodeGen.X86
             return label;
         }
     }
-}
+}

src/ARMeilleure/CodeGen/X86/CodeGenerator.cs

@@ -17,7 +17,7 @@ namespace ARMeilleure.CodeGen.X86
     static class CodeGenerator
     {
         private const int RegistersCount = 16;
-        private const int PageSize       = 0x1000;
+        private const int PageSize = 0x1000;
         private const int StackGuardSize = 0x2000;
 
         private static readonly Action<CodeGenContext, Operation>[] _instTable;
@@ -26,6 +26,7 @@ namespace ARMeilleure.CodeGen.X86
         {
             _instTable = new Action<CodeGenContext, Operation>[EnumUtils.GetCount(typeof(Instruction))];
 
+#pragma warning disable IDE0055 // Disable formatting
             Add(Instruction.Add,                     GenerateAdd);
             Add(Instruction.BitwiseAnd,              GenerateBitwiseAnd);
             Add(Instruction.BitwiseExclusiveOr,      GenerateBitwiseExclusiveOr);
@@ -85,6 +86,7 @@ namespace ARMeilleure.CodeGen.X86
             Add(Instruction.ZeroExtend16,            GenerateZeroExtend16);
             Add(Instruction.ZeroExtend32,            GenerateZeroExtend32);
             Add(Instruction.ZeroExtend8,             GenerateZeroExtend8);
+#pragma warning restore IDE0055
 
             static void Add(Instruction inst, Action<CodeGenContext, Operation> func)
             {
@@ -203,290 +205,290 @@ namespace ARMeilleure.CodeGen.X86
                 switch (info.Type)
                 {
                     case IntrinsicType.Comis_:
-                    {
-                        Operand dest = operation.Destination;
-                        Operand src1 = operation.GetSource(0);
-                        Operand src2 = operation.GetSource(1);
-
-                        switch (operation.Intrinsic)
-                        {
-                            case Intrinsic.X86Comisdeq:
-                                context.Assembler.Comisd(src1, src2);
-                                context.Assembler.Setcc(dest, X86Condition.Equal);
-                                break;
-
-                            case Intrinsic.X86Comisdge:
-                                context.Assembler.Comisd(src1, src2);
-                                context.Assembler.Setcc(dest, X86Condition.AboveOrEqual);
-                                break;
-
-                            case Intrinsic.X86Comisdlt:
-                                context.Assembler.Comisd(src1, src2);
-                                context.Assembler.Setcc(dest, X86Condition.Below);
-                                break;
-
-                            case Intrinsic.X86Comisseq:
-                                context.Assembler.Comiss(src1, src2);
-                                context.Assembler.Setcc(dest, X86Condition.Equal);
-                                break;
-
-                            case Intrinsic.X86Comissge:
-                                context.Assembler.Comiss(src1, src2);
-                                context.Assembler.Setcc(dest, X86Condition.AboveOrEqual);
-                                break;
-
-                            case Intrinsic.X86Comisslt:
-                                context.Assembler.Comiss(src1, src2);
-                                context.Assembler.Setcc(dest, X86Condition.Below);
-                                break;
-                        }
-
-                        context.Assembler.Movzx8(dest, dest, OperandType.I32);
-
-                        break;
-                    }
-
-                    case IntrinsicType.Mxcsr:
-                    {
-                        Operand offset = operation.GetSource(0);
-
-                        Debug.Assert(offset.Kind == OperandKind.Constant);
-                        Debug.Assert(offset.Type == OperandType.I32);
-
-                        int offs = offset.AsInt32() + context.CallArgsRegionSize;
-
-                        Operand rsp = Register(X86Register.Rsp);
-                        Operand memOp = MemoryOp(OperandType.I32, rsp, default, Multiplier.x1, offs);
-
-                        Debug.Assert(HardwareCapabilities.SupportsSse || HardwareCapabilities.SupportsVexEncoding);
-
-                        if (operation.Intrinsic == Intrinsic.X86Ldmxcsr)
-                        {
-                            Operand bits = operation.GetSource(1);
-                            Debug.Assert(bits.Type == OperandType.I32);
-
-                            context.Assembler.Mov(memOp, bits, OperandType.I32);
-                            context.Assembler.Ldmxcsr(memOp);
-                        }
-                        else if (operation.Intrinsic == Intrinsic.X86Stmxcsr)
                         {
                             Operand dest = operation.Destination;
-                            Debug.Assert(dest.Type == OperandType.I32);
+                            Operand src1 = operation.GetSource(0);
+                            Operand src2 = operation.GetSource(1);
 
-                            context.Assembler.Stmxcsr(memOp);
-                            context.Assembler.Mov(dest, memOp, OperandType.I32);
+                            switch (operation.Intrinsic)
+                            {
+                                case Intrinsic.X86Comisdeq:
+                                    context.Assembler.Comisd(src1, src2);
+                                    context.Assembler.Setcc(dest, X86Condition.Equal);
+                                    break;
+
+                                case Intrinsic.X86Comisdge:
+                                    context.Assembler.Comisd(src1, src2);
+                                    context.Assembler.Setcc(dest, X86Condition.AboveOrEqual);
+                                    break;
+
+                                case Intrinsic.X86Comisdlt:
+                                    context.Assembler.Comisd(src1, src2);
+                                    context.Assembler.Setcc(dest, X86Condition.Below);
+                                    break;
+
+                                case Intrinsic.X86Comisseq:
+                                    context.Assembler.Comiss(src1, src2);
+                                    context.Assembler.Setcc(dest, X86Condition.Equal);
+                                    break;
+
+                                case Intrinsic.X86Comissge:
+                                    context.Assembler.Comiss(src1, src2);
+                                    context.Assembler.Setcc(dest, X86Condition.AboveOrEqual);
+                                    break;
+
+                                case Intrinsic.X86Comisslt:
+                                    context.Assembler.Comiss(src1, src2);
+                                    context.Assembler.Setcc(dest, X86Condition.Below);
+                                    break;
+                            }
+
+                            context.Assembler.Movzx8(dest, dest, OperandType.I32);
+
+                            break;
                         }
 
-                        break;
-                    }
+                    case IntrinsicType.Mxcsr:
+                        {
+                            Operand offset = operation.GetSource(0);
+
+                            Debug.Assert(offset.Kind == OperandKind.Constant);
+                            Debug.Assert(offset.Type == OperandType.I32);
+
+                            int offs = offset.AsInt32() + context.CallArgsRegionSize;
+
+                            Operand rsp = Register(X86Register.Rsp);
+                            Operand memOp = MemoryOp(OperandType.I32, rsp, default, Multiplier.x1, offs);
+
+                            Debug.Assert(HardwareCapabilities.SupportsSse || HardwareCapabilities.SupportsVexEncoding);
+
+                            if (operation.Intrinsic == Intrinsic.X86Ldmxcsr)
+                            {
+                                Operand bits = operation.GetSource(1);
+                                Debug.Assert(bits.Type == OperandType.I32);
+
+                                context.Assembler.Mov(memOp, bits, OperandType.I32);
+                                context.Assembler.Ldmxcsr(memOp);
+                            }
+                            else if (operation.Intrinsic == Intrinsic.X86Stmxcsr)
+                            {
+                                Operand dest = operation.Destination;
+                                Debug.Assert(dest.Type == OperandType.I32);
+
+                                context.Assembler.Stmxcsr(memOp);
+                                context.Assembler.Mov(dest, memOp, OperandType.I32);
+                            }
+
+                            break;
+                        }
 
                     case IntrinsicType.PopCount:
-                    {
-                        Operand dest   = operation.Destination;
-                        Operand source = operation.GetSource(0);
+                        {
+                            Operand dest = operation.Destination;
+                            Operand source = operation.GetSource(0);
 
-                        EnsureSameType(dest, source);
+                            EnsureSameType(dest, source);
 
-                        Debug.Assert(dest.Type.IsInteger());
+                            Debug.Assert(dest.Type.IsInteger());
 
-                        context.Assembler.Popcnt(dest, source, dest.Type);
+                            context.Assembler.Popcnt(dest, source, dest.Type);
 
-                        break;
-                    }
+                            break;
+                        }
 
                     case IntrinsicType.Unary:
-                    {
-                        Operand dest   = operation.Destination;
-                        Operand source = operation.GetSource(0);
+                        {
+                            Operand dest = operation.Destination;
+                            Operand source = operation.GetSource(0);
 
-                        EnsureSameType(dest, source);
+                            EnsureSameType(dest, source);
 
-                        Debug.Assert(!dest.Type.IsInteger());
+                            Debug.Assert(!dest.Type.IsInteger());
 
-                        context.Assembler.WriteInstruction(info.Inst, dest, source);
+                            context.Assembler.WriteInstruction(info.Inst, dest, source);
 
-                        break;
-                    }
+                            break;
+                        }
 
                     case IntrinsicType.UnaryToGpr:
-                    {
-                        Operand dest   = operation.Destination;
-                        Operand source = operation.GetSource(0);
-
-                        Debug.Assert(dest.Type.IsInteger() && !source.Type.IsInteger());
-
-                        if (operation.Intrinsic == Intrinsic.X86Cvtsi2si)
                         {
-                            if (dest.Type == OperandType.I32)
-                            {
-                                context.Assembler.Movd(dest, source); // int _mm_cvtsi128_si32(__m128i a)
-                            }
-                            else /* if (dest.Type == OperandType.I64) */
-                            {
-                                context.Assembler.Movq(dest, source); // __int64 _mm_cvtsi128_si64(__m128i a)
-                            }
-                        }
-                        else
-                        {
-                            context.Assembler.WriteInstruction(info.Inst, dest, source, dest.Type);
-                        }
+                            Operand dest = operation.Destination;
+                            Operand source = operation.GetSource(0);
 
-                        break;
-                    }
+                            Debug.Assert(dest.Type.IsInteger() && !source.Type.IsInteger());
+
+                            if (operation.Intrinsic == Intrinsic.X86Cvtsi2si)
+                            {
+                                if (dest.Type == OperandType.I32)
+                                {
+                                    context.Assembler.Movd(dest, source); // int _mm_cvtsi128_si32(__m128i a)
+                                }
+                                else /* if (dest.Type == OperandType.I64) */
+                                {
+                                    context.Assembler.Movq(dest, source); // __int64 _mm_cvtsi128_si64(__m128i a)
+                                }
+                            }
+                            else
+                            {
+                                context.Assembler.WriteInstruction(info.Inst, dest, source, dest.Type);
+                            }
+
+                            break;
+                        }
 
                     case IntrinsicType.Binary:
-                    {
-                        Operand dest = operation.Destination;
-                        Operand src1 = operation.GetSource(0);
-                        Operand src2 = operation.GetSource(1);
-
-                        EnsureSameType(dest, src1);
-
-                        if (!HardwareCapabilities.SupportsVexEncoding)
                         {
-                            EnsureSameReg(dest, src1);
-                        }
+                            Operand dest = operation.Destination;
+                            Operand src1 = operation.GetSource(0);
+                            Operand src2 = operation.GetSource(1);
 
-                        Debug.Assert(!dest.Type.IsInteger());
-                        Debug.Assert(!src2.Type.IsInteger() || src2.Kind == OperandKind.Constant);
+                            EnsureSameType(dest, src1);
 
-                        context.Assembler.WriteInstruction(info.Inst, dest, src1, src2);
+                            if (!HardwareCapabilities.SupportsVexEncoding)
+                            {
+                                EnsureSameReg(dest, src1);
+                            }
 
-                        break;
-                    }
-
-                    case IntrinsicType.BinaryGpr:
-                    {
-                        Operand dest = operation.Destination;
-                        Operand src1 = operation.GetSource(0);
-                        Operand src2 = operation.GetSource(1);
-
-                        EnsureSameType(dest, src1);
-
-                        if (!HardwareCapabilities.SupportsVexEncoding)
-                        {
-                            EnsureSameReg(dest, src1);
-                        }
-
-                        Debug.Assert(!dest.Type.IsInteger() && src2.Type.IsInteger());
-
-                        context.Assembler.WriteInstruction(info.Inst, dest, src1, src2, src2.Type);
-
-                        break;
-                    }
-
-                    case IntrinsicType.Crc32:
-                    {
-                        Operand dest = operation.Destination;
-                        Operand src1 = operation.GetSource(0);
-                        Operand src2 = operation.GetSource(1);
-
-                        EnsureSameReg(dest, src1);
-
-                        Debug.Assert(dest.Type.IsInteger() && src1.Type.IsInteger() && src2.Type.IsInteger());
-
-                        context.Assembler.WriteInstruction(info.Inst, dest, src2, dest.Type);
-
-                        break;
-                    }
-
-                    case IntrinsicType.BinaryImm:
-                    {
-                        Operand dest = operation.Destination;
-                        Operand src1 = operation.GetSource(0);
-                        Operand src2 = operation.GetSource(1);
-
-                        EnsureSameType(dest, src1);
-
-                        if (!HardwareCapabilities.SupportsVexEncoding)
-                        {
-                            EnsureSameReg(dest, src1);
-                        }
-
-                        Debug.Assert(!dest.Type.IsInteger() && src2.Kind == OperandKind.Constant);
-
-                        context.Assembler.WriteInstruction(info.Inst, dest, src1, src2.AsByte());
-
-                        break;
-                    }
-
-                    case IntrinsicType.Ternary:
-                    {
-                        Operand dest = operation.Destination;
-                        Operand src1 = operation.GetSource(0);
-                        Operand src2 = operation.GetSource(1);
-                        Operand src3 = operation.GetSource(2);
-
-                        EnsureSameType(dest, src1, src2, src3);
-
-                        Debug.Assert(!dest.Type.IsInteger());
-
-                        if (info.Inst == X86Instruction.Blendvpd && HardwareCapabilities.SupportsVexEncoding)
-                        {
-                            context.Assembler.WriteInstruction(X86Instruction.Vblendvpd, dest, src1, src2, src3);
-                        }
-                        else if (info.Inst == X86Instruction.Blendvps && HardwareCapabilities.SupportsVexEncoding)
-                        {
-                            context.Assembler.WriteInstruction(X86Instruction.Vblendvps, dest, src1, src2, src3);
-                        }
-                        else if (info.Inst == X86Instruction.Pblendvb && HardwareCapabilities.SupportsVexEncoding)
-                        {
-                            context.Assembler.WriteInstruction(X86Instruction.Vpblendvb, dest, src1, src2, src3);
-                        }
-                        else
-                        {
-                            EnsureSameReg(dest, src1);
-
-                            Debug.Assert(src3.GetRegister().Index == 0);
+                            Debug.Assert(!dest.Type.IsInteger());
+                            Debug.Assert(!src2.Type.IsInteger() || src2.Kind == OperandKind.Constant);
 
                             context.Assembler.WriteInstruction(info.Inst, dest, src1, src2);
+
+                            break;
                         }
 
-                        break;
-                    }
+                    case IntrinsicType.BinaryGpr:
+                        {
+                            Operand dest = operation.Destination;
+                            Operand src1 = operation.GetSource(0);
+                            Operand src2 = operation.GetSource(1);
+
+                            EnsureSameType(dest, src1);
+
+                            if (!HardwareCapabilities.SupportsVexEncoding)
+                            {
+                                EnsureSameReg(dest, src1);
+                            }
+
+                            Debug.Assert(!dest.Type.IsInteger() && src2.Type.IsInteger());
+
+                            context.Assembler.WriteInstruction(info.Inst, dest, src1, src2, src2.Type);
+
+                            break;
+                        }
+
+                    case IntrinsicType.Crc32:
+                        {
+                            Operand dest = operation.Destination;
+                            Operand src1 = operation.GetSource(0);
+                            Operand src2 = operation.GetSource(1);
+
+                            EnsureSameReg(dest, src1);
+
+                            Debug.Assert(dest.Type.IsInteger() && src1.Type.IsInteger() && src2.Type.IsInteger());
+
+                            context.Assembler.WriteInstruction(info.Inst, dest, src2, dest.Type);
+
+                            break;
+                        }
+
+                    case IntrinsicType.BinaryImm:
+                        {
+                            Operand dest = operation.Destination;
+                            Operand src1 = operation.GetSource(0);
+                            Operand src2 = operation.GetSource(1);
+
+                            EnsureSameType(dest, src1);
+
+                            if (!HardwareCapabilities.SupportsVexEncoding)
+                            {
+                                EnsureSameReg(dest, src1);
+                            }
+
+                            Debug.Assert(!dest.Type.IsInteger() && src2.Kind == OperandKind.Constant);
+
+                            context.Assembler.WriteInstruction(info.Inst, dest, src1, src2.AsByte());
+
+                            break;
+                        }
+
+                    case IntrinsicType.Ternary:
+                        {
+                            Operand dest = operation.Destination;
+                            Operand src1 = operation.GetSource(0);
+                            Operand src2 = operation.GetSource(1);
+                            Operand src3 = operation.GetSource(2);
+
+                            EnsureSameType(dest, src1, src2, src3);
+
+                            Debug.Assert(!dest.Type.IsInteger());
+
+                            if (info.Inst == X86Instruction.Blendvpd && HardwareCapabilities.SupportsVexEncoding)
+                            {
+                                context.Assembler.WriteInstruction(X86Instruction.Vblendvpd, dest, src1, src2, src3);
+                            }
+                            else if (info.Inst == X86Instruction.Blendvps && HardwareCapabilities.SupportsVexEncoding)
+                            {
+                                context.Assembler.WriteInstruction(X86Instruction.Vblendvps, dest, src1, src2, src3);
+                            }
+                            else if (info.Inst == X86Instruction.Pblendvb && HardwareCapabilities.SupportsVexEncoding)
+                            {
+                                context.Assembler.WriteInstruction(X86Instruction.Vpblendvb, dest, src1, src2, src3);
+                            }
+                            else
+                            {
+                                EnsureSameReg(dest, src1);
+
+                                Debug.Assert(src3.GetRegister().Index == 0);
+
+                                context.Assembler.WriteInstruction(info.Inst, dest, src1, src2);
+                            }
+
+                            break;
+                        }
 
                     case IntrinsicType.TernaryImm:
-                    {
-                        Operand dest = operation.Destination;
-                        Operand src1 = operation.GetSource(0);
-                        Operand src2 = operation.GetSource(1);
-                        Operand src3 = operation.GetSource(2);
-
-                        EnsureSameType(dest, src1, src2);
-
-                        if (!HardwareCapabilities.SupportsVexEncoding)
                         {
-                            EnsureSameReg(dest, src1);
+                            Operand dest = operation.Destination;
+                            Operand src1 = operation.GetSource(0);
+                            Operand src2 = operation.GetSource(1);
+                            Operand src3 = operation.GetSource(2);
+
+                            EnsureSameType(dest, src1, src2);
+
+                            if (!HardwareCapabilities.SupportsVexEncoding)
+                            {
+                                EnsureSameReg(dest, src1);
+                            }
+
+                            Debug.Assert(!dest.Type.IsInteger() && src3.Kind == OperandKind.Constant);
+
+                            context.Assembler.WriteInstruction(info.Inst, dest, src1, src2, src3.AsByte());
+
+                            break;
                         }
 
-                        Debug.Assert(!dest.Type.IsInteger() && src3.Kind == OperandKind.Constant);
-
-                        context.Assembler.WriteInstruction(info.Inst, dest, src1, src2, src3.AsByte());
-
-                        break;
-                    }
-
                     case IntrinsicType.Fma:
-                    {
-                        Operand dest = operation.Destination;
-                        Operand src1 = operation.GetSource(0);
-                        Operand src2 = operation.GetSource(1);
-                        Operand src3 = operation.GetSource(2);
+                        {
+                            Operand dest = operation.Destination;
+                            Operand src1 = operation.GetSource(0);
+                            Operand src2 = operation.GetSource(1);
+                            Operand src3 = operation.GetSource(2);
 
-                        Debug.Assert(HardwareCapabilities.SupportsVexEncoding);
+                            Debug.Assert(HardwareCapabilities.SupportsVexEncoding);
 
-                        Debug.Assert(dest.Kind == OperandKind.Register && src1.Kind == OperandKind.Register && src2.Kind == OperandKind.Register);
-                        Debug.Assert(src3.Kind == OperandKind.Register || src3.Kind == OperandKind.Memory);
+                            Debug.Assert(dest.Kind == OperandKind.Register && src1.Kind == OperandKind.Register && src2.Kind == OperandKind.Register);
+                            Debug.Assert(src3.Kind == OperandKind.Register || src3.Kind == OperandKind.Memory);
 
-                        EnsureSameType(dest, src1, src2, src3);
-                        Debug.Assert(dest.Type == OperandType.V128);
+                            EnsureSameType(dest, src1, src2, src3);
+                            Debug.Assert(dest.Type == OperandType.V128);
 
-                        Debug.Assert(dest.Value == src1.Value);
+                            Debug.Assert(dest.Value == src1.Value);
 
-                        context.Assembler.WriteInstruction(info.Inst, dest, src2, src3);
+                            context.Assembler.WriteInstruction(info.Inst, dest, src2, src3);
 
-                        break;
-                    }
+                            break;
+                        }
                 }
             }
             else
@@ -592,7 +594,7 @@ namespace ARMeilleure.CodeGen.X86
 
         private static void GenerateBitwiseNot(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             ValidateUnOp(dest, source);
@@ -630,7 +632,7 @@ namespace ARMeilleure.CodeGen.X86
 
         private static void GenerateByteSwap(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             ValidateUnOp(dest, source);
@@ -761,19 +763,19 @@ namespace ARMeilleure.CodeGen.X86
             Operand src2 = operation.GetSource(1);
             Operand src3 = operation.GetSource(2);
 
-            EnsureSameReg (dest, src3);
+            EnsureSameReg(dest, src3);
             EnsureSameType(dest, src2, src3);
 
             Debug.Assert(dest.Type.IsInteger());
             Debug.Assert(src1.Type == OperandType.I32);
 
-            context.Assembler.Test  (src1, src1, src1.Type);
+            context.Assembler.Test(src1, src1, src1.Type);
             context.Assembler.Cmovcc(dest, src2, dest.Type, X86Condition.NotEqual);
         }
 
         private static void GenerateConvertI64ToI32(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type == OperandType.I32 && source.Type == OperandType.I64);
@@ -783,7 +785,7 @@ namespace ARMeilleure.CodeGen.X86
 
         private static void GenerateConvertToFP(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type == OperandType.FP32 || dest.Type == OperandType.FP64);
@@ -794,7 +796,7 @@ namespace ARMeilleure.CodeGen.X86
 
                 if (source.Type.IsInteger())
                 {
-                    context.Assembler.Xorps   (dest, dest, dest);
+                    context.Assembler.Xorps(dest, dest, dest);
                     context.Assembler.Cvtsi2ss(dest, dest, source, source.Type);
                 }
                 else /* if (source.Type == OperandType.FP64) */
@@ -810,7 +812,7 @@ namespace ARMeilleure.CodeGen.X86
 
                 if (source.Type.IsInteger())
                 {
-                    context.Assembler.Xorps   (dest, dest, dest);
+                    context.Assembler.Xorps(dest, dest, dest);
                     context.Assembler.Cvtsi2sd(dest, dest, source, source.Type);
                 }
                 else /* if (source.Type == OperandType.FP32) */
@@ -824,7 +826,7 @@ namespace ARMeilleure.CodeGen.X86
 
         private static void GenerateCopy(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             EnsureSameType(dest, source);
@@ -837,7 +839,7 @@ namespace ARMeilleure.CodeGen.X86
                 return;
             }
 
-            if (dest.Kind   == OperandKind.Register &&
+            if (dest.Kind == OperandKind.Register &&
                 source.Kind == OperandKind.Constant && source.Value == 0)
             {
                 // Assemble "mov reg, 0" as "xor reg, reg" as the later is more efficient.
@@ -855,7 +857,7 @@ namespace ARMeilleure.CodeGen.X86
 
         private static void GenerateCountLeadingZeros(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             EnsureSameType(dest, source);
@@ -888,9 +890,9 @@ namespace ARMeilleure.CodeGen.X86
 
         private static void GenerateDivide(CodeGenContext context, Operation operation)
         {
-            Operand dest     = operation.Destination;
+            Operand dest = operation.Destination;
             Operand dividend = operation.GetSource(0);
-            Operand divisor  = operation.GetSource(1);
+            Operand divisor = operation.GetSource(1);
 
             if (!dest.Type.IsInteger())
             {
@@ -938,7 +940,7 @@ namespace ARMeilleure.CodeGen.X86
 
         private static void GenerateFill(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand offset = operation.GetSource(0);
 
             Debug.Assert(offset.Kind == OperandKind.Constant);
@@ -954,7 +956,7 @@ namespace ARMeilleure.CodeGen.X86
 
         private static void GenerateLoad(CodeGenContext context, Operation operation)
         {
-            Operand value   =        operation.Destination;
+            Operand value = operation.Destination;
             Operand address = Memory(operation.GetSource(0), value.Type);
 
             GenerateLoad(context, address, value);
@@ -962,7 +964,7 @@ namespace ARMeilleure.CodeGen.X86
 
         private static void GenerateLoad16(CodeGenContext context, Operation operation)
         {
-            Operand value   =        operation.Destination;
+            Operand value = operation.Destination;
             Operand address = Memory(operation.GetSource(0), value.Type);
 
             Debug.Assert(value.Type.IsInteger());
@@ -972,7 +974,7 @@ namespace ARMeilleure.CodeGen.X86
 
         private static void GenerateLoad8(CodeGenContext context, Operation operation)
         {
-            Operand value   =        operation.Destination;
+            Operand value = operation.Destination;
             Operand address = Memory(operation.GetSource(0), value.Type);
 
             Debug.Assert(value.Type.IsInteger());
@@ -1039,7 +1041,7 @@ namespace ARMeilleure.CodeGen.X86
 
         private static void GenerateNegate(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             ValidateUnOp(dest, source);
@@ -1102,7 +1104,7 @@ namespace ARMeilleure.CodeGen.X86
 
         private static void GenerateSignExtend16(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -1112,7 +1114,7 @@ namespace ARMeilleure.CodeGen.X86
 
         private static void GenerateSignExtend32(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -1122,7 +1124,7 @@ namespace ARMeilleure.CodeGen.X86
 
         private static void GenerateSignExtend8(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -1158,7 +1160,7 @@ namespace ARMeilleure.CodeGen.X86
 
         private static void GenerateStackAlloc(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand offset = operation.GetSource(0);
 
             Debug.Assert(offset.Kind == OperandKind.Constant);
@@ -1174,7 +1176,7 @@ namespace ARMeilleure.CodeGen.X86
 
         private static void GenerateStore(CodeGenContext context, Operation operation)
         {
-            Operand value   =        operation.GetSource(1);
+            Operand value = operation.GetSource(1);
             Operand address = Memory(operation.GetSource(0), value.Type);
 
             GenerateStore(context, address, value);
@@ -1182,7 +1184,7 @@ namespace ARMeilleure.CodeGen.X86
 
         private static void GenerateStore16(CodeGenContext context, Operation operation)
         {
-            Operand value   =        operation.GetSource(1);
+            Operand value = operation.GetSource(1);
             Operand address = Memory(operation.GetSource(0), value.Type);
 
             Debug.Assert(value.Type.IsInteger());
@@ -1192,7 +1194,7 @@ namespace ARMeilleure.CodeGen.X86
 
         private static void GenerateStore8(CodeGenContext context, Operation operation)
         {
-            Operand value   =        operation.GetSource(1);
+            Operand value = operation.GetSource(1);
             Operand address = Memory(operation.GetSource(0), value.Type);
 
             Debug.Assert(value.Type.IsInteger());
@@ -1231,7 +1233,7 @@ namespace ARMeilleure.CodeGen.X86
 
         private static void GenerateVectorCreateScalar(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(!dest.Type.IsInteger() && source.Type.IsInteger());
@@ -1278,7 +1280,7 @@ namespace ARMeilleure.CodeGen.X86
                     mask1 = BitUtils.RotateRight(mask1, 8 - index * 2, 8);
 
                     context.Assembler.Pshufd(src1, src1, (byte)mask0);
-                    context.Assembler.Movd  (dest, src1);
+                    context.Assembler.Movd(dest, src1);
                     context.Assembler.Pshufd(src1, src1, (byte)mask1);
                 }
             }
@@ -1294,11 +1296,11 @@ namespace ARMeilleure.CodeGen.X86
                 }
                 else
                 {
-                    const byte mask = 0b01_00_11_10;
+                    const byte Mask = 0b01_00_11_10;
 
-                    context.Assembler.Pshufd(src1, src1, mask);
-                    context.Assembler.Movq  (dest, src1);
-                    context.Assembler.Pshufd(src1, src1, mask);
+                    context.Assembler.Pshufd(src1, src1, Mask);
+                    context.Assembler.Movq(dest, src1);
+                    context.Assembler.Pshufd(src1, src1, Mask);
                 }
             }
             else
@@ -1308,7 +1310,7 @@ namespace ARMeilleure.CodeGen.X86
                     (index == 1 && dest.Type == OperandType.FP64))
                 {
                     context.Assembler.Movhlps(dest, dest, src1);
-                    context.Assembler.Movq   (dest, dest);
+                    context.Assembler.Movq(dest, dest);
                 }
                 else
                 {
@@ -1455,11 +1457,11 @@ namespace ARMeilleure.CodeGen.X86
                             int mask0 = 0b11_10_01_00;
                             int mask1 = 0b11_10_01_00;
 
-                            mask0 = BitUtils.RotateRight(mask0,     index * 2, 8);
+                            mask0 = BitUtils.RotateRight(mask0, index * 2, 8);
                             mask1 = BitUtils.RotateRight(mask1, 8 - index * 2, 8);
 
                             context.Assembler.Pshufd(src1, src1, (byte)mask0); // Lane to be inserted in position 0.
-                            context.Assembler.Movss (dest, src1, src2);        // dest[127:0] = src1[127:32] | src2[31:0]
+                            context.Assembler.Movss(dest, src1, src2);         // dest[127:0] = src1[127:32] | src2[31:0]
                             context.Assembler.Pshufd(dest, dest, (byte)mask1); // Inserted lane in original position.
 
                             if (dest.GetRegister() != src1.GetRegister())
@@ -1555,7 +1557,7 @@ namespace ARMeilleure.CodeGen.X86
 
         private static void GenerateVectorZeroUpper64(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type == OperandType.V128 && source.Type == OperandType.V128);
@@ -1565,7 +1567,7 @@ namespace ARMeilleure.CodeGen.X86
 
         private static void GenerateVectorZeroUpper96(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type == OperandType.V128 && source.Type == OperandType.V128);
@@ -1575,7 +1577,7 @@ namespace ARMeilleure.CodeGen.X86
 
         private static void GenerateZeroExtend16(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -1585,7 +1587,7 @@ namespace ARMeilleure.CodeGen.X86
 
         private static void GenerateZeroExtend32(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -1601,7 +1603,7 @@ namespace ARMeilleure.CodeGen.X86
 
         private static void GenerateZeroExtend8(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -1613,13 +1615,25 @@ namespace ARMeilleure.CodeGen.X86
         {
             switch (value.Type)
             {
-                case OperandType.I32:  context.Assembler.Mov   (value, address, OperandType.I32); break;
-                case OperandType.I64:  context.Assembler.Mov   (value, address, OperandType.I64); break;
-                case OperandType.FP32: context.Assembler.Movd  (value, address);                  break;
-                case OperandType.FP64: context.Assembler.Movq  (value, address);                  break;
-                case OperandType.V128: context.Assembler.Movdqu(value, address);                  break;
+                case OperandType.I32:
+                    context.Assembler.Mov(value, address, OperandType.I32);
+                    break;
+                case OperandType.I64:
+                    context.Assembler.Mov(value, address, OperandType.I64);
+                    break;
+                case OperandType.FP32:
+                    context.Assembler.Movd(value, address);
+                    break;
+                case OperandType.FP64:
+                    context.Assembler.Movq(value, address);
+                    break;
+                case OperandType.V128:
+                    context.Assembler.Movdqu(value, address);
+                    break;
 
-                default: Debug.Assert(false); break;
+                default:
+                    Debug.Assert(false);
+                    break;
             }
         }
 
@@ -1627,13 +1641,25 @@ namespace ARMeilleure.CodeGen.X86
         {
             switch (value.Type)
             {
-                case OperandType.I32:  context.Assembler.Mov   (address, value, OperandType.I32); break;
-                case OperandType.I64:  context.Assembler.Mov   (address, value, OperandType.I64); break;
-                case OperandType.FP32: context.Assembler.Movd  (address, value);                  break;
-                case OperandType.FP64: context.Assembler.Movq  (address, value);                  break;
-                case OperandType.V128: context.Assembler.Movdqu(address, value);                  break;
+                case OperandType.I32:
+                    context.Assembler.Mov(address, value, OperandType.I32);
+                    break;
+                case OperandType.I64:
+                    context.Assembler.Mov(address, value, OperandType.I64);
+                    break;
+                case OperandType.FP32:
+                    context.Assembler.Movd(address, value);
+                    break;
+                case OperandType.FP64:
+                    context.Assembler.Movq(address, value);
+                    break;
+                case OperandType.V128:
+                    context.Assembler.Movdqu(address, value);
+                    break;
 
-                default: Debug.Assert(false); break;
+                default:
+                    Debug.Assert(false);
+                    break;
             }
         }
 
@@ -1670,21 +1696,21 @@ namespace ARMeilleure.CodeGen.X86
         [Conditional("DEBUG")]
         private static void ValidateUnOp(Operand dest, Operand source)
         {
-            EnsureSameReg (dest, source);
+            EnsureSameReg(dest, source);
             EnsureSameType(dest, source);
         }
 
         [Conditional("DEBUG")]
         private static void ValidateBinOp(Operand dest, Operand src1, Operand src2)
         {
-            EnsureSameReg (dest, src1);
+            EnsureSameReg(dest, src1);
             EnsureSameType(dest, src1, src2);
         }
 
         [Conditional("DEBUG")]
         private static void ValidateShift(Operand dest, Operand src1, Operand src2)
         {
-            EnsureSameReg (dest, src1);
+            EnsureSameReg(dest, src1);
             EnsureSameType(dest, src1);
 
             Debug.Assert(dest.Type.IsInteger() && src2.Type == OperandType.I32);
@@ -1722,7 +1748,7 @@ namespace ARMeilleure.CodeGen.X86
 
         private static UnwindInfo WritePrologue(CodeGenContext context)
         {
-            List<UnwindPushEntry> pushEntries = new List<UnwindPushEntry>();
+            List<UnwindPushEntry> pushEntries = new();
 
             Operand rsp = Register(X86Register.Rsp);
 
@@ -1827,11 +1853,11 @@ namespace ARMeilleure.CodeGen.X86
             // that the OS will map all pages that we'll use. We do that by
             // doing a dummy read on those pages, forcing a page fault and
             // the OS to map them. If they are already mapped, nothing happens.
-            const int pageMask = PageSize - 1;
+            const int PageMask = PageSize - 1;
 
-            size = (size + pageMask) & ~pageMask;
+            size = (size + PageMask) & ~PageMask;
 
-            Operand rsp  = Register(X86Register.Rsp);
+            Operand rsp = Register(X86Register.Rsp);
             Operand temp = Register(CallingConvention.GetIntReturnRegister());
 
             for (int offset = PageSize; offset < size; offset += PageSize)
@@ -1862,4 +1888,4 @@ namespace ARMeilleure.CodeGen.X86
             return Operand.Factory.Register((int)register, RegisterType.Vector, OperandType.V128);
         }
     }
-}
+}

src/ARMeilleure/CodeGen/X86/HardwareCapabilities.cs

@@ -47,7 +47,7 @@ namespace ARMeilleure.CodeGen.X86
                 0xc3, // ret
             };
 
-            using MemoryBlock memGetXcr0 = new MemoryBlock((ulong)asmGetXcr0.Length);
+            using MemoryBlock memGetXcr0 = new((ulong)asmGetXcr0.Length);
 
             memGetXcr0.Write(0, asmGetXcr0);
 
@@ -62,7 +62,7 @@ namespace ARMeilleure.CodeGen.X86
         public enum FeatureFlags1Edx
         {
             Sse = 1 << 25,
-            Sse2 = 1 << 26
+            Sse2 = 1 << 26,
         }
 
         [Flags]
@@ -79,7 +79,7 @@ namespace ARMeilleure.CodeGen.X86
             Xsave = 1 << 26,
             Osxsave = 1 << 27,
             Avx = 1 << 28,
-            F16c = 1 << 29
+            F16c = 1 << 29,
         }
 
         [Flags]
@@ -90,7 +90,7 @@ namespace ARMeilleure.CodeGen.X86
             Avx512dq = 1 << 17,
             Sha = 1 << 29,
             Avx512bw = 1 << 30,
-            Avx512vl = 1 << 31
+            Avx512vl = 1 << 31,
         }
 
         [Flags]
@@ -106,7 +106,7 @@ namespace ARMeilleure.CodeGen.X86
             YmmHi128 = 1 << 2,
             Opmask = 1 << 5,
             ZmmHi256 = 1 << 6,
-            Hi16Zmm = 1 << 7
+            Hi16Zmm = 1 << 7,
         }
 
         public static FeatureFlags1Edx FeatureInfo1Edx { get; }
@@ -141,4 +141,4 @@ namespace ARMeilleure.CodeGen.X86
         public static bool SupportsVexEncoding => SupportsAvx && !ForceLegacySse;
         public static bool SupportsEvexEncoding => SupportsAvx512F && !ForceLegacySse;
     }
-}
+}

src/ARMeilleure/CodeGen/X86/IntrinsicInfo.cs

@@ -3,7 +3,7 @@ namespace ARMeilleure.CodeGen.X86
     readonly struct IntrinsicInfo
     {
         public X86Instruction Inst { get; }
-        public IntrinsicType  Type { get; }
+        public IntrinsicType Type { get; }
 
         public IntrinsicInfo(X86Instruction inst, IntrinsicType type)
         {
@@ -11,4 +11,4 @@ namespace ARMeilleure.CodeGen.X86
             Type = type;
         }
     }
-}
+}

src/ARMeilleure/CodeGen/X86/IntrinsicTable.cs

@@ -5,12 +5,13 @@ namespace ARMeilleure.CodeGen.X86
 {
     static class IntrinsicTable
     {
-        private static IntrinsicInfo[] _intrinTable;
+        private static readonly IntrinsicInfo[] _intrinTable;
 
         static IntrinsicTable()
         {
             _intrinTable = new IntrinsicInfo[EnumUtils.GetCount(typeof(Intrinsic))];
 
+#pragma warning disable IDE0055 // Disable formatting
             Add(Intrinsic.X86Addpd,         new IntrinsicInfo(X86Instruction.Addpd,         IntrinsicType.Binary));
             Add(Intrinsic.X86Addps,         new IntrinsicInfo(X86Instruction.Addps,         IntrinsicType.Binary));
             Add(Intrinsic.X86Addsd,         new IntrinsicInfo(X86Instruction.Addsd,         IntrinsicType.Binary));
@@ -185,6 +186,7 @@ namespace ARMeilleure.CodeGen.X86
             Add(Intrinsic.X86Vpternlogd,    new IntrinsicInfo(X86Instruction.Vpternlogd,    IntrinsicType.TernaryImm));
             Add(Intrinsic.X86Xorpd,         new IntrinsicInfo(X86Instruction.Xorpd,         IntrinsicType.Binary));
             Add(Intrinsic.X86Xorps,         new IntrinsicInfo(X86Instruction.Xorps,         IntrinsicType.Binary));
+#pragma warning restore IDE0055
         }
 
         private static void Add(Intrinsic intrin, IntrinsicInfo info)
@@ -197,4 +199,4 @@ namespace ARMeilleure.CodeGen.X86
             return _intrinTable[(int)intrin];
         }
     }
-}
+}

src/ARMeilleure/CodeGen/X86/IntrinsicType.cs

@@ -13,6 +13,6 @@ namespace ARMeilleure.CodeGen.X86
         Crc32,
         Ternary,
         TernaryImm,
-        Fma
+        Fma,
     }
-}
+}

src/ARMeilleure/CodeGen/X86/Mxcsr.cs

@@ -10,6 +10,6 @@ namespace ARMeilleure.CodeGen.X86
         Rlo = 1 << 13, // Round Mode low bit.
         Um = 1 << 11,  // Underflow Mask.
         Dm = 1 << 8,   // Denormal Mask.
-        Daz = 1 << 6   // Denormals Are Zero.
+        Daz = 1 << 6, // Denormals Are Zero.
     }
 }

src/ARMeilleure/CodeGen/X86/PreAllocator.cs

@@ -104,11 +104,11 @@ namespace ARMeilleure.CodeGen.X86
                         case Instruction.Tailcall:
                             if (callConv == CallConvName.Windows)
                             {
-                                PreAllocatorWindows.InsertTailcallCopies(block.Operations, stackAlloc, node);
+                                PreAllocatorWindows.InsertTailcallCopies(block.Operations, node);
                             }
                             else
                             {
-                                PreAllocatorSystemV.InsertTailcallCopies(block.Operations, stackAlloc, node);
+                                PreAllocatorSystemV.InsertTailcallCopies(block.Operations, node);
                             }
                             break;
 
@@ -177,10 +177,7 @@ namespace ARMeilleure.CodeGen.X86
                     {
                         src2 = node.GetSource(1);
 
-                        Operand temp = src1;
-
-                        src1 = src2;
-                        src2 = temp;
+                        (src2, src1) = (src1, src2);
 
                         node.SetSource(0, src1);
                         node.SetSource(1, src2);
@@ -228,151 +225,151 @@ namespace ARMeilleure.CodeGen.X86
                 case Instruction.CompareAndSwap:
                 case Instruction.CompareAndSwap16:
                 case Instruction.CompareAndSwap8:
-                {
-                    OperandType type = node.GetSource(1).Type;
-
-                    if (type == OperandType.V128)
                     {
-                        // Handle the many restrictions of the compare and exchange (16 bytes) instruction:
-                        // - The expected value should be in RDX:RAX.
-                        // - The new value to be written should be in RCX:RBX.
-                        // - The value at the memory location is loaded to RDX:RAX.
-                        void SplitOperand(Operand source, Operand lr, Operand hr)
+                        OperandType type = node.GetSource(1).Type;
+
+                        if (type == OperandType.V128)
                         {
-                            nodes.AddBefore(node, Operation(Instruction.VectorExtract, lr, source, Const(0)));
-                            nodes.AddBefore(node, Operation(Instruction.VectorExtract, hr, source, Const(1)));
+                            // Handle the many restrictions of the compare and exchange (16 bytes) instruction:
+                            // - The expected value should be in RDX:RAX.
+                            // - The new value to be written should be in RCX:RBX.
+                            // - The value at the memory location is loaded to RDX:RAX.
+                            void SplitOperand(Operand source, Operand lr, Operand hr)
+                            {
+                                nodes.AddBefore(node, Operation(Instruction.VectorExtract, lr, source, Const(0)));
+                                nodes.AddBefore(node, Operation(Instruction.VectorExtract, hr, source, Const(1)));
+                            }
+
+                            Operand rax = Gpr(X86Register.Rax, OperandType.I64);
+                            Operand rbx = Gpr(X86Register.Rbx, OperandType.I64);
+                            Operand rcx = Gpr(X86Register.Rcx, OperandType.I64);
+                            Operand rdx = Gpr(X86Register.Rdx, OperandType.I64);
+
+                            SplitOperand(node.GetSource(1), rax, rdx);
+                            SplitOperand(node.GetSource(2), rbx, rcx);
+
+                            Operation operation = node;
+
+                            node = nodes.AddAfter(node, Operation(Instruction.VectorCreateScalar, dest, rax));
+                            nodes.AddAfter(node, Operation(Instruction.VectorInsert, dest, dest, rdx, Const(1)));
+
+                            operation.SetDestinations(new Operand[] { rdx, rax });
+                            operation.SetSources(new Operand[] { operation.GetSource(0), rdx, rax, rcx, rbx });
+                        }
+                        else
+                        {
+                            // Handle the many restrictions of the compare and exchange (32/64) instruction:
+                            // - The expected value should be in (E/R)AX.
+                            // - The value at the memory location is loaded to (E/R)AX.
+                            Operand expected = node.GetSource(1);
+                            Operand newValue = node.GetSource(2);
+
+                            Operand rax = Gpr(X86Register.Rax, expected.Type);
+
+                            nodes.AddBefore(node, Operation(Instruction.Copy, rax, expected));
+
+                            // We need to store the new value into a temp, since it may
+                            // be a constant, and this instruction does not support immediate operands.
+                            Operand temp = Local(newValue.Type);
+
+                            nodes.AddBefore(node, Operation(Instruction.Copy, temp, newValue));
+
+                            node.SetSources(new Operand[] { node.GetSource(0), rax, temp });
+
+                            nodes.AddAfter(node, Operation(Instruction.Copy, dest, rax));
+
+                            node.Destination = rax;
                         }
 
-                        Operand rax = Gpr(X86Register.Rax, OperandType.I64);
-                        Operand rbx = Gpr(X86Register.Rbx, OperandType.I64);
-                        Operand rcx = Gpr(X86Register.Rcx, OperandType.I64);
-                        Operand rdx = Gpr(X86Register.Rdx, OperandType.I64);
-
-                        SplitOperand(node.GetSource(1), rax, rdx);
-                        SplitOperand(node.GetSource(2), rbx, rcx);
-
-                        Operation operation = node;
-
-                        node = nodes.AddAfter(node, Operation(Instruction.VectorCreateScalar, dest, rax));
-                        nodes.AddAfter(node, Operation(Instruction.VectorInsert, dest, dest, rdx, Const(1)));
-
-                        operation.SetDestinations(new Operand[] { rdx, rax });
-                        operation.SetSources(new Operand[] { operation.GetSource(0), rdx, rax, rcx, rbx });
+                        break;
                     }
-                    else
-                    {
-                        // Handle the many restrictions of the compare and exchange (32/64) instruction:
-                        // - The expected value should be in (E/R)AX.
-                        // - The value at the memory location is loaded to (E/R)AX.
-                        Operand expected = node.GetSource(1);
-                        Operand newValue = node.GetSource(2);
-
-                        Operand rax = Gpr(X86Register.Rax, expected.Type);
-
-                        nodes.AddBefore(node, Operation(Instruction.Copy, rax, expected));
-
-                        // We need to store the new value into a temp, since it may
-                        // be a constant, and this instruction does not support immediate operands.
-                        Operand temp = Local(newValue.Type);
-
-                        nodes.AddBefore(node, Operation(Instruction.Copy, temp, newValue));
-
-                        node.SetSources(new Operand[] { node.GetSource(0), rax, temp });
-
-                        nodes.AddAfter(node, Operation(Instruction.Copy, dest, rax));
-
-                        node.Destination = rax;
-                    }
-
-                    break;
-                }
 
                 case Instruction.Divide:
                 case Instruction.DivideUI:
-                {
-                    // Handle the many restrictions of the division instructions:
-                    // - The dividend is always in RDX:RAX.
-                    // - The result is always in RAX.
-                    // - Additionally it also writes the remainder in RDX.
-                    if (dest.Type.IsInteger())
                     {
+                        // Handle the many restrictions of the division instructions:
+                        // - The dividend is always in RDX:RAX.
+                        // - The result is always in RAX.
+                        // - Additionally it also writes the remainder in RDX.
+                        if (dest.Type.IsInteger())
+                        {
+                            Operand src1 = node.GetSource(0);
+
+                            Operand rax = Gpr(X86Register.Rax, src1.Type);
+                            Operand rdx = Gpr(X86Register.Rdx, src1.Type);
+
+                            nodes.AddBefore(node, Operation(Instruction.Copy, rax, src1));
+                            nodes.AddBefore(node, Operation(Instruction.Clobber, rdx));
+
+                            nodes.AddAfter(node, Operation(Instruction.Copy, dest, rax));
+
+                            node.SetSources(new Operand[] { rdx, rax, node.GetSource(1) });
+                            node.Destination = rax;
+                        }
+
+                        break;
+                    }
+
+                case Instruction.Extended:
+                    {
+                        bool isBlend = node.Intrinsic == Intrinsic.X86Blendvpd ||
+                                   node.Intrinsic == Intrinsic.X86Blendvps ||
+                                   node.Intrinsic == Intrinsic.X86Pblendvb;
+
+                        // BLENDVPD, BLENDVPS, PBLENDVB last operand is always implied to be XMM0 when VEX is not supported.
+                        // SHA256RNDS2 always has an implied XMM0 as a last operand.
+                        if ((isBlend && !HardwareCapabilities.SupportsVexEncoding) || node.Intrinsic == Intrinsic.X86Sha256Rnds2)
+                        {
+                            Operand xmm0 = Xmm(X86Register.Xmm0, OperandType.V128);
+
+                            nodes.AddBefore(node, Operation(Instruction.Copy, xmm0, node.GetSource(2)));
+
+                            node.SetSource(2, xmm0);
+                        }
+
+                        break;
+                    }
+
+                case Instruction.Multiply64HighSI:
+                case Instruction.Multiply64HighUI:
+                    {
+                        // Handle the many restrictions of the i64 * i64 = i128 multiply instructions:
+                        // - The multiplicand is always in RAX.
+                        // - The lower 64-bits of the result is always in RAX.
+                        // - The higher 64-bits of the result is always in RDX.
                         Operand src1 = node.GetSource(0);
 
                         Operand rax = Gpr(X86Register.Rax, src1.Type);
                         Operand rdx = Gpr(X86Register.Rdx, src1.Type);
 
-                        nodes.AddBefore(node, Operation(Instruction.Copy,    rax, src1));
-                        nodes.AddBefore(node, Operation(Instruction.Clobber, rdx));
+                        nodes.AddBefore(node, Operation(Instruction.Copy, rax, src1));
 
-                        nodes.AddAfter(node, Operation(Instruction.Copy, dest, rax));
+                        node.SetSource(0, rax);
 
-                        node.SetSources(new Operand[] { rdx, rax, node.GetSource(1) });
-                        node.Destination = rax;
+                        nodes.AddAfter(node, Operation(Instruction.Copy, dest, rdx));
+
+                        node.SetDestinations(new Operand[] { rdx, rax });
+
+                        break;
                     }
 
-                    break;
-                }
-
-                case Instruction.Extended:
-                {
-                    bool isBlend = node.Intrinsic == Intrinsic.X86Blendvpd ||
-                                   node.Intrinsic == Intrinsic.X86Blendvps ||
-                                   node.Intrinsic == Intrinsic.X86Pblendvb;
-
-                    // BLENDVPD, BLENDVPS, PBLENDVB last operand is always implied to be XMM0 when VEX is not supported.
-                    // SHA256RNDS2 always has an implied XMM0 as a last operand.
-                    if ((isBlend && !HardwareCapabilities.SupportsVexEncoding) || node.Intrinsic == Intrinsic.X86Sha256Rnds2)
-                    {
-                        Operand xmm0 = Xmm(X86Register.Xmm0, OperandType.V128);
-
-                        nodes.AddBefore(node, Operation(Instruction.Copy, xmm0, node.GetSource(2)));
-
-                        node.SetSource(2, xmm0);
-                    }
-
-                    break;
-                }
-
-                case Instruction.Multiply64HighSI:
-                case Instruction.Multiply64HighUI:
-                {
-                    // Handle the many restrictions of the i64 * i64 = i128 multiply instructions:
-                    // - The multiplicand is always in RAX.
-                    // - The lower 64-bits of the result is always in RAX.
-                    // - The higher 64-bits of the result is always in RDX.
-                    Operand src1 = node.GetSource(0);
-
-                    Operand rax = Gpr(X86Register.Rax, src1.Type);
-                    Operand rdx = Gpr(X86Register.Rdx, src1.Type);
-
-                    nodes.AddBefore(node, Operation(Instruction.Copy, rax, src1));
-
-                    node.SetSource(0, rax);
-
-                    nodes.AddAfter(node, Operation(Instruction.Copy, dest, rdx));
-
-                    node.SetDestinations(new Operand[] { rdx, rax });
-
-                    break;
-                }
-
                 case Instruction.RotateRight:
                 case Instruction.ShiftLeft:
                 case Instruction.ShiftRightSI:
                 case Instruction.ShiftRightUI:
-                {
-                    // The shift register is always implied to be CL (low 8-bits of RCX or ECX).
-                    if (node.GetSource(1).Kind == OperandKind.LocalVariable)
                     {
-                        Operand rcx = Gpr(X86Register.Rcx, OperandType.I32);
+                        // The shift register is always implied to be CL (low 8-bits of RCX or ECX).
+                        if (node.GetSource(1).Kind == OperandKind.LocalVariable)
+                        {
+                            Operand rcx = Gpr(X86Register.Rcx, OperandType.I32);
 
-                        nodes.AddBefore(node, Operation(Instruction.Copy, rcx, node.GetSource(1)));
+                            nodes.AddBefore(node, Operation(Instruction.Copy, rcx, node.GetSource(1)));
 
-                        node.SetSource(1, rcx);
+                            node.SetSource(1, rcx);
+                        }
+
+                        break;
                     }
-
-                    break;
-                }
             }
         }
 
@@ -459,7 +456,7 @@ namespace ARMeilleure.CodeGen.X86
             // Unsigned integer to FP conversions are not supported on X86.
             // We need to turn them into signed integer to FP conversions, and
             // adjust the final result.
-            Operand dest   = node.Destination;
+            Operand dest = node.Destination;
             Operand source = node.GetSource(0);
 
             Debug.Assert(source.Type.IsInteger(), $"Invalid source type \"{source.Type}\".");
@@ -472,8 +469,8 @@ namespace ARMeilleure.CodeGen.X86
                 // and then use the 64-bits signed conversion instructions.
                 Operand zex = Local(OperandType.I64);
 
-                node = nodes.AddAfter(node, Operation(Instruction.ZeroExtend32, zex,  source));
-                node = nodes.AddAfter(node, Operation(Instruction.ConvertToFP,  dest, zex));
+                node = nodes.AddAfter(node, Operation(Instruction.ZeroExtend32, zex, source));
+                nodes.AddAfter(node, Operation(Instruction.ConvertToFP, dest, zex));
             }
             else /* if (source.Type == OperandType.I64) */
             {
@@ -487,15 +484,15 @@ namespace ARMeilleure.CodeGen.X86
                 // --- This can be done efficiently by adding the result to itself.
                 // -- Then, we need to add the least significant bit that was shifted out.
                 // --- We can convert the least significant bit to float, and add it to the result.
-                Operand lsb  = Local(OperandType.I64);
+                Operand lsb = Local(OperandType.I64);
                 Operand half = Local(OperandType.I64);
 
                 Operand lsbF = Local(dest.Type);
 
-                node = nodes.AddAfter(node, Operation(Instruction.Copy, lsb,  source));
+                node = nodes.AddAfter(node, Operation(Instruction.Copy, lsb, source));
                 node = nodes.AddAfter(node, Operation(Instruction.Copy, half, source));
 
-                node = nodes.AddAfter(node, Operation(Instruction.BitwiseAnd,   lsb,  lsb,  Const(1L)));
+                node = nodes.AddAfter(node, Operation(Instruction.BitwiseAnd, lsb, lsb, Const(1L)));
                 node = nodes.AddAfter(node, Operation(Instruction.ShiftRightUI, half, half, Const(1)));
 
                 node = nodes.AddAfter(node, Operation(Instruction.ConvertToFP, lsbF, lsb));
@@ -513,7 +510,7 @@ namespace ARMeilleure.CodeGen.X86
             // There's no SSE FP negate instruction, so we need to transform that into
             // a XOR of the value to be negated with a mask with the highest bit set.
             // This also produces -0 for a negation of the value 0.
-            Operand dest   = node.Destination;
+            Operand dest = node.Destination;
             Operand source = node.GetSource(0);
 
             Debug.Assert(dest.Type == OperandType.FP32 ||
@@ -569,14 +566,14 @@ namespace ARMeilleure.CodeGen.X86
             if ((index & 1) != 0)
             {
                 node = nodes.AddAfter(node, Operation(Instruction.ZeroExtend8, temp1, temp1));
-                node = nodes.AddAfter(node, Operation(Instruction.ShiftLeft,   temp2, temp2, Const(8)));
-                node = nodes.AddAfter(node, Operation(Instruction.BitwiseOr,   temp1, temp1, temp2));
+                node = nodes.AddAfter(node, Operation(Instruction.ShiftLeft, temp2, temp2, Const(8)));
+                node = nodes.AddAfter(node, Operation(Instruction.BitwiseOr, temp1, temp1, temp2));
             }
             else
             {
                 node = nodes.AddAfter(node, Operation(Instruction.ZeroExtend8, temp2, temp2));
-                node = nodes.AddAfter(node, Operation(Instruction.BitwiseAnd,  temp1, temp1, Const(0xff00)));
-                node = nodes.AddAfter(node, Operation(Instruction.BitwiseOr,   temp1, temp1, temp2));
+                node = nodes.AddAfter(node, Operation(Instruction.BitwiseAnd, temp1, temp1, Const(0xff00)));
+                node = nodes.AddAfter(node, Operation(Instruction.BitwiseOr, temp1, temp1, temp2));
             }
 
             Operation vinsOp = Operation(Instruction.VectorInsert16, dest, src1, temp1, Const(index >> 1));
@@ -709,16 +706,11 @@ namespace ARMeilleure.CodeGen.X86
 
         private static bool HasConstSrc1(Instruction inst)
         {
-            switch (inst)
+            return inst switch
             {
-                case Instruction.Copy:
-                case Instruction.LoadArgument:
-                case Instruction.Spill:
-                case Instruction.SpillArg:
-                    return true;
-            }
-
-            return false;
+                Instruction.Copy or Instruction.LoadArgument or Instruction.Spill or Instruction.SpillArg => true,
+                _ => false,
+            };
         }
 
         private static bool HasConstSrc2(Instruction inst)
@@ -762,15 +754,15 @@ namespace ARMeilleure.CodeGen.X86
 
                 case Instruction.BranchIf:
                 case Instruction.Compare:
-                {
-                    Operand comp = operation.GetSource(2);
+                    {
+                        Operand comp = operation.GetSource(2);
 
-                    Debug.Assert(comp.Kind == OperandKind.Constant);
+                        Debug.Assert(comp.Kind == OperandKind.Constant);
 
-                    var compType = (Comparison)comp.AsInt32();
+                        var compType = (Comparison)comp.AsInt32();
 
-                    return compType == Comparison.Equal || compType == Comparison.NotEqual;
-                }
+                        return compType == Comparison.Equal || compType == Comparison.NotEqual;
+                    }
             }
 
             return false;
@@ -793,4 +785,4 @@ namespace ARMeilleure.CodeGen.X86
             return info.Type != IntrinsicType.Crc32;
         }
     }
-}
+}

src/ARMeilleure/CodeGen/X86/PreAllocatorSystemV.cs

@@ -1,4 +1,3 @@
-using ARMeilleure.CodeGen.RegisterAllocators;
 using ARMeilleure.IntermediateRepresentation;
 using ARMeilleure.Translation;
 using System;
@@ -15,9 +14,9 @@ namespace ARMeilleure.CodeGen.X86
         {
             Operand dest = node.Destination;
 
-            List<Operand> sources = new List<Operand>
+            List<Operand> sources = new()
             {
-                node.GetSource(0)
+                node.GetSource(0),
             };
 
             int argsCount = node.SourcesCount - 1;
@@ -52,10 +51,10 @@ namespace ARMeilleure.CodeGen.X86
                 if (source.Type == OperandType.V128 && passOnReg)
                 {
                     // V128 is a struct, we pass each half on a GPR if possible.
-                    Operand argReg  = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64);
+                    Operand argReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64);
                     Operand argReg2 = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64);
 
-                    nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg,  source, Const(0)));
+                    nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg, source, Const(0)));
                     nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg2, source, Const(1)));
 
                     continue;
@@ -91,7 +90,7 @@ namespace ARMeilleure.CodeGen.X86
             {
                 if (dest.Type == OperandType.V128)
                 {
-                    Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(),     OperandType.I64);
+                    Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(), OperandType.I64);
                     Operand retHReg = Gpr(CallingConvention.GetIntReturnRegisterHigh(), OperandType.I64);
 
                     Operation operation = node;
@@ -116,11 +115,11 @@ namespace ARMeilleure.CodeGen.X86
             }
         }
 
-        public static void InsertTailcallCopies(IntrusiveList<Operation> nodes, StackAllocator stackAlloc, Operation node)
+        public static void InsertTailcallCopies(IntrusiveList<Operation> nodes, Operation node)
         {
-            List<Operand> sources = new List<Operand>
+            List<Operand> sources = new()
             {
-                node.GetSource(0)
+                node.GetSource(0),
             };
 
             int argsCount = node.SourcesCount - 1;
@@ -251,11 +250,11 @@ namespace ARMeilleure.CodeGen.X86
                         // V128 is a struct, we pass each half on a GPR if possible.
                         Operand pArg = Local(OperandType.V128);
 
-                        Operand argLReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount),     OperandType.I64);
+                        Operand argLReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount), OperandType.I64);
                         Operand argHReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount + 1), OperandType.I64);
 
                         Operation copyL = Operation(Instruction.VectorCreateScalar, pArg, argLReg);
-                        Operation copyH = Operation(Instruction.VectorInsert,       pArg, pArg, argHReg, Const(1));
+                        Operation copyH = Operation(Instruction.VectorInsert, pArg, pArg, argHReg, Const(1));
 
                         cctx.Cfg.Entry.Operations.AddFirst(copyH);
                         cctx.Cfg.Entry.Operations.AddFirst(copyL);
@@ -313,7 +312,7 @@ namespace ARMeilleure.CodeGen.X86
 
             if (source.Type == OperandType.V128)
             {
-                Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(),     OperandType.I64);
+                Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(), OperandType.I64);
                 Operand retHReg = Gpr(CallingConvention.GetIntReturnRegisterHigh(), OperandType.I64);
 
                 nodes.AddBefore(node, Operation(Instruction.VectorExtract, retLReg, source, Const(0)));
@@ -331,4 +330,4 @@ namespace ARMeilleure.CodeGen.X86
             }
         }
     }
-}
+}

src/ARMeilleure/CodeGen/X86/PreAllocatorWindows.cs

@@ -155,7 +155,7 @@ namespace ARMeilleure.CodeGen.X86
             node.SetSources(sources);
         }
 
-        public static void InsertTailcallCopies(IntrusiveList<Operation> nodes, StackAllocator stackAlloc, Operation node)
+        public static void InsertTailcallCopies(IntrusiveList<Operation> nodes, Operation node)
         {
             int argsCount = node.SourcesCount - 1;
             int maxArgs = CallingConvention.GetArgumentsOnRegsCount();
@@ -324,4 +324,4 @@ namespace ARMeilleure.CodeGen.X86
             node.SetSources(Array.Empty<Operand>());
         }
     }
-}
+}

src/ARMeilleure/CodeGen/X86/X86Condition.cs

@@ -5,22 +5,22 @@ namespace ARMeilleure.CodeGen.X86
 {
     enum X86Condition
     {
-        Overflow       = 0x0,
-        NotOverflow    = 0x1,
-        Below          = 0x2,
-        AboveOrEqual   = 0x3,
-        Equal          = 0x4,
-        NotEqual       = 0x5,
-        BelowOrEqual   = 0x6,
-        Above          = 0x7,
-        Sign           = 0x8,
-        NotSign        = 0x9,
-        ParityEven     = 0xa,
-        ParityOdd      = 0xb,
-        Less           = 0xc,
+        Overflow = 0x0,
+        NotOverflow = 0x1,
+        Below = 0x2,
+        AboveOrEqual = 0x3,
+        Equal = 0x4,
+        NotEqual = 0x5,
+        BelowOrEqual = 0x6,
+        Above = 0x7,
+        Sign = 0x8,
+        NotSign = 0x9,
+        ParityEven = 0xa,
+        ParityOdd = 0xb,
+        Less = 0xc,
         GreaterOrEqual = 0xd,
-        LessOrEqual    = 0xe,
-        Greater        = 0xf
+        LessOrEqual = 0xe,
+        Greater = 0xf,
     }
 
     static class ComparisonX86Extensions
@@ -29,6 +29,7 @@ namespace ARMeilleure.CodeGen.X86
         {
             return comp switch
             {
+#pragma warning disable IDE0055 // Disable formatting
                 Comparison.Equal            => X86Condition.Equal,
                 Comparison.NotEqual         => X86Condition.NotEqual,
                 Comparison.Greater          => X86Condition.Greater,
@@ -39,9 +40,10 @@ namespace ARMeilleure.CodeGen.X86
                 Comparison.Less             => X86Condition.Less,
                 Comparison.GreaterOrEqualUI => X86Condition.AboveOrEqual,
                 Comparison.LessUI           => X86Condition.Below,
+#pragma warning restore IDE0055
 
-                _ => throw new ArgumentException(null, nameof(comp))
+                _ => throw new ArgumentException(null, nameof(comp)),
             };
         }
     }
-}
+}

src/ARMeilleure/CodeGen/X86/X86Instruction.cs

@@ -226,6 +226,6 @@ namespace ARMeilleure.CodeGen.X86
         Xorpd,
         Xorps,
 
-        Count
+        Count,
     }
-}
+}

src/ARMeilleure/CodeGen/X86/X86Optimizer.cs

@@ -215,7 +215,7 @@ namespace ARMeilleure.CodeGen.X86
                         1 => Multiplier.x2,
                         2 => Multiplier.x4,
                         3 => Multiplier.x8,
-                        _ => Multiplier.x1
+                        _ => Multiplier.x1,
                     };
 
                     baseOp = indexOnSrc2 ? src1 : src2;

src/ARMeilleure/CodeGen/X86/X86Register.cs

@@ -1,5 +1,8 @@
+using System.Diagnostics.CodeAnalysis;
+
 namespace ARMeilleure.CodeGen.X86
 {
+    [SuppressMessage("Design", "CA1069: Enums values should not be duplicated")]
     enum X86Register
     {
         Invalid = -1,
@@ -12,8 +15,8 @@ namespace ARMeilleure.CodeGen.X86
         Rbp = 5,
         Rsi = 6,
         Rdi = 7,
-        R8  = 8,
-        R9  = 9,
+        R8 = 8,
+        R9 = 9,
         R10 = 10,
         R11 = 11,
         R12 = 12,
@@ -21,21 +24,21 @@ namespace ARMeilleure.CodeGen.X86
         R14 = 14,
         R15 = 15,
 
-        Xmm0  = 0,
-        Xmm1  = 1,
-        Xmm2  = 2,
-        Xmm3  = 3,
-        Xmm4  = 4,
-        Xmm5  = 5,
-        Xmm6  = 6,
-        Xmm7  = 7,
-        Xmm8  = 8,
-        Xmm9  = 9,
+        Xmm0 = 0,
+        Xmm1 = 1,
+        Xmm2 = 2,
+        Xmm3 = 3,
+        Xmm4 = 4,
+        Xmm5 = 5,
+        Xmm6 = 6,
+        Xmm7 = 7,
+        Xmm8 = 8,
+        Xmm9 = 9,
         Xmm10 = 10,
         Xmm11 = 11,
         Xmm12 = 12,
         Xmm13 = 13,
         Xmm14 = 14,
-        Xmm15 = 15
+        Xmm15 = 15,
     }
-}
+}

src/ARMeilleure/Common/ArenaAllocator.cs

@@ -82,8 +82,10 @@ namespace ARMeilleure.Common
             }
             else
             {
-                _page = new PageInfo();
-                _page.Pointer = (byte*)NativeAllocator.Instance.Allocate(_pageSize);
+                _page = new PageInfo
+                {
+                    Pointer = (byte*)NativeAllocator.Instance.Allocate(_pageSize),
+                };
 
                 _pages.Add(_page);
             }
@@ -106,7 +108,7 @@ namespace ARMeilleure.Common
             // Free excess pages that was allocated.
             while (_pages.Count > _pageCount)
             {
-                NativeAllocator.Instance.Free(_pages[_pages.Count - 1].Pointer);
+                NativeAllocator.Instance.Free(_pages[^1].Pointer);
 
                 _pages.RemoveAt(_pages.Count - 1);
             }
@@ -125,12 +127,13 @@ namespace ARMeilleure.Common
 
             // If arena is used frequently, keep pages for longer. Otherwise keep pages for a shorter amount of time.
             int now = Environment.TickCount;
-            int count = (now - _lastReset) switch {
+            int count = (now - _lastReset) switch
+            {
                 >= 5000 => 0,
                 >= 2500 => 50,
                 >= 1000 => 100,
-                >= 10   => 1500,
-                _       => 5000
+                >= 10 => 1500,
+                _ => 5000,
             };
 
             for (int i = _pages.Count - 1; i >= 0; i--)

src/ARMeilleure/Common/BitMap.cs

@@ -138,7 +138,7 @@ namespace ARMeilleure.Common
                 var newSpan = new Span<long>(_masks, _count);
 
                 oldSpan.CopyTo(newSpan);
-                newSpan.Slice(oldSpan.Length).Clear();
+                newSpan[oldSpan.Length..].Clear();
 
                 _allocator.Free(oldMask);
             }
@@ -176,8 +176,8 @@ namespace ARMeilleure.Common
             private int _bit;
             private readonly BitMap _map;
 
-            public int Current => (int)_index * IntSize + _bit;
-            object IEnumerator.Current => Current;
+            public readonly int Current => (int)_index * IntSize + _bit;
+            readonly object IEnumerator.Current => Current;
 
             public Enumerator(BitMap map)
             {
@@ -214,9 +214,9 @@ namespace ARMeilleure.Common
                 return true;
             }
 
-            public void Reset() { }
+            public readonly void Reset() { }
 
-            public void Dispose() { }
+            public readonly void Dispose() { }
         }
     }
-}
+}

src/ARMeilleure/Decoders/Block.cs

@@ -5,10 +5,10 @@ namespace ARMeilleure.Decoders
 {
     class Block
     {
-        public ulong Address    { get; set; }
+        public ulong Address { get; set; }
         public ulong EndAddress { get; set; }
 
-        public Block Next   { get; set; }
+        public Block Next { get; set; }
         public Block Branch { get; set; }
 
         public bool Exit { get; set; }
@@ -43,14 +43,14 @@ namespace ARMeilleure.Decoders
 
             rightBlock.EndAddress = EndAddress;
 
-            rightBlock.Next   = Next;
+            rightBlock.Next = Next;
             rightBlock.Branch = Branch;
 
             rightBlock.OpCodes.AddRange(OpCodes.GetRange(splitIndex, splitCount));
 
             EndAddress = rightBlock.Address;
 
-            Next   = rightBlock;
+            Next = rightBlock;
             Branch = null;
 
             OpCodes.RemoveRange(splitIndex, splitCount);
@@ -58,9 +58,9 @@ namespace ARMeilleure.Decoders
 
         private static int BinarySearch(List<OpCode> opCodes, ulong address)
         {
-            int left   = 0;
+            int left = 0;
             int middle = 0;
-            int right  = opCodes.Count - 1;
+            int right = opCodes.Count - 1;
 
             while (left <= right)
             {
@@ -92,10 +92,10 @@ namespace ARMeilleure.Decoders
         {
             if (OpCodes.Count > 0)
             {
-                return OpCodes[OpCodes.Count - 1];
+                return OpCodes[^1];
             }
 
             return null;
         }
     }
-}
+}

src/ARMeilleure/Decoders/Condition.cs

@@ -2,22 +2,22 @@ namespace ARMeilleure.Decoders
 {
     enum Condition
     {
-        Eq   = 0,
-        Ne   = 1,
+        Eq = 0,
+        Ne = 1,
         GeUn = 2,
         LtUn = 3,
-        Mi   = 4,
-        Pl   = 5,
-        Vs   = 6,
-        Vc   = 7,
+        Mi = 4,
+        Pl = 5,
+        Vs = 6,
+        Vc = 7,
         GtUn = 8,
         LeUn = 9,
-        Ge   = 10,
-        Lt   = 11,
-        Gt   = 12,
-        Le   = 13,
-        Al   = 14,
-        Nv   = 15
+        Ge = 10,
+        Lt = 11,
+        Gt = 12,
+        Le = 13,
+        Al = 14,
+        Nv = 15,
     }
 
     static class ConditionExtensions
@@ -29,4 +29,4 @@ namespace ARMeilleure.Decoders
             return (Condition)((int)cond ^ 1);
         }
     }
-}
+}

src/ARMeilleure/Decoders/DataOp.cs

@@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders
 {
     enum DataOp
     {
-        Adr        = 0,
+        Adr = 0,
         Arithmetic = 1,
-        Logical    = 2,
-        BitField   = 3
+        Logical = 2,
+        BitField = 3,
     }
-}
+}

src/ARMeilleure/Decoders/Decoder.cs

@@ -20,11 +20,11 @@ namespace ARMeilleure.Decoders
 
         public static Block[] Decode(IMemoryManager memory, ulong address, ExecutionMode mode, bool highCq, DecoderMode dMode)
         {
-            List<Block> blocks = new List<Block>();
+            List<Block> blocks = new();
 
-            Queue<Block> workQueue = new Queue<Block>();
+            Queue<Block> workQueue = new();
 
-            Dictionary<ulong, Block> visited = new Dictionary<ulong, Block>();
+            Dictionary<ulong, Block> visited = new();
 
             Debug.Assert(MaxInstsPerFunctionLowCq <= MaxInstsPerFunction);
 
@@ -163,7 +163,7 @@ namespace ARMeilleure.Decoders
         {
             index = 0;
 
-            int left  = 0;
+            int left = 0;
             int right = blocks.Count - 1;
 
             while (left <= right)
@@ -196,9 +196,9 @@ namespace ARMeilleure.Decoders
 
         private static void FillBlock(
             IMemoryManager memory,
-            ExecutionMode  mode,
-            Block          block,
-            ulong          limitAddress)
+            ExecutionMode mode,
+            Block block,
+            ulong limitAddress)
         {
             ulong address = block.Address;
             int itBlockSize = 0;
@@ -241,12 +241,12 @@ namespace ARMeilleure.Decoders
         private static bool IsUnconditionalBranch(OpCode opCode)
         {
             return opCode is OpCodeBImmAl ||
-                   opCode is OpCodeBReg   || IsAarch32UnconditionalBranch(opCode);
+                   opCode is OpCodeBReg || IsAarch32UnconditionalBranch(opCode);
         }
 
         private static bool IsAarch32UnconditionalBranch(OpCode opCode)
         {
-            if (!(opCode is OpCode32 op))
+            if (opCode is not OpCode32 op)
             {
                 return false;
             }
@@ -290,9 +290,9 @@ namespace ARMeilleure.Decoders
 
                 if (opCode is IOpCode32Mem opMem)
                 {
-                    rt     = opMem.Rt;
-                    rn     = opMem.Rn;
-                    wBack  = opMem.WBack;
+                    rt = opMem.Rt;
+                    rn = opMem.Rn;
+                    wBack = opMem.WBack;
                     isLoad = opMem.IsLoad;
 
                     // For the dual load, we also need to take into account the
@@ -304,12 +304,12 @@ namespace ARMeilleure.Decoders
                 }
                 else if (opCode is IOpCode32MemMult opMemMult)
                 {
-                    const int pcMask = 1 << RegisterAlias.Aarch32Pc;
+                    const int PCMask = 1 << RegisterAlias.Aarch32Pc;
 
-                    rt     = (opMemMult.RegisterMask & pcMask) != 0 ? RegisterAlias.Aarch32Pc : 0;
-                    rn     =  opMemMult.Rn;
-                    wBack  =  opMemMult.PostOffset != 0;
-                    isLoad =  opMemMult.IsLoad;
+                    rt = (opMemMult.RegisterMask & PCMask) != 0 ? RegisterAlias.Aarch32Pc : 0;
+                    rn = opMemMult.Rn;
+                    wBack = opMemMult.PostOffset != 0;
+                    isLoad = opMemMult.IsLoad;
                 }
                 else
                 {
@@ -388,4 +388,4 @@ namespace ARMeilleure.Decoders
             }
         }
     }
-}
+}

src/ARMeilleure/Decoders/DecoderHelper.cs

@@ -10,7 +10,7 @@ namespace ARMeilleure.Decoders
             Imm8ToFP64Table = BuildImm8ToFP64Table();
         }
 
-        public static readonly uint[]  Imm8ToFP32Table;
+        public static readonly uint[] Imm8ToFP32Table;
         public static readonly ulong[] Imm8ToFP64Table;
 
         private static uint[] BuildImm8ToFP32Table()
@@ -40,47 +40,47 @@ namespace ARMeilleure.Decoders
         // abcdefgh -> aBbbbbbc defgh000 00000000 00000000 (B = ~b)
         private static uint ExpandImm8ToFP32(uint imm)
         {
-            uint MoveBit(uint bits, int from, int to)
+            static uint MoveBit(uint bits, int from, int to)
             {
                 return ((bits >> from) & 1U) << to;
             }
 
             return MoveBit(imm, 7, 31) | MoveBit(~imm, 6, 30) |
-                   MoveBit(imm, 6, 29) | MoveBit( imm, 6, 28) |
-                   MoveBit(imm, 6, 27) | MoveBit( imm, 6, 26) |
-                   MoveBit(imm, 6, 25) | MoveBit( imm, 5, 24) |
-                   MoveBit(imm, 4, 23) | MoveBit( imm, 3, 22) |
-                   MoveBit(imm, 2, 21) | MoveBit( imm, 1, 20) |
+                   MoveBit(imm, 6, 29) | MoveBit(imm, 6, 28) |
+                   MoveBit(imm, 6, 27) | MoveBit(imm, 6, 26) |
+                   MoveBit(imm, 6, 25) | MoveBit(imm, 5, 24) |
+                   MoveBit(imm, 4, 23) | MoveBit(imm, 3, 22) |
+                   MoveBit(imm, 2, 21) | MoveBit(imm, 1, 20) |
                    MoveBit(imm, 0, 19);
         }
 
         // abcdefgh -> aBbbbbbb bbcdefgh 00000000 00000000 00000000 00000000 00000000 00000000 (B = ~b)
         private static ulong ExpandImm8ToFP64(ulong imm)
         {
-            ulong MoveBit(ulong bits, int from, int to)
+            static ulong MoveBit(ulong bits, int from, int to)
             {
                 return ((bits >> from) & 1UL) << to;
             }
 
             return MoveBit(imm, 7, 63) | MoveBit(~imm, 6, 62) |
-                   MoveBit(imm, 6, 61) | MoveBit( imm, 6, 60) |
-                   MoveBit(imm, 6, 59) | MoveBit( imm, 6, 58) |
-                   MoveBit(imm, 6, 57) | MoveBit( imm, 6, 56) |
-                   MoveBit(imm, 6, 55) | MoveBit( imm, 6, 54) |
-                   MoveBit(imm, 5, 53) | MoveBit( imm, 4, 52) |
-                   MoveBit(imm, 3, 51) | MoveBit( imm, 2, 50) |
-                   MoveBit(imm, 1, 49) | MoveBit( imm, 0, 48);
+                   MoveBit(imm, 6, 61) | MoveBit(imm, 6, 60) |
+                   MoveBit(imm, 6, 59) | MoveBit(imm, 6, 58) |
+                   MoveBit(imm, 6, 57) | MoveBit(imm, 6, 56) |
+                   MoveBit(imm, 6, 55) | MoveBit(imm, 6, 54) |
+                   MoveBit(imm, 5, 53) | MoveBit(imm, 4, 52) |
+                   MoveBit(imm, 3, 51) | MoveBit(imm, 2, 50) |
+                   MoveBit(imm, 1, 49) | MoveBit(imm, 0, 48);
         }
 
         public struct BitMask
         {
             public long WMask;
             public long TMask;
-            public int  Pos;
-            public int  Shift;
+            public int Pos;
+            public int Shift;
             public bool IsUndefined;
 
-            public static BitMask Invalid => new BitMask { IsUndefined = true };
+            public static BitMask Invalid => new() { IsUndefined = true };
         }
 
         public static BitMask DecodeBitMask(int opCode, bool immediate)
@@ -88,7 +88,7 @@ namespace ARMeilleure.Decoders
             int immS = (opCode >> 10) & 0x3f;
             int immR = (opCode >> 16) & 0x3f;
 
-            int n  = (opCode >> 22) & 1;
+            int n = (opCode >> 22) & 1;
             int sf = (opCode >> 31) & 1;
 
             int length = BitUtils.HighestBitSet((~immS & 0x3f) | (n << 6));
@@ -115,7 +115,7 @@ namespace ARMeilleure.Decoders
 
             if (r > 0)
             {
-                wMask  = BitUtils.RotateRight(wMask, r, size);
+                wMask = BitUtils.RotateRight(wMask, r, size);
                 wMask &= BitUtils.FillWithOnes(size);
             }
 
@@ -124,8 +124,8 @@ namespace ARMeilleure.Decoders
                 WMask = BitUtils.Replicate(wMask, size),
                 TMask = BitUtils.Replicate(tMask, size),
 
-                Pos   = immS,
-                Shift = immR
+                Pos = immS,
+                Shift = immR,
             };
         }
 
@@ -164,4 +164,4 @@ namespace ARMeilleure.Decoders
             return false;
         }
     }
-}
+}

src/ARMeilleure/Decoders/DecoderMode.cs

@@ -6,4 +6,4 @@
         SingleBlock,
         SingleInstruction,
     }
-}
+}

src/ARMeilleure/Decoders/IOpCode.cs

@@ -14,4 +14,4 @@ namespace ARMeilleure.Decoders
 
         OperandType GetOperandType();
     }
-}
+}

src/ARMeilleure/Decoders/IOpCode32.cs

@@ -6,4 +6,4 @@ namespace ARMeilleure.Decoders
 
         uint GetPc();
     }
-}
+}

src/ARMeilleure/Decoders/IOpCode32Alu.cs

@@ -5,4 +5,4 @@ namespace ARMeilleure.Decoders
         int Rd { get; }
         int Rn { get; }
     }
-}
+}

src/ARMeilleure/Decoders/IOpCode32AluImm.cs

@@ -6,4 +6,4 @@
 
         bool IsRotated { get; }
     }
-}
+}

src/ARMeilleure/Decoders/IOpCode32AluImm16.cs

@@ -4,4 +4,4 @@ namespace ARMeilleure.Decoders
     {
         int Immediate { get; }
     }
-}
+}

src/ARMeilleure/Decoders/IOpCode32AluRsImm.cs

@@ -7,4 +7,4 @@
 
         ShiftType ShiftType { get; }
     }
-}
+}

src/ARMeilleure/Decoders/IOpCode32AluRsReg.cs

@@ -7,4 +7,4 @@
 
         ShiftType ShiftType { get; }
     }
-}
+}

src/ARMeilleure/Decoders/IOpCode32BImm.cs

@@ -1,4 +1,4 @@
 namespace ARMeilleure.Decoders
 {
     interface IOpCode32BImm : IOpCode32, IOpCodeBImm { }
-}
+}

src/ARMeilleure/Decoders/IOpCode32BReg.cs

@@ -4,4 +4,4 @@ namespace ARMeilleure.Decoders
     {
         int Rm { get; }
     }
-}
+}

src/ARMeilleure/Decoders/IOpCode32Exception.cs

@@ -4,4 +4,4 @@
     {
         int Id { get; }
     }
-}
+}

src/ARMeilleure/Decoders/IOpCode32HasSetFlags.cs

@@ -4,4 +4,4 @@
     {
         bool? SetFlags { get; }
     }
-}
+}

src/ARMeilleure/Decoders/IOpCode32Mem.cs

@@ -13,4 +13,4 @@ namespace ARMeilleure.Decoders
 
         int Immediate { get; }
     }
-}
+}

src/ARMeilleure/Decoders/IOpCode32MemMult.cs

@@ -12,4 +12,4 @@ namespace ARMeilleure.Decoders
 
         int Offset { get; }
     }
-}
+}

src/ARMeilleure/Decoders/IOpCode32MemReg.cs

@@ -4,4 +4,4 @@
     {
         int Rm { get; }
     }
-}
+}

src/ARMeilleure/Decoders/IOpCode32MemRsImm.cs

@@ -5,4 +5,4 @@ namespace ARMeilleure.Decoders
         int Rm { get; }
         ShiftType ShiftType { get; }
     }
-}
+}

src/ARMeilleure/Decoders/IOpCodeAlu.cs

@@ -7,4 +7,4 @@ namespace ARMeilleure.Decoders
 
         DataOp DataOp { get; }
     }
-}
+}