Implemented in IR the managed methods of the ShlReg region of the SoftFallback class. (#3700)

* Implemented in IR the managed methods of the Saturating region ...

... of the SoftFallback class (the SatQ ones).

The need to natively manage the Fpcr and Fpsr system registers is still a fact.

Contributes to https://github.com/Ryujinx/Ryujinx/issues/2917 ; I will open another PR to implement in Intrinsics-branchless the methods of the Saturation region as well (the SatXXXToXXX ones).

All instructions involved have been tested locally in both release and debug modes, in both lowcq and highcq.

* Ptc.InternalVersion = 3665

* Addressed PR feedback.

* Implemented in IR the managed methods of the ShlReg region of the SoftFallback class.

It also includes the last two SatQ ones (following up on https://github.com/Ryujinx/Ryujinx/pull/3665).

All instructions involved have been tested locally in both release and debug modes, in both lowcq and highcq.

* Update InstEmitSimdHelper.cs

ARMeilleure/Decoders/IOpCode32AluBf.cs

@@ -7,5 +7,8 @@
 
         int Msb { get; }
         int Lsb { get; }
+
+        int SourceMask => (int)(0xFFFFFFFF >> (31 - Msb));
+        int DestMask => SourceMask & (int)(0xFFFFFFFF << Lsb);
     }
 }

ARMeilleure/Decoders/IOpCode32AluImm16.cs

@@ -0,0 +1,7 @@
+namespace ARMeilleure.Decoders
+{
+    interface IOpCode32AluImm16 : IOpCode32Alu
+    {
+        int Immediate { get; }
+    }
+}

ARMeilleure/Decoders/IOpCode32AluMla.cs

@@ -0,0 +1,11 @@
+namespace ARMeilleure.Decoders
+{
+    interface IOpCode32AluMla : IOpCode32AluReg
+    {
+        int Ra { get; }
+
+        bool NHigh { get; }
+        bool MHigh { get; }
+        bool R { get; }
+    }
+}

ARMeilleure/Decoders/IOpCode32AluUmull.cs

@@ -0,0 +1,13 @@
+namespace ARMeilleure.Decoders
+{
+    interface IOpCode32AluUmull : IOpCode32, IOpCode32HasSetFlags
+    {
+        int RdLo { get; }
+        int RdHi { get; }
+        int Rn { get; }
+        int Rm { get; }
+
+        bool NHigh { get; }
+        bool MHigh { get; }
+    }
+}

ARMeilleure/Decoders/OpCode32.cs

@@ -13,16 +13,13 @@ namespace ARMeilleure.Decoders
             Cond = (Condition)((uint)opCode >> 28);
         }
 
-        public bool IsThumb()
-        {
-            return this is OpCodeT16 || this is OpCodeT32;
-        }
+        public bool IsThumb { get; protected init; } = false;
 
         public uint GetPc()
         {
             // Due to backwards compatibility and legacy behavior of ARMv4 CPUs pipeline,
             // the PC actually points 2 instructions ahead.
-            if (IsThumb())
+            if (IsThumb)
             {
                 // PC is ahead by 4 in thumb mode whether or not the current instruction
                 // is 16 or 32 bit.

ARMeilleure/Decoders/OpCode32AluBf.cs

@@ -6,12 +6,8 @@
         public int Rn { get; }
 
         public int Msb { get; }
-
         public int Lsb { get; }
 
-        public int SourceMask => (int)(0xFFFFFFFF >> (31 - Msb));
-        public int DestMask => SourceMask & (int)(0xFFFFFFFF << Lsb);
-
         public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluBf(inst, address, opCode);
 
         public OpCode32AluBf(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)

ARMeilleure/Decoders/OpCode32AluImm16.cs

@@ -1,6 +1,6 @@
 namespace ARMeilleure.Decoders
 {
-    class OpCode32AluImm16 : OpCode32Alu
+    class OpCode32AluImm16 : OpCode32Alu, IOpCode32AluImm16
     {
         public int Immediate { get; }
 

ARMeilleure/Decoders/OpCode32AluMla.cs

@@ -1,6 +1,6 @@
 namespace ARMeilleure.Decoders
 {
-    class OpCode32AluMla : OpCode32, IOpCode32AluReg
+    class OpCode32AluMla : OpCode32, IOpCode32AluMla
     {
         public int Rn { get; }
         public int Rm { get; }

ARMeilleure/Decoders/OpCode32AluUmull.cs

@@ -1,6 +1,6 @@
 namespace ARMeilleure.Decoders
 {
-    class OpCode32AluUmull : OpCode32, IOpCode32HasSetFlags
+    class OpCode32AluUmull : OpCode32, IOpCode32AluUmull
     {
         public int RdLo { get; }
         public int RdHi { get; }
@@ -11,7 +11,6 @@
         public bool MHigh { get; }
 
         public bool? SetFlags { get; }
-        public DataOp DataOp { get; }
 
         public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluUmull(inst, address, opCode);
 
@@ -26,7 +25,6 @@
             MHigh = ((opCode >> 6) & 0x1) == 1;
 
             SetFlags = ((opCode >> 20) & 0x1) != 0;
-            DataOp = DataOp.Arithmetic;
         }
     }
 }

ARMeilleure/Decoders/OpCode32Simd.cs

@@ -7,14 +7,15 @@
         public bool F { get; protected set; }
         public bool U { get; }
 
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Simd(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Simd(inst, address, opCode, false);
+        public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32Simd(inst, address, opCode, true);
 
-        public OpCode32Simd(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32Simd(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
         {
             Size = (opCode >> 20) & 0x3;
             Q = ((opCode >> 6) & 0x1) != 0;
             F = ((opCode >> 10) & 0x1) != 0;
-            U = ((opCode >> 24) & 0x1) != 0;
+            U = ((opCode >> (isThumb ? 28 : 24)) & 0x1) != 0;
             Opc = (opCode >> 7) & 0x3;
 
             RegisterSize = Q ? RegisterSize.Simd128 : RegisterSize.Simd64;

ARMeilleure/Decoders/OpCode32SimdBase.cs

@@ -47,6 +47,9 @@ namespace ARMeilleure.Decoders
             throw new InvalidOperationException();
         }
 
-        public OpCode32SimdBase(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
+        protected OpCode32SimdBase(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
+        {
+            IsThumb = isThumb;
+        }
     }
 }

ARMeilleure/Decoders/OpCode32SimdBinary.cs

@@ -5,9 +5,10 @@
     /// </summary>
     class OpCode32SimdBinary : OpCode32SimdReg
     {
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdBinary(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdBinary(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdBinary(inst, address, opCode, true);
 
-        public OpCode32SimdBinary(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdBinary(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
         {
             Size = 3;
 

ARMeilleure/Decoders/OpCode32SimdCmpZ.cs

@@ -2,9 +2,10 @@
 {
     class OpCode32SimdCmpZ : OpCode32Simd
     {
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCmpZ(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCmpZ(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCmpZ(inst, address, opCode, true);
 
-        public OpCode32SimdCmpZ(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdCmpZ(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
         {
             Size = (opCode >> 18) & 0x3;
 

ARMeilleure/Decoders/OpCode32SimdCvtFI.cs

@@ -2,9 +2,10 @@
 {
     class OpCode32SimdCvtFI : OpCode32SimdS
     {
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCvtFI(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCvtFI(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCvtFI(inst, address, opCode, true);
 
-        public OpCode32SimdCvtFI(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdCvtFI(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
         {
             Opc = (opCode >> 7) & 0x1;
 

ARMeilleure/Decoders/OpCode32SimdDupElem.cs

@@ -4,9 +4,10 @@
     {
         public int Index { get; }
 
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdDupElem(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdDupElem(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdDupElem(inst, address, opCode, true);
 
-        public OpCode32SimdDupElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdDupElem(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
         {
             var opc = (opCode >> 16) & 0xf;
 

ARMeilleure/Decoders/OpCode32SimdDupGP.cs

@@ -7,10 +7,13 @@
         public int Rt { get; }
         public bool Q { get; }
 
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdDupGP(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdDupGP(inst, address, opCode, false);
+        public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdDupGP(inst, address, opCode, true);
 
-        public OpCode32SimdDupGP(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdDupGP(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
         {
+            IsThumb = isThumb;
+
             Size = 2 - (((opCode >> 21) & 0x2) | ((opCode >> 5) & 0x1)); // B:E - 0 for 32, 16 then 8.
             if (Size == -1)
             {

ARMeilleure/Decoders/OpCode32SimdExt.cs

@@ -4,9 +4,10 @@
     {
         public int Immediate { get; }
 
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdExt(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdExt(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdExt(inst, address, opCode, true);
 
-        public OpCode32SimdExt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdExt(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
         {
             Immediate = (opCode >> 8) & 0xf;
             Size = 0;

ARMeilleure/Decoders/OpCode32SimdImm.cs

@@ -6,9 +6,10 @@
         public long Immediate { get; }
         public int Elems => GetBytesCount() >> Size;
 
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm(inst, address, opCode, false);
+        public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm(inst, address, opCode, true);
 
-        public OpCode32SimdImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdImm(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
         {
             Vd = (opCode >> 12) & 0xf;
             Vd |= (opCode >> 18) & 0x10;
@@ -22,7 +23,7 @@
 
             imm = ((uint)opCode >> 0) & 0xf;
             imm |= ((uint)opCode >> 12) & 0x70;
-            imm |= ((uint)opCode >> 17) & 0x80;
+            imm |= ((uint)opCode >> (isThumb ? 21 : 17)) & 0x80;
 
             (Immediate, Size) = OpCodeSimdHelper.GetSimdImmediateAndSize(cMode, op, imm);
 

ARMeilleure/Decoders/OpCode32SimdImm44.cs

@@ -7,10 +7,13 @@
         public int Size { get; }
         public int Elems { get; }
 
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm44(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm44(inst, address, opCode, false);
+        public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm44(inst, address, opCode, true);
 
-        public OpCode32SimdImm44(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdImm44(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
         {
+            IsThumb = isThumb;
+
             Size = (opCode >> 8) & 0x3;
 
             bool single = Size != 3;

ARMeilleure/Decoders/OpCode32SimdLong.cs

@@ -4,9 +4,10 @@
     {
         public bool U { get; }
 
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdLong(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdLong(inst, address, opCode, false);
+        public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdLong(inst, address, opCode, true);
 
-        public OpCode32SimdLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdLong(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
         {
             int imm3h = (opCode >> 19) & 0x7;
 
@@ -18,7 +19,7 @@
                 case 4: Size = 2; break;
             }
 
-            U = ((opCode >> 24) & 0x1) != 0;
+            U = ((opCode >> (isThumb ? 28 : 24)) & 0x1) != 0;
 
             RegisterSize = RegisterSize.Simd64;
 

ARMeilleure/Decoders/OpCode32SimdMemImm.cs

@@ -8,10 +8,13 @@
         public bool Add { get; }
         public int Immediate { get; }
 
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemImm(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemImm(inst, address, opCode, false);
+        public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemImm(inst, address, opCode, true);
 
-        public OpCode32SimdMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdMemImm(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
         {
+            IsThumb = isThumb;
+
             Immediate = opCode & 0xff;
 
             Rn = (opCode >> 16) & 0xf;

ARMeilleure/Decoders/OpCode32SimdMemMult.cs

@@ -12,10 +12,13 @@
         public bool DoubleWidth { get; }
         public bool Add { get; }
 
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemMult(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemMult(inst, address, opCode, false);
+        public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemMult(inst, address, opCode, true);
 
-        public OpCode32SimdMemMult(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdMemMult(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
         {
+            IsThumb = isThumb;
+
             Rn = (opCode >> 16) & 0xf;
 
             bool isLoad = (opCode & (1 << 20)) != 0;

ARMeilleure/Decoders/OpCode32SimdMemPair.cs

@@ -1,11 +1,10 @@
 using ARMeilleure.State;
-using System;
 
 namespace ARMeilleure.Decoders
 {
     class OpCode32SimdMemPair : OpCode32, IOpCode32Simd
     {
-        private static int[] RegsMap =
+        private static int[] _regsMap =
         {
             1, 1, 4, 2,
             1, 1, 3, 1,
@@ -24,10 +23,13 @@ namespace ARMeilleure.Decoders
         public int Regs { get; }
         public int Increment { get; }
 
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemPair(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemPair(inst, address, opCode, false);
+        public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemPair(inst, address, opCode, true);
 
-        public OpCode32SimdMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdMemPair(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
         {
+            IsThumb = isThumb;
+
             Vd = (opCode >> 12) & 0xf;
             Vd |= (opCode >> 18) & 0x10;
 
@@ -40,9 +42,9 @@ namespace ARMeilleure.Decoders
             WBack = Rm != RegisterAlias.Aarch32Pc;
             RegisterIndex = Rm != RegisterAlias.Aarch32Pc && Rm != RegisterAlias.Aarch32Sp;
 
-            Regs = RegsMap[(opCode >> 8) & 0xf];
+            Regs = _regsMap[(opCode >> 8) & 0xf];
 
-            Increment = Math.Min(Regs, ((opCode >> 8) & 0x1) + 1);
+            Increment = ((opCode >> 8) & 0x1) + 1;
         }
     }
 }

ARMeilleure/Decoders/OpCode32SimdMemSingle.cs

@@ -15,10 +15,13 @@ namespace ARMeilleure.Decoders
         public bool Replicate { get; }
         public int Increment { get; }
 
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemSingle(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemSingle(inst, address, opCode, false);
+        public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemSingle(inst, address, opCode, true);
 
-        public OpCode32SimdMemSingle(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdMemSingle(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
         {
+            IsThumb = isThumb;
+
             Vd = (opCode >> 12) & 0xf;
             Vd |= (opCode >> 18) & 0x10;
 

ARMeilleure/Decoders/OpCode32SimdMovGp.cs

@@ -11,10 +11,13 @@
         public int Opc1 { get; }
         public int Opc2 { get; }
 
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGp(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGp(inst, address, opCode, false);
+        public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGp(inst, address, opCode, true);
 
-        public OpCode32SimdMovGp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdMovGp(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
         {
+            IsThumb = isThumb;
+
             // Which one is used is instruction dependant.
             Op = (opCode >> 20) & 0x1;
 

ARMeilleure/Decoders/OpCode32SimdMovGpDouble.cs

@@ -9,10 +9,13 @@
         public int Rt2 { get; }
         public int Op { get; }
 
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpDouble(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpDouble(inst, address, opCode, false);
+        public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpDouble(inst, address, opCode, true);
 
-        public OpCode32SimdMovGpDouble(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdMovGpDouble(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
         {
+            IsThumb = isThumb;
+
             // Which one is used is instruction dependant.
             Op = (opCode >> 20) & 0x1;
 

ARMeilleure/Decoders/OpCode32SimdMovGpElem.cs

@@ -11,10 +11,13 @@
 
         public int Index { get; }
 
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpElem(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpElem(inst, address, opCode, false);
+        public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpElem(inst, address, opCode, true);
 
-        public OpCode32SimdMovGpElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdMovGpElem(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
         {
+            IsThumb = isThumb;
+
             Op = (opCode >> 20) & 0x1;
             U = ((opCode >> 23) & 1) != 0;
 

ARMeilleure/Decoders/OpCode32SimdMovn.cs

@@ -2,9 +2,10 @@ namespace ARMeilleure.Decoders
 {
     class OpCode32SimdMovn : OpCode32Simd
     {
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovn(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovn(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovn(inst, address, opCode, true);
 
-        public OpCode32SimdMovn(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdMovn(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
         {
             Size = (opCode >> 18) & 0x3;
         }

ARMeilleure/Decoders/OpCode32SimdReg.cs

@@ -8,9 +8,10 @@
         public int In => GetQuadwordSubindex(Vn) << (3 - Size);
         public int Fn => GetQuadwordSubindex(Vn) << (1 - (Size & 1));
 
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdReg(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdReg(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdReg(inst, address, opCode, true);
 
-        public OpCode32SimdReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdReg(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
         {
             Vn = ((opCode >> 3) & 0x10) | ((opCode >> 16) & 0xf);
 

ARMeilleure/Decoders/OpCode32SimdRegElem.cs

@@ -2,11 +2,12 @@
 {
     class OpCode32SimdRegElem : OpCode32SimdReg
     {
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElem(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElem(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElem(inst, address, opCode, true);
 
-        public OpCode32SimdRegElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdRegElem(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
         {
-            Q = ((opCode >> 24) & 0x1) != 0;
+            Q = ((opCode >> (isThumb ? 28 : 24)) & 0x1) != 0;
             F = ((opCode >> 8) & 0x1) != 0;
             Size = (opCode >> 20) & 0x3;
 

ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs

@@ -2,9 +2,10 @@
 {
     class OpCode32SimdRegElemLong : OpCode32SimdRegElem
     {
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElemLong(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElemLong(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElemLong(inst, address, opCode, true);
 
-        public OpCode32SimdRegElemLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdRegElemLong(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
         {
             Q = false;
             F = false;

ARMeilleure/Decoders/OpCode32SimdRegLong.cs

@@ -4,9 +4,10 @@
     {
         public bool Polynomial { get; }
 
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegLong(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegLong(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegLong(inst, address, opCode, true);
 
-        public OpCode32SimdRegLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdRegLong(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
         {
             Q = false;
             RegisterSize = RegisterSize.Simd64;

ARMeilleure/Decoders/OpCode32SimdRegS.cs

@@ -4,9 +4,10 @@
     {
         public int Vn { get; }
 
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegS(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegS(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegS(inst, address, opCode, true);
 
-        public OpCode32SimdRegS(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdRegS(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
         {
             bool single = Size != 3;
             if (single)

ARMeilleure/Decoders/OpCode32SimdRegWide.cs

@@ -2,9 +2,10 @@
 {
     class OpCode32SimdRegWide : OpCode32SimdReg
     {
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegWide(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegWide(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegWide(inst, address, opCode, true);
 
-        public OpCode32SimdRegWide(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdRegWide(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
         {
             Q = false;
             RegisterSize = RegisterSize.Simd64;

ARMeilleure/Decoders/OpCode32SimdRev.cs

@@ -2,9 +2,10 @@
 {
     class OpCode32SimdRev : OpCode32SimdCmpZ
     {
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRev(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRev(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRev(inst, address, opCode, true);
 
-        public OpCode32SimdRev(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdRev(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
         {
             if (Opc + Size >= 3)
             {

ARMeilleure/Decoders/OpCode32SimdS.cs

@@ -8,10 +8,13 @@
         public int Opc2 { get; } // opc2 or RM (opc2<1:0>) [Vcvt, Vrint].
         public int Size { get; protected set; }
 
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdS(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdS(inst, address, opCode, false);
+        public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdS(inst, address, opCode, true);
 
-        public OpCode32SimdS(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdS(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
         {
+            IsThumb = isThumb;
+
             Opc = (opCode >> 15) & 0x3;
             Opc2 = (opCode >> 16) & 0x7;
 

ARMeilleure/Decoders/OpCode32SimdSel.cs

@@ -4,9 +4,10 @@
     {
         public OpCode32SimdSelMode Cc { get; }
 
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSel(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSel(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSel(inst, address, opCode, true);
 
-        public OpCode32SimdSel(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdSel(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
         {
             Cc = (OpCode32SimdSelMode)((opCode >> 20) & 3);
         }

ARMeilleure/Decoders/OpCode32SimdShImm.cs

@@ -4,9 +4,10 @@
     {
         public int Shift { get; }
 
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImm(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImm(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImm(inst, address, opCode, true);
 
-        public OpCode32SimdShImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdShImm(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
         {
             int imm6 = (opCode >> 16) & 0x3f;
             int limm6 = ((opCode >> 1) & 0x40) | imm6;

ARMeilleure/Decoders/OpCode32SimdShImmLong.cs

@@ -4,9 +4,10 @@
     {
         public int Shift { get; }
 
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImmLong(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImmLong(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImmLong(inst, address, opCode, true);
 
-        public OpCode32SimdShImmLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdShImmLong(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
         {
             Q = false;
             RegisterSize = RegisterSize.Simd64;

ARMeilleure/Decoders/OpCode32SimdShImmNarrow.cs

@@ -2,8 +2,9 @@
 {
     class OpCode32SimdShImmNarrow : OpCode32SimdShImm
     {
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImmNarrow(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImmNarrow(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImmNarrow(inst, address, opCode, true);
 
-        public OpCode32SimdShImmNarrow(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
+        public OpCode32SimdShImmNarrow(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb) { }
     }
 }

ARMeilleure/Decoders/OpCode32SimdSpecial.cs

@@ -5,10 +5,13 @@
         public int Rt { get; }
         public int Sreg { get; }
 
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSpecial(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSpecial(inst, address, opCode, false);
+        public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSpecial(inst, address, opCode, true);
 
-        public OpCode32SimdSpecial(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdSpecial(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
         {
+            IsThumb = isThumb;
+
             Rt = (opCode >> 12) & 0xf;
             Sreg = (opCode >> 16) & 0xf;
         }

ARMeilleure/Decoders/OpCode32SimdSqrte.cs

@@ -2,9 +2,10 @@
 {
     class OpCode32SimdSqrte : OpCode32Simd
     {
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSqrte(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSqrte(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSqrte(inst, address, opCode, true);
 
-        public OpCode32SimdSqrte(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdSqrte(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
         {
             Size = (opCode >> 18) & 0x1;
             F = ((opCode >> 8) & 0x1) != 0;

ARMeilleure/Decoders/OpCode32SimdTbl.cs

@@ -4,9 +4,10 @@
     {
         public int Length { get; }
 
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdTbl(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdTbl(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdTbl(inst, address, opCode, true);
 
-        public OpCode32SimdTbl(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdTbl(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
         {
             Length = (opCode >> 8) & 3;
             Size = 0;

ARMeilleure/Decoders/OpCodeT16.cs

@@ -8,6 +8,7 @@ namespace ARMeilleure.Decoders
         {
             Cond = Condition.Al;
 
+            IsThumb = true;
             OpCodeSizeInBytes = 2;
         }
     }

ARMeilleure/Decoders/OpCodeT32.cs

@@ -8,6 +8,7 @@
         {
             Cond = Condition.Al;
 
+            IsThumb = true;
             OpCodeSizeInBytes = 4;
         }
     }

ARMeilleure/Decoders/OpCodeT32AluBf.cs

@@ -0,0 +1,22 @@
+namespace ARMeilleure.Decoders
+{
+    class OpCodeT32AluBf : OpCodeT32, IOpCode32AluBf
+    {
+        public int Rd { get; }
+        public int Rn { get; }
+
+        public int Msb { get; }
+        public int Lsb { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32AluBf(inst, address, opCode);
+
+        public OpCodeT32AluBf(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        {
+            Rd = (opCode >> 8) & 0xf;
+            Rn = (opCode >> 16) & 0xf;
+
+            Msb = (opCode >> 0) & 0x1f;
+            Lsb = ((opCode >> 6) & 0x3) | ((opCode >> 10) & 0x1c);
+        }
+    }
+}

ARMeilleure/Decoders/OpCodeT32AluMla.cs

@@ -0,0 +1,29 @@
+namespace ARMeilleure.Decoders
+{
+    class OpCodeT32AluMla : OpCodeT32, IOpCode32AluMla
+    {
+        public int Rn { get; }
+        public int Rm { get; }
+        public int Ra { get; }
+        public int Rd { get; }
+
+        public bool NHigh { get; }
+        public bool MHigh { get; }
+        public bool R { get; }
+        public bool? SetFlags => false;
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32AluMla(inst, address, opCode);
+
+        public OpCodeT32AluMla(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        {
+            Rm = (opCode >> 0) & 0xf;
+            Rd = (opCode >> 8) & 0xf;
+            Ra = (opCode >> 12) & 0xf;
+            Rn = (opCode >> 16) & 0xf;
+            R = (opCode & (1 << 4)) != 0;
+
+            MHigh = ((opCode >> 4) & 0x1) == 1;
+            NHigh = ((opCode >> 5) & 0x1) == 1;
+        }
+    }
+}

ARMeilleure/Decoders/OpCodeT32AluUmull.cs

@@ -0,0 +1,28 @@
+namespace ARMeilleure.Decoders
+{
+    class OpCodeT32AluUmull : OpCodeT32, IOpCode32AluUmull
+    {
+        public int RdLo { get; }
+        public int RdHi { get; }
+        public int Rn { get; }
+        public int Rm { get; }
+
+        public bool NHigh { get; }
+        public bool MHigh { get; }
+
+        public bool? SetFlags => false;
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32AluUmull(inst, address, opCode);
+
+        public OpCodeT32AluUmull(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        {
+            Rm = (opCode >> 0) & 0xf;
+            RdHi = (opCode >> 8) & 0xf;
+            RdLo = (opCode >> 12) & 0xf;
+            Rn = (opCode >> 16) & 0xf;
+
+            MHigh = ((opCode >> 4) & 0x1) == 1;
+            NHigh = ((opCode >> 5) & 0x1) == 1;
+        }
+    }
+}

ARMeilleure/Decoders/OpCodeT32AluUx.cs

@@ -0,0 +1,18 @@
+using ARMeilleure.State;
+
+namespace ARMeilleure.Decoders
+{
+    class OpCodeT32AluUx : OpCodeT32AluReg, IOpCode32AluUx
+    {
+        public int Rotate { get; }
+        public int RotateBits => Rotate * 8;
+        public bool Add => Rn != RegisterAlias.Aarch32Pc;
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32AluUx(inst, address, opCode);
+
+        public OpCodeT32AluUx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        {
+            Rotate = (opCode >> 4) & 0x3;
+        }
+    }
+}

ARMeilleure/Decoders/OpCodeT32BImm24.cs

@@ -27,7 +27,7 @@ namespace ARMeilleure.Decoders
             int i2 = j2 ^ s ^ 1;
 
             int imm32 = imm11 | (imm10 << 11) | (i2 << 21) | (i1 << 22) | (s << 23);
-            imm32 = (imm32 << 9) >> 8;
+            imm32 = (imm32 << 8) >> 7;
 
             Immediate = pc + imm32;
         }

ARMeilleure/Decoders/OpCodeT32MemLdEx.cs

@@ -4,6 +4,7 @@ namespace ARMeilleure.Decoders
     {
         public int Rd => 0;
         public int Rt { get; }
+        public int Rt2 { get; }
         public int Rn { get; }
 
         public bool WBack => false;
@@ -17,6 +18,7 @@ namespace ARMeilleure.Decoders
 
         public OpCodeT32MemLdEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
+            Rt2 = (opCode >> 8) & 0xf;
             Rt = (opCode >> 12) & 0xf;
             Rn = (opCode >> 16) & 0xf;
         }

ARMeilleure/Decoders/OpCodeT32MemStEx.cs

@@ -4,6 +4,7 @@ namespace ARMeilleure.Decoders
     {
         public int Rd { get; }
         public int Rt { get; }
+        public int Rt2 { get; }
         public int Rn { get; }
 
         public bool WBack => false;
@@ -18,6 +19,7 @@ namespace ARMeilleure.Decoders
         public OpCodeT32MemStEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
         {
             Rd = (opCode >> 0) & 0xf;
+            Rt2 = (opCode >> 8) & 0xf;
             Rt = (opCode >> 12) & 0xf;
             Rn = (opCode >> 16) & 0xf;
         }

ARMeilleure/Decoders/OpCodeT32MovImm16.cs

@@ -1,9 +1,6 @@
-using ARMeilleure.Common;
-using System.Runtime.Intrinsics;
-
 namespace ARMeilleure.Decoders
 {
-    class OpCodeT32MovImm16 : OpCodeT32Alu, IOpCode32AluImm
+    class OpCodeT32MovImm16 : OpCodeT32Alu, IOpCode32AluImm16
     {
         public int Immediate { get; }
 

ARMeilleure/Decoders/OpCodeTable.cs

@@ -93,6 +93,7 @@ namespace ARMeilleure.Decoders
             SetA64("00011010110xxxxx010101xxxxxxxxxx", InstName.Crc32ch,         InstEmit.Crc32ch,         OpCodeAluBinary.Create);
             SetA64("00011010110xxxxx010110xxxxxxxxxx", InstName.Crc32cw,         InstEmit.Crc32cw,         OpCodeAluBinary.Create);
             SetA64("10011010110xxxxx010111xxxxxxxxxx", InstName.Crc32cx,         InstEmit.Crc32cx,         OpCodeAluBinary.Create);
+            SetA64("11010101000000110010001010011111", InstName.Csdb,            InstEmit.Csdb,            OpCodeSystem.Create);
             SetA64("x0011010100xxxxxxxxx00xxxxxxxxxx", InstName.Csel,            InstEmit.Csel,            OpCodeCsel.Create);
             SetA64("x0011010100xxxxxxxxx01xxxxxxxxxx", InstName.Csinc,           InstEmit.Csinc,           OpCodeCsel.Create);
             SetA64("x1011010100xxxxxxxxx00xxxxxxxxxx", InstName.Csinv,           InstEmit.Csinv,           OpCodeCsel.Create);
@@ -107,7 +108,6 @@ namespace ARMeilleure.Decoders
             SetA64("11001010xx0xxxxxxxxxxxxxxxxxxxxx", InstName.Eor,             InstEmit.Eor,             OpCodeAluRs.Create);
             SetA64("00010011100xxxxx0xxxxxxxxxxxxxxx", InstName.Extr,            InstEmit.Extr,            OpCodeAluRs.Create);
             SetA64("10010011110xxxxxxxxxxxxxxxxxxxxx", InstName.Extr,            InstEmit.Extr,            OpCodeAluRs.Create);
-            SetA64("11010101000000110010xxxxxxx11111", InstName.Hint,            InstEmit.Hint,            OpCodeSystem.Create);
             SetA64("11010101000000110011xxxx11011111", InstName.Isb,             InstEmit.Isb,             OpCodeSystem.Create);
             SetA64("xx001000110xxxxx1xxxxxxxxxxxxxxx", InstName.Ldar,            InstEmit.Ldar,            OpCodeMemEx.Create);
             SetA64("1x001000011xxxxx1xxxxxxxxxxxxxxx", InstName.Ldaxp,           InstEmit.Ldaxp,           OpCodeMemEx.Create);
@@ -159,6 +159,8 @@ namespace ARMeilleure.Decoders
             SetA64("00010011000xxxxx0xxxxxxxxxxxxxxx", InstName.Sbfm,            InstEmit.Sbfm,            OpCodeBfm.Create);
             SetA64("1001001101xxxxxxxxxxxxxxxxxxxxxx", InstName.Sbfm,            InstEmit.Sbfm,            OpCodeBfm.Create);
             SetA64("x0011010110xxxxx000011xxxxxxxxxx", InstName.Sdiv,            InstEmit.Sdiv,            OpCodeAluBinary.Create);
+            SetA64("11010101000000110010000010011111", InstName.Sev,             InstEmit.Nop,             OpCodeSystem.Create);
+            SetA64("11010101000000110010000010111111", InstName.Sevl,            InstEmit.Nop,             OpCodeSystem.Create);
             SetA64("10011011001xxxxx0xxxxxxxxxxxxxxx", InstName.Smaddl,          InstEmit.Smaddl,          OpCodeMul.Create);
             SetA64("10011011001xxxxx1xxxxxxxxxxxxxxx", InstName.Smsubl,          InstEmit.Smsubl,          OpCodeMul.Create);
             SetA64("10011011010xxxxx0xxxxxxxxxxxxxxx", InstName.Smulh,           InstEmit.Smulh,           OpCodeMul.Create);
@@ -191,6 +193,9 @@ namespace ARMeilleure.Decoders
             SetA64("10011011101xxxxx0xxxxxxxxxxxxxxx", InstName.Umaddl,          InstEmit.Umaddl,          OpCodeMul.Create);
             SetA64("10011011101xxxxx1xxxxxxxxxxxxxxx", InstName.Umsubl,          InstEmit.Umsubl,          OpCodeMul.Create);
             SetA64("10011011110xxxxx0xxxxxxxxxxxxxxx", InstName.Umulh,           InstEmit.Umulh,           OpCodeMul.Create);
+            SetA64("11010101000000110010000001011111", InstName.Wfe,             InstEmit.Nop,             OpCodeSystem.Create);
+            SetA64("11010101000000110010000001111111", InstName.Wfi,             InstEmit.Nop,             OpCodeSystem.Create);
+            SetA64("11010101000000110010000000111111", InstName.Yield,           InstEmit.Nop,             OpCodeSystem.Create);
 
             // FP & SIMD
             SetA64("0101111011100000101110xxxxxxxxxx", InstName.Abs_S,           InstEmit.Abs_S,           OpCodeSimd.Create);
@@ -669,6 +674,17 @@ namespace ARMeilleure.Decoders
             SetA32("<<<<0010001xxxxxxxxxxxxxxxxxxxxx", InstName.Eor,     InstEmit32.Eor,     OpCode32AluImm.Create);
             SetA32("<<<<0000001xxxxxxxxxxxxxxxx0xxxx", InstName.Eor,     InstEmit32.Eor,     OpCode32AluRsImm.Create);
             SetA32("<<<<0000001xxxxxxxxxxxxx0xx1xxxx", InstName.Eor,     InstEmit32.Eor,     OpCode32AluRsReg.Create);
+            SetA32("<<<<0011001000001111000000010000", InstName.Esb,     InstEmit32.Nop,     OpCode32.Create); // Error Synchronization Barrier (FEAT_RAS)
+            SetA32("<<<<001100100000111100000000011x", InstName.Hint,    InstEmit32.Nop,     OpCode32.Create); // Reserved Hint
+            SetA32("<<<<0011001000001111000000001xxx", InstName.Hint,    InstEmit32.Nop,     OpCode32.Create); // Reserved Hint
+            SetA32("<<<<0011001000001111000000010001", InstName.Hint,    InstEmit32.Nop,     OpCode32.Create); // Reserved Hint
+            SetA32("<<<<0011001000001111000000010011", InstName.Hint,    InstEmit32.Nop,     OpCode32.Create); // Reserved Hint
+            SetA32("<<<<0011001000001111000000010101", InstName.Hint,    InstEmit32.Nop,     OpCode32.Create); // Reserved Hint
+            SetA32("<<<<001100100000111100000001011x", InstName.Hint,    InstEmit32.Nop,     OpCode32.Create); // Reserved Hint
+            SetA32("<<<<0011001000001111000000011xxx", InstName.Hint,    InstEmit32.Nop,     OpCode32.Create); // Reserved Hint
+            SetA32("<<<<00110010000011110000001xxxxx", InstName.Hint,    InstEmit32.Nop,     OpCode32.Create); // Reserved Hint
+            SetA32("<<<<0011001000001111000001xxxxxx", InstName.Hint,    InstEmit32.Nop,     OpCode32.Create); // Reserved Hint
+            SetA32("<<<<001100100000111100001xxxxxxx", InstName.Hint,    InstEmit32.Nop,     OpCode32.Create); // Reserved Hint
             SetA32("1111010101111111111100000110xxxx", InstName.Isb,     InstEmit32.Nop,     OpCode32.Create);
             SetA32("<<<<00011001xxxxxxxx110010011111", InstName.Lda,     InstEmit32.Lda,     OpCode32MemLdEx.Create);
             SetA32("<<<<00011101xxxxxxxx110010011111", InstName.Ldab,    InstEmit32.Ldab,    OpCode32MemLdEx.Create);
@@ -727,11 +743,15 @@ namespace ARMeilleure.Decoders
             SetA32("<<<<0010111xxxxxxxxxxxxxxxxxxxxx", InstName.Rsc,     InstEmit32.Rsc,     OpCode32AluImm.Create);
             SetA32("<<<<0000111xxxxxxxxxxxxxxxx0xxxx", InstName.Rsc,     InstEmit32.Rsc,     OpCode32AluRsImm.Create);
             SetA32("<<<<0000111xxxxxxxxxxxxx0xx1xxxx", InstName.Rsc,     InstEmit32.Rsc,     OpCode32AluRsReg.Create);
+            SetA32("<<<<01100001xxxxxxxx11111001xxxx", InstName.Sadd8,   InstEmit32.Sadd8,   OpCode32AluReg.Create);
             SetA32("<<<<0010110xxxxxxxxxxxxxxxxxxxxx", InstName.Sbc,     InstEmit32.Sbc,     OpCode32AluImm.Create);
             SetA32("<<<<0000110xxxxxxxxxxxxxxxx0xxxx", InstName.Sbc,     InstEmit32.Sbc,     OpCode32AluRsImm.Create);
             SetA32("<<<<0000110xxxxxxxxxxxxx0xx1xxxx", InstName.Sbc,     InstEmit32.Sbc,     OpCode32AluRsReg.Create);
             SetA32("<<<<0111101xxxxxxxxxxxxxx101xxxx", InstName.Sbfx,    InstEmit32.Sbfx,    OpCode32AluBf.Create);
             SetA32("<<<<01110001xxxx1111xxxx0001xxxx", InstName.Sdiv,    InstEmit32.Sdiv,    OpCode32AluMla.Create);
+            SetA32("<<<<01101000xxxxxxxx11111011xxxx", InstName.Sel,     InstEmit32.Sel,     OpCode32AluReg.Create);
+            SetA32("<<<<0011001000001111000000000100", InstName.Sev,     InstEmit32.Nop,     OpCode32.Create);
+            SetA32("<<<<0011001000001111000000000101", InstName.Sevl,    InstEmit32.Nop,     OpCode32.Create);
             SetA32("<<<<01100011xxxxxxxx11111001xxxx", InstName.Shadd8,  InstEmit32.Shadd8,  OpCode32AluReg.Create);
             SetA32("<<<<01100011xxxxxxxx11111111xxxx", InstName.Shsub8,  InstEmit32.Shsub8,  OpCode32AluReg.Create);
             SetA32("<<<<00010000xxxxxxxxxxxx1xx0xxxx", InstName.Smla__,  InstEmit32.Smla__,  OpCode32AluMla.Create);
@@ -745,6 +765,7 @@ namespace ARMeilleure.Decoders
             SetA32("<<<<00010010xxxx0000xxxx1x10xxxx", InstName.Smulw_,  InstEmit32.Smulw_,  OpCode32AluMla.Create);
             SetA32("<<<<0110101xxxxxxxxxxxxxxx01xxxx", InstName.Ssat,    InstEmit32.Ssat,    OpCode32Sat.Create);
             SetA32("<<<<01101010xxxxxxxx11110011xxxx", InstName.Ssat16,  InstEmit32.Ssat16,  OpCode32Sat16.Create);
+            SetA32("<<<<01100001xxxxxxxx11111111xxxx", InstName.Ssub8,   InstEmit32.Ssub8,   OpCode32AluReg.Create);
             SetA32("<<<<00011000xxxx111111001001xxxx", InstName.Stl,     InstEmit32.Stl,     OpCode32MemStEx.Create);
             SetA32("<<<<00011100xxxx111111001001xxxx", InstName.Stlb,    InstEmit32.Stlb,    OpCode32MemStEx.Create);
             SetA32("<<<<00011000xxxxxxxx11101001xxxx", InstName.Stlex,   InstEmit32.Stlex,   OpCode32MemStEx.Create);
@@ -776,9 +797,11 @@ namespace ARMeilleure.Decoders
             SetA32("<<<<00010011xxxx0000xxxxxxx0xxxx", InstName.Teq,     InstEmit32.Teq,     OpCode32AluRsImm.Create);
             SetA32("<<<<00010011xxxx0000xxxx0xx1xxxx", InstName.Teq,     InstEmit32.Teq,     OpCode32AluRsReg.Create);
             SetA32("<<<<0111111111111101111011111110", InstName.Trap,    InstEmit32.Trap,    OpCode32Exception.Create);
+            SetA32("<<<<0011001000001111000000010010", InstName.Tsb,     InstEmit32.Nop,     OpCode32.Create); // Trace Synchronization Barrier (FEAT_TRF)
             SetA32("<<<<00110001xxxx0000xxxxxxxxxxxx", InstName.Tst,     InstEmit32.Tst,     OpCode32AluImm.Create);
             SetA32("<<<<00010001xxxx0000xxxxxxx0xxxx", InstName.Tst,     InstEmit32.Tst,     OpCode32AluRsImm.Create);
             SetA32("<<<<00010001xxxx0000xxxx0xx1xxxx", InstName.Tst,     InstEmit32.Tst,     OpCode32AluRsReg.Create);
+            SetA32("<<<<01100101xxxxxxxx11111001xxxx", InstName.Uadd8,   InstEmit32.Uadd8,   OpCode32AluReg.Create);
             SetA32("<<<<0111111xxxxxxxxxxxxxx101xxxx", InstName.Ubfx,    InstEmit32.Ubfx,    OpCode32AluBf.Create);
             SetA32("<<<<01110011xxxx1111xxxx0001xxxx", InstName.Udiv,    InstEmit32.Udiv,    OpCode32AluMla.Create);
             SetA32("<<<<01100111xxxxxxxx11111001xxxx", InstName.Uhadd8,  InstEmit32.Uhadd8,  OpCode32AluReg.Create);
@@ -788,207 +811,237 @@ namespace ARMeilleure.Decoders
             SetA32("<<<<0000100xxxxxxxxxxxxx1001xxxx", InstName.Umull,   InstEmit32.Umull,   OpCode32AluUmull.Create);
             SetA32("<<<<0110111xxxxxxxxxxxxxxx01xxxx", InstName.Usat,    InstEmit32.Usat,    OpCode32Sat.Create);
             SetA32("<<<<01101110xxxxxxxx11110011xxxx", InstName.Usat16,  InstEmit32.Usat16,  OpCode32Sat16.Create);
+            SetA32("<<<<01100101xxxxxxxx11111111xxxx", InstName.Usub8,   InstEmit32.Usub8,   OpCode32AluReg.Create);
             SetA32("<<<<01101110xxxxxxxxxx000111xxxx", InstName.Uxtb,    InstEmit32.Uxtb,    OpCode32AluUx.Create);
             SetA32("<<<<01101100xxxxxxxxxx000111xxxx", InstName.Uxtb16,  InstEmit32.Uxtb16,  OpCode32AluUx.Create);
             SetA32("<<<<01101111xxxxxxxxxx000111xxxx", InstName.Uxth,    InstEmit32.Uxth,    OpCode32AluUx.Create);
+            SetA32("<<<<0011001000001111000000000010", InstName.Wfe,     InstEmit32.Nop,     OpCode32.Create);
+            SetA32("<<<<0011001000001111000000000011", InstName.Wfi,     InstEmit32.Nop,     OpCode32.Create);
+            SetA32("<<<<0011001000001111000000000001", InstName.Yield,   InstEmit32.Nop,     OpCode32.Create);
 
-            // FP & SIMD
-            SetA32("111100111x110000xxx0001101x0xxx0", InstName.Aesd_V,      InstEmit32.Aesd_V,      OpCode32Simd.Create);
-            SetA32("111100111x110000xxx0001100x0xxx0", InstName.Aese_V,      InstEmit32.Aese_V,      OpCode32Simd.Create);
-            SetA32("111100111x110000xxx0001111x0xxx0", InstName.Aesimc_V,    InstEmit32.Aesimc_V,    OpCode32Simd.Create);
-            SetA32("111100111x110000xxx0001110x0xxx0", InstName.Aesmc_V,     InstEmit32.Aesmc_V,     OpCode32Simd.Create);
-            SetA32("111100110x00xxx0xxx01100x1x0xxx0", InstName.Sha256h_V,   InstEmit32.Sha256h_V,   OpCode32SimdReg.Create);
-            SetA32("111100110x01xxx0xxx01100x1x0xxx0", InstName.Sha256h2_V,  InstEmit32.Sha256h2_V,  OpCode32SimdReg.Create);
-            SetA32("111100111x111010xxx0001111x0xxx0", InstName.Sha256su0_V, InstEmit32.Sha256su0_V, OpCode32Simd.Create);
-            SetA32("111100110x10xxx0xxx01100x1x0xxx0", InstName.Sha256su1_V, InstEmit32.Sha256su1_V, OpCode32SimdReg.Create);
-            SetA32("1111001x0x<<xxxxxxxx0111xxx0xxxx", InstName.Vabd,        InstEmit32.Vabd_I,      OpCode32SimdReg.Create);
-            SetA32("1111001x1x<<xxxxxxxx0111x0x0xxxx", InstName.Vabdl,       InstEmit32.Vabdl_I,     OpCode32SimdRegLong.Create);
-            SetA32("<<<<11101x110000xxxx101x11x0xxxx", InstName.Vabs,        InstEmit32.Vabs_S,      OpCode32SimdS.Create);
-            SetA32("111100111x11<<01xxxx00110xx0xxxx", InstName.Vabs,        InstEmit32.Vabs_V,      OpCode32SimdCmpZ.Create);
-            SetA32("111100111x111001xxxx01110xx0xxxx", InstName.Vabs,        InstEmit32.Vabs_V,      OpCode32SimdCmpZ.Create);
-            SetA32("111100100xxxxxxxxxxx1000xxx0xxxx", InstName.Vadd,        InstEmit32.Vadd_I,      OpCode32SimdReg.Create);
-            SetA32("<<<<11100x11xxxxxxxx101xx0x0xxxx", InstName.Vadd,        InstEmit32.Vadd_S,      OpCode32SimdRegS.Create);
-            SetA32("111100100x00xxxxxxxx1101xxx0xxxx", InstName.Vadd,        InstEmit32.Vadd_V,      OpCode32SimdReg.Create);
-            SetA32("1111001x1x<<xxxxxxx00000x0x0xxxx", InstName.Vaddl,       InstEmit32.Vaddl_I,     OpCode32SimdRegLong.Create);
-            SetA32("1111001x1x<<xxxxxxx00001x0x0xxxx", InstName.Vaddw,       InstEmit32.Vaddw_I,     OpCode32SimdRegWide.Create);
-            SetA32("111100100x00xxxxxxxx0001xxx1xxxx", InstName.Vand,        InstEmit32.Vand_I,      OpCode32SimdBinary.Create);
-            SetA32("111100100x01xxxxxxxx0001xxx1xxxx", InstName.Vbic,        InstEmit32.Vbic_I,      OpCode32SimdBinary.Create);
-            SetA32("1111001x1x000xxxxxxx<<x10x11xxxx", InstName.Vbic,        InstEmit32.Vbic_II,     OpCode32SimdImm.Create);
-            SetA32("111100110x11xxxxxxxx0001xxx1xxxx", InstName.Vbif,        InstEmit32.Vbif,        OpCode32SimdBinary.Create);
-            SetA32("111100110x10xxxxxxxx0001xxx1xxxx", InstName.Vbit,        InstEmit32.Vbit,        OpCode32SimdBinary.Create);
-            SetA32("111100110x01xxxxxxxx0001xxx1xxxx", InstName.Vbsl,        InstEmit32.Vbsl,        OpCode32SimdBinary.Create);
-            SetA32("111100110x<<xxxxxxxx1000xxx1xxxx", InstName.Vceq,        InstEmit32.Vceq_I,      OpCode32SimdReg.Create);
-            SetA32("111100100x00xxxxxxxx1110xxx0xxxx", InstName.Vceq,        InstEmit32.Vceq_V,      OpCode32SimdReg.Create);
-            SetA32("111100111x11xx01xxxx0x010xx0xxxx", InstName.Vceq,        InstEmit32.Vceq_Z,      OpCode32SimdCmpZ.Create);
-            SetA32("1111001x0x<<xxxxxxxx0011xxx1xxxx", InstName.Vcge,        InstEmit32.Vcge_I,      OpCode32SimdReg.Create);
-            SetA32("111100110x00xxxxxxxx1110xxx0xxxx", InstName.Vcge,        InstEmit32.Vcge_V,      OpCode32SimdReg.Create);
-            SetA32("111100111x11xx01xxxx0x001xx0xxxx", InstName.Vcge,        InstEmit32.Vcge_Z,      OpCode32SimdCmpZ.Create);
-            SetA32("1111001x0x<<xxxxxxxx0011xxx0xxxx", InstName.Vcgt,        InstEmit32.Vcgt_I,      OpCode32SimdReg.Create);
-            SetA32("111100110x10xxxxxxxx1110xxx0xxxx", InstName.Vcgt,        InstEmit32.Vcgt_V,      OpCode32SimdReg.Create);
-            SetA32("111100111x11xx01xxxx0x000xx0xxxx", InstName.Vcgt,        InstEmit32.Vcgt_Z,      OpCode32SimdCmpZ.Create);
-            SetA32("111100111x11xx01xxxx0x011xx0xxxx", InstName.Vcle,        InstEmit32.Vcle_Z,      OpCode32SimdCmpZ.Create);
-            SetA32("111100111x11xx01xxxx0x100xx0xxxx", InstName.Vclt,        InstEmit32.Vclt_Z,      OpCode32SimdCmpZ.Create);
-            SetA32("<<<<11101x11010xxxxx101x01x0xxxx", InstName.Vcmp,        InstEmit32.Vcmp,        OpCode32SimdS.Create);
-            SetA32("<<<<11101x11010xxxxx101x11x0xxxx", InstName.Vcmpe,       InstEmit32.Vcmpe,       OpCode32SimdS.Create);
-            SetA32("111100111x110000xxxx01010xx0xxxx", InstName.Vcnt,        InstEmit32.Vcnt,        OpCode32SimdCmpZ.Create);
-            SetA32("<<<<11101x110111xxxx101x11x0xxxx", InstName.Vcvt,        InstEmit32.Vcvt_FD,     OpCode32SimdS.Create); // FP 32 and 64, scalar.
-            SetA32("<<<<11101x11110xxxxx101x11x0xxxx", InstName.Vcvt,        InstEmit32.Vcvt_FI,     OpCode32SimdCvtFI.Create); // FP32 to int.
-            SetA32("<<<<11101x111000xxxx101xx1x0xxxx", InstName.Vcvt,        InstEmit32.Vcvt_FI,     OpCode32SimdCvtFI.Create); // Int to FP32.
-            SetA32("111111101x1111xxxxxx101xx1x0xxxx", InstName.Vcvt,        InstEmit32.Vcvt_RM,     OpCode32SimdCvtFI.Create); // The many FP32 to int encodings (fp).
-            SetA32("111100111x111011xxxx011xxxx0xxxx", InstName.Vcvt,        InstEmit32.Vcvt_V,      OpCode32SimdCmpZ.Create); // FP and integer, vector.
-            SetA32("<<<<11101x00xxxxxxxx101xx0x0xxxx", InstName.Vdiv,        InstEmit32.Vdiv_S,      OpCode32SimdRegS.Create);
-            SetA32("<<<<11101xx0xxxxxxxx1011x0x10000", InstName.Vdup,        InstEmit32.Vdup,        OpCode32SimdDupGP.Create);
-            SetA32("111100111x11xxxxxxxx11000xx0xxxx", InstName.Vdup,        InstEmit32.Vdup_1,      OpCode32SimdDupElem.Create);
-            SetA32("111100110x00xxxxxxxx0001xxx1xxxx", InstName.Veor,        InstEmit32.Veor_I,      OpCode32SimdBinary.Create);
-            SetA32("111100101x11xxxxxxxxxxxxxxx0xxxx", InstName.Vext,        InstEmit32.Vext,        OpCode32SimdExt.Create);
-            SetA32("<<<<11101x10xxxxxxxx101xx0x0xxxx", InstName.Vfma,        InstEmit32.Vfma_S,      OpCode32SimdRegS.Create);
-            SetA32("111100100x00xxxxxxxx1100xxx1xxxx", InstName.Vfma,        InstEmit32.Vfma_V,      OpCode32SimdReg.Create);
-            SetA32("<<<<11101x10xxxxxxxx101xx1x0xxxx", InstName.Vfms,        InstEmit32.Vfms_S,      OpCode32SimdRegS.Create);
-            SetA32("111100100x10xxxxxxxx1100xxx1xxxx", InstName.Vfms,        InstEmit32.Vfms_V,      OpCode32SimdReg.Create);
-            SetA32("<<<<11101x01xxxxxxxx101xx1x0xxxx", InstName.Vfnma,       InstEmit32.Vfnma_S,     OpCode32SimdRegS.Create);
-            SetA32("<<<<11101x01xxxxxxxx101xx0x0xxxx", InstName.Vfnms,       InstEmit32.Vfnms_S,     OpCode32SimdRegS.Create);
-            SetA32("1111001x0x<<xxxxxxxx0000xxx0xxxx", InstName.Vhadd,       InstEmit32.Vhadd,       OpCode32SimdReg.Create);
-            SetA32("111101001x10xxxxxxxxxx00xxxxxxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemSingle.Create);
-            SetA32("111101000x10xxxxxxxx0111xxxxxxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemPair.Create); // Regs = 1.
-            SetA32("111101000x10xxxxxxxx1010xxxxxxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemPair.Create); // Regs = 2.
-            SetA32("111101000x10xxxxxxxx0110xxxxxxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemPair.Create); // Regs = 3.
-            SetA32("111101000x10xxxxxxxx0010xxxxxxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemPair.Create); // Regs = 4.
-            SetA32("111101001x10xxxxxxxxxx01xxxxxxxx", InstName.Vld2,        InstEmit32.Vld2,        OpCode32SimdMemSingle.Create);
-            SetA32("111101000x10xxxxxxxx100xxxxxxxxx", InstName.Vld2,        InstEmit32.Vld2,        OpCode32SimdMemPair.Create); // Regs = 1, inc = 1/2 (itype).
-            SetA32("111101000x10xxxxxxxx0011xxxxxxxx", InstName.Vld2,        InstEmit32.Vld2,        OpCode32SimdMemPair.Create); // Regs = 2, inc = 2.
-            SetA32("111101001x10xxxxxxxxxx10xxxxxxxx", InstName.Vld3,        InstEmit32.Vld3,        OpCode32SimdMemSingle.Create);
-            SetA32("111101000x10xxxxxxxx010xxxxxxxxx", InstName.Vld3,        InstEmit32.Vld3,        OpCode32SimdMemPair.Create); // Inc = 1/2 (itype).
-            SetA32("111101001x10xxxxxxxxxx11xxxxxxxx", InstName.Vld4,        InstEmit32.Vld4,        OpCode32SimdMemSingle.Create);
-            SetA32("111101000x10xxxxxxxx000xxxxxxxxx", InstName.Vld4,        InstEmit32.Vld4,        OpCode32SimdMemPair.Create); // Inc = 1/2 (itype).
-            SetA32("<<<<11001x01xxxxxxxx1011xxxxxxx0", InstName.Vldm,        InstEmit32.Vldm,        OpCode32SimdMemMult.Create);
-            SetA32("<<<<11001x11xxxxxxxx1011xxxxxxx0", InstName.Vldm,        InstEmit32.Vldm,        OpCode32SimdMemMult.Create);
-            SetA32("<<<<11010x11xxxxxxxx1011xxxxxxx0", InstName.Vldm,        InstEmit32.Vldm,        OpCode32SimdMemMult.Create);
-            SetA32("<<<<11001x01xxxxxxxx1010xxxxxxxx", InstName.Vldm,        InstEmit32.Vldm,        OpCode32SimdMemMult.Create);
-            SetA32("<<<<11001x11xxxxxxxx1010xxxxxxxx", InstName.Vldm,        InstEmit32.Vldm,        OpCode32SimdMemMult.Create);
-            SetA32("<<<<11010x11xxxxxxxx1010xxxxxxxx", InstName.Vldm,        InstEmit32.Vldm,        OpCode32SimdMemMult.Create);
-            SetA32("<<<<1101xx01xxxxxxxx101xxxxxxxxx", InstName.Vldr,        InstEmit32.Vldr,        OpCode32SimdMemImm.Create);
-            SetA32("1111001x0x<<xxxxxxxx0110xxx0xxxx", InstName.Vmax,        InstEmit32.Vmax_I,      OpCode32SimdReg.Create);
-            SetA32("111100100x00xxxxxxxx1111xxx0xxxx", InstName.Vmax,        InstEmit32.Vmax_V,      OpCode32SimdReg.Create);
-            SetA32("1111001x0x<<xxxxxxxx0110xxx1xxxx", InstName.Vmin,        InstEmit32.Vmin_I,      OpCode32SimdReg.Create);
-            SetA32("111100100x10xxxxxxxx1111xxx0xxxx", InstName.Vmin,        InstEmit32.Vmin_V,      OpCode32SimdReg.Create);
-            SetA32("111111101x00xxxxxxxx10>>x0x0xxxx", InstName.Vmaxnm,      InstEmit32.Vmaxnm_S,    OpCode32SimdRegS.Create);
-            SetA32("111100110x0xxxxxxxxx1111xxx1xxxx", InstName.Vmaxnm,      InstEmit32.Vmaxnm_V,    OpCode32SimdReg.Create);
-            SetA32("111111101x00xxxxxxxx10>>x1x0xxxx", InstName.Vminnm,      InstEmit32.Vminnm_S,    OpCode32SimdRegS.Create);
-            SetA32("111100110x1xxxxxxxxx1111xxx1xxxx", InstName.Vminnm,      InstEmit32.Vminnm_V,    OpCode32SimdReg.Create);
-            SetA32("1111001x1x<<xxxxxxxx000xx1x0xxxx", InstName.Vmla,        InstEmit32.Vmla_1,      OpCode32SimdRegElem.Create);
-            SetA32("111100100xxxxxxxxxxx1001xxx0xxxx", InstName.Vmla,        InstEmit32.Vmla_I,      OpCode32SimdReg.Create);
-            SetA32("<<<<11100x00xxxxxxxx101xx0x0xxxx", InstName.Vmla,        InstEmit32.Vmla_S,      OpCode32SimdRegS.Create);
-            SetA32("111100100x00xxxxxxxx1101xxx1xxxx", InstName.Vmla,        InstEmit32.Vmla_V,      OpCode32SimdReg.Create);
-            SetA32("1111001x1x<<xxxxxxx01000x0x0xxxx", InstName.Vmlal,       InstEmit32.Vmlal_I,     OpCode32SimdRegLong.Create);
-            SetA32("1111001x1x<<xxxxxxxx010xx1x0xxxx", InstName.Vmls,        InstEmit32.Vmls_1,      OpCode32SimdRegElem.Create);
-            SetA32("<<<<11100x00xxxxxxxx101xx1x0xxxx", InstName.Vmls,        InstEmit32.Vmls_S,      OpCode32SimdRegS.Create);
-            SetA32("111100100x10xxxxxxxx1101xxx1xxxx", InstName.Vmls,        InstEmit32.Vmls_V,      OpCode32SimdReg.Create);
-            SetA32("111100110xxxxxxxxxxx1001xxx0xxxx", InstName.Vmls,        InstEmit32.Vmls_I,      OpCode32SimdReg.Create);
-            SetA32("1111001x1x<<xxxxxxx01010x0x0xxxx", InstName.Vmlsl,       InstEmit32.Vmlsl_I,     OpCode32SimdRegLong.Create);
-            SetA32("<<<<11100xx0xxxxxxxx1011xxx10000", InstName.Vmov,        InstEmit32.Vmov_G1,     OpCode32SimdMovGpElem.Create); // From gen purpose.
-            SetA32("<<<<1110xxx1xxxxxxxx1011xxx10000", InstName.Vmov,        InstEmit32.Vmov_G1,     OpCode32SimdMovGpElem.Create); // To gen purpose.
-            SetA32("<<<<1100010xxxxxxxxx101000x1xxxx", InstName.Vmov,        InstEmit32.Vmov_G2,     OpCode32SimdMovGpDouble.Create); // To/from gen purpose x2 and single precision x2.
-            SetA32("<<<<1100010xxxxxxxxx101100x1xxxx", InstName.Vmov,        InstEmit32.Vmov_GD,     OpCode32SimdMovGpDouble.Create); // To/from gen purpose x2 and double precision.
-            SetA32("<<<<1110000xxxxxxxxx1010x0010000", InstName.Vmov,        InstEmit32.Vmov_GS,     OpCode32SimdMovGp.Create); // To/from gen purpose and single precision.
-            SetA32("1111001x1x000xxxxxxx0xx00x01xxxx", InstName.Vmov,        InstEmit32.Vmov_I,      OpCode32SimdImm.Create); // D/Q vector I32.
-            SetA32("<<<<11101x11xxxxxxxx101x0000xxxx", InstName.Vmov,        InstEmit32.Vmov_I,      OpCode32SimdImm44.Create); // Scalar f16/32/64 based on size 01 10 11.
-            SetA32("1111001x1x000xxxxxxx10x00x01xxxx", InstName.Vmov,        InstEmit32.Vmov_I,      OpCode32SimdImm.Create); // D/Q I16.
-            SetA32("1111001x1x000xxxxxxx11xx0x01xxxx", InstName.Vmov,        InstEmit32.Vmov_I,      OpCode32SimdImm.Create); // D/Q (dt - from cmode).
-            SetA32("1111001x1x000xxxxxxx11100x11xxxx", InstName.Vmov,        InstEmit32.Vmov_I,      OpCode32SimdImm.Create); // D/Q I64.
-            SetA32("<<<<11101x110000xxxx101x01x0xxxx", InstName.Vmov,        InstEmit32.Vmov_S,      OpCode32SimdS.Create);
-            SetA32("1111001x1x001000xxx0101000x1xxxx", InstName.Vmovl,       InstEmit32.Vmovl,       OpCode32SimdLong.Create);
-            SetA32("1111001x1x010000xxx0101000x1xxxx", InstName.Vmovl,       InstEmit32.Vmovl,       OpCode32SimdLong.Create);
-            SetA32("1111001x1x100000xxx0101000x1xxxx", InstName.Vmovl,       InstEmit32.Vmovl,       OpCode32SimdLong.Create);
-            SetA32("111100111x11<<10xxxx001000x0xxx0", InstName.Vmovn,       InstEmit32.Vmovn,       OpCode32SimdMovn.Create);
-            SetA32("<<<<11101111xxxxxxxx101000010000", InstName.Vmrs,        InstEmit32.Vmrs,        OpCode32SimdSpecial.Create);
-            SetA32("<<<<11101110xxxxxxxx101000010000", InstName.Vmsr,        InstEmit32.Vmsr,        OpCode32SimdSpecial.Create);
-            SetA32("1111001x1x<<xxxxxxxx100xx1x0xxxx", InstName.Vmul,        InstEmit32.Vmul_1,      OpCode32SimdRegElem.Create);
-            SetA32("111100100x<<xxxxxxxx1001xxx1xxxx", InstName.Vmul,        InstEmit32.Vmul_I,      OpCode32SimdReg.Create);
-            SetA32("111100110x00xxxxxxxx1001xxx1xxxx", InstName.Vmul,        InstEmit32.Vmul_I,      OpCode32SimdReg.Create);
-            SetA32("<<<<11100x10xxxxxxxx101xx0x0xxxx", InstName.Vmul,        InstEmit32.Vmul_S,      OpCode32SimdRegS.Create);
-            SetA32("111100110x00xxxxxxxx1101xxx1xxxx", InstName.Vmul,        InstEmit32.Vmul_V,      OpCode32SimdReg.Create);
-            SetA32("1111001x1x<<xxxxxxx01010x1x0xxxx", InstName.Vmull,       InstEmit32.Vmull_1,     OpCode32SimdRegElemLong.Create);
-            SetA32("1111001x1x<<xxxxxxx01100x0x0xxxx", InstName.Vmull,       InstEmit32.Vmull_I,     OpCode32SimdRegLong.Create);
-            SetA32("111100101xx0xxxxxxx01110x0x0xxxx", InstName.Vmull,       InstEmit32.Vmull_I,     OpCode32SimdRegLong.Create); // P8/P64
-            SetA32("111100111x110000xxxx01011xx0xxxx", InstName.Vmvn,        InstEmit32.Vmvn_I,      OpCode32SimdBinary.Create);
-            SetA32("1111001x1x000xxxxxxx0xx00x11xxxx", InstName.Vmvn,        InstEmit32.Vmvn_II,     OpCode32SimdImm.Create); // D/Q vector I32.
-            SetA32("1111001x1x000xxxxxxx10x00x11xxxx", InstName.Vmvn,        InstEmit32.Vmvn_II,     OpCode32SimdImm.Create);
-            SetA32("1111001x1x000xxxxxxx110x0x11xxxx", InstName.Vmvn,        InstEmit32.Vmvn_II,     OpCode32SimdImm.Create);
-            SetA32("<<<<11101x110001xxxx101x01x0xxxx", InstName.Vneg,        InstEmit32.Vneg_S,      OpCode32SimdS.Create);
-            SetA32("111100111x11<<01xxxx00111xx0xxxx", InstName.Vneg,        InstEmit32.Vneg_V,      OpCode32SimdCmpZ.Create);
-            SetA32("111100111x111001xxxx01111xx0xxxx", InstName.Vneg,        InstEmit32.Vneg_V,      OpCode32SimdCmpZ.Create);
-            SetA32("<<<<11100x01xxxxxxxx101xx1x0xxxx", InstName.Vnmla,       InstEmit32.Vnmla_S,     OpCode32SimdRegS.Create);
-            SetA32("<<<<11100x01xxxxxxxx101xx0x0xxxx", InstName.Vnmls,       InstEmit32.Vnmls_S,     OpCode32SimdRegS.Create);
-            SetA32("<<<<11100x10xxxxxxxx101xx1x0xxxx", InstName.Vnmul,       InstEmit32.Vnmul_S,     OpCode32SimdRegS.Create);
-            SetA32("111100100x11xxxxxxxx0001xxx1xxxx", InstName.Vorn,        InstEmit32.Vorn_I,      OpCode32SimdBinary.Create);
-            SetA32("111100100x10xxxxxxxx0001xxx1xxxx", InstName.Vorr,        InstEmit32.Vorr_I,      OpCode32SimdBinary.Create);
-            SetA32("1111001x1x000xxxxxxx<<x10x01xxxx", InstName.Vorr,        InstEmit32.Vorr_II,     OpCode32SimdImm.Create);
-            SetA32("111100100x<<xxxxxxxx1011x0x1xxxx", InstName.Vpadd,       InstEmit32.Vpadd_I,     OpCode32SimdReg.Create);
-            SetA32("111100110x00xxxxxxxx1101x0x0xxxx", InstName.Vpadd,       InstEmit32.Vpadd_V,     OpCode32SimdReg.Create);
-            SetA32("111100111x11<<00xxxx0010xxx0xxxx", InstName.Vpaddl,      InstEmit32.Vpaddl,      OpCode32SimdCmpZ.Create);
-            SetA32("1111001x0x<<xxxxxxxx1010x0x0xxxx", InstName.Vpmax,       InstEmit32.Vpmax_I,     OpCode32SimdReg.Create);
-            SetA32("111100110x00xxxxxxxx1111x0x0xxxx", InstName.Vpmax,       InstEmit32.Vpmax_V,     OpCode32SimdReg.Create);
-            SetA32("1111001x0x<<xxxxxxxx1010x0x1xxxx", InstName.Vpmin,       InstEmit32.Vpmin_I,     OpCode32SimdReg.Create);
-            SetA32("111100110x10xxxxxxxx1111x0x0xxxx", InstName.Vpmin,       InstEmit32.Vpmin_V,     OpCode32SimdReg.Create);
-            SetA32("1111001x0xxxxxxxxxxx0000xxx1xxxx", InstName.Vqadd,       InstEmit32.Vqadd,       OpCode32SimdReg.Create);
-            SetA32("111100100x01xxxxxxxx1011xxx0xxxx", InstName.Vqdmulh,     InstEmit32.Vqdmulh,     OpCode32SimdReg.Create);
-            SetA32("111100100x10xxxxxxxx1011xxx0xxxx", InstName.Vqdmulh,     InstEmit32.Vqdmulh,     OpCode32SimdReg.Create);
-            SetA32("111100111x11<<10xxxx00101xx0xxx0", InstName.Vqmovn,      InstEmit32.Vqmovn,      OpCode32SimdMovn.Create);
-            SetA32("111100111x11<<10xxxx001001x0xxx0", InstName.Vqmovun,     InstEmit32.Vqmovun,     OpCode32SimdMovn.Create);
-            SetA32("1111001x1x>>>xxxxxxx100101x1xxx0", InstName.Vqrshrn,     InstEmit32.Vqrshrn,     OpCode32SimdShImmNarrow.Create);
-            SetA32("111100111x>>>xxxxxxx100001x1xxx0", InstName.Vqrshrun,    InstEmit32.Vqrshrun,    OpCode32SimdShImmNarrow.Create);
-            SetA32("1111001x1x>>>xxxxxxx100100x1xxx0", InstName.Vqshrn,      InstEmit32.Vqshrn,      OpCode32SimdShImmNarrow.Create);
-            SetA32("111100111x>>>xxxxxxx100000x1xxx0", InstName.Vqshrun,     InstEmit32.Vqshrun,     OpCode32SimdShImmNarrow.Create);
-            SetA32("1111001x0xxxxxxxxxxx0010xxx1xxxx", InstName.Vqsub,       InstEmit32.Vqsub,       OpCode32SimdReg.Create);
-            SetA32("111100111x111011xxxx010x0xx0xxxx", InstName.Vrecpe,      InstEmit32.Vrecpe,      OpCode32SimdSqrte.Create);
-            SetA32("111100100x00xxxxxxxx1111xxx1xxxx", InstName.Vrecps,      InstEmit32.Vrecps,      OpCode32SimdReg.Create);
-            SetA32("111100111x11xx00xxxx000<<xx0xxxx", InstName.Vrev,        InstEmit32.Vrev,        OpCode32SimdRev.Create);
-            SetA32("1111001x0x<<xxxxxxxx0001xxx0xxxx", InstName.Vrhadd,      InstEmit32.Vrhadd,      OpCode32SimdReg.Create);
-            SetA32("111111101x1110xxxxxx101x01x0xxxx", InstName.Vrint,       InstEmit32.Vrint_RM,    OpCode32SimdS.Create);
-            SetA32("<<<<11101x110110xxxx101x11x0xxxx", InstName.Vrint,       InstEmit32.Vrint_Z,     OpCode32SimdS.Create);
-            SetA32("<<<<11101x110111xxxx101x01x0xxxx", InstName.Vrintx,      InstEmit32.Vrintx_S,    OpCode32SimdS.Create);
-            SetA32("1111001x1x>>>xxxxxxx0010>xx1xxxx", InstName.Vrshr,       InstEmit32.Vrshr,       OpCode32SimdShImm.Create);
-            SetA32("111100101x>>>xxxxxxx100001x1xxx0", InstName.Vrshrn,      InstEmit32.Vrshrn,      OpCode32SimdShImmNarrow.Create);
-            SetA32("111100111x111011xxxx010x1xx0xxxx", InstName.Vrsqrte,     InstEmit32.Vrsqrte,     OpCode32SimdSqrte.Create);
-            SetA32("111100100x10xxxxxxxx1111xxx1xxxx", InstName.Vrsqrts,     InstEmit32.Vrsqrts,     OpCode32SimdReg.Create);
-            SetA32("1111001x1x>>>xxxxxxx0011>xx1xxxx", InstName.Vrsra,       InstEmit32.Vrsra,       OpCode32SimdShImm.Create);
-            SetA32("111111100xxxxxxxxxxx101xx0x0xxxx", InstName.Vsel,        InstEmit32.Vsel,        OpCode32SimdSel.Create);
-            SetA32("111100101x>>>xxxxxxx0101>xx1xxxx", InstName.Vshl,        InstEmit32.Vshl,        OpCode32SimdShImm.Create);
-            SetA32("1111001x0xxxxxxxxxxx0100xxx0xxxx", InstName.Vshl,        InstEmit32.Vshl_I,      OpCode32SimdReg.Create);
-            SetA32("1111001x1x>>>xxxxxxx101000x1xxxx", InstName.Vshll,       InstEmit32.Vshll,       OpCode32SimdShImmLong.Create); // A1 encoding.
-            SetA32("1111001x1x>>>xxxxxxx0000>xx1xxxx", InstName.Vshr,        InstEmit32.Vshr,        OpCode32SimdShImm.Create);
-            SetA32("111100101x>>>xxxxxxx100000x1xxx0", InstName.Vshrn,       InstEmit32.Vshrn,       OpCode32SimdShImmNarrow.Create);
-            SetA32("<<<<11101x110001xxxx101x11x0xxxx", InstName.Vsqrt,       InstEmit32.Vsqrt_S,     OpCode32SimdS.Create);
-            SetA32("1111001x1x>>>xxxxxxx0001>xx1xxxx", InstName.Vsra,        InstEmit32.Vsra,        OpCode32SimdShImm.Create);
-            SetA32("111101001x00xxxxxxxx<<00xxxxxxxx", InstName.Vst1,        InstEmit32.Vst1,        OpCode32SimdMemSingle.Create);
-            SetA32("111101000x00xxxxxxxx0111xxxxxxxx", InstName.Vst1,        InstEmit32.Vst1,        OpCode32SimdMemPair.Create); // Regs = 1.
-            SetA32("111101000x00xxxxxxxx1010xxxxxxxx", InstName.Vst1,        InstEmit32.Vst1,        OpCode32SimdMemPair.Create); // Regs = 2.
-            SetA32("111101000x00xxxxxxxx0110xxxxxxxx", InstName.Vst1,        InstEmit32.Vst1,        OpCode32SimdMemPair.Create); // Regs = 3.
-            SetA32("111101000x00xxxxxxxx0010xxxxxxxx", InstName.Vst1,        InstEmit32.Vst1,        OpCode32SimdMemPair.Create); // Regs = 4.
-            SetA32("111101001x00xxxxxxxx<<01xxxxxxxx", InstName.Vst2,        InstEmit32.Vst2,        OpCode32SimdMemSingle.Create);
-            SetA32("111101000x00xxxxxxxx100xxxxxxxxx", InstName.Vst2,        InstEmit32.Vst2,        OpCode32SimdMemPair.Create); // Regs = 1, inc = 1/2 (itype).
-            SetA32("111101000x00xxxxxxxx0011xxxxxxxx", InstName.Vst2,        InstEmit32.Vst2,        OpCode32SimdMemPair.Create); // Regs = 2, inc = 2.
-            SetA32("111101001x00xxxxxxxx<<10xxxxxxxx", InstName.Vst3,        InstEmit32.Vst3,        OpCode32SimdMemSingle.Create);
-            SetA32("111101000x00xxxxxxxx010xxxxxxxxx", InstName.Vst3,        InstEmit32.Vst3,        OpCode32SimdMemPair.Create); // Inc = 1/2 (itype).
-            SetA32("111101001x00xxxxxxxx<<11xxxxxxxx", InstName.Vst4,        InstEmit32.Vst4,        OpCode32SimdMemSingle.Create);
-            SetA32("111101000x00xxxxxxxx000xxxxxxxxx", InstName.Vst4,        InstEmit32.Vst4,        OpCode32SimdMemPair.Create); // Inc = 1/2 (itype).
-            SetA32("<<<<11001x00xxxxxxxx1011xxxxxxx0", InstName.Vstm,        InstEmit32.Vstm,        OpCode32SimdMemMult.Create);
-            SetA32("<<<<11001x10xxxxxxxx1011xxxxxxx0", InstName.Vstm,        InstEmit32.Vstm,        OpCode32SimdMemMult.Create);
-            SetA32("<<<<11010x10xxxxxxxx1011xxxxxxx0", InstName.Vstm,        InstEmit32.Vstm,        OpCode32SimdMemMult.Create);
-            SetA32("<<<<11001x00xxxxxxxx1010xxxxxxxx", InstName.Vstm,        InstEmit32.Vstm,        OpCode32SimdMemMult.Create);
-            SetA32("<<<<11001x10xxxxxxxx1010xxxxxxxx", InstName.Vstm,        InstEmit32.Vstm,        OpCode32SimdMemMult.Create);
-            SetA32("<<<<11010x10xxxxxxxx1010xxxxxxxx", InstName.Vstm,        InstEmit32.Vstm,        OpCode32SimdMemMult.Create);
-            SetA32("<<<<1101xx00xxxxxxxx101xxxxxxxxx", InstName.Vstr,        InstEmit32.Vstr,        OpCode32SimdMemImm.Create);
-            SetA32("111100110xxxxxxxxxxx1000xxx0xxxx", InstName.Vsub,        InstEmit32.Vsub_I,      OpCode32SimdReg.Create);
-            SetA32("<<<<11100x11xxxxxxxx101xx1x0xxxx", InstName.Vsub,        InstEmit32.Vsub_S,      OpCode32SimdRegS.Create);
-            SetA32("111100100x10xxxxxxxx1101xxx0xxxx", InstName.Vsub,        InstEmit32.Vsub_V,      OpCode32SimdReg.Create);
-            SetA32("1111001x1x<<xxxxxxx00010x0x0xxxx", InstName.Vsubl,       InstEmit32.Vsubl_I,     OpCode32SimdRegLong.Create);
-            SetA32("1111001x1x<<xxxxxxx00011x0x0xxxx", InstName.Vsubw,       InstEmit32.Vsubw_I,     OpCode32SimdRegWide.Create);
-            SetA32("111100111x11xxxxxxxx10xxxxx0xxxx", InstName.Vtbl,        InstEmit32.Vtbl,        OpCode32SimdTbl.Create);
-            SetA32("111100111x11<<10xxxx00001xx0xxxx", InstName.Vtrn,        InstEmit32.Vtrn,        OpCode32SimdCmpZ.Create);
-            SetA32("111100100x<<xxxxxxxx1000xxx1xxxx", InstName.Vtst,        InstEmit32.Vtst,        OpCode32SimdReg.Create);
-            SetA32("111100111x11<<10xxxx00010xx0xxxx", InstName.Vuzp,        InstEmit32.Vuzp,        OpCode32SimdCmpZ.Create);
-            SetA32("111100111x11<<10xxxx00011xx0xxxx", InstName.Vzip,        InstEmit32.Vzip,        OpCode32SimdCmpZ.Create);
+            // VFP
+            SetVfp("<<<<11101x110000xxxx101x11x0xxxx", InstName.Vabs,   InstEmit32.Vabs_S,   OpCode32SimdS.Create,           OpCode32SimdS.CreateT32);
+            SetVfp("<<<<11100x11xxxxxxxx101xx0x0xxxx", InstName.Vadd,   InstEmit32.Vadd_S,   OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+            SetVfp("<<<<11101x11010xxxxx101x01x0xxxx", InstName.Vcmp,   InstEmit32.Vcmp,     OpCode32SimdS.Create,           OpCode32SimdS.CreateT32);
+            SetVfp("<<<<11101x11010xxxxx101x11x0xxxx", InstName.Vcmpe,  InstEmit32.Vcmpe,    OpCode32SimdS.Create,           OpCode32SimdS.CreateT32);
+            SetVfp("<<<<11101x110111xxxx101x11x0xxxx", InstName.Vcvt,   InstEmit32.Vcvt_FD,  OpCode32SimdS.Create,           OpCode32SimdS.CreateT32); // FP 32 and 64, scalar.
+            SetVfp("<<<<11101x11110xxxxx101x11x0xxxx", InstName.Vcvt,   InstEmit32.Vcvt_FI,  OpCode32SimdCvtFI.Create,       OpCode32SimdCvtFI.CreateT32); // FP32 to int.
+            SetVfp("<<<<11101x111000xxxx101xx1x0xxxx", InstName.Vcvt,   InstEmit32.Vcvt_FI,  OpCode32SimdCvtFI.Create,       OpCode32SimdCvtFI.CreateT32); // Int to FP32.
+            SetVfp("111111101x1111xxxxxx101xx1x0xxxx", InstName.Vcvt,   InstEmit32.Vcvt_RM,  OpCode32SimdCvtFI.Create,       OpCode32SimdCvtFI.CreateT32); // The many FP32 to int encodings (fp).
+            SetVfp("<<<<11101x00xxxxxxxx101xx0x0xxxx", InstName.Vdiv,   InstEmit32.Vdiv_S,   OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+            SetVfp("<<<<11101xx0xxxxxxxx1011x0x10000", InstName.Vdup,   InstEmit32.Vdup,     OpCode32SimdDupGP.Create,       OpCode32SimdDupGP.CreateT32);
+            SetVfp("<<<<11101x10xxxxxxxx101xx0x0xxxx", InstName.Vfma,   InstEmit32.Vfma_S,   OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+            SetVfp("<<<<11101x10xxxxxxxx101xx1x0xxxx", InstName.Vfms,   InstEmit32.Vfms_S,   OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+            SetVfp("<<<<11101x01xxxxxxxx101xx1x0xxxx", InstName.Vfnma,  InstEmit32.Vfnma_S,  OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+            SetVfp("<<<<11101x01xxxxxxxx101xx0x0xxxx", InstName.Vfnms,  InstEmit32.Vfnms_S,  OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+            SetVfp("<<<<11001x01xxxxxxxx1011xxxxxxx0", InstName.Vldm,   InstEmit32.Vldm,     OpCode32SimdMemMult.Create,     OpCode32SimdMemMult.CreateT32);
+            SetVfp("<<<<11001x11xxxxxxxx1011xxxxxxx0", InstName.Vldm,   InstEmit32.Vldm,     OpCode32SimdMemMult.Create,     OpCode32SimdMemMult.CreateT32);
+            SetVfp("<<<<11010x11xxxxxxxx1011xxxxxxx0", InstName.Vldm,   InstEmit32.Vldm,     OpCode32SimdMemMult.Create,     OpCode32SimdMemMult.CreateT32);
+            SetVfp("<<<<11001x01xxxxxxxx1010xxxxxxxx", InstName.Vldm,   InstEmit32.Vldm,     OpCode32SimdMemMult.Create,     OpCode32SimdMemMult.CreateT32);
+            SetVfp("<<<<11001x11xxxxxxxx1010xxxxxxxx", InstName.Vldm,   InstEmit32.Vldm,     OpCode32SimdMemMult.Create,     OpCode32SimdMemMult.CreateT32);
+            SetVfp("<<<<11010x11xxxxxxxx1010xxxxxxxx", InstName.Vldm,   InstEmit32.Vldm,     OpCode32SimdMemMult.Create,     OpCode32SimdMemMult.CreateT32);
+            SetVfp("<<<<1101xx01xxxxxxxx101xxxxxxxxx", InstName.Vldr,   InstEmit32.Vldr,     OpCode32SimdMemImm.Create,      OpCode32SimdMemImm.CreateT32);
+            SetVfp("111111101x00xxxxxxxx10>>x0x0xxxx", InstName.Vmaxnm, InstEmit32.Vmaxnm_S, OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+            SetVfp("111111101x00xxxxxxxx10>>x1x0xxxx", InstName.Vminnm, InstEmit32.Vminnm_S, OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+            SetVfp("<<<<11100x00xxxxxxxx101xx0x0xxxx", InstName.Vmla,   InstEmit32.Vmla_S,   OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+            SetVfp("<<<<11100x00xxxxxxxx101xx1x0xxxx", InstName.Vmls,   InstEmit32.Vmls_S,   OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+            SetVfp("<<<<11100xx0xxxxxxxx1011xxx10000", InstName.Vmov,   InstEmit32.Vmov_G1,  OpCode32SimdMovGpElem.Create,   OpCode32SimdMovGpElem.CreateT32); // From gen purpose.
+            SetVfp("<<<<1110xxx1xxxxxxxx1011xxx10000", InstName.Vmov,   InstEmit32.Vmov_G1,  OpCode32SimdMovGpElem.Create,   OpCode32SimdMovGpElem.CreateT32); // To gen purpose.
+            SetVfp("<<<<1100010xxxxxxxxx101000x1xxxx", InstName.Vmov,   InstEmit32.Vmov_G2,  OpCode32SimdMovGpDouble.Create, OpCode32SimdMovGpDouble.CreateT32); // To/from gen purpose x2 and single precision x2.
+            SetVfp("<<<<1100010xxxxxxxxx101100x1xxxx", InstName.Vmov,   InstEmit32.Vmov_GD,  OpCode32SimdMovGpDouble.Create, OpCode32SimdMovGpDouble.CreateT32); // To/from gen purpose x2 and double precision.
+            SetVfp("<<<<1110000xxxxxxxxx1010x0010000", InstName.Vmov,   InstEmit32.Vmov_GS,  OpCode32SimdMovGp.Create,       OpCode32SimdMovGp.CreateT32); // To/from gen purpose and single precision.
+            SetVfp("<<<<11101x11xxxxxxxx101x0000xxxx", InstName.Vmov,   InstEmit32.Vmov_I,   OpCode32SimdImm44.Create,       OpCode32SimdImm44.CreateT32); // Scalar f16/32/64 based on size 01 10 11.
+            SetVfp("<<<<11101x110000xxxx101x01x0xxxx", InstName.Vmov,   InstEmit32.Vmov_S,   OpCode32SimdS.Create,           OpCode32SimdS.CreateT32);
+            SetVfp("<<<<11101111xxxxxxxx101000010000", InstName.Vmrs,   InstEmit32.Vmrs,     OpCode32SimdSpecial.Create,     OpCode32SimdSpecial.CreateT32);
+            SetVfp("<<<<11101110xxxxxxxx101000010000", InstName.Vmsr,   InstEmit32.Vmsr,     OpCode32SimdSpecial.Create,     OpCode32SimdSpecial.CreateT32);
+            SetVfp("<<<<11100x10xxxxxxxx101xx0x0xxxx", InstName.Vmul,   InstEmit32.Vmul_S,   OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+            SetVfp("<<<<11101x110001xxxx101x01x0xxxx", InstName.Vneg,   InstEmit32.Vneg_S,   OpCode32SimdS.Create,           OpCode32SimdS.CreateT32);
+            SetVfp("<<<<11100x01xxxxxxxx101xx1x0xxxx", InstName.Vnmla,  InstEmit32.Vnmla_S,  OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+            SetVfp("<<<<11100x01xxxxxxxx101xx0x0xxxx", InstName.Vnmls,  InstEmit32.Vnmls_S,  OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+            SetVfp("<<<<11100x10xxxxxxxx101xx1x0xxxx", InstName.Vnmul,  InstEmit32.Vnmul_S,  OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+            SetVfp("111111101x1110xxxxxx101x01x0xxxx", InstName.Vrint,  InstEmit32.Vrint_RM, OpCode32SimdS.Create,           OpCode32SimdS.CreateT32);
+            SetVfp("<<<<11101x110110xxxx101x11x0xxxx", InstName.Vrint,  InstEmit32.Vrint_Z,  OpCode32SimdS.Create,           OpCode32SimdS.CreateT32);
+            SetVfp("<<<<11101x110111xxxx101x01x0xxxx", InstName.Vrintx, InstEmit32.Vrintx_S, OpCode32SimdS.Create,           OpCode32SimdS.CreateT32);
+            SetVfp("<<<<11101x110001xxxx101x11x0xxxx", InstName.Vsqrt,  InstEmit32.Vsqrt_S,  OpCode32SimdS.Create,           OpCode32SimdS.CreateT32);
+            SetVfp("111111100xxxxxxxxxxx101xx0x0xxxx", InstName.Vsel,   InstEmit32.Vsel,     OpCode32SimdSel.Create,         OpCode32SimdSel.CreateT32);
+            SetVfp("<<<<11001x00xxxxxxxx1011xxxxxxx0", InstName.Vstm,   InstEmit32.Vstm,     OpCode32SimdMemMult.Create,     OpCode32SimdMemMult.CreateT32);
+            SetVfp("<<<<11001x10xxxxxxxx1011xxxxxxx0", InstName.Vstm,   InstEmit32.Vstm,     OpCode32SimdMemMult.Create,     OpCode32SimdMemMult.CreateT32);
+            SetVfp("<<<<11010x10xxxxxxxx1011xxxxxxx0", InstName.Vstm,   InstEmit32.Vstm,     OpCode32SimdMemMult.Create,     OpCode32SimdMemMult.CreateT32);
+            SetVfp("<<<<11001x00xxxxxxxx1010xxxxxxxx", InstName.Vstm,   InstEmit32.Vstm,     OpCode32SimdMemMult.Create,     OpCode32SimdMemMult.CreateT32);
+            SetVfp("<<<<11001x10xxxxxxxx1010xxxxxxxx", InstName.Vstm,   InstEmit32.Vstm,     OpCode32SimdMemMult.Create,     OpCode32SimdMemMult.CreateT32);
+            SetVfp("<<<<11010x10xxxxxxxx1010xxxxxxxx", InstName.Vstm,   InstEmit32.Vstm,     OpCode32SimdMemMult.Create,     OpCode32SimdMemMult.CreateT32);
+            SetVfp("<<<<1101xx00xxxxxxxx101xxxxxxxxx", InstName.Vstr,   InstEmit32.Vstr,     OpCode32SimdMemImm.Create,      OpCode32SimdMemImm.CreateT32);
+            SetVfp("<<<<11100x11xxxxxxxx101xx1x0xxxx", InstName.Vsub,   InstEmit32.Vsub_S,   OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+
+            // ASIMD
+            SetAsimd("111100111x110000xxx0001101x0xxx0", InstName.Aesd_V,      InstEmit32.Aesd_V,      OpCode32Simd.Create,            OpCode32Simd.CreateT32);
+            SetAsimd("111100111x110000xxx0001100x0xxx0", InstName.Aese_V,      InstEmit32.Aese_V,      OpCode32Simd.Create,            OpCode32Simd.CreateT32);
+            SetAsimd("111100111x110000xxx0001111x0xxx0", InstName.Aesimc_V,    InstEmit32.Aesimc_V,    OpCode32Simd.Create,            OpCode32Simd.CreateT32);
+            SetAsimd("111100111x110000xxx0001110x0xxx0", InstName.Aesmc_V,     InstEmit32.Aesmc_V,     OpCode32Simd.Create,            OpCode32Simd.CreateT32);
+            SetAsimd("111100110x00xxx0xxx01100x1x0xxx0", InstName.Sha256h_V,   InstEmit32.Sha256h_V,   OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100110x01xxx0xxx01100x1x0xxx0", InstName.Sha256h2_V,  InstEmit32.Sha256h2_V,  OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100111x111010xxx0001111x0xxx0", InstName.Sha256su0_V, InstEmit32.Sha256su0_V, OpCode32Simd.Create,            OpCode32Simd.CreateT32);
+            SetAsimd("111100110x10xxx0xxx01100x1x0xxx0", InstName.Sha256su1_V, InstEmit32.Sha256su1_V, OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("1111001x0x<<xxxxxxxx0111xxx0xxxx", InstName.Vabd,        InstEmit32.Vabd_I,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("1111001x1x<<xxxxxxxx0111x0x0xxxx", InstName.Vabdl,       InstEmit32.Vabdl_I,     OpCode32SimdRegLong.Create,     OpCode32SimdRegLong.CreateT32);
+            SetAsimd("111100111x11<<01xxxx00110xx0xxxx", InstName.Vabs,        InstEmit32.Vabs_V,      OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("111100111x111001xxxx01110xx0xxxx", InstName.Vabs,        InstEmit32.Vabs_V,      OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("111100100xxxxxxxxxxx1000xxx0xxxx", InstName.Vadd,        InstEmit32.Vadd_I,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100100x00xxxxxxxx1101xxx0xxxx", InstName.Vadd,        InstEmit32.Vadd_V,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("1111001x1x<<xxxxxxx00000x0x0xxxx", InstName.Vaddl,       InstEmit32.Vaddl_I,     OpCode32SimdRegLong.Create,     OpCode32SimdRegLong.CreateT32);
+            SetAsimd("1111001x1x<<xxxxxxx00001x0x0xxxx", InstName.Vaddw,       InstEmit32.Vaddw_I,     OpCode32SimdRegWide.Create,     OpCode32SimdRegWide.CreateT32);
+            SetAsimd("111100100x00xxxxxxxx0001xxx1xxxx", InstName.Vand,        InstEmit32.Vand_I,      OpCode32SimdBinary.Create,      OpCode32SimdBinary.CreateT32);
+            SetAsimd("111100100x01xxxxxxxx0001xxx1xxxx", InstName.Vbic,        InstEmit32.Vbic_I,      OpCode32SimdBinary.Create,      OpCode32SimdBinary.CreateT32);
+            SetAsimd("1111001x1x000xxxxxxx<<x10x11xxxx", InstName.Vbic,        InstEmit32.Vbic_II,     OpCode32SimdImm.Create,         OpCode32SimdImm.CreateT32);
+            SetAsimd("111100110x11xxxxxxxx0001xxx1xxxx", InstName.Vbif,        InstEmit32.Vbif,        OpCode32SimdBinary.Create,      OpCode32SimdBinary.CreateT32);
+            SetAsimd("111100110x10xxxxxxxx0001xxx1xxxx", InstName.Vbit,        InstEmit32.Vbit,        OpCode32SimdBinary.Create,      OpCode32SimdBinary.CreateT32);
+            SetAsimd("111100110x01xxxxxxxx0001xxx1xxxx", InstName.Vbsl,        InstEmit32.Vbsl,        OpCode32SimdBinary.Create,      OpCode32SimdBinary.CreateT32);
+            SetAsimd("111100110x<<xxxxxxxx1000xxx1xxxx", InstName.Vceq,        InstEmit32.Vceq_I,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100100x00xxxxxxxx1110xxx0xxxx", InstName.Vceq,        InstEmit32.Vceq_V,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100111x11xx01xxxx0x010xx0xxxx", InstName.Vceq,        InstEmit32.Vceq_Z,      OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("1111001x0x<<xxxxxxxx0011xxx1xxxx", InstName.Vcge,        InstEmit32.Vcge_I,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100110x00xxxxxxxx1110xxx0xxxx", InstName.Vcge,        InstEmit32.Vcge_V,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100111x11xx01xxxx0x001xx0xxxx", InstName.Vcge,        InstEmit32.Vcge_Z,      OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("1111001x0x<<xxxxxxxx0011xxx0xxxx", InstName.Vcgt,        InstEmit32.Vcgt_I,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100110x10xxxxxxxx1110xxx0xxxx", InstName.Vcgt,        InstEmit32.Vcgt_V,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100111x11xx01xxxx0x000xx0xxxx", InstName.Vcgt,        InstEmit32.Vcgt_Z,      OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("111100111x11xx01xxxx0x011xx0xxxx", InstName.Vcle,        InstEmit32.Vcle_Z,      OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("111100111x11xx01xxxx0x100xx0xxxx", InstName.Vclt,        InstEmit32.Vclt_Z,      OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("111100111x110000xxxx01010xx0xxxx", InstName.Vcnt,        InstEmit32.Vcnt,        OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("111100111x111011xxxx011xxxx0xxxx", InstName.Vcvt,        InstEmit32.Vcvt_V,      OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32); // FP and integer, vector.
+            SetAsimd("111100111x11xxxxxxxx11000xx0xxxx", InstName.Vdup,        InstEmit32.Vdup_1,      OpCode32SimdDupElem.Create,     OpCode32SimdDupElem.CreateT32);
+            SetAsimd("111100110x00xxxxxxxx0001xxx1xxxx", InstName.Veor,        InstEmit32.Veor_I,      OpCode32SimdBinary.Create,      OpCode32SimdBinary.CreateT32);
+            SetAsimd("111100101x11xxxxxxxxxxxxxxx0xxxx", InstName.Vext,        InstEmit32.Vext,        OpCode32SimdExt.Create,         OpCode32SimdExt.CreateT32);
+            SetAsimd("111100100x00xxxxxxxx1100xxx1xxxx", InstName.Vfma,        InstEmit32.Vfma_V,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100100x10xxxxxxxx1100xxx1xxxx", InstName.Vfms,        InstEmit32.Vfms_V,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("1111001x0x<<xxxxxxxx0000xxx0xxxx", InstName.Vhadd,       InstEmit32.Vhadd,       OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111101001x10xxxxxxxx0000xxx0xxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x10xxxxxxxx0100xx0xxxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x10xxxxxxxx1000x000xxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x10xxxxxxxx1000x011xxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x10xxxxxxxx110000x0xxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x10xxxxxxxx110001xxxxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x10xxxxxxxx110010xxxxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101000x10xxxxxxxx0111xx0xxxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Regs = 1.
+            SetAsimd("111101000x10xxxxxxxx1010xx<<xxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Regs = 2.
+            SetAsimd("111101000x10xxxxxxxx0110xx0xxxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Regs = 3.
+            SetAsimd("111101000x10xxxxxxxx0010xxxxxxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Regs = 4.
+            SetAsimd("111101001x10xxxxxxxx0x01xxxxxxxx", InstName.Vld2,        InstEmit32.Vld2,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x10xxxxxxxx1001xx0xxxxx", InstName.Vld2,        InstEmit32.Vld2,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x10xxxxxxxx1101<<xxxxxx", InstName.Vld2,        InstEmit32.Vld2,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101000x10xxxxxxxx100x<<0xxxxx", InstName.Vld2,        InstEmit32.Vld2,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Regs = 1, inc = 1/2 (itype).
+            SetAsimd("111101000x10xxxxxxxx100x<<10xxxx", InstName.Vld2,        InstEmit32.Vld2,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Regs = 1, inc = 1/2 (itype).
+            SetAsimd("111101000x10xxxxxxxx0011<<xxxxxx", InstName.Vld2,        InstEmit32.Vld2,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Regs = 2, inc = 2.
+            SetAsimd("111101001x10xxxxxxxx0x10xxx0xxxx", InstName.Vld3,        InstEmit32.Vld3,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x10xxxxxxxx1010xx00xxxx", InstName.Vld3,        InstEmit32.Vld3,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x10xxxxxxxx1110<<x0xxxx", InstName.Vld3,        InstEmit32.Vld3,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101000x10xxxxxxxx010x<<0xxxxx", InstName.Vld3,        InstEmit32.Vld3,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Inc = 1/2 (itype).
+            SetAsimd("111101001x10xxxxxxxx0x11xxxxxxxx", InstName.Vld4,        InstEmit32.Vld4,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x10xxxxxxxx1011xx<<xxxx", InstName.Vld4,        InstEmit32.Vld4,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x10xxxxxxxx1111<<x>xxxx", InstName.Vld4,        InstEmit32.Vld4,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101000x10xxxxxxxx000x<<xxxxxx", InstName.Vld4,        InstEmit32.Vld4,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Inc = 1/2 (itype).
+            SetAsimd("1111001x0x<<xxxxxxxx0110xxx0xxxx", InstName.Vmax,        InstEmit32.Vmax_I,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100100x00xxxxxxxx1111xxx0xxxx", InstName.Vmax,        InstEmit32.Vmax_V,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("1111001x0x<<xxxxxxxx0110xxx1xxxx", InstName.Vmin,        InstEmit32.Vmin_I,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100100x10xxxxxxxx1111xxx0xxxx", InstName.Vmin,        InstEmit32.Vmin_V,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100110x0xxxxxxxxx1111xxx1xxxx", InstName.Vmaxnm,      InstEmit32.Vmaxnm_V,    OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100110x1xxxxxxxxx1111xxx1xxxx", InstName.Vminnm,      InstEmit32.Vminnm_V,    OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("1111001x1x<<xxxxxxxx000xx1x0xxxx", InstName.Vmla,        InstEmit32.Vmla_1,      OpCode32SimdRegElem.Create,     OpCode32SimdRegElem.CreateT32);
+            SetAsimd("111100100xxxxxxxxxxx1001xxx0xxxx", InstName.Vmla,        InstEmit32.Vmla_I,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100100x00xxxxxxxx1101xxx1xxxx", InstName.Vmla,        InstEmit32.Vmla_V,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("1111001x1x<<xxxxxxx01000x0x0xxxx", InstName.Vmlal,       InstEmit32.Vmlal_I,     OpCode32SimdRegLong.Create,     OpCode32SimdRegLong.CreateT32);
+            SetAsimd("1111001x1x<<xxxxxxxx010xx1x0xxxx", InstName.Vmls,        InstEmit32.Vmls_1,      OpCode32SimdRegElem.Create,     OpCode32SimdRegElem.CreateT32);
+            SetAsimd("111100100x10xxxxxxxx1101xxx1xxxx", InstName.Vmls,        InstEmit32.Vmls_V,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100110xxxxxxxxxxx1001xxx0xxxx", InstName.Vmls,        InstEmit32.Vmls_I,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("1111001x1x<<xxxxxxx01010x0x0xxxx", InstName.Vmlsl,       InstEmit32.Vmlsl_I,     OpCode32SimdRegLong.Create,     OpCode32SimdRegLong.CreateT32);
+            SetAsimd("1111001x1x000xxxxxxx0xx00x01xxxx", InstName.Vmov,        InstEmit32.Vmov_I,      OpCode32SimdImm.Create,         OpCode32SimdImm.CreateT32); // D/Q vector I32.
+            SetAsimd("1111001x1x000xxxxxxx10x00x01xxxx", InstName.Vmov,        InstEmit32.Vmov_I,      OpCode32SimdImm.Create,         OpCode32SimdImm.CreateT32); // D/Q I16.
+            SetAsimd("1111001x1x000xxxxxxx11xx0x01xxxx", InstName.Vmov,        InstEmit32.Vmov_I,      OpCode32SimdImm.Create,         OpCode32SimdImm.CreateT32); // D/Q (dt - from cmode).
+            SetAsimd("1111001x1x000xxxxxxx11100x11xxxx", InstName.Vmov,        InstEmit32.Vmov_I,      OpCode32SimdImm.Create,         OpCode32SimdImm.CreateT32); // D/Q I64.
+            SetAsimd("1111001x1x001000xxx0101000x1xxxx", InstName.Vmovl,       InstEmit32.Vmovl,       OpCode32SimdLong.Create,        OpCode32SimdLong.CreateT32);
+            SetAsimd("1111001x1x010000xxx0101000x1xxxx", InstName.Vmovl,       InstEmit32.Vmovl,       OpCode32SimdLong.Create,        OpCode32SimdLong.CreateT32);
+            SetAsimd("1111001x1x100000xxx0101000x1xxxx", InstName.Vmovl,       InstEmit32.Vmovl,       OpCode32SimdLong.Create,        OpCode32SimdLong.CreateT32);
+            SetAsimd("111100111x11<<10xxxx001000x0xxx0", InstName.Vmovn,       InstEmit32.Vmovn,       OpCode32SimdMovn.Create,        OpCode32SimdMovn.CreateT32);
+            SetAsimd("1111001x1x<<xxxxxxxx100xx1x0xxxx", InstName.Vmul,        InstEmit32.Vmul_1,      OpCode32SimdRegElem.Create,     OpCode32SimdRegElem.CreateT32);
+            SetAsimd("111100100x<<xxxxxxxx1001xxx1xxxx", InstName.Vmul,        InstEmit32.Vmul_I,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100110x00xxxxxxxx1001xxx1xxxx", InstName.Vmul,        InstEmit32.Vmul_I,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100110x00xxxxxxxx1101xxx1xxxx", InstName.Vmul,        InstEmit32.Vmul_V,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("1111001x1x<<xxxxxxx01010x1x0xxxx", InstName.Vmull,       InstEmit32.Vmull_1,     OpCode32SimdRegElemLong.Create, OpCode32SimdRegElemLong.CreateT32);
+            SetAsimd("1111001x1x<<xxxxxxx01100x0x0xxxx", InstName.Vmull,       InstEmit32.Vmull_I,     OpCode32SimdRegLong.Create,     OpCode32SimdRegLong.CreateT32);
+            SetAsimd("111100101xx0xxxxxxx01110x0x0xxxx", InstName.Vmull,       InstEmit32.Vmull_I,     OpCode32SimdRegLong.Create,     OpCode32SimdRegLong.CreateT32); // P8/P64
+            SetAsimd("111100111x110000xxxx01011xx0xxxx", InstName.Vmvn,        InstEmit32.Vmvn_I,      OpCode32SimdBinary.Create,      OpCode32SimdBinary.CreateT32);
+            SetAsimd("1111001x1x000xxxxxxx0xx00x11xxxx", InstName.Vmvn,        InstEmit32.Vmvn_II,     OpCode32SimdImm.Create,         OpCode32SimdImm.CreateT32); // D/Q vector I32.
+            SetAsimd("1111001x1x000xxxxxxx10x00x11xxxx", InstName.Vmvn,        InstEmit32.Vmvn_II,     OpCode32SimdImm.Create,         OpCode32SimdImm.CreateT32);
+            SetAsimd("1111001x1x000xxxxxxx110x0x11xxxx", InstName.Vmvn,        InstEmit32.Vmvn_II,     OpCode32SimdImm.Create,         OpCode32SimdImm.CreateT32);
+            SetAsimd("111100111x11<<01xxxx00111xx0xxxx", InstName.Vneg,        InstEmit32.Vneg_V,      OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("111100111x111001xxxx01111xx0xxxx", InstName.Vneg,        InstEmit32.Vneg_V,      OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("111100100x11xxxxxxxx0001xxx1xxxx", InstName.Vorn,        InstEmit32.Vorn_I,      OpCode32SimdBinary.Create,      OpCode32SimdBinary.CreateT32);
+            SetAsimd("111100100x10xxxxxxxx0001xxx1xxxx", InstName.Vorr,        InstEmit32.Vorr_I,      OpCode32SimdBinary.Create,      OpCode32SimdBinary.CreateT32);
+            SetAsimd("1111001x1x000xxxxxxx<<x10x01xxxx", InstName.Vorr,        InstEmit32.Vorr_II,     OpCode32SimdImm.Create,         OpCode32SimdImm.CreateT32);
+            SetAsimd("111100100x<<xxxxxxxx1011x0x1xxxx", InstName.Vpadd,       InstEmit32.Vpadd_I,     OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100110x00xxxxxxxx1101x0x0xxxx", InstName.Vpadd,       InstEmit32.Vpadd_V,     OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100111x11<<00xxxx0010xxx0xxxx", InstName.Vpaddl,      InstEmit32.Vpaddl,      OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("1111001x0x<<xxxxxxxx1010x0x0xxxx", InstName.Vpmax,       InstEmit32.Vpmax_I,     OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100110x00xxxxxxxx1111x0x0xxxx", InstName.Vpmax,       InstEmit32.Vpmax_V,     OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("1111001x0x<<xxxxxxxx1010x0x1xxxx", InstName.Vpmin,       InstEmit32.Vpmin_I,     OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100110x10xxxxxxxx1111x0x0xxxx", InstName.Vpmin,       InstEmit32.Vpmin_V,     OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("1111001x0xxxxxxxxxxx0000xxx1xxxx", InstName.Vqadd,       InstEmit32.Vqadd,       OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100100x01xxxxxxxx1011xxx0xxxx", InstName.Vqdmulh,     InstEmit32.Vqdmulh,     OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100100x10xxxxxxxx1011xxx0xxxx", InstName.Vqdmulh,     InstEmit32.Vqdmulh,     OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100111x11<<10xxxx00101xx0xxx0", InstName.Vqmovn,      InstEmit32.Vqmovn,      OpCode32SimdMovn.Create,        OpCode32SimdMovn.CreateT32);
+            SetAsimd("111100111x11<<10xxxx001001x0xxx0", InstName.Vqmovun,     InstEmit32.Vqmovun,     OpCode32SimdMovn.Create,        OpCode32SimdMovn.CreateT32);
+            SetAsimd("1111001x1x>>>xxxxxxx100101x1xxx0", InstName.Vqrshrn,     InstEmit32.Vqrshrn,     OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32);
+            SetAsimd("111100111x>>>xxxxxxx100001x1xxx0", InstName.Vqrshrun,    InstEmit32.Vqrshrun,    OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32);
+            SetAsimd("1111001x1x>>>xxxxxxx100100x1xxx0", InstName.Vqshrn,      InstEmit32.Vqshrn,      OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32);
+            SetAsimd("111100111x>>>xxxxxxx100000x1xxx0", InstName.Vqshrun,     InstEmit32.Vqshrun,     OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32);
+            SetAsimd("1111001x0xxxxxxxxxxx0010xxx1xxxx", InstName.Vqsub,       InstEmit32.Vqsub,       OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100111x111011xxxx010x0xx0xxxx", InstName.Vrecpe,      InstEmit32.Vrecpe,      OpCode32SimdSqrte.Create,       OpCode32SimdSqrte.CreateT32);
+            SetAsimd("111100100x00xxxxxxxx1111xxx1xxxx", InstName.Vrecps,      InstEmit32.Vrecps,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100111x11xx00xxxx000<<xx0xxxx", InstName.Vrev,        InstEmit32.Vrev,        OpCode32SimdRev.Create,         OpCode32SimdRev.CreateT32);
+            SetAsimd("1111001x0x<<xxxxxxxx0001xxx0xxxx", InstName.Vrhadd,      InstEmit32.Vrhadd,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100111x111010xxxx01010xx0xxxx", InstName.Vrinta,      InstEmit32.Vrinta_V,    OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("111100111x111010xxxx01101xx0xxxx", InstName.Vrintm,      InstEmit32.Vrintm_V,    OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("111100111x111010xxxx01000xx0xxxx", InstName.Vrintn,      InstEmit32.Vrintn_V,    OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("111100111x111010xxxx01111xx0xxxx", InstName.Vrintp,      InstEmit32.Vrintp_V,    OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("1111001x1x>>>xxxxxxx0010>xx1xxxx", InstName.Vrshr,       InstEmit32.Vrshr,       OpCode32SimdShImm.Create,       OpCode32SimdShImm.CreateT32);
+            SetAsimd("111100101x>>>xxxxxxx100001x1xxx0", InstName.Vrshrn,      InstEmit32.Vrshrn,      OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32);
+            SetAsimd("111100111x111011xxxx010x1xx0xxxx", InstName.Vrsqrte,     InstEmit32.Vrsqrte,     OpCode32SimdSqrte.Create,       OpCode32SimdSqrte.CreateT32);
+            SetAsimd("111100100x10xxxxxxxx1111xxx1xxxx", InstName.Vrsqrts,     InstEmit32.Vrsqrts,     OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("1111001x1x>>>xxxxxxx0011>xx1xxxx", InstName.Vrsra,       InstEmit32.Vrsra,       OpCode32SimdShImm.Create,       OpCode32SimdShImm.CreateT32);
+            SetAsimd("111100101x>>>xxxxxxx0101>xx1xxxx", InstName.Vshl,        InstEmit32.Vshl,        OpCode32SimdShImm.Create,       OpCode32SimdShImm.CreateT32);
+            SetAsimd("1111001x0xxxxxxxxxxx0100xxx0xxxx", InstName.Vshl,        InstEmit32.Vshl_I,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("1111001x1x>>>xxxxxxx101000x1xxxx", InstName.Vshll,       InstEmit32.Vshll,       OpCode32SimdShImmLong.Create,   OpCode32SimdShImmLong.CreateT32); // A1 encoding.
+            SetAsimd("1111001x1x>>>xxxxxxx0000>xx1xxxx", InstName.Vshr,        InstEmit32.Vshr,        OpCode32SimdShImm.Create,       OpCode32SimdShImm.CreateT32);
+            SetAsimd("111100101x>>>xxxxxxx100000x1xxx0", InstName.Vshrn,       InstEmit32.Vshrn,       OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32);
+            SetAsimd("1111001x1x>>>xxxxxxx0001>xx1xxxx", InstName.Vsra,        InstEmit32.Vsra,        OpCode32SimdShImm.Create,       OpCode32SimdShImm.CreateT32);
+            SetAsimd("111101001x00xxxxxxxx0000xxx0xxxx", InstName.Vst1,        InstEmit32.Vst1,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x00xxxxxxxx0100xx0xxxxx", InstName.Vst1,        InstEmit32.Vst1,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x00xxxxxxxx1000x000xxxx", InstName.Vst1,        InstEmit32.Vst1,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x00xxxxxxxx1000x011xxxx", InstName.Vst1,        InstEmit32.Vst1,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101000x00xxxxxxxx0111xx0xxxxx", InstName.Vst1,        InstEmit32.Vst1,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Regs = 1.
+            SetAsimd("111101000x00xxxxxxxx1010xx<<xxxx", InstName.Vst1,        InstEmit32.Vst1,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Regs = 2.
+            SetAsimd("111101000x00xxxxxxxx0110xx0xxxxx", InstName.Vst1,        InstEmit32.Vst1,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Regs = 3.
+            SetAsimd("111101000x00xxxxxxxx0010xxxxxxxx", InstName.Vst1,        InstEmit32.Vst1,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Regs = 4.
+            SetAsimd("111101001x00xxxxxxxx0x01xxxxxxxx", InstName.Vst2,        InstEmit32.Vst2,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x00xxxxxxxx1001xx0xxxxx", InstName.Vst2,        InstEmit32.Vst2,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101000x00xxxxxxxx100x<<0xxxxx", InstName.Vst2,        InstEmit32.Vst2,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Regs = 1, inc = 1/2 (itype).
+            SetAsimd("111101000x00xxxxxxxx100x<<10xxxx", InstName.Vst2,        InstEmit32.Vst2,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Regs = 1, inc = 1/2 (itype).
+            SetAsimd("111101000x00xxxxxxxx0011<<xxxxxx", InstName.Vst2,        InstEmit32.Vst2,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Regs = 2, inc = 2.
+            SetAsimd("111101001x00xxxxxxxx0x10xxx0xxxx", InstName.Vst3,        InstEmit32.Vst3,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x00xxxxxxxx1010xx00xxxx", InstName.Vst3,        InstEmit32.Vst3,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101000x00xxxxxxxx010x<<0xxxxx", InstName.Vst3,        InstEmit32.Vst3,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Inc = 1/2 (itype).
+            SetAsimd("111101001x00xxxxxxxx0x11xxxxxxxx", InstName.Vst4,        InstEmit32.Vst4,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x00xxxxxxxx1011xx<<xxxx", InstName.Vst4,        InstEmit32.Vst4,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101000x00xxxxxxxx000x<<xxxxxx", InstName.Vst4,        InstEmit32.Vst4,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Inc = 1/2 (itype).
+            SetAsimd("111100110xxxxxxxxxxx1000xxx0xxxx", InstName.Vsub,        InstEmit32.Vsub_I,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100100x10xxxxxxxx1101xxx0xxxx", InstName.Vsub,        InstEmit32.Vsub_V,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("1111001x1x<<xxxxxxx00010x0x0xxxx", InstName.Vsubl,       InstEmit32.Vsubl_I,     OpCode32SimdRegLong.Create,     OpCode32SimdRegLong.CreateT32);
+            SetAsimd("1111001x1x<<xxxxxxx00011x0x0xxxx", InstName.Vsubw,       InstEmit32.Vsubw_I,     OpCode32SimdRegWide.Create,     OpCode32SimdRegWide.CreateT32);
+            SetAsimd("111100111x11xxxxxxxx10xxxxx0xxxx", InstName.Vtbl,        InstEmit32.Vtbl,        OpCode32SimdTbl.Create,         OpCode32SimdTbl.CreateT32);
+            SetAsimd("111100111x11<<10xxxx00001xx0xxxx", InstName.Vtrn,        InstEmit32.Vtrn,        OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("111100100x<<xxxxxxxx1000xxx1xxxx", InstName.Vtst,        InstEmit32.Vtst,        OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100111x11<<10xxxx00010xx0xxxx", InstName.Vuzp,        InstEmit32.Vuzp,        OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("111100111x11<<10xxxx00011xx0xxxx", InstName.Vzip,        InstEmit32.Vzip,        OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
 #endregion
 
 #region "OpCode Table (AArch32, T16)"
@@ -1054,7 +1107,14 @@ namespace ARMeilleure.Decoders
             SetT16("1011101011xxxxxx", InstName.Revsh,  InstEmit32.Revsh,   OpCodeT16AluRegLow.Create);
             SetT16("101110x1xxxxxxxx", InstName.Cbnz,   InstEmit32.Cbnz,    OpCodeT16BImmCmp.Create);
             SetT16("1011110xxxxxxxxx", InstName.Pop,    InstEmit32.Ldm,     OpCodeT16MemStack.Create);
-            SetT16("10111111xxxx0000", InstName.Nop,    InstEmit32.Nop,     OpCodeT16.Create);
+            SetT16("1011111100000000", InstName.Nop,    InstEmit32.Nop,     OpCodeT16.Create);
+            SetT16("1011111100010000", InstName.Yield,  InstEmit32.Nop,     OpCodeT16.Create);
+            SetT16("1011111100100000", InstName.Wfe,    InstEmit32.Nop,     OpCodeT16.Create);
+            SetT16("1011111100110000", InstName.Wfi,    InstEmit32.Nop,     OpCodeT16.Create);
+            SetT16("1011111101000000", InstName.Sev,    InstEmit32.Nop,     OpCodeT16.Create);
+            SetT16("1011111101010000", InstName.Sevl,   InstEmit32.Nop,     OpCodeT16.Create);
+            SetT16("10111111011x0000", InstName.Hint,   InstEmit32.Nop,     OpCodeT16.Create); // Hint instruction
+            SetT16("101111111xxx0000", InstName.Hint,   InstEmit32.Nop,     OpCodeT16.Create); // Hint instruction
             SetT16("10111111xxxx>>>>", InstName.It,     InstEmit32.It,      OpCodeT16IfThen.Create);
             SetT16("11000xxxxxxxxxxx", InstName.Stm,    InstEmit32.Stm,     OpCodeT16MemMult.Create);
             SetT16("11001xxxxxxxxxxx", InstName.Ldm,    InstEmit32.Ldm,     OpCodeT16MemMult.Create);
@@ -1074,6 +1134,8 @@ namespace ARMeilleure.Decoders
             SetT32("11110x00000<xxxx0xxx<<<<xxxxxxxx", InstName.And,      InstEmit32.And,      OpCodeT32AluImm.Create);
             SetT32("11110x<<<xxxxxxx10x0xxxxxxxxxxxx", InstName.B,        InstEmit32.B,        OpCodeT32BImm20.Create);
             SetT32("11110xxxxxxxxxxx10x1xxxxxxxxxxxx", InstName.B,        InstEmit32.B,        OpCodeT32BImm24.Create);
+            SetT32("11110011011011110xxxxxxxxx0xxxxx", InstName.Bfc,      InstEmit32.Bfc,      OpCodeT32AluBf.Create);
+            SetT32("111100110110<<<<0xxxxxxxxx0xxxxx", InstName.Bfi,      InstEmit32.Bfi,      OpCodeT32AluBf.Create);
             SetT32("11101010001xxxxx0xxxxxxxxxxxxxxx", InstName.Bic,      InstEmit32.Bic,      OpCodeT32AluRsImm.Create);
             SetT32("11110x00001xxxxx0xxxxxxxxxxxxxxx", InstName.Bic,      InstEmit32.Bic,      OpCodeT32AluImm.Create);
             SetT32("11110xxxxxxxxxxx11x1xxxxxxxxxxxx", InstName.Bl,       InstEmit32.Bl,       OpCodeT32BImm24.Create);
@@ -1083,39 +1145,64 @@ namespace ARMeilleure.Decoders
             SetT32("11110x010001xxxx0xxx1111xxxxxxxx", InstName.Cmn,      InstEmit32.Cmn,      OpCodeT32AluImm.Create);
             SetT32("111010111011xxxx0xxx1111xxxxxxxx", InstName.Cmp,      InstEmit32.Cmp,      OpCodeT32AluRsImm.Create);
             SetT32("11110x011011xxxx0xxx1111xxxxxxxx", InstName.Cmp,      InstEmit32.Cmp,      OpCodeT32AluImm.Create);
+            SetT32("11110011101011111000000000010100", InstName.Csdb,     InstEmit32.Csdb,     OpCodeT32.Create);
             SetT32("11101010100<xxxx0xxx<<<<xxxxxxxx", InstName.Eor,      InstEmit32.Eor,      OpCodeT32AluRsImm.Create);
             SetT32("11110x00100<xxxx0xxx<<<<xxxxxxxx", InstName.Eor,      InstEmit32.Eor,      OpCodeT32AluImm.Create);
+            SetT32("11110011101011111000000000010000", InstName.Esb,      InstEmit32.Nop,      OpCodeT32.Create); // Error Synchronization Barrier (FEAT_RAS)
+            SetT32("1111001110101111100000000000011x", InstName.Hint,     InstEmit32.Nop,      OpCodeT32.Create); // Reserved Hint
+            SetT32("11110011101011111000000000001xxx", InstName.Hint,     InstEmit32.Nop,      OpCodeT32.Create); // Reserved Hint
+            SetT32("11110011101011111000000000010001", InstName.Hint,     InstEmit32.Nop,      OpCodeT32.Create); // Reserved Hint
+            SetT32("11110011101011111000000000010011", InstName.Hint,     InstEmit32.Nop,      OpCodeT32.Create); // Reserved Hint
+            SetT32("11110011101011111000000000010101", InstName.Hint,     InstEmit32.Nop,      OpCodeT32.Create); // Reserved Hint
+            SetT32("1111001110101111100000000001011x", InstName.Hint,     InstEmit32.Nop,      OpCodeT32.Create); // Reserved Hint
+            SetT32("11110011101011111000000000011xxx", InstName.Hint,     InstEmit32.Nop,      OpCodeT32.Create); // Reserved Hint
+            SetT32("111100111010111110000000001xxxxx", InstName.Hint,     InstEmit32.Nop,      OpCodeT32.Create); // Reserved Hint
+            SetT32("11110011101011111000000001xxxxxx", InstName.Hint,     InstEmit32.Nop,      OpCodeT32.Create); // Reserved Hint
+            SetT32("1111001110101111100000001xxxxxxx", InstName.Hint,     InstEmit32.Nop,      OpCodeT32.Create); // Reserved Hint
             SetT32("111010001101xxxxxxxx111110101111", InstName.Lda,      InstEmit32.Lda,      OpCodeT32MemLdEx.Create);
+            SetT32("111010001101xxxxxxxx111110001111", InstName.Ldab,     InstEmit32.Ldab,     OpCodeT32MemLdEx.Create);
             SetT32("111010001101xxxxxxxx111111101111", InstName.Ldaex,    InstEmit32.Ldaex,    OpCodeT32MemLdEx.Create);
+            SetT32("111010001101xxxxxxxx111111001111", InstName.Ldaexb,   InstEmit32.Ldaexb,   OpCodeT32MemLdEx.Create);
+            SetT32("111010001101xxxxxxxxxxxx11111111", InstName.Ldaexd,   InstEmit32.Ldaexd,   OpCodeT32MemLdEx.Create);
+            SetT32("111010001101xxxxxxxx111111011111", InstName.Ldaexh,   InstEmit32.Ldaexh,   OpCodeT32MemLdEx.Create);
+            SetT32("111010001101xxxxxxxx111110011111", InstName.Ldah,     InstEmit32.Ldah,     OpCodeT32MemLdEx.Create);
             SetT32("1110100010x1xxxxxxxxxxxxxxxxxxxx", InstName.Ldm,      InstEmit32.Ldm,      OpCodeT32MemMult.Create);
             SetT32("1110100100x1xxxxxxxxxxxxxxxxxxxx", InstName.Ldm,      InstEmit32.Ldm,      OpCodeT32MemMult.Create);
-            SetT32("111110000101xxxx<<<<10x1xxxxxxxx", InstName.Ldr,      InstEmit32.Ldr,      OpCodeT32MemImm8.Create);
-            SetT32("111110000101xxxx<<<<1100xxxxxxxx", InstName.Ldr,      InstEmit32.Ldr,      OpCodeT32MemImm8.Create);
-            SetT32("111110000101xxxx<<<<11x1xxxxxxxx", InstName.Ldr,      InstEmit32.Ldr,      OpCodeT32MemImm8.Create);
+            SetT32("111110000101xxxxxxxx10x1xxxxxxxx", InstName.Ldr,      InstEmit32.Ldr,      OpCodeT32MemImm8.Create);
+            SetT32("111110000101xxxxxxxx1100xxxxxxxx", InstName.Ldr,      InstEmit32.Ldr,      OpCodeT32MemImm8.Create);
+            SetT32("111110000101xxxxxxxx11x1xxxxxxxx", InstName.Ldr,      InstEmit32.Ldr,      OpCodeT32MemImm8.Create);
             SetT32("111110001101xxxxxxxxxxxxxxxxxxxx", InstName.Ldr,      InstEmit32.Ldr,      OpCodeT32MemImm12.Create);
             SetT32("111110000101<<<<xxxx000000xxxxxx", InstName.Ldr,      InstEmit32.Ldr,      OpCodeT32MemRsImm.Create);
-            SetT32("111110000001xxxx<<<<10x1xxxxxxxx", InstName.Ldrb,     InstEmit32.Ldrb,     OpCodeT32MemImm8.Create);
+            SetT32("111110000001xxxxxxxx10x1xxxxxxxx", InstName.Ldrb,     InstEmit32.Ldrb,     OpCodeT32MemImm8.Create);
             SetT32("111110000001xxxx<<<<1100xxxxxxxx", InstName.Ldrb,     InstEmit32.Ldrb,     OpCodeT32MemImm8.Create);
-            SetT32("111110000001xxxx<<<<11x1xxxxxxxx", InstName.Ldrb,     InstEmit32.Ldrb,     OpCodeT32MemImm8.Create);
-            SetT32("111110001001xxxxxxxxxxxxxxxxxxxx", InstName.Ldrb,     InstEmit32.Ldrb,     OpCodeT32MemImm12.Create);
+            SetT32("111110000001xxxxxxxx11x1xxxxxxxx", InstName.Ldrb,     InstEmit32.Ldrb,     OpCodeT32MemImm8.Create);
+            SetT32("111110001001xxxx<<<<xxxxxxxxxxxx", InstName.Ldrb,     InstEmit32.Ldrb,     OpCodeT32MemImm12.Create);
+            SetT32("111110000001xxxx<<<<000000xxxxxx", InstName.Ldrb,     InstEmit32.Ldrb,     OpCodeT32MemRsImm.Create);
             SetT32("11101000x111<<<<xxxxxxxxxxxxxxxx", InstName.Ldrd,     InstEmit32.Ldrd,     OpCodeT32MemImm8D.Create);
             SetT32("11101001x1x1<<<<xxxxxxxxxxxxxxxx", InstName.Ldrd,     InstEmit32.Ldrd,     OpCodeT32MemImm8D.Create);
-            SetT32("111110000011xxxx<<<<10x1xxxxxxxx", InstName.Ldrh,     InstEmit32.Ldrh,     OpCodeT32MemImm8.Create);
+            SetT32("111110000011xxxxxxxx10x1xxxxxxxx", InstName.Ldrh,     InstEmit32.Ldrh,     OpCodeT32MemImm8.Create);
             SetT32("111110000011xxxx<<<<1100xxxxxxxx", InstName.Ldrh,     InstEmit32.Ldrh,     OpCodeT32MemImm8.Create);
-            SetT32("111110000011xxxx<<<<11x1xxxxxxxx", InstName.Ldrh,     InstEmit32.Ldrh,     OpCodeT32MemImm8.Create);
-            SetT32("111110001011xxxxxxxxxxxxxxxxxxxx", InstName.Ldrh,     InstEmit32.Ldrh,     OpCodeT32MemImm12.Create);
-            SetT32("111110010001xxxx<<<<10x1xxxxxxxx", InstName.Ldrsb,    InstEmit32.Ldrsb,    OpCodeT32MemImm8.Create);
+            SetT32("111110000011xxxxxxxx11x1xxxxxxxx", InstName.Ldrh,     InstEmit32.Ldrh,     OpCodeT32MemImm8.Create);
+            SetT32("111110001011xxxx<<<<xxxxxxxxxxxx", InstName.Ldrh,     InstEmit32.Ldrh,     OpCodeT32MemImm12.Create);
+            SetT32("111110000011xxxx<<<<000000xxxxxx", InstName.Ldrh,     InstEmit32.Ldrh,     OpCodeT32MemRsImm.Create);
+            SetT32("111110010001xxxxxxxx10x1xxxxxxxx", InstName.Ldrsb,    InstEmit32.Ldrsb,    OpCodeT32MemImm8.Create);
             SetT32("111110010001xxxx<<<<1100xxxxxxxx", InstName.Ldrsb,    InstEmit32.Ldrsb,    OpCodeT32MemImm8.Create);
-            SetT32("111110010001xxxx<<<<11x1xxxxxxxx", InstName.Ldrsb,    InstEmit32.Ldrsb,    OpCodeT32MemImm8.Create);
-            SetT32("111110011001xxxxxxxxxxxxxxxxxxxx", InstName.Ldrsb,    InstEmit32.Ldrsb,    OpCodeT32MemImm12.Create);
-            SetT32("111110010011xxxx<<<<10x1xxxxxxxx", InstName.Ldrsh,    InstEmit32.Ldrsh,    OpCodeT32MemImm8.Create);
+            SetT32("111110010001xxxxxxxx11x1xxxxxxxx", InstName.Ldrsb,    InstEmit32.Ldrsb,    OpCodeT32MemImm8.Create);
+            SetT32("111110011001xxxx<<<<xxxxxxxxxxxx", InstName.Ldrsb,    InstEmit32.Ldrsb,    OpCodeT32MemImm12.Create);
+            SetT32("111110010001xxxx<<<<000000xxxxxx", InstName.Ldrsb,    InstEmit32.Ldrsb,    OpCodeT32MemRsImm.Create);
+            SetT32("111110010011xxxxxxxx10x1xxxxxxxx", InstName.Ldrsh,    InstEmit32.Ldrsh,    OpCodeT32MemImm8.Create);
             SetT32("111110010011xxxx<<<<1100xxxxxxxx", InstName.Ldrsh,    InstEmit32.Ldrsh,    OpCodeT32MemImm8.Create);
-            SetT32("111110010011xxxx<<<<11x1xxxxxxxx", InstName.Ldrsh,    InstEmit32.Ldrsh,    OpCodeT32MemImm8.Create);
-            SetT32("111110011011xxxxxxxxxxxxxxxxxxxx", InstName.Ldrsh,    InstEmit32.Ldrsh,    OpCodeT32MemImm12.Create);
+            SetT32("111110010011xxxxxxxx11x1xxxxxxxx", InstName.Ldrsh,    InstEmit32.Ldrsh,    OpCodeT32MemImm8.Create);
+            SetT32("111110011011xxxx<<<<xxxxxxxxxxxx", InstName.Ldrsh,    InstEmit32.Ldrsh,    OpCodeT32MemImm12.Create);
+            SetT32("111110010011xxxx<<<<000000xxxxxx", InstName.Ldrsh,    InstEmit32.Ldrsh,    OpCodeT32MemRsImm.Create);
+            SetT32("111110110000xxxx<<<<xxxx0000xxxx", InstName.Mla,      InstEmit32.Mla,      OpCodeT32AluMla.Create);
+            SetT32("111110110000xxxxxxxxxxxx0001xxxx", InstName.Mls,      InstEmit32.Mls,      OpCodeT32AluMla.Create);
             SetT32("11101010010x11110xxxxxxxxxxxxxxx", InstName.Mov,      InstEmit32.Mov,      OpCodeT32AluRsImm.Create);
             SetT32("111110100xxxxxxx1111xxxx0000xxxx", InstName.Mov,      InstEmit32.Mov,      OpCodeT32ShiftReg.Create);
             SetT32("11110x00010x11110xxxxxxxxxxxxxxx", InstName.Mov,      InstEmit32.Mov,      OpCodeT32AluImm.Create);
             SetT32("11110x100100xxxx0xxxxxxxxxxxxxxx", InstName.Mov,      InstEmit32.Mov,      OpCodeT32MovImm16.Create);
+            SetT32("11110x101100xxxx0xxxxxxxxxxxxxxx", InstName.Movt,     InstEmit32.Movt,     OpCodeT32MovImm16.Create);
+            SetT32("111110110000xxxx1111xxxx0000xxxx", InstName.Mul,      InstEmit32.Mul,      OpCodeT32AluMla.Create);
             SetT32("11101010011x11110xxxxxxxxxxxxxxx", InstName.Mvn,      InstEmit32.Mvn,      OpCodeT32AluRsImm.Create);
             SetT32("11110x00011x11110xxxxxxxxxxxxxxx", InstName.Mvn,      InstEmit32.Mvn,      OpCodeT32AluImm.Create);
             SetT32("11110011101011111000000000000000", InstName.Nop,      InstEmit32.Nop,      OpCodeT32.Create);
@@ -1123,30 +1210,85 @@ namespace ARMeilleure.Decoders
             SetT32("11110x00011x<<<<0xxxxxxxxxxxxxxx", InstName.Orn,      InstEmit32.Orn,      OpCodeT32AluImm.Create);
             SetT32("11101010010x<<<<0xxxxxxxxxxxxxxx", InstName.Orr,      InstEmit32.Orr,      OpCodeT32AluRsImm.Create);
             SetT32("11110x00010x<<<<0xxxxxxxxxxxxxxx", InstName.Orr,      InstEmit32.Orr,      OpCodeT32AluImm.Create);
+            SetT32("1111100010x1xxxx1111xxxxxxxxxxxx", InstName.Pld,      InstEmit32.Nop,      OpCodeT32.Create);
+            SetT32("1111100000x1xxxx11111100xxxxxxxx", InstName.Pld,      InstEmit32.Nop,      OpCodeT32.Create);
+            SetT32("1111100000x1xxxx1111000000xxxxxx", InstName.Pld,      InstEmit32.Nop,      OpCodeT32.Create);
             SetT32("11101011110xxxxx0xxxxxxxxxxxxxxx", InstName.Rsb,      InstEmit32.Rsb,      OpCodeT32AluRsImm.Create);
             SetT32("11110x01110xxxxx0xxxxxxxxxxxxxxx", InstName.Rsb,      InstEmit32.Rsb,      OpCodeT32AluImm.Create);
+            SetT32("111110101000xxxx1111xxxx0000xxxx", InstName.Sadd8,    InstEmit32.Sadd8,    OpCodeT32AluReg.Create);
             SetT32("11101011011xxxxx0xxxxxxxxxxxxxxx", InstName.Sbc,      InstEmit32.Sbc,      OpCodeT32AluRsImm.Create);
             SetT32("11110x01011xxxxx0xxxxxxxxxxxxxxx", InstName.Sbc,      InstEmit32.Sbc,      OpCodeT32AluImm.Create);
+            SetT32("111100110100xxxx0xxxxxxxxx0xxxxx", InstName.Sbfx,     InstEmit32.Sbfx,     OpCodeT32AluBf.Create);
+            SetT32("111110111001xxxx1111xxxx1111xxxx", InstName.Sdiv,     InstEmit32.Sdiv,     OpCodeT32AluMla.Create);
+            SetT32("111110101010xxxx1111xxxx1000xxxx", InstName.Sel,      InstEmit32.Sel,      OpCodeT32AluReg.Create);
+            SetT32("111110101000xxxx1111xxxx0010xxxx", InstName.Shadd8,   InstEmit32.Shadd8,   OpCodeT32AluReg.Create);
+            SetT32("111110101100xxxx1111xxxx0010xxxx", InstName.Shsub8,   InstEmit32.Shsub8,   OpCodeT32AluReg.Create);
+            SetT32("11110011101011111000000000000100", InstName.Sev,      InstEmit32.Nop,      OpCodeT32.Create);
+            SetT32("11110011101011111000000000000101", InstName.Sevl,     InstEmit32.Nop,      OpCodeT32.Create);
+            SetT32("111110110001xxxx<<<<xxxx00xxxxxx", InstName.Smla__,   InstEmit32.Smla__,   OpCodeT32AluMla.Create);
+            SetT32("111110111100xxxxxxxxxxxx0000xxxx", InstName.Smlal,    InstEmit32.Smlal,    OpCodeT32AluUmull.Create);
+            SetT32("111110111100xxxxxxxxxxxx10xxxxxx", InstName.Smlal__,  InstEmit32.Smlal__,  OpCodeT32AluUmull.Create);
+            SetT32("111110110011xxxx<<<<xxxx000xxxxx", InstName.Smlaw_,   InstEmit32.Smlaw_,   OpCodeT32AluMla.Create);
+            SetT32("111110110101xxxx<<<<xxxx000xxxxx", InstName.Smmla,    InstEmit32.Smmla,    OpCodeT32AluMla.Create);
+            SetT32("111110110110xxxxxxxxxxxx000xxxxx", InstName.Smmls,    InstEmit32.Smmls,    OpCodeT32AluMla.Create);
+            SetT32("111110110001xxxx1111xxxx00xxxxxx", InstName.Smul__,   InstEmit32.Smul__,   OpCodeT32AluMla.Create);
+            SetT32("111110111000xxxxxxxxxxxx0000xxxx", InstName.Smull,    InstEmit32.Smull,    OpCodeT32AluUmull.Create);
+            SetT32("111110110011xxxx1111xxxx000xxxxx", InstName.Smulw_,   InstEmit32.Smulw_,   OpCodeT32AluMla.Create);
+            SetT32("111110101100xxxx1111xxxx0000xxxx", InstName.Ssub8,    InstEmit32.Ssub8,    OpCodeT32AluReg.Create);
+            SetT32("111010001100xxxxxxxx111110101111", InstName.Stl,      InstEmit32.Stl,      OpCodeT32MemStEx.Create);
+            SetT32("111010001100xxxxxxxx111110001111", InstName.Stlb,     InstEmit32.Stlb,     OpCodeT32MemStEx.Create);
             SetT32("111010001100xxxxxxxx11111110xxxx", InstName.Stlex,    InstEmit32.Stlex,    OpCodeT32MemStEx.Create);
+            SetT32("111010001100xxxxxxxx11111100xxxx", InstName.Stlexb,   InstEmit32.Stlexb,   OpCodeT32MemStEx.Create);
+            SetT32("111010001100xxxxxxxxxxxx1111xxxx", InstName.Stlexd,   InstEmit32.Stlexd,   OpCodeT32MemStEx.Create);
+            SetT32("111010001100xxxxxxxx11111101xxxx", InstName.Stlexh,   InstEmit32.Stlexh,   OpCodeT32MemStEx.Create);
+            SetT32("111010001100xxxxxxxx111110011111", InstName.Stlh,     InstEmit32.Stlh,     OpCodeT32MemStEx.Create);
             SetT32("1110100010x0xxxx0xxxxxxxxxxxxxxx", InstName.Stm,      InstEmit32.Stm,      OpCodeT32MemMult.Create);
             SetT32("1110100100x0xxxx0xxxxxxxxxxxxxxx", InstName.Stm,      InstEmit32.Stm,      OpCodeT32MemMult.Create);
-            SetT32("111110000100xxxxxxxx1<<>xxxxxxxx", InstName.Str,      InstEmit32.Str,      OpCodeT32MemImm8.Create);
-            SetT32("111110001100xxxxxxxxxxxxxxxxxxxx", InstName.Str,      InstEmit32.Str,      OpCodeT32MemImm12.Create);
+            SetT32("111110000100<<<<xxxx10x1xxxxxxxx", InstName.Str,      InstEmit32.Str,      OpCodeT32MemImm8.Create);
+            SetT32("111110000100<<<<xxxx1100xxxxxxxx", InstName.Str,      InstEmit32.Str,      OpCodeT32MemImm8.Create);
+            SetT32("111110000100<<<<xxxx11x1xxxxxxxx", InstName.Str,      InstEmit32.Str,      OpCodeT32MemImm8.Create);
+            SetT32("111110001100<<<<xxxxxxxxxxxxxxxx", InstName.Str,      InstEmit32.Str,      OpCodeT32MemImm12.Create);
             SetT32("111110000100<<<<xxxx000000xxxxxx", InstName.Str,      InstEmit32.Str,      OpCodeT32MemRsImm.Create);
-            SetT32("111110000000xxxxxxxx1<<>xxxxxxxx", InstName.Strb,     InstEmit32.Strb,     OpCodeT32MemImm8.Create);
-            SetT32("111110001000xxxxxxxxxxxxxxxxxxxx", InstName.Strb,     InstEmit32.Strb,     OpCodeT32MemImm12.Create);
+            SetT32("111110000000<<<<xxxx10x1xxxxxxxx", InstName.Strb,     InstEmit32.Strb,     OpCodeT32MemImm8.Create);
+            SetT32("111110000000<<<<xxxx1100xxxxxxxx", InstName.Strb,     InstEmit32.Strb,     OpCodeT32MemImm8.Create);
+            SetT32("111110000000<<<<xxxx11x1xxxxxxxx", InstName.Strb,     InstEmit32.Strb,     OpCodeT32MemImm8.Create);
+            SetT32("111110001000<<<<xxxxxxxxxxxxxxxx", InstName.Strb,     InstEmit32.Strb,     OpCodeT32MemImm12.Create);
+            SetT32("111110000000<<<<xxxx000000xxxxxx", InstName.Strb,     InstEmit32.Strb,     OpCodeT32MemRsImm.Create);
             SetT32("11101000x110<<<<xxxxxxxxxxxxxxxx", InstName.Strd,     InstEmit32.Strd,     OpCodeT32MemImm8D.Create);
             SetT32("11101001x1x0<<<<xxxxxxxxxxxxxxxx", InstName.Strd,     InstEmit32.Strd,     OpCodeT32MemImm8D.Create);
-            SetT32("111110000010xxxxxxxx1<<>xxxxxxxx", InstName.Strh,     InstEmit32.Strh,     OpCodeT32MemImm8.Create);
-            SetT32("111110001010xxxxxxxxxxxxxxxxxxxx", InstName.Strh,     InstEmit32.Strh,     OpCodeT32MemImm12.Create);
+            SetT32("111110000010<<<<xxxx10x1xxxxxxxx", InstName.Strh,     InstEmit32.Strh,     OpCodeT32MemImm8.Create);
+            SetT32("111110000010<<<<xxxx1100xxxxxxxx", InstName.Strh,     InstEmit32.Strh,     OpCodeT32MemImm8.Create);
+            SetT32("111110000010<<<<xxxx11x1xxxxxxxx", InstName.Strh,     InstEmit32.Strh,     OpCodeT32MemImm8.Create);
+            SetT32("111110001010<<<<xxxxxxxxxxxxxxxx", InstName.Strh,     InstEmit32.Strh,     OpCodeT32MemImm12.Create);
+            SetT32("111110000010<<<<xxxx000000xxxxxx", InstName.Strh,     InstEmit32.Strh,     OpCodeT32MemRsImm.Create);
             SetT32("11101011101<xxxx0xxx<<<<xxxxxxxx", InstName.Sub,      InstEmit32.Sub,      OpCodeT32AluRsImm.Create);
             SetT32("11110x01101<xxxx0xxx<<<<xxxxxxxx", InstName.Sub,      InstEmit32.Sub,      OpCodeT32AluImm.Create);
+            SetT32("11110x101010xxxx0xxxxxxxxxxxxxxx", InstName.Sub,      InstEmit32.Sub,      OpCodeT32AluImm12.Create);
+            SetT32("111110100100xxxx1111xxxx10xxxxxx", InstName.Sxtb,     InstEmit32.Sxtb,     OpCodeT32AluUx.Create);
+            SetT32("111110100010xxxx1111xxxx10xxxxxx", InstName.Sxtb16,   InstEmit32.Sxtb16,   OpCodeT32AluUx.Create);
+            SetT32("111110100000xxxx1111xxxx10xxxxxx", InstName.Sxth,     InstEmit32.Sxth,     OpCodeT32AluUx.Create);
             SetT32("111010001101xxxx111100000000xxxx", InstName.Tbb,      InstEmit32.Tbb,      OpCodeT32Tb.Create);
             SetT32("111010001101xxxx111100000001xxxx", InstName.Tbh,      InstEmit32.Tbh,      OpCodeT32Tb.Create);
             SetT32("111010101001xxxx0xxx1111xxxxxxxx", InstName.Teq,      InstEmit32.Teq,      OpCodeT32AluRsImm.Create);
             SetT32("11110x001001xxxx0xxx1111xxxxxxxx", InstName.Teq,      InstEmit32.Teq,      OpCodeT32AluImm.Create);
+            SetT32("11110011101011111000000000010010", InstName.Tsb,      InstEmit32.Nop,      OpCodeT32.Create); // Trace Synchronization Barrier (FEAT_TRF)
             SetT32("111010100001xxxx0xxx1111xxxxxxxx", InstName.Tst,      InstEmit32.Tst,      OpCodeT32AluRsImm.Create);
             SetT32("11110x000001xxxx0xxx1111xxxxxxxx", InstName.Tst,      InstEmit32.Tst,      OpCodeT32AluImm.Create);
+            SetT32("111110101000xxxx1111xxxx0100xxxx", InstName.Uadd8,    InstEmit32.Uadd8,    OpCodeT32AluReg.Create);
+            SetT32("111100111100xxxx0xxxxxxxxx0xxxxx", InstName.Ubfx,     InstEmit32.Ubfx,     OpCodeT32AluBf.Create);
+            SetT32("111110111011xxxx1111xxxx1111xxxx", InstName.Udiv,     InstEmit32.Udiv,     OpCodeT32AluMla.Create);
+            SetT32("111110101000xxxx1111xxxx0110xxxx", InstName.Uhadd8,   InstEmit32.Uhadd8,   OpCodeT32AluReg.Create);
+            SetT32("111110101100xxxx1111xxxx0110xxxx", InstName.Uhsub8,   InstEmit32.Uhsub8,   OpCodeT32AluReg.Create);
+            SetT32("111110111110xxxxxxxxxxxx0110xxxx", InstName.Umaal,    InstEmit32.Umaal,    OpCodeT32AluUmull.Create);
+            SetT32("111110111110xxxxxxxxxxxx0000xxxx", InstName.Umlal,    InstEmit32.Umlal,    OpCodeT32AluUmull.Create);
+            SetT32("111110111010xxxxxxxxxxxx0000xxxx", InstName.Umull,    InstEmit32.Umull,    OpCodeT32AluUmull.Create);
+            SetT32("111110101100xxxx1111xxxx0100xxxx", InstName.Usub8,    InstEmit32.Usub8,    OpCodeT32AluReg.Create);
+            SetT32("111110100101xxxx1111xxxx10xxxxxx", InstName.Uxtb,     InstEmit32.Uxtb,     OpCodeT32AluUx.Create);
+            SetT32("111110100011xxxx1111xxxx10xxxxxx", InstName.Uxtb16,   InstEmit32.Uxtb16,   OpCodeT32AluUx.Create);
+            SetT32("111110100001xxxx1111xxxx10xxxxxx", InstName.Uxth,     InstEmit32.Uxth,     OpCodeT32AluUx.Create);
+            SetT32("11110011101011111000000000000010", InstName.Wfe,      InstEmit32.Nop,      OpCodeT32.Create);
+            SetT32("11110011101011111000000000000011", InstName.Wfi,      InstEmit32.Nop,      OpCodeT32.Create);
+            SetT32("11110011101011111000000000000001", InstName.Yield,    InstEmit32.Nop,      OpCodeT32.Create);
 #endregion
 
             FillFastLookupTable(InstA32FastLookup, AllInstA32, ToFastLookupIndexA);
@@ -1203,6 +1345,46 @@ namespace ARMeilleure.Decoders
             Set(reversedEncoding, AllInstT32, new InstDescriptor(name, emitter), reversedMakeOp);
         }
 
+        private static void SetVfp(string encoding, InstName name, InstEmitter emitter, MakeOp makeOpA32, MakeOp makeOpT32)
+        {
+            SetA32(encoding, name, emitter, makeOpA32);
+
+            string thumbEncoding = encoding;
+            if (thumbEncoding.StartsWith("<<<<"))
+            {
+                thumbEncoding = "1110" + thumbEncoding.Substring(4);
+            }
+            SetT32(thumbEncoding, name, emitter, makeOpT32);
+        }
+
+        private static void SetAsimd(string encoding, InstName name, InstEmitter emitter, MakeOp makeOpA32, MakeOp makeOpT32)
+        {
+            SetA32(encoding, name, emitter, makeOpA32);
+
+            string thumbEncoding = encoding;
+            if (thumbEncoding.StartsWith("11110100"))
+            {
+                thumbEncoding = "11111001" + encoding.Substring(8);
+            }
+            else if (thumbEncoding.StartsWith("1111001x"))
+            {
+                thumbEncoding = "111x1111" + encoding.Substring(8);
+            }
+            else if (thumbEncoding.StartsWith("11110010"))
+            {
+                thumbEncoding = "11101111" + encoding.Substring(8);
+            }
+            else if (thumbEncoding.StartsWith("11110011"))
+            {
+                thumbEncoding = "11111111" + encoding.Substring(8);
+            }
+            else
+            {
+                throw new ArgumentException("Invalid ASIMD instruction encoding");
+            }
+            SetT32(thumbEncoding, name, emitter, makeOpT32);
+        }
+
         private static void SetA64(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp)
         {
             Set(encoding, AllInstA64, new InstDescriptor(name, emitter), makeOp);

ARMeilleure/Instructions/InstEmitAlu32.cs

@@ -74,7 +74,7 @@ namespace ARMeilleure.Instructions
 
         public static void Bfc(ArmEmitterContext context)
         {
-            OpCode32AluBf op = (OpCode32AluBf)context.CurrOp;
+            IOpCode32AluBf op = (IOpCode32AluBf)context.CurrOp;
 
             Operand d = GetIntA32(context, op.Rd);
             Operand res = context.BitwiseAnd(d, Const(~op.DestMask));
@@ -84,7 +84,7 @@ namespace ARMeilleure.Instructions
 
         public static void Bfi(ArmEmitterContext context)
         {
-            OpCode32AluBf op = (OpCode32AluBf)context.CurrOp;
+            IOpCode32AluBf op = (IOpCode32AluBf)context.CurrOp;
 
             Operand n = GetIntA32(context, op.Rn);
             Operand d = GetIntA32(context, op.Rd);
@@ -185,7 +185,7 @@ namespace ARMeilleure.Instructions
 
         public static void Movt(ArmEmitterContext context)
         {
-            OpCode32AluImm16 op = (OpCode32AluImm16)context.CurrOp;
+            IOpCode32AluImm16 op = (IOpCode32AluImm16)context.CurrOp;
 
             Operand d = GetIntA32(context, op.Rd);
             Operand imm = Const(op.Immediate << 16); // Immeditate value as top halfword.
@@ -363,6 +363,11 @@ namespace ARMeilleure.Instructions
             EmitAluStore(context, res);
         }
 
+        public static void Sadd8(ArmEmitterContext context)
+        {
+            EmitAddSub8(context, add: true, unsigned: false);
+        }
+
         public static void Sbc(ArmEmitterContext context)
         {
             IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
@@ -389,7 +394,7 @@ namespace ARMeilleure.Instructions
 
         public static void Sbfx(ArmEmitterContext context)
         {
-            OpCode32AluBf op = (OpCode32AluBf)context.CurrOp;
+            IOpCode32AluBf op = (IOpCode32AluBf)context.CurrOp;
 
             var msb = op.Lsb + op.Msb; // For this instruction, the msb is actually a width.
 
@@ -401,17 +406,38 @@ namespace ARMeilleure.Instructions
 
         public static void Sdiv(ArmEmitterContext context)
         {
-            EmitDiv(context, false);
+            EmitDiv(context, unsigned: false);
+        }
+
+        public static void Sel(ArmEmitterContext context)
+        {
+            IOpCode32AluReg op = (IOpCode32AluReg)context.CurrOp;
+
+            Operand n = GetIntA32(context, op.Rn);
+            Operand m = GetIntA32(context, op.Rm);
+
+            Operand ge0 = context.ZeroExtend8(OperandType.I32, context.Negate(GetFlag(PState.GE0Flag)));
+            Operand ge1 = context.ZeroExtend8(OperandType.I32, context.Negate(GetFlag(PState.GE1Flag)));
+            Operand ge2 = context.ZeroExtend8(OperandType.I32, context.Negate(GetFlag(PState.GE2Flag)));
+            Operand ge3 = context.Negate(GetFlag(PState.GE3Flag));
+
+            Operand mask = context.BitwiseOr(ge0, context.ShiftLeft(ge1, Const(8)));
+            mask = context.BitwiseOr(mask, context.ShiftLeft(ge2, Const(16)));
+            mask = context.BitwiseOr(mask, context.ShiftLeft(ge3, Const(24)));
+
+            Operand res = context.BitwiseOr(context.BitwiseAnd(n, mask), context.BitwiseAnd(m, context.BitwiseNot(mask)));
+
+            SetIntA32(context, op.Rd, res);
         }
 
         public static void Shadd8(ArmEmitterContext context)
         {
-            EmitHadd8(context, false);
+            EmitHadd8(context, unsigned: false);
         }
 
         public static void Shsub8(ArmEmitterContext context)
         {
-            EmitHsub8(context, false);
+            EmitHsub8(context, unsigned: false);
         }
 
         public static void Ssat(ArmEmitterContext context)
@@ -428,6 +454,11 @@ namespace ARMeilleure.Instructions
             EmitSat16(context, -(1 << op.SatImm), (1 << op.SatImm) - 1);
         }
 
+        public static void Ssub8(ArmEmitterContext context)
+        {
+            EmitAddSub8(context, add: false, unsigned: false);
+        }
+
         public static void Sub(ArmEmitterContext context)
         {
             IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
@@ -482,9 +513,14 @@ namespace ARMeilleure.Instructions
             EmitNZFlagsCheck(context, res);
         }
 
+        public static void Uadd8(ArmEmitterContext context)
+        {
+            EmitAddSub8(context, add: true, unsigned: true);
+        }
+
         public static void Ubfx(ArmEmitterContext context)
         {
-            OpCode32AluBf op = (OpCode32AluBf)context.CurrOp;
+            IOpCode32AluBf op = (IOpCode32AluBf)context.CurrOp;
 
             var msb = op.Lsb + op.Msb; // For this instruction, the msb is actually a width.
 
@@ -496,17 +532,17 @@ namespace ARMeilleure.Instructions
 
         public static void Udiv(ArmEmitterContext context)
         {
-            EmitDiv(context, true);
+            EmitDiv(context, unsigned: true);
         }
 
         public static void Uhadd8(ArmEmitterContext context)
         {
-            EmitHadd8(context, true);
+            EmitHadd8(context, unsigned: true);
         }
 
         public static void Uhsub8(ArmEmitterContext context)
         {
-            EmitHsub8(context, true);
+            EmitHsub8(context, unsigned: true);
         }
 
         public static void Usat(ArmEmitterContext context)
@@ -523,6 +559,11 @@ namespace ARMeilleure.Instructions
             EmitSat16(context, 0, (1 << op.SatImm) - 1);
         }
 
+        public static void Usub8(ArmEmitterContext context)
+        {
+            EmitAddSub8(context, add: false, unsigned: true);
+        }
+
         public static void Uxtb(ArmEmitterContext context)
         {
             EmitSignExtend(context, false, 8);
@@ -678,9 +719,40 @@ namespace ARMeilleure.Instructions
             context.MarkLabel(lblEnd);
         }
 
+        private static void EmitAddSub8(ArmEmitterContext context, bool add, bool unsigned)
+        {
+            IOpCode32AluReg op = (IOpCode32AluReg)context.CurrOp;
+
+            Operand n = GetIntA32(context, op.Rn);
+            Operand m = GetIntA32(context, op.Rm);
+
+            Operand res = Const(0);
+
+            for (int byteSel = 0; byteSel < 4; byteSel++)
+            {
+                Operand shift = Const(byteSel * 8);
+
+                Operand nByte = context.ShiftRightUI(n, shift);
+                Operand mByte = context.ShiftRightUI(m, shift);
+
+                nByte = unsigned ? context.ZeroExtend8(OperandType.I32, nByte) : context.SignExtend8(OperandType.I32, nByte);
+                mByte = unsigned ? context.ZeroExtend8(OperandType.I32, mByte) : context.SignExtend8(OperandType.I32, mByte);
+
+                Operand resByte = add ? context.Add(nByte, mByte) : context.Subtract(nByte, mByte);
+
+                res = context.BitwiseOr(res, context.ShiftLeft(context.ZeroExtend8(OperandType.I32, resByte), shift));
+
+                SetFlag(context, PState.GE0Flag + byteSel, unsigned && add
+                    ? context.ShiftRightUI(resByte, Const(8))
+                    : context.ShiftRightUI(context.BitwiseNot(resByte), Const(31)));
+            }
+
+            SetIntA32(context, op.Rd, res);
+        }
+
         private static void EmitHadd8(ArmEmitterContext context, bool unsigned)
         {
-            OpCode32AluReg op = (OpCode32AluReg)context.CurrOp;
+            IOpCode32AluReg op = (IOpCode32AluReg)context.CurrOp;
 
             Operand m = GetIntA32(context, op.Rm);
             Operand n = GetIntA32(context, op.Rn);
@@ -710,7 +782,7 @@ namespace ARMeilleure.Instructions
 
         private static void EmitHsub8(ArmEmitterContext context, bool unsigned)
         {
-            OpCode32AluReg op = (OpCode32AluReg)context.CurrOp;
+            IOpCode32AluReg op = (IOpCode32AluReg)context.CurrOp;
 
             Operand m = GetIntA32(context, op.Rm);
             Operand n = GetIntA32(context, op.Rn);

ARMeilleure/Instructions/InstEmitAluHelper.cs

@@ -128,7 +128,7 @@ namespace ARMeilleure.Instructions
         {
             Debug.Assert(value.Type == OperandType.I32);
 
-            if (((OpCode32)context.CurrOp).IsThumb())
+            if (((OpCode32)context.CurrOp).IsThumb)
             {
                 bool isReturn = IsA32Return(context);
                 if (!isReturn)
@@ -205,7 +205,7 @@ namespace ARMeilleure.Instructions
                     return Const(op.Immediate);
                 }
 
-                case OpCode32AluImm16 op: return Const(op.Immediate);
+                case IOpCode32AluImm16 op: return Const(op.Immediate);
 
                 case IOpCode32AluRsImm op: return GetMShiftedByImmediate(context, op, setCarry);
                 case IOpCode32AluRsReg op: return GetMShiftedByReg(context, op, setCarry);

ARMeilleure/Instructions/InstEmitFlow32.cs

@@ -34,7 +34,7 @@ namespace ARMeilleure.Instructions
 
             uint pc = op.GetPc();
 
-            bool isThumb = ((OpCode32)context.CurrOp).IsThumb();
+            bool isThumb = ((OpCode32)context.CurrOp).IsThumb;
 
             uint currentPc = isThumb
                 ? pc | 1
@@ -61,7 +61,7 @@ namespace ARMeilleure.Instructions
             Operand addr = context.Copy(GetIntA32(context, op.Rm));
             Operand bitOne = context.BitwiseAnd(addr, Const(1));
 
-            bool isThumb = ((OpCode32)context.CurrOp).IsThumb();
+            bool isThumb = ((OpCode32)context.CurrOp).IsThumb;
 
             uint currentPc = isThumb
                 ? (pc - 2) | 1

ARMeilleure/Instructions/InstEmitMemoryEx.cs

@@ -26,6 +26,11 @@ namespace ARMeilleure.Instructions
             EmitClearExclusive(context);
         }
 
+        public static void Csdb(ArmEmitterContext context)
+        {
+            // Execute as no-op.
+        }
+
         public static void Dmb(ArmEmitterContext context) => EmitBarrier(context);
         public static void Dsb(ArmEmitterContext context) => EmitBarrier(context);
 

ARMeilleure/Instructions/InstEmitMemoryEx32.cs

@@ -172,13 +172,13 @@ namespace ARMeilleure.Instructions
                     context.BranchIfTrue(lblBigEndian, GetFlag(PState.EFlag));
 
                     SetIntA32(context, op.Rt, valueLow);
-                    SetIntA32(context, op.Rt | 1, valueHigh);
+                    SetIntA32(context, op.Rt2, valueHigh);
 
                     context.Branch(lblEnd);
 
                     context.MarkLabel(lblBigEndian);
 
-                    SetIntA32(context, op.Rt | 1, valueLow);
+                    SetIntA32(context, op.Rt2, valueLow);
                     SetIntA32(context, op.Rt, valueHigh);
 
                     context.MarkLabel(lblEnd);
@@ -195,7 +195,7 @@ namespace ARMeilleure.Instructions
                     // Split the result into 2 words (based on endianness)
 
                     Operand lo = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rt));
-                    Operand hi = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rt | 1));
+                    Operand hi = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rt2));
 
                     Operand lblBigEndian = Label();
                     Operand lblEnd = Label();

ARMeilleure/Instructions/InstEmitMul32.cs

@@ -25,7 +25,7 @@ namespace ARMeilleure.Instructions
 
         public static void Mla(ArmEmitterContext context)
         {
-            OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
+            IOpCode32AluMla op = (IOpCode32AluMla)context.CurrOp;
 
             Operand n = GetAluN(context);
             Operand m = GetAluM(context);
@@ -43,7 +43,7 @@ namespace ARMeilleure.Instructions
 
         public static void Mls(ArmEmitterContext context)
         {
-            OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
+            IOpCode32AluMla op = (IOpCode32AluMla)context.CurrOp;
 
             Operand n = GetAluN(context);
             Operand m = GetAluM(context);
@@ -71,7 +71,7 @@ namespace ARMeilleure.Instructions
 
         private static void EmitSmmul(ArmEmitterContext context, MullFlags flags)
         {
-            OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
+            IOpCode32AluMla op = (IOpCode32AluMla)context.CurrOp;
 
             Operand n = context.SignExtend32(OperandType.I64, GetIntA32(context, op.Rn));
             Operand m = context.SignExtend32(OperandType.I64, GetIntA32(context, op.Rm));
@@ -99,7 +99,7 @@ namespace ARMeilleure.Instructions
 
         public static void Smla__(ArmEmitterContext context)
         {
-            OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
+            IOpCode32AluMla op = (IOpCode32AluMla)context.CurrOp;
 
             Operand n = GetIntA32(context, op.Rn);
             Operand m = GetIntA32(context, op.Rm);
@@ -142,7 +142,7 @@ namespace ARMeilleure.Instructions
 
         public static void Smlal__(ArmEmitterContext context)
         {
-            OpCode32AluUmull op = (OpCode32AluUmull)context.CurrOp;
+            IOpCode32AluUmull op = (IOpCode32AluUmull)context.CurrOp;
 
             Operand n = GetIntA32(context, op.Rn);
             Operand m = GetIntA32(context, op.Rm);
@@ -180,7 +180,7 @@ namespace ARMeilleure.Instructions
 
         public static void Smlaw_(ArmEmitterContext context)
         {
-            OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
+            IOpCode32AluMla op = (IOpCode32AluMla)context.CurrOp;
 
             Operand n = GetIntA32(context, op.Rn);
             Operand m = GetIntA32(context, op.Rm);
@@ -210,7 +210,7 @@ namespace ARMeilleure.Instructions
 
         public static void Smul__(ArmEmitterContext context)
         {
-            OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
+            IOpCode32AluMla op = (IOpCode32AluMla)context.CurrOp;
 
             Operand n = GetIntA32(context, op.Rn);
             Operand m = GetIntA32(context, op.Rm);
@@ -240,7 +240,7 @@ namespace ARMeilleure.Instructions
 
         public static void Smull(ArmEmitterContext context)
         {
-            OpCode32AluUmull op = (OpCode32AluUmull)context.CurrOp;
+            IOpCode32AluUmull op = (IOpCode32AluUmull)context.CurrOp;
 
             Operand n = context.SignExtend32(OperandType.I64, GetIntA32(context, op.Rn));
             Operand m = context.SignExtend32(OperandType.I64, GetIntA32(context, op.Rm));
@@ -261,7 +261,7 @@ namespace ARMeilleure.Instructions
 
         public static void Smulw_(ArmEmitterContext context)
         {
-            OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
+            IOpCode32AluMla op = (IOpCode32AluMla)context.CurrOp;
 
             Operand n = GetIntA32(context, op.Rn);
             Operand m = GetIntA32(context, op.Rm);
@@ -285,7 +285,7 @@ namespace ARMeilleure.Instructions
 
         public static void Umaal(ArmEmitterContext context)
         {
-            OpCode32AluUmull op = (OpCode32AluUmull)context.CurrOp;
+            IOpCode32AluUmull op = (IOpCode32AluUmull)context.CurrOp;
 
             Operand n   = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rn));
             Operand m   = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rm));
@@ -310,7 +310,7 @@ namespace ARMeilleure.Instructions
 
         public static void Umull(ArmEmitterContext context)
         {
-            OpCode32AluUmull op = (OpCode32AluUmull)context.CurrOp;
+            IOpCode32AluUmull op = (IOpCode32AluUmull)context.CurrOp;
 
             Operand n = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rn));
             Operand m = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rm));
@@ -331,7 +331,7 @@ namespace ARMeilleure.Instructions
 
         private static void EmitMlal(ArmEmitterContext context, bool signed)
         {
-            OpCode32AluUmull op = (OpCode32AluUmull)context.CurrOp;
+            IOpCode32AluUmull op = (IOpCode32AluUmull)context.CurrOp;
 
             Operand n = GetIntA32(context, op.Rn);
             Operand m = GetIntA32(context, op.Rm);

ARMeilleure/Instructions/InstEmitSimdCvt32.cs

@@ -323,6 +323,60 @@ namespace ARMeilleure.Instructions
             }
         }
 
+        // VRINTA (vector).
+        public static void Vrinta_V(ArmEmitterContext context)
+        {
+            EmitVectorUnaryOpF32(context, (m) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, m));
+        }
+
+        // VRINTM (vector).
+        public static void Vrintm_V(ArmEmitterContext context)
+        {
+            if (Optimizations.UseSse2)
+            {
+                EmitVectorUnaryOpSimd32(context, (m) =>
+                {
+                    return context.AddIntrinsic(Intrinsic.X86Roundps, m, Const(X86GetRoundControl(FPRoundingMode.TowardsMinusInfinity)));
+                });
+            }
+            else
+            {
+                EmitVectorUnaryOpF32(context, (m) => EmitUnaryMathCall(context, nameof(Math.Floor), m));
+            }
+        }
+
+        // VRINTN (vector).
+        public static void Vrintn_V(ArmEmitterContext context)
+        {
+            if (Optimizations.UseSse2)
+            {
+                EmitVectorUnaryOpSimd32(context, (m) =>
+                {
+                    return context.AddIntrinsic(Intrinsic.X86Roundps, m, Const(X86GetRoundControl(FPRoundingMode.ToNearest)));
+                });
+            }
+            else
+            {
+                EmitVectorUnaryOpF32(context, (m) => EmitRoundMathCall(context, MidpointRounding.ToEven, m));
+            }
+        }
+
+        // VRINTP (vector).
+        public static void Vrintp_V(ArmEmitterContext context)
+        {
+            if (Optimizations.UseSse2)
+            {
+                EmitVectorUnaryOpSimd32(context, (m) =>
+                {
+                    return context.AddIntrinsic(Intrinsic.X86Roundps, m, Const(X86GetRoundControl(FPRoundingMode.TowardsPlusInfinity)));
+                });
+            }
+            else
+            {
+                EmitVectorUnaryOpF32(context, (m) => EmitUnaryMathCall(context, nameof(Math.Ceiling), m));
+            }
+        }
+
         // VRINTZ (floating-point).
         public static void Vrint_Z(ArmEmitterContext context)
         {

ARMeilleure/Instructions/InstEmitSimdHelper.cs

@@ -1533,29 +1533,88 @@ namespace ARMeilleure.Instructions
             context.Copy(d, res);
         }
 
-        // TSrc (16bit, 32bit, 64bit; signed) > TDst (8bit, 16bit, 32bit; signed, unsigned).
-        // long SignedSrcSignedDstSatQ(long op, int size); ulong SignedSrcUnsignedDstSatQ(long op, int size);
-        public static Operand EmitSignedSrcSatQ(ArmEmitterContext context, Operand op, int sizeDst, bool signedDst)
+        // long SignedSignSatQ(long op, int size);
+        public static Operand EmitSignedSignSatQ(ArmEmitterContext context, Operand op, int size)
         {
-            Debug.Assert(op.Type == OperandType.I64 && (uint)sizeDst <= 2u);
+            int eSize = 8 << size;
+
+            Debug.Assert(op.Type == OperandType.I64);
+            Debug.Assert(eSize == 8 || eSize == 16 || eSize == 32 || eSize == 64);
 
             Operand lbl1 = Label();
             Operand lblEnd = Label();
 
-            int eSize = 8 << sizeDst;
+            Operand zeroL = Const(0L);
+            Operand maxT = Const((1L << (eSize - 1)) - 1L);
+            Operand minT = Const(-(1L << (eSize - 1)));
 
-            Operand maxT = signedDst ? Const((1L << (eSize - 1)) - 1L) : Const((1UL << eSize) - 1UL);
-            Operand minT = signedDst ? Const(-(1L << (eSize - 1))) : Const(0UL);
+            Operand res = context.Copy(context.AllocateLocal(OperandType.I64), zeroL);
 
-            Operand res = context.Copy(context.AllocateLocal(OperandType.I64), op);
-
-            context.BranchIf(lbl1, res, maxT, Comparison.LessOrEqual);
+            context.BranchIf(lbl1, op, zeroL, Comparison.LessOrEqual);
             context.Copy(res, maxT);
             context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
             context.Branch(lblEnd);
 
             context.MarkLabel(lbl1);
-            context.BranchIf(lblEnd, res, minT, Comparison.GreaterOrEqual);
+            context.BranchIf(lblEnd, op, zeroL, Comparison.GreaterOrEqual);
+            context.Copy(res, minT);
+            context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
+            context.Branch(lblEnd);
+
+            context.MarkLabel(lblEnd);
+
+            return res;
+        }
+
+        // private static ulong UnsignedSignSatQ(ulong op, int size);
+        public static Operand EmitUnsignedSignSatQ(ArmEmitterContext context, Operand op, int size)
+        {
+            int eSize = 8 << size;
+
+            Debug.Assert(op.Type == OperandType.I64);
+            Debug.Assert(eSize == 8 || eSize == 16 || eSize == 32 || eSize == 64);
+
+            Operand lblEnd = Label();
+
+            Operand zeroUL = Const(0UL);
+            Operand maxT = Const(ulong.MaxValue >> (64 - eSize));
+
+            Operand res = context.Copy(context.AllocateLocal(OperandType.I64), zeroUL);
+
+            context.BranchIf(lblEnd, op, zeroUL, Comparison.LessOrEqualUI);
+            context.Copy(res, maxT);
+            context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
+            context.Branch(lblEnd);
+
+            context.MarkLabel(lblEnd);
+
+            return res;
+        }
+
+        // TSrc (16bit, 32bit, 64bit; signed) > TDst (8bit, 16bit, 32bit; signed, unsigned).
+        // long SignedSrcSignedDstSatQ(long op, int size); ulong SignedSrcUnsignedDstSatQ(long op, int size);
+        public static Operand EmitSignedSrcSatQ(ArmEmitterContext context, Operand op, int sizeDst, bool signedDst)
+        {
+            int eSizeDst = 8 << sizeDst;
+
+            Debug.Assert(op.Type == OperandType.I64);
+            Debug.Assert(eSizeDst == 8 || eSizeDst == 16 || eSizeDst == 32);
+
+            Operand lbl1 = Label();
+            Operand lblEnd = Label();
+
+            Operand maxT = signedDst ? Const((1L << (eSizeDst - 1)) - 1L) : Const((1UL << eSizeDst) - 1UL);
+            Operand minT = signedDst ? Const(-(1L << (eSizeDst - 1))) : Const(0UL);
+
+            Operand res = context.Copy(context.AllocateLocal(OperandType.I64), op);
+
+            context.BranchIf(lbl1, op, maxT, Comparison.LessOrEqual);
+            context.Copy(res, maxT);
+            context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
+            context.Branch(lblEnd);
+
+            context.MarkLabel(lbl1);
+            context.BranchIf(lblEnd, op, minT, Comparison.GreaterOrEqual);
             context.Copy(res, minT);
             context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
             context.Branch(lblEnd);
@@ -1569,18 +1628,19 @@ namespace ARMeilleure.Instructions
         // long UnsignedSrcSignedDstSatQ(ulong op, int size); ulong UnsignedSrcUnsignedDstSatQ(ulong op, int size);
         public static Operand EmitUnsignedSrcSatQ(ArmEmitterContext context, Operand op, int sizeDst, bool signedDst)
         {
-            Debug.Assert(op.Type == OperandType.I64 && (uint)sizeDst <= 2u);
+            int eSizeDst = 8 << sizeDst;
+
+            Debug.Assert(op.Type == OperandType.I64);
+            Debug.Assert(eSizeDst == 8 || eSizeDst == 16 || eSizeDst == 32);
 
             Operand lblEnd = Label();
 
-            int eSize = 8 << sizeDst;
-
-            Operand maxL = signedDst ? Const((1L << (eSize - 1)) - 1L) : Const((1UL << eSize) - 1UL);
+            Operand maxT = signedDst ? Const((1L << (eSizeDst - 1)) - 1L) : Const((1UL << eSizeDst) - 1UL);
 
             Operand res = context.Copy(context.AllocateLocal(OperandType.I64), op);
 
-            context.BranchIf(lblEnd, res, maxL, Comparison.LessOrEqualUI);
-            context.Copy(res, maxL);
+            context.BranchIf(lblEnd, op, maxT, Comparison.LessOrEqualUI);
+            context.Copy(res, maxT);
             context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
             context.Branch(lblEnd);
 
@@ -1601,7 +1661,7 @@ namespace ARMeilleure.Instructions
 
             Operand res = context.Copy(context.AllocateLocal(OperandType.I64), op);
 
-            context.BranchIf(lblEnd, res, minL, Comparison.NotEqual);
+            context.BranchIf(lblEnd, op, minL, Comparison.NotEqual);
             context.Copy(res, maxL);
             context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
             context.Branch(lblEnd);
@@ -1620,15 +1680,16 @@ namespace ARMeilleure.Instructions
 
             Operand minL = Const(long.MinValue);
             Operand maxL = Const(long.MaxValue);
-            Operand zero = Const(0L);
+            Operand zeroL = Const(0L);
 
-            Operand res = context.Copy(context.AllocateLocal(OperandType.I64), context.Add(op1, op2));
+            Operand add = context.Add(op1, op2);
+            Operand res = context.Copy(context.AllocateLocal(OperandType.I64), add);
 
             Operand left = context.BitwiseNot(context.BitwiseExclusiveOr(op1, op2));
-            Operand right = context.BitwiseExclusiveOr(op1, res);
-            context.BranchIf(lblEnd, context.BitwiseAnd(left, right), zero, Comparison.GreaterOrEqual);
+            Operand right = context.BitwiseExclusiveOr(op1, add);
+            context.BranchIf(lblEnd, context.BitwiseAnd(left, right), zeroL, Comparison.GreaterOrEqual);
 
-            Operand isPositive = context.ICompareGreaterOrEqual(op1, zero);
+            Operand isPositive = context.ICompareGreaterOrEqual(op1, zeroL);
             context.Copy(res, context.ConditionalSelect(isPositive, maxL, minL));
             context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
             context.Branch(lblEnd);
@@ -1647,9 +1708,10 @@ namespace ARMeilleure.Instructions
 
             Operand maxUL = Const(ulong.MaxValue);
 
-            Operand res = context.Copy(context.AllocateLocal(OperandType.I64), context.Add(op1, op2));
+            Operand add = context.Add(op1, op2);
+            Operand res = context.Copy(context.AllocateLocal(OperandType.I64), add);
 
-            context.BranchIf(lblEnd, res, op1, Comparison.GreaterOrEqualUI);
+            context.BranchIf(lblEnd, add, op1, Comparison.GreaterOrEqualUI);
             context.Copy(res, maxUL);
             context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
             context.Branch(lblEnd);
@@ -1668,15 +1730,16 @@ namespace ARMeilleure.Instructions
 
             Operand minL = Const(long.MinValue);
             Operand maxL = Const(long.MaxValue);
-            Operand zero = Const(0L);
+            Operand zeroL = Const(0L);
 
-            Operand res = context.Copy(context.AllocateLocal(OperandType.I64), context.Subtract(op1, op2));
+            Operand sub = context.Subtract(op1, op2);
+            Operand res = context.Copy(context.AllocateLocal(OperandType.I64), sub);
 
             Operand left = context.BitwiseExclusiveOr(op1, op2);
-            Operand right = context.BitwiseExclusiveOr(op1, res);
-            context.BranchIf(lblEnd, context.BitwiseAnd(left, right), zero, Comparison.GreaterOrEqual);
+            Operand right = context.BitwiseExclusiveOr(op1, sub);
+            context.BranchIf(lblEnd, context.BitwiseAnd(left, right), zeroL, Comparison.GreaterOrEqual);
 
-            Operand isPositive = context.ICompareGreaterOrEqual(op1, zero);
+            Operand isPositive = context.ICompareGreaterOrEqual(op1, zeroL);
             context.Copy(res, context.ConditionalSelect(isPositive, maxL, minL));
             context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
             context.Branch(lblEnd);
@@ -1693,12 +1756,13 @@ namespace ARMeilleure.Instructions
 
             Operand lblEnd = Label();
 
-            Operand zero = Const(0L);
+            Operand zeroL = Const(0L);
 
-            Operand res = context.Copy(context.AllocateLocal(OperandType.I64), context.Subtract(op1, op2));
+            Operand sub = context.Subtract(op1, op2);
+            Operand res = context.Copy(context.AllocateLocal(OperandType.I64), sub);
 
             context.BranchIf(lblEnd, op1, op2, Comparison.GreaterOrEqualUI);
-            context.Copy(res, zero);
+            context.Copy(res, zeroL);
             context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
             context.Branch(lblEnd);
 
@@ -1717,25 +1781,26 @@ namespace ARMeilleure.Instructions
             Operand lblEnd = Label();
 
             Operand maxL = Const(long.MaxValue);
-            Operand zero = Const(0L);
+            Operand zeroL = Const(0L);
 
-            Operand res = context.Copy(context.AllocateLocal(OperandType.I64), context.Add(op1, op2));
+            Operand add = context.Add(op1, op2);
+            Operand res = context.Copy(context.AllocateLocal(OperandType.I64), add);
 
             context.BranchIf(lbl1, op1, maxL, Comparison.GreaterUI);
-            Operand notOp2AndRes = context.BitwiseAnd(context.BitwiseNot(op2), res);
-            context.BranchIf(lblEnd, notOp2AndRes, zero, Comparison.GreaterOrEqual);
+            Operand notOp2AndRes = context.BitwiseAnd(context.BitwiseNot(op2), add);
+            context.BranchIf(lblEnd, notOp2AndRes, zeroL, Comparison.GreaterOrEqual);
             context.Copy(res, maxL);
             context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
             context.Branch(lblEnd);
 
             context.MarkLabel(lbl1);
-            context.BranchIf(lbl2, op2, zero, Comparison.Less);
+            context.BranchIf(lbl2, op2, zeroL, Comparison.Less);
             context.Copy(res, maxL);
             context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
             context.Branch(lblEnd);
 
             context.MarkLabel(lbl2);
-            context.BranchIf(lblEnd, res, maxL, Comparison.LessOrEqualUI);
+            context.BranchIf(lblEnd, add, maxL, Comparison.LessOrEqualUI);
             context.Copy(res, maxL);
             context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
             context.Branch(lblEnd);
@@ -1755,20 +1820,21 @@ namespace ARMeilleure.Instructions
 
             Operand maxUL = Const(ulong.MaxValue);
             Operand maxL = Const(long.MaxValue);
-            Operand zero = Const(0L);
+            Operand zeroL = Const(0L);
 
-            Operand res = context.Copy(context.AllocateLocal(OperandType.I64), context.Add(op1, op2));
+            Operand add = context.Add(op1, op2);
+            Operand res = context.Copy(context.AllocateLocal(OperandType.I64), add);
 
-            context.BranchIf(lbl1, op1, zero, Comparison.Less);
-            context.BranchIf(lblEnd, res, op1, Comparison.GreaterOrEqualUI);
+            context.BranchIf(lbl1, op1, zeroL, Comparison.Less);
+            context.BranchIf(lblEnd, add, op1, Comparison.GreaterOrEqualUI);
             context.Copy(res, maxUL);
             context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
             context.Branch(lblEnd);
 
             context.MarkLabel(lbl1);
             context.BranchIf(lblEnd, op2, maxL, Comparison.GreaterUI);
-            context.BranchIf(lblEnd, res, zero, Comparison.GreaterOrEqual);
-            context.Copy(res, zero);
+            context.BranchIf(lblEnd, add, zeroL, Comparison.GreaterOrEqual);
+            context.Copy(res, zeroL);
             context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
             context.Branch(lblEnd);
 

ARMeilleure/Instructions/InstEmitSimdMemory32.cs

@@ -67,7 +67,7 @@ namespace ARMeilleure.Instructions
 
                 for (int i = 0; i < count; i++)
                 {
-                    // Write an element from a double simd register.
+                    // Accesses an element from a double simd register.
                     Operand address = context.Add(n, Const(offset));
                     if (eBytes == 8)
                     {
@@ -131,6 +131,7 @@ namespace ARMeilleure.Instructions
             {
                 OpCode32SimdMemPair op = (OpCode32SimdMemPair)context.CurrOp;
 
+                int increment = count > 1 ? op.Increment : 1;
                 int eBytes = 1 << op.Size;
 
                 Operand n = context.Copy(GetIntA32(context, op.Rn));
@@ -144,7 +145,7 @@ namespace ARMeilleure.Instructions
                         int elemD = d + reg;
                         for (int i = 0; i < count; i++)
                         {
-                            // Write an element from a double simd register
+                            // Accesses an element from a double simd register,
                             // add ebytes for each element.
                             Operand address = context.Add(n, Const(offset));
                             int index = ((elemD & 1) << (3 - op.Size)) + elem;
@@ -161,7 +162,6 @@ namespace ARMeilleure.Instructions
                             }
                             else
                             {
-
                                 if (load)
                                 {
                                     EmitLoadSimd(context, address, GetVecA32(elemD >> 1), elemD >> 1, index, op.Size);
@@ -173,7 +173,7 @@ namespace ARMeilleure.Instructions
                             }
 
                             offset += eBytes;
-                            elemD += op.Increment;
+                            elemD += increment;
                         }
                     }
                 }

ARMeilleure/Instructions/InstEmitSimdShift.cs

@@ -188,23 +188,7 @@ namespace ARMeilleure.Instructions
 
         public static void Sqrshl_V(ArmEmitterContext context)
         {
-            OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
-
-            Operand res = context.VectorZero();
-
-            int elems = op.GetBytesCount() >> op.Size;
-
-            for (int index = 0; index < elems; index++)
-            {
-                Operand ne = EmitVectorExtractSx(context, op.Rn, index, op.Size);
-                Operand me = EmitVectorExtractSx(context, op.Rm, index, op.Size);
-
-                Operand e = context.Call(typeof(SoftFallback).GetMethod(nameof(SoftFallback.SignedShlRegSatQ)), ne, me, Const(1), Const(op.Size));
-
-                res = EmitVectorInsert(context, res, e, index, op.Size);
-            }
-
-            context.Copy(GetVec(op.Rd), res);
+            EmitShlRegOp(context, ShlRegFlags.Signed | ShlRegFlags.Round | ShlRegFlags.Saturating);
         }
 
         public static void Sqrshrn_S(ArmEmitterContext context)
@@ -229,23 +213,7 @@ namespace ARMeilleure.Instructions
 
         public static void Sqshl_V(ArmEmitterContext context)
         {
-            OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
-
-            Operand res = context.VectorZero();
-
-            int elems = op.GetBytesCount() >> op.Size;
-
-            for (int index = 0; index < elems; index++)
-            {
-                Operand ne = EmitVectorExtractSx(context, op.Rn, index, op.Size);
-                Operand me = EmitVectorExtractSx(context, op.Rm, index, op.Size);
-
-                Operand e = context.Call(typeof(SoftFallback).GetMethod(nameof(SoftFallback.SignedShlRegSatQ)), ne, me, Const(0), Const(op.Size));
-
-                res = EmitVectorInsert(context, res, e, index, op.Size);
-            }
-
-            context.Copy(GetVec(op.Rd), res);
+            EmitShlRegOp(context, ShlRegFlags.Signed | ShlRegFlags.Saturating);
         }
 
         public static void Sqshrn_S(ArmEmitterContext context)
@@ -280,23 +248,7 @@ namespace ARMeilleure.Instructions
 
         public static void Srshl_V(ArmEmitterContext context)
         {
-            OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
-
-            Operand res = context.VectorZero();
-
-            int elems = op.GetBytesCount() >> op.Size;
-
-            for (int index = 0; index < elems; index++)
-            {
-                Operand ne = EmitVectorExtractSx(context, op.Rn, index, op.Size);
-                Operand me = EmitVectorExtractSx(context, op.Rm, index, op.Size);
-
-                Operand e = context.Call(typeof(SoftFallback).GetMethod(nameof(SoftFallback.SignedShlReg)), ne, me, Const(1), Const(op.Size));
-
-                res = EmitVectorInsert(context, res, e, index, op.Size);
-            }
-
-            context.Copy(GetVec(op.Rd), res);
+            EmitShlRegOp(context, ShlRegFlags.Signed | ShlRegFlags.Round);
         }
 
         public static void Srshr_S(ArmEmitterContext context)
@@ -393,12 +345,12 @@ namespace ARMeilleure.Instructions
 
         public static void Sshl_S(ArmEmitterContext context)
         {
-            EmitSshlOrUshl(context, signed: true, scalar: true);
+            EmitShlRegOp(context, ShlRegFlags.Scalar | ShlRegFlags.Signed);
         }
 
         public static void Sshl_V(ArmEmitterContext context)
         {
-            EmitSshlOrUshl(context, signed: true, scalar: false);
+            EmitShlRegOp(context, ShlRegFlags.Signed);
         }
 
         public static void Sshll_V(ArmEmitterContext context)
@@ -506,23 +458,7 @@ namespace ARMeilleure.Instructions
 
         public static void Uqrshl_V(ArmEmitterContext context)
         {
-            OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
-
-            Operand res = context.VectorZero();
-
-            int elems = op.GetBytesCount() >> op.Size;
-
-            for (int index = 0; index < elems; index++)
-            {
-                Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size);
-                Operand me = EmitVectorExtractZx(context, op.Rm, index, op.Size);
-
-                Operand e = context.Call(typeof(SoftFallback).GetMethod(nameof(SoftFallback.UnsignedShlRegSatQ)), ne, me, Const(1), Const(op.Size));
-
-                res = EmitVectorInsert(context, res, e, index, op.Size);
-            }
-
-            context.Copy(GetVec(op.Rd), res);
+            EmitShlRegOp(context, ShlRegFlags.Round | ShlRegFlags.Saturating);
         }
 
         public static void Uqrshrn_S(ArmEmitterContext context)
@@ -537,23 +473,7 @@ namespace ARMeilleure.Instructions
 
         public static void Uqshl_V(ArmEmitterContext context)
         {
-            OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
-
-            Operand res = context.VectorZero();
-
-            int elems = op.GetBytesCount() >> op.Size;
-
-            for (int index = 0; index < elems; index++)
-            {
-                Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size);
-                Operand me = EmitVectorExtractZx(context, op.Rm, index, op.Size);
-
-                Operand e = context.Call(typeof(SoftFallback).GetMethod(nameof(SoftFallback.UnsignedShlRegSatQ)), ne, me, Const(0), Const(op.Size));
-
-                res = EmitVectorInsert(context, res, e, index, op.Size);
-            }
-
-            context.Copy(GetVec(op.Rd), res);
+            EmitShlRegOp(context, ShlRegFlags.Saturating);
         }
 
         public static void Uqshrn_S(ArmEmitterContext context)
@@ -568,23 +488,7 @@ namespace ARMeilleure.Instructions
 
         public static void Urshl_V(ArmEmitterContext context)
         {
-            OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
-
-            Operand res = context.VectorZero();
-
-            int elems = op.GetBytesCount() >> op.Size;
-
-            for (int index = 0; index < elems; index++)
-            {
-                Operand ne = EmitVectorExtractZx(context, op.Rn, index, op.Size);
-                Operand me = EmitVectorExtractZx(context, op.Rm, index, op.Size);
-
-                Operand e = context.Call(typeof(SoftFallback).GetMethod(nameof(SoftFallback.UnsignedShlReg)), ne, me, Const(1), Const(op.Size));
-
-                res = EmitVectorInsert(context, res, e, index, op.Size);
-            }
-
-            context.Copy(GetVec(op.Rd), res);
+            EmitShlRegOp(context, ShlRegFlags.Round);
         }
 
         public static void Urshr_S(ArmEmitterContext context)
@@ -677,12 +581,12 @@ namespace ARMeilleure.Instructions
 
         public static void Ushl_S(ArmEmitterContext context)
         {
-            EmitSshlOrUshl(context, signed: false, scalar: true);
+            EmitShlRegOp(context, ShlRegFlags.Scalar);
         }
 
         public static void Ushl_V(ArmEmitterContext context)
         {
-            EmitSshlOrUshl(context, signed: false, scalar: false);
+            EmitShlRegOp(context, ShlRegFlags.None);
         }
 
         public static void Ushll_V(ArmEmitterContext context)
@@ -872,43 +776,6 @@ namespace ARMeilleure.Instructions
             context.Copy(GetVec(op.Rd), res);
         }
 
-        private static Operand EmitShlRegOp(ArmEmitterContext context, Operand op, Operand shiftLsB, int size, bool signed)
-        {
-            Debug.Assert(op.Type       == OperandType.I64);
-            Debug.Assert(shiftLsB.Type == OperandType.I32);
-            Debug.Assert((uint)size < 4u);
-
-            Operand negShiftLsB = context.Negate(shiftLsB);
-
-            Operand isInRange = context.BitwiseAnd(
-                context.ICompareLess(shiftLsB,    Const(8 << size)),
-                context.ICompareLess(negShiftLsB, Const(8 << size)));
-
-            Operand isPositive = context.ICompareGreaterOrEqual(shiftLsB, Const(0));
-
-            Operand shl = context.ShiftLeft(op, shiftLsB);
-
-            Operand sarOrShr = signed
-                ? context.ShiftRightSI(op, negShiftLsB)
-                : context.ShiftRightUI(op, negShiftLsB);
-
-            Operand res = context.ConditionalSelect(isPositive, shl, sarOrShr);
-
-            if (signed)
-            {
-                Operand isPositive2 = context.ICompareGreaterOrEqual(op, Const(0L));
-
-                Operand res2 = context.ConditionalSelect(isPositive2, Const(0L), Const(-1L));
-                        res2 = context.ConditionalSelect(isPositive,  Const(0L), res2);
-
-                return context.ConditionalSelect(isInRange, res, res2);
-            }
-            else
-            {
-                return context.ConditionalSelect(isInRange, res, Const(0UL));
-            }
-        }
-
         private static void EmitVectorShrImmNarrowOpZx(ArmEmitterContext context, bool round)
         {
             OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp;
@@ -1168,8 +1035,23 @@ namespace ARMeilleure.Instructions
             }
         }
 
-        private static void EmitSshlOrUshl(ArmEmitterContext context, bool signed, bool scalar)
+        [Flags]
+        private enum ShlRegFlags
         {
+            None = 0,
+            Scalar = 1 << 0,
+            Signed = 1 << 1,
+            Round = 1 << 2,
+            Saturating = 1 << 3
+        }
+
+        private static void EmitShlRegOp(ArmEmitterContext context, ShlRegFlags flags = ShlRegFlags.None)
+        {
+            bool scalar = flags.HasFlag(ShlRegFlags.Scalar);
+            bool signed = flags.HasFlag(ShlRegFlags.Signed);
+            bool round = flags.HasFlag(ShlRegFlags.Round);
+            bool saturating = flags.HasFlag(ShlRegFlags.Saturating);
+
             OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
 
             Operand res = context.VectorZero();
@@ -1178,15 +1060,225 @@ namespace ARMeilleure.Instructions
 
             for (int index = 0; index < elems; index++)
             {
-                Operand ne = EmitVectorExtract  (context, op.Rn, index, op.Size, signed);
-                Operand me = EmitVectorExtractSx(context, op.Rm, index << op.Size, 0);
+                Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size, signed);
+                Operand me = EmitVectorExtractSx(context, op.Rm, index << op.Size, size: 0);
 
-                Operand e = EmitShlRegOp(context, ne, context.ConvertI64ToI32(me), op.Size, signed);
+                Operand e = !saturating
+                    ? EmitShlReg(context, ne, context.ConvertI64ToI32(me), round, op.Size, signed)
+                    : EmitShlRegSatQ(context, ne, context.ConvertI64ToI32(me), round, op.Size, signed);
 
                 res = EmitVectorInsert(context, res, e, index, op.Size);
             }
 
             context.Copy(GetVec(op.Rd), res);
         }
+
+        // long SignedShlReg(long op, int shiftLsB, bool round, int size);
+        // ulong UnsignedShlReg(ulong op, int shiftLsB, bool round, int size);
+        private static Operand EmitShlReg(ArmEmitterContext context, Operand op, Operand shiftLsB, bool round, int size, bool signed)
+        {
+            int eSize = 8 << size;
+
+            Debug.Assert(op.Type == OperandType.I64);
+            Debug.Assert(shiftLsB.Type == OperandType.I32);
+            Debug.Assert(eSize == 8 || eSize == 16 || eSize == 32 || eSize == 64);
+
+            Operand lbl1 = Label();
+            Operand lblEnd = Label();
+
+            Operand eSizeOp = Const(eSize);
+            Operand zero = Const(0);
+            Operand zeroL = Const(0L);
+
+            Operand res = context.Copy(context.AllocateLocal(OperandType.I64), op);
+
+            context.BranchIf(lbl1, shiftLsB, zero, Comparison.GreaterOrEqual);
+            context.Copy(res, signed
+                ? EmitSignedShrReg(context, op, context.Negate(shiftLsB), round, eSize)
+                : EmitUnsignedShrReg(context, op, context.Negate(shiftLsB), round, eSize));
+            context.Branch(lblEnd);
+
+            context.MarkLabel(lbl1);
+            context.BranchIf(lblEnd, shiftLsB, zero, Comparison.LessOrEqual);
+            Operand shl = context.ShiftLeft(op, shiftLsB);
+            Operand isGreaterOrEqual = context.ICompareGreaterOrEqual(shiftLsB, eSizeOp);
+            context.Copy(res, context.ConditionalSelect(isGreaterOrEqual, zeroL, shl));
+            context.Branch(lblEnd);
+
+            context.MarkLabel(lblEnd);
+
+            return res;
+        }
+
+        // long SignedShlRegSatQ(long op, int shiftLsB, bool round, int size);
+        // ulong UnsignedShlRegSatQ(ulong op, int shiftLsB, bool round, int size);
+        private static Operand EmitShlRegSatQ(ArmEmitterContext context, Operand op, Operand shiftLsB, bool round, int size, bool signed)
+        {
+            int eSize = 8 << size;
+
+            Debug.Assert(op.Type == OperandType.I64);
+            Debug.Assert(shiftLsB.Type == OperandType.I32);
+            Debug.Assert(eSize == 8 || eSize == 16 || eSize == 32 || eSize == 64);
+
+            Operand lbl1 = Label();
+            Operand lbl2 = Label();
+            Operand lblEnd = Label();
+
+            Operand eSizeOp = Const(eSize);
+            Operand zero = Const(0);
+
+            Operand res = context.Copy(context.AllocateLocal(OperandType.I64), op);
+
+            context.BranchIf(lbl1, shiftLsB, zero, Comparison.GreaterOrEqual);
+            context.Copy(res, signed
+                ? EmitSignedShrReg(context, op, context.Negate(shiftLsB), round, eSize)
+                : EmitUnsignedShrReg(context, op, context.Negate(shiftLsB), round, eSize));
+            context.Branch(lblEnd);
+
+            context.MarkLabel(lbl1);
+            context.BranchIf(lblEnd, shiftLsB, zero, Comparison.LessOrEqual);
+            context.BranchIf(lbl2, shiftLsB, eSizeOp, Comparison.Less);
+            context.Copy(res, signed
+                ? EmitSignedSignSatQ(context, op, size)
+                : EmitUnsignedSignSatQ(context, op, size));
+            context.Branch(lblEnd);
+
+            context.MarkLabel(lbl2);
+            Operand shl = context.ShiftLeft(op, shiftLsB);
+            if (eSize == 64)
+            {
+                Operand sarOrShr = signed
+                    ? context.ShiftRightSI(shl, shiftLsB)
+                    : context.ShiftRightUI(shl, shiftLsB);
+                context.Copy(res, shl);
+                context.BranchIf(lblEnd, sarOrShr, op, Comparison.Equal);
+                context.Copy(res, signed
+                    ? EmitSignedSignSatQ(context, op, size)
+                    : EmitUnsignedSignSatQ(context, op, size));
+            }
+            else
+            {
+                context.Copy(res, signed
+                    ? EmitSignedSrcSatQ(context, shl, size, signedDst: true)
+                    : EmitUnsignedSrcSatQ(context, shl, size, signedDst: false));
+            }
+            context.Branch(lblEnd);
+
+            context.MarkLabel(lblEnd);
+
+            return res;
+        }
+
+        // shift := [1, 128]; eSize := {8, 16, 32, 64}.
+        // long SignedShrReg(long op, int shift, bool round, int eSize);
+        private static Operand EmitSignedShrReg(ArmEmitterContext context, Operand op, Operand shift, bool round, int eSize)
+        {
+            if (round)
+            {
+                Operand lblEnd = Label();
+
+                Operand eSizeOp = Const(eSize);
+                Operand zeroL = Const(0L);
+                Operand one = Const(1);
+                Operand oneL = Const(1L);
+
+                Operand res = context.Copy(context.AllocateLocal(OperandType.I64), zeroL);
+
+                context.BranchIf(lblEnd, shift, eSizeOp, Comparison.GreaterOrEqual);
+                Operand roundConst = context.ShiftLeft(oneL, context.Subtract(shift, one));
+                Operand add = context.Add(op, roundConst);
+                Operand sar = context.ShiftRightSI(add, shift);
+                if (eSize == 64)
+                {
+                    Operand shr = context.ShiftRightUI(add, shift);
+                    Operand left = context.BitwiseAnd(context.Negate(op), context.BitwiseExclusiveOr(op, add));
+                    Operand isLess = context.ICompareLess(left, zeroL);
+                    context.Copy(res, context.ConditionalSelect(isLess, shr, sar));
+                }
+                else
+                {
+                    context.Copy(res, sar);
+                }
+                context.Branch(lblEnd);
+
+                context.MarkLabel(lblEnd);
+
+                return res;
+            }
+            else
+            {
+                Operand lblEnd = Label();
+
+                Operand eSizeOp = Const(eSize);
+                Operand zeroL = Const(0L);
+                Operand negOneL = Const(-1L);
+
+                Operand sar = context.ShiftRightSI(op, shift);
+                Operand res = context.Copy(context.AllocateLocal(OperandType.I64), sar);
+
+                context.BranchIf(lblEnd, shift, eSizeOp, Comparison.Less);
+                Operand isLess = context.ICompareLess(op, zeroL);
+                context.Copy(res, context.ConditionalSelect(isLess, negOneL, zeroL));
+                context.Branch(lblEnd);
+
+                context.MarkLabel(lblEnd);
+
+                return res;
+            }
+        }
+
+        // shift := [1, 128]; eSize := {8, 16, 32, 64}.
+        // ulong UnsignedShrReg(ulong op, int shift, bool round, int eSize);
+        private static Operand EmitUnsignedShrReg(ArmEmitterContext context, Operand op, Operand shift, bool round, int eSize)
+        {
+            if (round)
+            {
+                Operand lblEnd = Label();
+
+                Operand zeroUL = Const(0UL);
+                Operand one = Const(1);
+                Operand oneUL = Const(1UL);
+                Operand eSizeMaxOp = Const(64);
+                Operand oneShl63UL = Const(1UL << 63);
+
+                Operand res = context.Copy(context.AllocateLocal(OperandType.I64), zeroUL);
+
+                context.BranchIf(lblEnd, shift, eSizeMaxOp, Comparison.Greater);
+                Operand roundConst = context.ShiftLeft(oneUL, context.Subtract(shift, one));
+                Operand add = context.Add(op, roundConst);
+                Operand shr = context.ShiftRightUI(add, shift);
+                Operand isEqual = context.ICompareEqual(shift, eSizeMaxOp);
+                context.Copy(res, context.ConditionalSelect(isEqual, zeroUL, shr));
+                if (eSize == 64)
+                {
+                    context.BranchIf(lblEnd, add, op, Comparison.GreaterOrEqualUI);
+                    Operand right = context.BitwiseOr(shr, context.ShiftRightUI(oneShl63UL, context.Subtract(shift, one)));
+                    context.Copy(res, context.ConditionalSelect(isEqual, oneUL, right));
+                }
+                context.Branch(lblEnd);
+
+                context.MarkLabel(lblEnd);
+
+                return res;
+            }
+            else
+            {
+                Operand lblEnd = Label();
+
+                Operand eSizeOp = Const(eSize);
+                Operand zeroUL = Const(0UL);
+
+                Operand shr = context.ShiftRightUI(op, shift);
+                Operand res = context.Copy(context.AllocateLocal(OperandType.I64), shr);
+
+                context.BranchIf(lblEnd, shift, eSizeOp, Comparison.Less);
+                context.Copy(res, zeroUL);
+                context.Branch(lblEnd);
+
+                context.MarkLabel(lblEnd);
+
+                return res;
+            }
+        }
     }
 }

ARMeilleure/Instructions/InstEmitSystem.cs

@@ -15,11 +15,6 @@ namespace ARMeilleure.Instructions
         private const int DczSizeLog2 = 4; // Log2 size in words
         public const int DczSizeInBytes = 4 << DczSizeLog2;
 
-        public static void Hint(ArmEmitterContext context)
-        {
-            // Execute as no-op.
-        }
-
         public static void Isb(ArmEmitterContext context)
         {
             // Execute as no-op.

ARMeilleure/Instructions/InstName.cs

@@ -45,6 +45,7 @@ namespace ARMeilleure.Instructions
         Dsb,
         Eon,
         Eor,
+        Esb,
         Extr,
         Hint,
         Isb,
@@ -81,6 +82,9 @@ namespace ARMeilleure.Instructions
         Sbcs,
         Sbfm,
         Sdiv,
+        Sel,
+        Sev,
+        Sevl,
         Shsub8,
         Smaddl,
         Smsubl,
@@ -104,12 +108,16 @@ namespace ARMeilleure.Instructions
         Sys,
         Tbnz,
         Tbz,
+        Tsb,
         Ubfm,
         Udiv,
         Umaddl,
         Umsubl,
         Umulh,
         Und,
+        Wfe,
+        Wfi,
+        Yield,
 
         // FP & SIMD (AArch64)
         Abs_S,
@@ -519,6 +527,7 @@ namespace ARMeilleure.Instructions
         Revsh,
         Rsb,
         Rsc,
+        Sadd8,
         Sbfx,
         Shadd8,
         Smla__,
@@ -529,6 +538,7 @@ namespace ARMeilleure.Instructions
         Smmls,
         Smul__,
         Smmul,
+        Ssub8,
         Stl,
         Stlb,
         Stlex,
@@ -550,6 +560,7 @@ namespace ARMeilleure.Instructions
         Teq,
         Trap,
         Tst,
+        Uadd8,
         Ubfx,
         Uhadd8,
         Uhsub8,
@@ -558,6 +569,7 @@ namespace ARMeilleure.Instructions
         Umull,
         Usat,
         Usat16,
+        Usub8,
         Uxtb,
         Uxtb16,
         Uxth,
@@ -636,6 +648,10 @@ namespace ARMeilleure.Instructions
         Vrev,
         Vrhadd,
         Vrint,
+        Vrinta,
+        Vrintm,
+        Vrintn,
+        Vrintp,
         Vrintx,
         Vrshr,
         Vrshrn,

ARMeilleure/Instructions/SoftFallback.cs

@@ -5,287 +5,6 @@ namespace ARMeilleure.Instructions
 {
     static class SoftFallback
     {
-#region "ShlReg"
-        public static long SignedShlReg(long value, long shift, bool round, int size)
-        {
-            int eSize = 8 << size;
-
-            int shiftLsB = (sbyte)shift;
-
-            if (shiftLsB < 0)
-            {
-                return SignedShrReg(value, -shiftLsB, round, eSize);
-            }
-            else if (shiftLsB > 0)
-            {
-                if (shiftLsB >= eSize)
-                {
-                    return 0L;
-                }
-
-                return value << shiftLsB;
-            }
-            else /* if (shiftLsB == 0) */
-            {
-                return value;
-            }
-        }
-
-        public static ulong UnsignedShlReg(ulong value, ulong shift, bool round, int size)
-        {
-            int eSize = 8 << size;
-
-            int shiftLsB = (sbyte)shift;
-
-            if (shiftLsB < 0)
-            {
-                return UnsignedShrReg(value, -shiftLsB, round, eSize);
-            }
-            else if (shiftLsB > 0)
-            {
-                if (shiftLsB >= eSize)
-                {
-                    return 0UL;
-                }
-
-                return value << shiftLsB;
-            }
-            else /* if (shiftLsB == 0) */
-            {
-                return value;
-            }
-        }
-
-        public static long SignedShlRegSatQ(long value, long shift, bool round, int size)
-        {
-            ExecutionContext context = NativeInterface.GetContext();
-
-            int eSize = 8 << size;
-
-            int shiftLsB = (sbyte)shift;
-
-            if (shiftLsB < 0)
-            {
-                return SignedShrReg(value, -shiftLsB, round, eSize);
-            }
-            else if (shiftLsB > 0)
-            {
-                if (shiftLsB >= eSize)
-                {
-                    return SignedSignSatQ(value, eSize, context);
-                }
-
-                if (eSize == 64)
-                {
-                    long shl = value << shiftLsB;
-                    long shr = shl   >> shiftLsB;
-
-                    if (shr != value)
-                    {
-                        return SignedSignSatQ(value, eSize, context);
-                    }
-                    else /* if (shr == value) */
-                    {
-                        return shl;
-                    }
-                }
-                else /* if (eSize != 64) */
-                {
-                    return SignedSrcSignedDstSatQ(value << shiftLsB, size); // InstEmitSimdHelper.EmitSignedSrcSatQ(signedDst: true).
-                }
-            }
-            else /* if (shiftLsB == 0) */
-            {
-                return value;
-            }
-        }
-
-        public static ulong UnsignedShlRegSatQ(ulong value, ulong shift, bool round, int size)
-        {
-            ExecutionContext context = NativeInterface.GetContext();
-
-            int eSize = 8 << size;
-
-            int shiftLsB = (sbyte)shift;
-
-            if (shiftLsB < 0)
-            {
-                return UnsignedShrReg(value, -shiftLsB, round, eSize);
-            }
-            else if (shiftLsB > 0)
-            {
-                if (shiftLsB >= eSize)
-                {
-                    return UnsignedSignSatQ(value, eSize, context);
-                }
-
-                if (eSize == 64)
-                {
-                    ulong shl = value << shiftLsB;
-                    ulong shr = shl   >> shiftLsB;
-
-                    if (shr != value)
-                    {
-                        return UnsignedSignSatQ(value, eSize, context);
-                    }
-                    else /* if (shr == value) */
-                    {
-                        return shl;
-                    }
-                }
-                else /* if (eSize != 64) */
-                {
-                    return UnsignedSrcUnsignedDstSatQ(value << shiftLsB, size); // InstEmitSimdHelper.EmitUnsignedSrcSatQ(signedDst: false).
-                }
-            }
-            else /* if (shiftLsB == 0) */
-            {
-                return value;
-            }
-        }
-
-        private static long SignedShrReg(long value, int shift, bool round, int eSize) // shift := [1, 128]; eSize := {8, 16, 32, 64}.
-        {
-            if (round)
-            {
-                if (shift >= eSize)
-                {
-                    return 0L;
-                }
-
-                long roundConst = 1L << (shift - 1);
-
-                long add = value + roundConst;
-
-                if (eSize == 64)
-                {
-                    if ((~value & (value ^ add)) < 0L)
-                    {
-                        return (long)((ulong)add >> shift);
-                    }
-                    else
-                    {
-                        return add >> shift;
-                    }
-                }
-                else /* if (eSize != 64) */
-                {
-                    return add >> shift;
-                }
-            }
-            else /* if (!round) */
-            {
-                if (shift >= eSize)
-                {
-                    if (value < 0L)
-                    {
-                        return -1L;
-                    }
-                    else /* if (value >= 0L) */
-                    {
-                        return 0L;
-                    }
-                }
-
-                return value >> shift;
-            }
-        }
-
-        private static ulong UnsignedShrReg(ulong value, int shift, bool round, int eSize) // shift := [1, 128]; eSize := {8, 16, 32, 64}.
-        {
-            if (round)
-            {
-                if (shift > 64)
-                {
-                    return 0UL;
-                }
-
-                ulong roundConst = 1UL << (shift - 1);
-
-                ulong add = value + roundConst;
-
-                if (eSize == 64)
-                {
-                    if ((add < value) && (add < roundConst))
-                    {
-                        if (shift == 64)
-                        {
-                            return 1UL;
-                        }
-
-                        return (add >> shift) | (0x8000000000000000UL >> (shift - 1));
-                    }
-                    else
-                    {
-                        if (shift == 64)
-                        {
-                            return 0UL;
-                        }
-
-                        return add >> shift;
-                    }
-                }
-                else /* if (eSize != 64) */
-                {
-                    if (shift == 64)
-                    {
-                        return 0UL;
-                    }
-
-                    return add >> shift;
-                }
-            }
-            else /* if (!round) */
-            {
-                if (shift >= eSize)
-                {
-                    return 0UL;
-                }
-
-                return value >> shift;
-            }
-        }
-
-        private static long SignedSignSatQ(long op, int eSize, ExecutionContext context) // eSize := {8, 16, 32, 64}.
-        {
-            long tMaxValue =  (1L << (eSize - 1)) - 1L;
-            long tMinValue = -(1L << (eSize - 1));
-
-            if (op > 0L)
-            {
-                context.Fpsr |= FPSR.Qc;
-
-                return tMaxValue;
-            }
-            else if (op < 0L)
-            {
-                context.Fpsr |= FPSR.Qc;
-
-                return tMinValue;
-            }
-            else
-            {
-                return 0L;
-            }
-        }
-
-        private static ulong UnsignedSignSatQ(ulong op, int eSize, ExecutionContext context) // eSize := {8, 16, 32, 64}.
-        {
-            ulong tMaxValue = ulong.MaxValue >> (64 - eSize);
-
-            if (op > 0UL)
-            {
-                context.Fpsr |= FPSR.Qc;
-
-                return tMaxValue;
-            }
-            else
-            {
-                return 0UL;
-            }
-        }
-#endregion
-
 #region "ShrImm64"
         public static long SignedShrImm64(long value, long roundConst, int shift)
         {
@@ -508,55 +227,6 @@ namespace ARMeilleure.Instructions
         }
 #endregion
 
-#region "Saturating"
-        private static long SignedSrcSignedDstSatQ(long op, int size)
-        {
-            ExecutionContext context = NativeInterface.GetContext();
-
-            int eSize = 8 << size;
-
-            long tMaxValue =  (1L << (eSize - 1)) - 1L;
-            long tMinValue = -(1L << (eSize - 1));
-
-            if (op > tMaxValue)
-            {
-                context.Fpsr |= FPSR.Qc;
-
-                return tMaxValue;
-            }
-            else if (op < tMinValue)
-            {
-                context.Fpsr |= FPSR.Qc;
-
-                return tMinValue;
-            }
-            else
-            {
-                return op;
-            }
-        }
-
-        private static ulong UnsignedSrcUnsignedDstSatQ(ulong op, int size)
-        {
-            ExecutionContext context = NativeInterface.GetContext();
-
-            int eSize = 8 << size;
-
-            ulong tMaxValue = (1UL << eSize) - 1UL;
-
-            if (op > tMaxValue)
-            {
-                context.Fpsr |= FPSR.Qc;
-
-                return tMaxValue;
-            }
-            else
-            {
-                return op;
-            }
-        }
-#endregion
-
 #region "Count"
         public static ulong CountLeadingSigns(ulong value, int size) // size is 8, 16, 32 or 64 (SIMD&FP or Base Inst.).
         {

ARMeilleure/State/PState.cs

@@ -4,6 +4,10 @@ namespace ARMeilleure.State
     {
         TFlag = 5,
         EFlag = 9,
+        GE0Flag = 16,
+        GE1Flag = 17,
+        GE2Flag = 18,
+        GE3Flag = 19,
         QFlag = 27,
         VFlag = 28,
         CFlag = 29,

ARMeilleure/Translation/Delegates.cs

@@ -179,8 +179,6 @@ namespace ARMeilleure.Translation
             SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Sha1SchedulePart2)));
             SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Sha256SchedulePart1)));
             SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Sha256SchedulePart2)));
-            SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.SignedShlReg)));
-            SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.SignedShlRegSatQ)));
             SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.SignedShrImm64)));
             SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl1)));
             SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl2)));
@@ -190,8 +188,6 @@ namespace ARMeilleure.Translation
             SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx2)));
             SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx3)));
             SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx4)));
-            SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.UnsignedShlReg)));
-            SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.UnsignedShlRegSatQ)));
             SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.UnsignedShrImm64)));
 
             SetDelegateInfo(typeof(SoftFloat16_32).GetMethod(nameof(SoftFloat16_32.FPConvert)));

ARMeilleure/Translation/PTC/Ptc.cs

@@ -27,7 +27,7 @@ namespace ARMeilleure.Translation.PTC
         private const string OuterHeaderMagicString = "PTCohd\0\0";
         private const string InnerHeaderMagicString = "PTCihd\0\0";
 
-        private const uint InternalVersion = 3683; //! To be incremented manually for each change to the ARMeilleure project.
+        private const uint InternalVersion = 3700; //! To be incremented manually for each change to the ARMeilleure project.
 
         private const string ActualDir = "0";
         private const string BackupDir = "1";

README.md

@@ -27,7 +27,7 @@
     </a>
     <br>
     <br>
-    <img src="https://raw.githubusercontent.com/Ryujinx/Ryujinx-Website/master/static/public/shell_fullsize.png">
+    <img src="https://raw.githubusercontent.com/Ryujinx/Ryujinx-Website/master/public/assets/images/shell.png">
 </p>
 
 <h5 align="center">
@@ -36,8 +36,8 @@
 
 ## Compatibility
 
-As of January 2022, Ryujinx has been tested on approximately 3,500 titles; over 3,200 boot past menus and into gameplay, with roughly 2,500 of those being considered playable.
-You can check out the compatibility list [here](https://github.com/Ryujinx/Ryujinx-Games-List/issues). Anyone is free to submit an updated test on an existing game entry; simply follow the new issue template and testing guidelines, or post as a reply to the applicable game issue. Use the search function to see if a game has been tested already!
+As of September 2022, Ryujinx has been tested on approximately 3,600 titles; over 3,400 boot past menus and into gameplay, with roughly 2,700 of those being considered playable. You can check out the compatibility list [here](https://github.com/Ryujinx/Ryujinx-Games-List/issues).  
+Anyone is free to submit a new game test or update an existing game test entry; simply follow the new issue template and testing guidelines, or post as a reply to the applicable game issue. Use the search function to see if a game has been tested already!
 
 ## Usage
 
@@ -118,11 +118,11 @@ If you'd like to support the project financially, Ryujinx has an active Patreon
     <img src="https://images.squarespace-cdn.com/content/v1/560c1d39e4b0b4fae0c9cf2a/1567548955044-WVD994WZP76EWF15T0L3/Patreon+Button.png?format=500w" width="150">
 </a>
 
-All the developers working on the project do so on their free time, but the project has several expenses:
+All developers working on the project do so in their free time, but the project has several expenses:
 * Hackable Nintendo Switch consoles to reverse-engineer the hardware
 * Additional computer hardware for testing purposes (e.g. GPUs to diagnose graphical bugs, etc.)
-* Licenses for various software development tools (e.g. Jetbrains, LDN servers, IDA)
-* Web hosting and infrastructure maintenance
+* Licenses for various software development tools (e.g. Jetbrains, IDA)
+* Web hosting and infrastructure maintenance (e.g. LDN servers)
 
 All funds received through Patreon are considered a donation to support the project. Patrons receive early access to progress reports and exclusive access to developer interviews.
 

Ryujinx.Common/Collections/IntrusiveRedBlackTreeNode.cs

@@ -5,10 +5,10 @@ namespace Ryujinx.Common.Collections
     /// </summary>
     public class IntrusiveRedBlackTreeNode<T> where T : IntrusiveRedBlackTreeNode<T>
     {
-        public bool Color = true;
-        public T Left;
-        public T Right;
-        public T Parent;
+        internal bool Color = true;
+        internal T Left;
+        internal T Right;
+        internal T Parent;
 
         public T Predecessor => IntrusiveRedBlackTreeImpl<T>.PredecessorOf((T)this);
         public T Successor => IntrusiveRedBlackTreeImpl<T>.SuccessorOf((T)this);

Ryujinx.Cpu/Jit/MemoryManagerHostMapped.cs

@@ -274,7 +274,8 @@ namespace Ryujinx.Cpu.Jit
         /// <inheritdoc/>
         public void Write(ulong va, ReadOnlySpan<byte> data)
         {
-            try {
+            try
+            {
                 SignalMemoryTracking(va, (ulong)data.Length, write: true);
 
                 _addressSpaceMirror.Write(va, data);

Ryujinx.Graphics.GAL/Capabilities.cs

@@ -26,6 +26,7 @@ namespace Ryujinx.Graphics.GAL
         public readonly bool SupportsNonConstantTextureOffset;
         public readonly bool SupportsShaderBallot;
         public readonly bool SupportsTextureShadowLod;
+        public readonly bool SupportsViewportIndex;
         public readonly bool SupportsViewportSwizzle;
         public readonly bool SupportsIndirectParameters;
 
@@ -59,6 +60,7 @@ namespace Ryujinx.Graphics.GAL
             bool supportsNonConstantTextureOffset,
             bool supportsShaderBallot,
             bool supportsTextureShadowLod,
+            bool supportsViewportIndex,
             bool supportsViewportSwizzle,
             bool supportsIndirectParameters,
             uint maximumUniformBuffersPerStage,
@@ -89,6 +91,7 @@ namespace Ryujinx.Graphics.GAL
             SupportsNonConstantTextureOffset = supportsNonConstantTextureOffset;
             SupportsShaderBallot = supportsShaderBallot;
             SupportsTextureShadowLod = supportsTextureShadowLod;
+            SupportsViewportIndex = supportsViewportIndex;
             SupportsViewportSwizzle = supportsViewportSwizzle;
             SupportsIndirectParameters = supportsIndirectParameters;
             MaximumUniformBuffersPerStage = maximumUniformBuffersPerStage;

Ryujinx.Graphics.Gpu/Engine/Threed/SemaphoreUpdater.cs

@@ -1,4 +1,5 @@
 using Ryujinx.Graphics.GAL;
+using System;
 
 namespace Ryujinx.Graphics.Gpu.Engine.Threed
 {
@@ -151,10 +152,21 @@ namespace Ryujinx.Graphics.Gpu.Engine.Threed
 
             ulong ticks = _context.GetTimestamp();
 
+            float divisor = type switch
+            {
+                ReportCounterType.SamplesPassed => _channel.TextureManager.RenderTargetScale * _channel.TextureManager.RenderTargetScale,
+                _ => 1f
+            };
+
             ICounterEvent counter = null;
 
             void resultHandler(object evt, ulong result)
             {
+                if (divisor != 1f)
+                {
+                    result = (ulong)MathF.Ceiling(result / divisor);
+                }
+
                 CounterData counterData = new CounterData
                 {
                     Counter = result,

Ryujinx.Graphics.Gpu/Image/TextureBindingsManager.cs

@@ -47,6 +47,7 @@ namespace Ryujinx.Graphics.Gpu.Image
 
             public int TextureHandle;
             public int SamplerHandle;
+            public Format ImageFormat;
             public int InvalidatedSequence;
             public Texture CachedTexture;
             public Sampler CachedSampler;
@@ -564,6 +565,9 @@ namespace Ryujinx.Graphics.Gpu.Image
                     // Buffers are frequently re-created to accomodate larger data, so we need to re-bind
                     // to ensure we're not using a old buffer that was already deleted.
                     _channel.BufferManager.SetBufferTextureStorage(stage, hostTexture, texture.Range.GetSubRange(0).Address, texture.Size, bindingInfo, bindingInfo.Format, false);
+
+                    // Cache is not used for buffer texture, it must always rebind.
+                    state.CachedTexture = null;
                 }
                 else
                 {
@@ -659,14 +663,16 @@ namespace Ryujinx.Graphics.Gpu.Image
                         cachedTexture?.SignalModified();
                     }
 
-                    if ((usageFlags & TextureUsageFlags.NeedsScaleValue) != 0 &&
-                        UpdateScale(state.CachedTexture, usageFlags, scaleIndex, stage))
+                    Format format = bindingInfo.Format == 0 ? cachedTexture.Format : bindingInfo.Format;
+
+                    if (state.ImageFormat != format ||
+                        ((usageFlags & TextureUsageFlags.NeedsScaleValue) != 0 &&
+                        UpdateScale(state.CachedTexture, usageFlags, scaleIndex, stage)))
                     {
                         ITexture hostTextureRebind = state.CachedTexture.GetTargetTexture(bindingInfo.Target);
 
-                        Format format = bindingInfo.Format == 0 ? cachedTexture.Format : bindingInfo.Format;
-
                         state.Texture = hostTextureRebind;
+                        state.ImageFormat = format;
 
                         _context.Renderer.Pipeline.SetImage(bindingInfo.Binding, hostTextureRebind, format);
                     }
@@ -696,6 +702,9 @@ namespace Ryujinx.Graphics.Gpu.Image
                     }
 
                     _channel.BufferManager.SetBufferTextureStorage(stage, hostTexture, texture.Range.GetSubRange(0).Address, texture.Size, bindingInfo, format, true);
+
+                    // Cache is not used for buffer texture, it must always rebind.
+                    state.CachedTexture = null;
                 }
                 else
                 {
@@ -721,6 +730,8 @@ namespace Ryujinx.Graphics.Gpu.Image
                             format = texture.Format;
                         }
 
+                        state.ImageFormat = format;
+
                         _context.Renderer.Pipeline.SetImage(bindingInfo.Binding, hostTexture, format);
                     }
 

Ryujinx.Graphics.Gpu/Shader/DiskCache/DiskCacheHostStorage.cs

@@ -22,7 +22,7 @@ namespace Ryujinx.Graphics.Gpu.Shader.DiskCache
         private const ushort FileFormatVersionMajor = 1;
         private const ushort FileFormatVersionMinor = 2;
         private const uint FileFormatVersionPacked = ((uint)FileFormatVersionMajor << 16) | FileFormatVersionMinor;
-        private const uint CodeGenVersion = 3672;
+        private const uint CodeGenVersion = 3697;
 
         private const string SharedTocFileName = "shared.toc";
         private const string SharedDataFileName = "shared.data";
@@ -827,4 +827,4 @@ namespace Ryujinx.Graphics.Gpu.Shader.DiskCache
             }
         }
     }
-}
+}

Ryujinx.Graphics.Gpu/Shader/GpuAccessorBase.cs

@@ -134,6 +134,8 @@ namespace Ryujinx.Graphics.Gpu.Shader
 
         public bool QueryHostSupportsTextureShadowLod() => _context.Capabilities.SupportsTextureShadowLod;
 
+        public bool QueryHostSupportsViewportIndex() => _context.Capabilities.SupportsViewportIndex;
+
         /// <summary>
         /// Converts a packed Maxwell texture format to the shader translator texture format.
         /// </summary>

Ryujinx.Graphics.OpenGL/OpenGLRenderer.cs

@@ -120,6 +120,7 @@ namespace Ryujinx.Graphics.OpenGL
                 supportsNonConstantTextureOffset: HwCapabilities.SupportsNonConstantTextureOffset,
                 supportsShaderBallot: HwCapabilities.SupportsShaderBallot,
                 supportsTextureShadowLod: HwCapabilities.SupportsTextureShadowLod,
+                supportsViewportIndex: true,
                 supportsViewportSwizzle: HwCapabilities.SupportsViewportSwizzle,
                 supportsIndirectParameters: HwCapabilities.SupportsIndirectParameters,
                 maximumUniformBuffersPerStage: 13, // TODO: Avoid hardcoding those limits here and get from driver?

Ryujinx.Graphics.Shader/IGpuAccessor.cs

@@ -267,6 +267,15 @@ namespace Ryujinx.Graphics.Shader
             return true;
         }
 
+        /// <summary>
+        /// Queries host GPU shader viewport index output support.
+        /// </summary>
+        /// <returns>True if the GPU and driver supports shader viewport index output, false otherwise</returns>
+        bool QueryHostSupportsViewportIndex()
+        {
+            return true;
+        }
+
         /// <summary>
         /// Queries the point size from the GPU state, used when it is not explicitly set on the shader.
         /// </summary>

Ryujinx.Graphics.Shader/Instructions/InstEmitTexture.cs

@@ -16,7 +16,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
             { 0b0111, 0b1011, 0b1101, 0b1110, 0b1111, 0b0000, 0b0000, 0b0000 }
         };
 
-        private const bool Sample1DAs2D = true;
+        public const bool Sample1DAs2D = true;
 
         private enum TexsType
         {

Ryujinx.Graphics.Shader/IntermediateRepresentation/Operation.cs

@@ -180,6 +180,18 @@ namespace Ryujinx.Graphics.Shader.IntermediateRepresentation
             _sources[index] = source;
         }
 
+        public void InsertSource(int index, Operand source)
+        {
+            Operand[] newSources = new Operand[_sources.Length + 1];
+
+            Array.Copy(_sources, 0, newSources, 0, index);
+            Array.Copy(_sources, index, newSources, index + 1, _sources.Length - index);
+
+            newSources[index] = source;
+
+            _sources = newSources;
+        }
+
         protected void RemoveSource(int index)
         {
             SetSource(index, null);

Ryujinx.Graphics.Shader/IntermediateRepresentation/TextureOperation.cs

@@ -60,5 +60,10 @@ namespace Ryujinx.Graphics.Shader.IntermediateRepresentation
             CbufSlot = cbufSlot;
             Handle = handle;
         }
+
+        public void SetLodLevelFlag()
+        {
+            Flags |= TextureFlags.LodLevel;
+        }
     }
 }

Ryujinx.Graphics.Shader/Translation/AttributeInfo.cs

@@ -78,6 +78,11 @@ namespace Ryujinx.Graphics.Shader.Translation
 
         public static bool Validate(ShaderConfig config, int value, bool isOutAttr)
         {
+            if (value == AttributeConsts.ViewportIndex && !config.GpuAccessor.QueryHostSupportsViewportIndex())
+            {
+                return false;
+            }
+
             return From(config, value, isOutAttr).IsValid;
         }
 

Ryujinx.Graphics.Shader/Translation/Optimizations/BindlessElimination.cs

@@ -1,4 +1,5 @@
-using Ryujinx.Graphics.Shader.IntermediateRepresentation;
+using Ryujinx.Graphics.Shader.Instructions;
+using Ryujinx.Graphics.Shader.IntermediateRepresentation;
 using System.Collections.Generic;
 
 namespace Ryujinx.Graphics.Shader.Translation.Optimizations
@@ -30,11 +31,19 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations
                     texOp.Inst == Instruction.TextureSize)
                 {
                     Operand bindlessHandle = Utils.FindLastOperation(texOp.GetSource(0), block);
-                    bool rewriteSamplerType = texOp.Inst == Instruction.TextureSize;
+
+                    // Some instructions do not encode an accurate sampler type:
+                    // - Most instructions uses the same type for 1D and Buffer.
+                    // - Query instructions may not have any type.
+                    // For those cases, we need to try getting the type from current GPU state,
+                    // as long bindless elimination is successful and we know where the texture descriptor is located.
+                    bool rewriteSamplerType =
+                        texOp.Type == SamplerType.TextureBuffer ||
+                        texOp.Inst == Instruction.TextureSize;
 
                     if (bindlessHandle.Type == OperandType.ConstantBuffer)
                     {
-                        SetHandle(config, texOp, bindlessHandle.GetCbufOffset(), bindlessHandle.GetCbufSlot(), rewriteSamplerType);
+                        SetHandle(config, texOp, bindlessHandle.GetCbufOffset(), bindlessHandle.GetCbufSlot(), rewriteSamplerType, isImage: false);
                         continue;
                     }
 
@@ -137,7 +146,8 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations
                             texOp,
                             TextureHandle.PackOffsets(src0.GetCbufOffset(), ((src1.Value >> 20) & 0xfff), handleType),
                             TextureHandle.PackSlots(src0.GetCbufSlot(), 0),
-                            rewriteSamplerType);
+                            rewriteSamplerType,
+                            isImage: false);
                     }
                     else if (src1.Type == OperandType.ConstantBuffer)
                     {
@@ -146,7 +156,8 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations
                             texOp,
                             TextureHandle.PackOffsets(src0.GetCbufOffset(), src1.GetCbufOffset(), handleType),
                             TextureHandle.PackSlots(src0.GetCbufSlot(), src1.GetCbufSlot()),
-                            rewriteSamplerType);
+                            rewriteSamplerType,
+                            isImage: false);
                     }
                 }
                 else if (texOp.Inst == Instruction.ImageLoad ||
@@ -172,7 +183,9 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations
                             }
                         }
 
-                        SetHandle(config, texOp, cbufOffset, cbufSlot, false);
+                        bool rewriteSamplerType = texOp.Type == SamplerType.TextureBuffer;
+
+                        SetHandle(config, texOp, cbufOffset, cbufSlot, rewriteSamplerType, isImage: true);
                     }
                 }
             }
@@ -209,13 +222,39 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations
             return null;
         }
 
-        private static void SetHandle(ShaderConfig config, TextureOperation texOp, int cbufOffset, int cbufSlot, bool rewriteSamplerType)
+        private static void SetHandle(ShaderConfig config, TextureOperation texOp, int cbufOffset, int cbufSlot, bool rewriteSamplerType, bool isImage)
         {
             texOp.SetHandle(cbufOffset, cbufSlot);
 
             if (rewriteSamplerType)
             {
-                texOp.Type = config.GpuAccessor.QuerySamplerType(cbufOffset, cbufSlot);
+                SamplerType newType = config.GpuAccessor.QuerySamplerType(cbufOffset, cbufSlot);
+
+                if (texOp.Inst.IsTextureQuery())
+                {
+                    texOp.Type = newType;
+                }
+                else if (texOp.Type == SamplerType.TextureBuffer && newType == SamplerType.Texture1D)
+                {
+                    int coordsCount = 1;
+
+                    if (InstEmit.Sample1DAs2D)
+                    {
+                        newType = SamplerType.Texture2D;
+                        texOp.InsertSource(coordsCount++, OperandHelper.Const(0));
+                    }
+
+                    if (!isImage &&
+                        (texOp.Flags & TextureFlags.IntCoords) != 0 &&
+                        (texOp.Flags & TextureFlags.LodLevel) == 0)
+                    {
+                        // IntCoords textures must always have explicit LOD.
+                        texOp.SetLodLevelFlag();
+                        texOp.InsertSource(coordsCount, OperandHelper.Const(0));
+                    }
+
+                    texOp.Type = newType;
+                }
             }
 
             config.SetUsedTexture(texOp.Inst, texOp.Type, texOp.Format, texOp.Flags, cbufSlot, cbufOffset);

Ryujinx.Graphics.Vulkan/AutoFlushCounter.cs

@@ -0,0 +1,73 @@
+using System;
+using System.Diagnostics;
+
+namespace Ryujinx.Graphics.Vulkan
+{
+    internal class AutoFlushCounter
+    {
+        // How often to flush on framebuffer change.
+        private readonly static long FramebufferFlushTimer = Stopwatch.Frequency / 1000;
+
+        private const int MinDrawCountForFlush = 10;
+        private const int InitialQueryCountForFlush = 32;
+
+        private long _lastFlush;
+        private ulong _lastDrawCount;
+        private bool _hasPendingQuery;
+        private int _queryCount;
+
+        public void RegisterFlush(ulong drawCount)
+        {
+            _lastFlush = Stopwatch.GetTimestamp();
+            _lastDrawCount = drawCount;
+
+            _hasPendingQuery = false;
+        }
+
+        public bool RegisterPendingQuery()
+        {
+            _hasPendingQuery = true;
+
+            // Interrupt render passes to flush queries, so that early results arrive sooner.
+            if (++_queryCount == InitialQueryCountForFlush)
+            {
+                return true;
+            }
+
+            return false;
+        }
+
+        public bool ShouldFlushQuery()
+        {
+            return _hasPendingQuery;
+        }
+
+        public bool ShouldFlush(ulong drawCount)
+        {
+            _queryCount = 0;
+
+            if (_hasPendingQuery)
+            {
+                return true;
+            }
+
+            long draws = (long)(drawCount - _lastDrawCount);
+
+            if (draws < MinDrawCountForFlush)
+            {
+                if (draws == 0)
+                {
+                    _lastFlush = Stopwatch.GetTimestamp();
+                }
+
+                return false;
+            }
+
+            long flushTimeout = FramebufferFlushTimer;
+
+            long now = Stopwatch.GetTimestamp();
+
+            return now > _lastFlush + flushTimeout;
+        }
+    }
+}

Ryujinx.Graphics.Vulkan/FormatCapabilities.cs

@@ -108,6 +108,10 @@ namespace Ryujinx.Graphics.Vulkan
                 {
                     format = VkFormat.D32SfloatS8Uint;
                 }
+                else if (srcFormat == GAL.Format.R4G4B4A4Unorm)
+                {
+                    format = VkFormat.R4G4B4A4UnormPack16;
+                }
                 else
                 {
                     Logger.Error?.Print(LogClass.Gpu, $"Format {srcFormat} is not supported by the host.");

Ryujinx.Graphics.Vulkan/FormatTable.cs

@@ -6,11 +6,11 @@ namespace Ryujinx.Graphics.Vulkan
 {
     static class FormatTable
     {
-        private static readonly VkFormat[] Table;
+        private static readonly VkFormat[] _table;
 
         static FormatTable()
         {
-            Table = new VkFormat[Enum.GetNames(typeof(Format)).Length];
+            _table = new VkFormat[Enum.GetNames(typeof(Format)).Length];
 
             Add(Format.R8Unorm,             VkFormat.R8Unorm);
             Add(Format.R8Snorm,             VkFormat.R8SNorm);
@@ -68,7 +68,7 @@ namespace Ryujinx.Graphics.Vulkan
             Add(Format.D32FloatS8Uint,      VkFormat.D32SfloatS8Uint);
             Add(Format.R8G8B8A8Srgb,        VkFormat.R8G8B8A8Srgb);
             Add(Format.R4G4Unorm,           VkFormat.R4G4UnormPack8);
-            Add(Format.R4G4B4A4Unorm,       VkFormat.R4G4B4A4UnormPack16);
+            Add(Format.R4G4B4A4Unorm,       VkFormat.A4B4G4R4UnormPack16Ext);
             Add(Format.R5G5B5X1Unorm,       VkFormat.A1R5G5B5UnormPack16);
             Add(Format.R5G5B5A1Unorm,       VkFormat.A1R5G5B5UnormPack16);
             Add(Format.R5G6B5Unorm,         VkFormat.R5G6B5UnormPack16);
@@ -161,12 +161,12 @@ namespace Ryujinx.Graphics.Vulkan
 
         private static void Add(Format format, VkFormat vkFormat)
         {
-            Table[(int)format] = vkFormat;
+            _table[(int)format] = vkFormat;
         }
 
         public static VkFormat GetFormat(Format format)
         {
-            return Table[(int)format];
+            return _table[(int)format];
         }
     }
 }

Ryujinx.Graphics.Vulkan/PipelineBase.cs

@@ -19,6 +19,8 @@ namespace Ryujinx.Graphics.Vulkan
         protected readonly Device Device;
         public readonly PipelineCache PipelineCache;
 
+        protected readonly AutoFlushCounter AutoFlush;
+
         private PipelineDynamicState _dynamicState;
         private PipelineState _newState;
         private bool _stateDirty;
@@ -70,6 +72,8 @@ namespace Ryujinx.Graphics.Vulkan
             Gd = gd;
             Device = device;
 
+            AutoFlush = new AutoFlushCounter();
+
             var pipelineCacheCreateInfo = new PipelineCacheCreateInfo()
             {
                 SType = StructureType.PipelineCacheCreateInfo

Ryujinx.Graphics.Vulkan/PipelineFull.cs

@@ -10,8 +10,6 @@ namespace Ryujinx.Graphics.Vulkan
     {
         private const ulong MinByteWeightForFlush = 256 * 1024 * 1024; // MB
 
-        private bool _hasPendingQuery;
-
         private readonly List<QueryPool> _activeQueries;
         private CounterQueueEvent _activeConditionalRender;
 
@@ -158,9 +156,8 @@ namespace Ryujinx.Graphics.Vulkan
 
         private void FlushPendingQuery()
         {
-            if (_hasPendingQuery)
+            if (AutoFlush.ShouldFlushQuery())
             {
-                _hasPendingQuery = false;
                 FlushCommandsImpl();
             }
         }
@@ -211,6 +208,7 @@ namespace Ryujinx.Graphics.Vulkan
 
         public void FlushCommandsImpl()
         {
+            AutoFlush.RegisterFlush(DrawCount);
             EndRenderPass();
 
             foreach (var queryPool in _activeQueries)
@@ -277,12 +275,18 @@ namespace Ryujinx.Graphics.Vulkan
         {
             _pendingQueryCopies.Add(query);
 
-            _hasPendingQuery = true;
+            if (AutoFlush.RegisterPendingQuery())
+            {
+                FlushCommandsImpl();
+            }
         }
 
         protected override void SignalAttachmentChange()
         {
-            FlushPendingQuery();
+            if (AutoFlush.ShouldFlush(DrawCount))
+            {
+                FlushCommandsImpl();
+            }
         }
 
         protected override void SignalRenderPassEnd()

Ryujinx.Graphics.Vulkan/TextureView.cs

@@ -74,17 +74,7 @@ namespace Ryujinx.Graphics.Vulkan
                 swizzleR = swizzleB;
                 swizzleB = temp;
             }
-            else if (info.Format == GAL.Format.R4G4B4A4Unorm)
-            {
-                var tempG = swizzleG;
-                var tempB = swizzleB;
-
-                swizzleB = swizzleA;
-                swizzleG = swizzleR;
-                swizzleR = tempG;
-                swizzleA = tempB;
-            }
-            else if (info.Format == GAL.Format.A1B5G5R5Unorm)
+            else if (VkFormat == VkFormat.R4G4B4A4UnormPack16 || info.Format == GAL.Format.A1B5G5R5Unorm)
             {
                 var tempB = swizzleB;
                 var tempA = swizzleA;

Ryujinx.Graphics.Vulkan/VulkanRenderer.cs

@@ -380,7 +380,7 @@ namespace Ryujinx.Graphics.Vulkan
             return BufferManager.GetData(buffer, offset, size);
         }
 
-        public Capabilities GetCapabilities()
+        public unsafe Capabilities GetCapabilities()
         {
             FormatFeatureFlags compressedFormatFeatureFlags =
                 FormatFeatureFlags.FormatFeatureSampledImageBit |
@@ -409,7 +409,19 @@ namespace Ryujinx.Graphics.Vulkan
                 GAL.Format.Bc7Srgb,
                 GAL.Format.Bc7Unorm);
 
-            Api.GetPhysicalDeviceFeatures(_physicalDevice, out var features);
+
+            PhysicalDeviceVulkan12Features featuresVk12 = new PhysicalDeviceVulkan12Features()
+            {
+                SType = StructureType.PhysicalDeviceVulkan12Features
+            };
+
+            PhysicalDeviceFeatures2 features2 = new PhysicalDeviceFeatures2()
+            {
+                SType = StructureType.PhysicalDeviceFeatures2,
+                PNext = &featuresVk12
+            };
+
+            Api.GetPhysicalDeviceFeatures2(_physicalDevice, &features2);
             Api.GetPhysicalDeviceProperties(_physicalDevice, out var properties);
 
             var limits = properties.Limits;
@@ -419,7 +431,7 @@ namespace Ryujinx.Graphics.Vulkan
                 GpuVendor,
                 hasFrontFacingBug: IsIntelWindows,
                 hasVectorIndexingBug: Vendor == Vendor.Qualcomm,
-                supportsAstcCompression: features.TextureCompressionAstcLdr,
+                supportsAstcCompression: features2.Features.TextureCompressionAstcLdr,
                 supportsBc123Compression: supportsBc123CompressionFormat,
                 supportsBc45Compression: supportsBc45CompressionFormat,
                 supportsBc67Compression: supportsBc67CompressionFormat,
@@ -429,12 +441,13 @@ namespace Ryujinx.Graphics.Vulkan
                 supportsFragmentShaderInterlock: Capabilities.SupportsFragmentShaderInterlock,
                 supportsFragmentShaderOrderingIntel: false,
                 supportsGeometryShaderPassthrough: Capabilities.SupportsGeometryShaderPassthrough,
-                supportsImageLoadFormatted: features.ShaderStorageImageReadWithoutFormat,
+                supportsImageLoadFormatted: features2.Features.ShaderStorageImageReadWithoutFormat,
                 supportsMismatchingViewFormat: true,
                 supportsCubemapView: !IsAmdGcn,
                 supportsNonConstantTextureOffset: false,
                 supportsShaderBallot: false,
                 supportsTextureShadowLod: false,
+                supportsViewportIndex: featuresVk12.ShaderOutputViewportIndex,
                 supportsViewportSwizzle: false,
                 supportsIndirectParameters: Capabilities.SupportsIndirectParameters,
                 maximumUniformBuffersPerStage: Constants.MaxUniformBuffersPerStage,

Ryujinx.Memory/WindowsShared/IntervalTree.cs

@@ -1,453 +0,0 @@
-using Ryujinx.Common.Collections;
-using System;
-using System.Collections.Generic;
-
-namespace Ryujinx.Memory.WindowsShared
-{
-    /// <summary>
-    /// An Augmented Interval Tree based off of the "TreeDictionary"'s Red-Black Tree. Allows fast overlap checking of ranges.
-    /// </summary>
-    /// <typeparam name="K">Key</typeparam>
-    /// <typeparam name="V">Value</typeparam>
-    class IntervalTree<K, V> : IntrusiveRedBlackTreeImpl<IntervalTreeNode<K, V>> where K : IComparable<K>
-    {
-        private const int ArrayGrowthSize = 32;
-
-        #region Public Methods
-
-        /// <summary>
-        /// Gets the values of the interval whose key is <paramref name="key"/>.
-        /// </summary>
-        /// <param name="key">Key of the node value to get</param>
-        /// <param name="value">Value with the given <paramref name="key"/></param>
-        /// <returns>True if the key is on the dictionary, false otherwise</returns>
-        public bool TryGet(K key, out V value)
-        {
-            IntervalTreeNode<K, V> node = GetNode(key);
-
-            if (node == null)
-            {
-                value = default;
-                return false;
-            }
-
-            value = node.Value;
-            return true;
-        }
-
-        /// <summary>
-        /// Returns the start addresses of the intervals whose start and end keys overlap the given range.
-        /// </summary>
-        /// <param name="start">Start of the range</param>
-        /// <param name="end">End of the range</param>
-        /// <param name="overlaps">Overlaps array to place results in</param>
-        /// <param name="overlapCount">Index to start writing results into the array. Defaults to 0</param>
-        /// <returns>Number of intervals found</returns>
-        public int Get(K start, K end, ref IntervalTreeNode<K, V>[] overlaps, int overlapCount = 0)
-        {
-            GetNodes(Root, start, end, ref overlaps, ref overlapCount);
-
-            return overlapCount;
-        }
-
-        /// <summary>
-        /// Adds a new interval into the tree whose start is <paramref name="start"/>, end is <paramref name="end"/> and value is <paramref name="value"/>.
-        /// </summary>
-        /// <param name="start">Start of the range to add</param>
-        /// <param name="end">End of the range to insert</param>
-        /// <param name="value">Value to add</param>
-        /// <exception cref="ArgumentNullException"><paramref name="value"/> is null</exception>
-        public void Add(K start, K end, V value)
-        {
-            if (value == null)
-            {
-                throw new ArgumentNullException(nameof(value));
-            }
-
-            BSTInsert(start, end, value, null, out _);
-        }
-
-        /// <summary>
-        /// Removes a value from the tree, searching for it with <paramref name="key"/>.
-        /// </summary>
-        /// <param name="key">Key of the node to remove</param>
-        /// <returns>Number of deleted values</returns>
-        public int Remove(K key)
-        {
-            return Remove(GetNode(key));
-        }
-
-        /// <summary>
-        /// Removes a value from the tree, searching for it with <paramref name="key"/>.
-        /// </summary>
-        /// <param name="nodeToDelete">Node to be removed</param>
-        /// <returns>Number of deleted values</returns>
-        public int Remove(IntervalTreeNode<K, V> nodeToDelete)
-        {
-            if (nodeToDelete == null)
-            {
-                return 0;
-            }
-
-            Delete(nodeToDelete);
-
-            Count--;
-
-            return 1;
-        }
-
-        /// <summary>
-        /// Adds all the nodes in the dictionary into <paramref name="list"/>.
-        /// </summary>
-        /// <returns>A list of all values sorted by Key Order</returns>
-        public List<V> AsList()
-        {
-            List<V> list = new List<V>();
-
-            AddToList(Root, list);
-
-            return list;
-        }
-
-        #endregion
-
-        #region Private Methods (BST)
-
-        /// <summary>
-        /// Adds all values that are children of or contained within <paramref name="node"/> into <paramref name="list"/>, in Key Order.
-        /// </summary>
-        /// <param name="node">The node to search for values within</param>
-        /// <param name="list">The list to add values to</param>
-        private void AddToList(IntervalTreeNode<K, V> node, List<V> list)
-        {
-            if (node == null)
-            {
-                return;
-            }
-
-            AddToList(node.Left, list);
-
-            list.Add(node.Value);
-
-            AddToList(node.Right, list);
-        }
-
-        /// <summary>
-        /// Retrieve the node reference whose key is <paramref name="key"/>, or null if no such node exists.
-        /// </summary>
-        /// <param name="key">Key of the node to get</param>
-        /// <exception cref="ArgumentNullException"><paramref name="key"/> is null</exception>
-        /// <returns>Node reference in the tree</returns>
-        private IntervalTreeNode<K, V> GetNode(K key)
-        {
-            if (key == null)
-            {
-                throw new ArgumentNullException(nameof(key));
-            }
-
-            IntervalTreeNode<K, V> node = Root;
-            while (node != null)
-            {
-                int cmp = key.CompareTo(node.Start);
-                if (cmp < 0)
-                {
-                    node = node.Left;
-                }
-                else if (cmp > 0)
-                {
-                    node = node.Right;
-                }
-                else
-                {
-                    return node;
-                }
-            }
-            return null;
-        }
-
-        /// <summary>
-        /// Retrieve all nodes that overlap the given start and end keys.
-        /// </summary>
-        /// <param name="start">Start of the range</param>
-        /// <param name="end">End of the range</param>
-        /// <param name="overlaps">Overlaps array to place results in</param>
-        /// <param name="overlapCount">Overlaps count to update</param>
-        private void GetNodes(IntervalTreeNode<K, V> node, K start, K end, ref IntervalTreeNode<K, V>[] overlaps, ref int overlapCount)
-        {
-            if (node == null || start.CompareTo(node.Max) >= 0)
-            {
-                return;
-            }
-
-            GetNodes(node.Left, start, end, ref overlaps, ref overlapCount);
-
-            bool endsOnRight = end.CompareTo(node.Start) > 0;
-            if (endsOnRight)
-            {
-                if (start.CompareTo(node.End) < 0)
-                {
-                    if (overlaps.Length >= overlapCount)
-                    {
-                        Array.Resize(ref overlaps, overlapCount + ArrayGrowthSize);
-                    }
-
-                    overlaps[overlapCount++] = node;
-                }
-
-                GetNodes(node.Right, start, end, ref overlaps, ref overlapCount);
-            }
-        }
-
-        /// <summary>
-        /// Propagate an increase in max value starting at the given node, heading up the tree.
-        /// This should only be called if the max increases - not for rebalancing or removals.
-        /// </summary>
-        /// <param name="node">The node to start propagating from</param>
-        private void PropagateIncrease(IntervalTreeNode<K, V> node)
-        {
-            K max = node.Max;
-            IntervalTreeNode<K, V> ptr = node;
-
-            while ((ptr = ptr.Parent) != null)
-            {
-                if (max.CompareTo(ptr.Max) > 0)
-                {
-                    ptr.Max = max;
-                }
-                else
-                {
-                    break;
-                }
-            }
-        }
-
-        /// <summary>
-        /// Propagate recalculating max value starting at the given node, heading up the tree.
-        /// This fully recalculates the max value from all children when there is potential for it to decrease.
-        /// </summary>
-        /// <param name="node">The node to start propagating from</param>
-        private void PropagateFull(IntervalTreeNode<K, V> node)
-        {
-            IntervalTreeNode<K, V> ptr = node;
-
-            do
-            {
-                K max = ptr.End;
-
-                if (ptr.Left != null && ptr.Left.Max.CompareTo(max) > 0)
-                {
-                    max = ptr.Left.Max;
-                }
-
-                if (ptr.Right != null && ptr.Right.Max.CompareTo(max) > 0)
-                {
-                    max = ptr.Right.Max;
-                }
-
-                ptr.Max = max;
-            } while ((ptr = ptr.Parent) != null);
-        }
-
-        /// <summary>
-        /// Insertion Mechanism for the interval tree. Similar to a BST insert, with the start of the range as the key.
-        /// Iterates the tree starting from the root and inserts a new node where all children in the left subtree are less than <paramref name="start"/>, and all children in the right subtree are greater than <paramref name="start"/>.
-        /// Each node can contain multiple values, and has an end address which is the maximum of all those values.
-        /// Post insertion, the "max" value of the node and all parents are updated.
-        /// </summary>
-        /// <param name="start">Start of the range to insert</param>
-        /// <param name="end">End of the range to insert</param>
-        /// <param name="value">Value to insert</param>
-        /// <param name="updateFactoryCallback">Optional factory used to create a new value if <paramref name="start"/> is already on the tree</param>
-        /// <param name="outNode">Node that was inserted or modified</param>
-        /// <returns>True if <paramref name="start"/> was not yet on the tree, false otherwise</returns>
-        private bool BSTInsert(K start, K end, V value, Func<K, V, V> updateFactoryCallback, out IntervalTreeNode<K, V> outNode)
-        {
-            IntervalTreeNode<K, V> parent = null;
-            IntervalTreeNode<K, V> node = Root;
-
-            while (node != null)
-            {
-                parent = node;
-                int cmp = start.CompareTo(node.Start);
-                if (cmp < 0)
-                {
-                    node = node.Left;
-                }
-                else if (cmp > 0)
-                {
-                    node = node.Right;
-                }
-                else
-                {
-                    outNode = node;
-
-                    if (updateFactoryCallback != null)
-                    {
-                        // Replace
-                        node.Value = updateFactoryCallback(start, node.Value);
-
-                        int endCmp = end.CompareTo(node.End);
-
-                        if (endCmp > 0)
-                        {
-                            node.End = end;
-                            if (end.CompareTo(node.Max) > 0)
-                            {
-                                node.Max = end;
-                                PropagateIncrease(node);
-                                RestoreBalanceAfterInsertion(node);
-                            }
-                        }
-                        else if (endCmp < 0)
-                        {
-                            node.End = end;
-                            PropagateFull(node);
-                        }
-                    }
-
-                    return false;
-                }
-            }
-            IntervalTreeNode<K, V> newNode = new IntervalTreeNode<K, V>(start, end, value, parent);
-            if (newNode.Parent == null)
-            {
-                Root = newNode;
-            }
-            else if (start.CompareTo(parent.Start) < 0)
-            {
-                parent.Left = newNode;
-            }
-            else
-            {
-                parent.Right = newNode;
-            }
-
-            PropagateIncrease(newNode);
-            Count++;
-            RestoreBalanceAfterInsertion(newNode);
-            outNode = newNode;
-            return true;
-        }
-
-        /// <summary>
-        /// Removes the value from the dictionary after searching for it with <paramref name="key">.
-        /// </summary>
-        /// <param name="key">Tree node to be removed</param>
-        private void Delete(IntervalTreeNode<K, V> nodeToDelete)
-        {
-            IntervalTreeNode<K, V> replacementNode;
-
-            if (LeftOf(nodeToDelete) == null || RightOf(nodeToDelete) == null)
-            {
-                replacementNode = nodeToDelete;
-            }
-            else
-            {
-                replacementNode = nodeToDelete.Predecessor;
-            }
-
-            IntervalTreeNode<K, V> tmp = LeftOf(replacementNode) ?? RightOf(replacementNode);
-
-            if (tmp != null)
-            {
-                tmp.Parent = ParentOf(replacementNode);
-            }
-
-            if (ParentOf(replacementNode) == null)
-            {
-                Root = tmp;
-            }
-            else if (replacementNode == LeftOf(ParentOf(replacementNode)))
-            {
-                ParentOf(replacementNode).Left = tmp;
-            }
-            else
-            {
-                ParentOf(replacementNode).Right = tmp;
-            }
-
-            if (replacementNode != nodeToDelete)
-            {
-                nodeToDelete.Start = replacementNode.Start;
-                nodeToDelete.Value = replacementNode.Value;
-                nodeToDelete.End = replacementNode.End;
-                nodeToDelete.Max = replacementNode.Max;
-            }
-
-            PropagateFull(replacementNode);
-
-            if (tmp != null && ColorOf(replacementNode) == Black)
-            {
-                RestoreBalanceAfterRemoval(tmp);
-            }
-        }
-
-        #endregion
-
-        #region Private Methods (RBL)
-
-        protected override void RotateLeft(IntervalTreeNode<K, V> node)
-        {
-            if (node != null)
-            {
-                base.RotateLeft(node);
-
-                PropagateFull(node);
-            }
-        }
-
-        protected override void RotateRight(IntervalTreeNode<K, V> node)
-        {
-            if (node != null)
-            {
-                base.RotateRight(node);
-
-                PropagateFull(node);
-            }
-        }
-
-        #endregion
-
-        public bool ContainsKey(K key)
-        {
-            return GetNode(key) != null;
-        }
-    }
-
-    /// <summary>
-    /// Represents a node in the IntervalTree which contains start and end keys of type K, and a value of generic type V.
-    /// </summary>
-    /// <typeparam name="K">Key type of the node</typeparam>
-    /// <typeparam name="V">Value type of the node</typeparam>
-    class IntervalTreeNode<K, V> : IntrusiveRedBlackTreeNode<IntervalTreeNode<K, V>>
-    {
-        /// <summary>
-        /// The start of the range.
-        /// </summary>
-        public K Start;
-
-        /// <summary>
-        /// The end of the range.
-        /// </summary>
-        public K End;
-
-        /// <summary>
-        /// The maximum end value of this node and all its children.
-        /// </summary>
-        public K Max;
-
-        /// <summary>
-        /// Value stored on this node.
-        /// </summary>
-        public V Value;
-
-        public IntervalTreeNode(K start, K end, V value, IntervalTreeNode<K, V> parent)
-        {
-            Start = start;
-            End = end;
-            Max = end;
-            Value = value;
-            Parent = parent;
-        }
-    }
-}

Ryujinx.Memory/WindowsShared/MappingTree.cs

@@ -0,0 +1,87 @@
+using Ryujinx.Common.Collections;
+using System;
+
+namespace Ryujinx.Memory.WindowsShared
+{
+    /// <summary>
+    /// A intrusive Red-Black Tree that also supports getting nodes overlapping a given range.
+    /// </summary>
+    /// <typeparam name="T">Type of the value stored on the node</typeparam>
+    class MappingTree<T> : IntrusiveRedBlackTree<RangeNode<T>>
+    {
+        private const int ArrayGrowthSize = 16;
+
+        public int GetNodes(ulong start, ulong end, ref RangeNode<T>[] overlaps, int overlapCount = 0)
+        {
+            RangeNode<T> node = this.GetNodeByKey(start);
+
+            for (; node != null; node = node.Successor)
+            {
+                if (overlaps.Length <= overlapCount)
+                {
+                    Array.Resize(ref overlaps, overlapCount + ArrayGrowthSize);
+                }
+
+                overlaps[overlapCount++] = node;
+
+                if (node.End >= end)
+                {
+                    break;
+                }
+            }
+
+            return overlapCount;
+        }
+    }
+
+    class RangeNode<T> : IntrusiveRedBlackTreeNode<RangeNode<T>>, IComparable<RangeNode<T>>, IComparable<ulong>
+    {
+        public ulong Start { get; }
+        public ulong End { get; private set; }
+        public T Value { get; }
+
+        public RangeNode(ulong start, ulong end, T value)
+        {
+            Start = start;
+            End = end;
+            Value = value;
+        }
+
+        public void Extend(ulong sizeDelta)
+        {
+            End += sizeDelta;
+        }
+
+        public int CompareTo(RangeNode<T> other)
+        {
+            if (Start < other.Start)
+            {
+                return -1;
+            }
+            else if (Start <= other.End - 1UL)
+            {
+                return 0;
+            }
+            else
+            {
+                return 1;
+            }
+        }
+
+        public int CompareTo(ulong address)
+        {
+            if (address < Start)
+            {
+                return 1;
+            }
+            else if (address <= End - 1UL)
+            {
+                return 0;
+            }
+            else
+            {
+                return -1;
+            }
+        }
+    }
+}

Ryujinx.Memory/WindowsShared/PlaceholderManager.cs

@@ -1,3 +1,4 @@
+using Ryujinx.Common.Collections;
 using Ryujinx.Common.Memory.PartialUnmaps;
 using System;
 using System.Diagnostics;
@@ -13,10 +14,10 @@ namespace Ryujinx.Memory.WindowsShared
     [SupportedOSPlatform("windows")]
     class PlaceholderManager
     {
-        private const ulong MinimumPageSize = 0x1000;
+        private const int InitialOverlapsSize = 10;
 
-        private readonly IntervalTree<ulong, ulong> _mappings;
-        private readonly IntervalTree<ulong, MemoryPermission> _protections;
+        private readonly MappingTree<ulong> _mappings;
+        private readonly MappingTree<MemoryPermission> _protections;
         private readonly IntPtr _partialUnmapStatePtr;
         private readonly Thread _partialUnmapTrimThread;
 
@@ -25,8 +26,8 @@ namespace Ryujinx.Memory.WindowsShared
         /// </summary>
         public PlaceholderManager()
         {
-            _mappings = new IntervalTree<ulong, ulong>();
-            _protections = new IntervalTree<ulong, MemoryPermission>();
+            _mappings = new MappingTree<ulong>();
+            _protections = new MappingTree<MemoryPermission>();
 
             _partialUnmapStatePtr = PartialUnmapState.GlobalState;
 
@@ -67,7 +68,12 @@ namespace Ryujinx.Memory.WindowsShared
         {
             lock (_mappings)
             {
-                _mappings.Add(address, address + size, ulong.MaxValue);
+                _mappings.Add(new RangeNode<ulong>(address, address + size, ulong.MaxValue));
+            }
+
+            lock (_protections)
+            {
+                _protections.Add(new RangeNode<MemoryPermission>(address, address + size, MemoryPermission.None));
             }
         }
 
@@ -81,35 +87,30 @@ namespace Ryujinx.Memory.WindowsShared
         {
             ulong endAddress = address + size;
 
-            var overlaps = Array.Empty<IntervalTreeNode<ulong, ulong>>();
-            int count;
-
             lock (_mappings)
             {
-                count = _mappings.Get(address, endAddress, ref overlaps);
+                RangeNode<ulong> node = _mappings.GetNodeByKey(address);
+                RangeNode<ulong> successorNode;
 
-                for (int index = 0; index < count; index++)
+                for (; node != null; node = successorNode)
                 {
-                    var overlap = overlaps[index];
+                    successorNode = node.Successor;
 
-                    if (IsMapped(overlap.Value))
+                    if (IsMapped(node.Value))
                     {
-                        if (!WindowsApi.UnmapViewOfFile2(WindowsApi.CurrentProcessHandle, (IntPtr)overlap.Start, 2))
+                        if (!WindowsApi.UnmapViewOfFile2(WindowsApi.CurrentProcessHandle, (IntPtr)node.Start, 2))
                         {
                             throw new WindowsApiException("UnmapViewOfFile2");
                         }
                     }
 
-                    _mappings.Remove(overlap);
-                }
-            }
+                    _mappings.Remove(node);
 
-            if (count > 1)
-            {
-                CheckFreeResult(WindowsApi.VirtualFree(
-                    (IntPtr)address,
-                    (IntPtr)size,
-                    AllocationType.Release | AllocationType.CoalescePlaceholders));
+                    if (node.End >= endAddress)
+                    {
+                        break;
+                    }
+                }
             }
 
             RemoveProtection(address, size);
@@ -130,8 +131,8 @@ namespace Ryujinx.Memory.WindowsShared
 
             try
             {
-                UnmapViewInternal(sharedMemory, location, size, owner);
-                MapViewInternal(sharedMemory, srcOffset, location, size);
+                UnmapViewInternal(sharedMemory, location, size, owner, updateProtection: false);
+                MapViewInternal(sharedMemory, srcOffset, location, size, updateProtection: true);
             }
             finally
             {
@@ -146,8 +147,9 @@ namespace Ryujinx.Memory.WindowsShared
         /// <param name="srcOffset">Offset in the shared memory to map</param>
         /// <param name="location">Address to map the view into</param>
         /// <param name="size">Size of the view in bytes</param>
+        /// <param name="updateProtection">Indicates if the memory protections should be updated after the map</param>
         /// <exception cref="WindowsApiException">Thrown when the Windows API returns an error mapping the memory</exception>
-        private void MapViewInternal(IntPtr sharedMemory, ulong srcOffset, IntPtr location, IntPtr size)
+        private void MapViewInternal(IntPtr sharedMemory, ulong srcOffset, IntPtr location, IntPtr size, bool updateProtection)
         {
             SplitForMap((ulong)location, (ulong)size, srcOffset);
 
@@ -166,6 +168,11 @@ namespace Ryujinx.Memory.WindowsShared
             {
                 throw new WindowsApiException("MapViewOfFile3");
             }
+
+            if (updateProtection)
+            {
+                UpdateProtection((ulong)location, (ulong)size, MemoryPermission.ReadAndWrite);
+            }
         }
 
         /// <summary>
@@ -178,18 +185,17 @@ namespace Ryujinx.Memory.WindowsShared
         {
             ulong endAddress = address + size;
 
-            var overlaps = Array.Empty<IntervalTreeNode<ulong, ulong>>();
+            var overlaps = new RangeNode<ulong>[InitialOverlapsSize];
 
             lock (_mappings)
             {
-                int count = _mappings.Get(address, endAddress, ref overlaps);
+                int count = _mappings.GetNodes(address, endAddress, ref overlaps);
 
                 Debug.Assert(count == 1);
                 Debug.Assert(!IsMapped(overlaps[0].Value));
 
                 var overlap = overlaps[0];
 
-                // Tree operations might modify the node start/end values, so save a copy before we modify the tree.
                 ulong overlapStart = overlap.Start;
                 ulong overlapEnd = overlap.End;
                 ulong overlapValue = overlap.Value;
@@ -206,8 +212,8 @@ namespace Ryujinx.Memory.WindowsShared
                         (IntPtr)size,
                         AllocationType.Release | AllocationType.PreservePlaceholder));
 
-                    _mappings.Add(overlapStart, address, overlapValue);
-                    _mappings.Add(endAddress, overlapEnd, AddBackingOffset(overlapValue, endAddress - overlapStart));
+                    _mappings.Add(new RangeNode<ulong>(overlapStart, address, overlapValue));
+                    _mappings.Add(new RangeNode<ulong>(endAddress, overlapEnd, AddBackingOffset(overlapValue, endAddress - overlapStart)));
                 }
                 else if (overlapStartsBefore)
                 {
@@ -218,7 +224,7 @@ namespace Ryujinx.Memory.WindowsShared
                         (IntPtr)overlappedSize,
                         AllocationType.Release | AllocationType.PreservePlaceholder));
 
-                    _mappings.Add(overlapStart, address, overlapValue);
+                    _mappings.Add(new RangeNode<ulong>(overlapStart, address, overlapValue));
                 }
                 else if (overlapEndsAfter)
                 {
@@ -229,10 +235,10 @@ namespace Ryujinx.Memory.WindowsShared
                         (IntPtr)overlappedSize,
                         AllocationType.Release | AllocationType.PreservePlaceholder));
 
-                    _mappings.Add(endAddress, overlapEnd, AddBackingOffset(overlapValue, overlappedSize));
+                    _mappings.Add(new RangeNode<ulong>(endAddress, overlapEnd, AddBackingOffset(overlapValue, overlappedSize)));
                 }
 
-                _mappings.Add(address, endAddress, backingOffset);
+                _mappings.Add(new RangeNode<ulong>(address, endAddress, backingOffset));
             }
         }
 
@@ -254,7 +260,7 @@ namespace Ryujinx.Memory.WindowsShared
 
             try
             {
-                UnmapViewInternal(sharedMemory, location, size, owner);
+                UnmapViewInternal(sharedMemory, location, size, owner, updateProtection: true);
             }
             finally
             {
@@ -273,19 +279,20 @@ namespace Ryujinx.Memory.WindowsShared
         /// <param name="location">Address to unmap</param>
         /// <param name="size">Size of the region to unmap in bytes</param>
         /// <param name="owner">Memory block that owns the mapping</param>
+        /// <param name="updateProtection">Indicates if the memory protections should be updated after the unmap</param>
         /// <exception cref="WindowsApiException">Thrown when the Windows API returns an error unmapping or remapping the memory</exception>
-        private void UnmapViewInternal(IntPtr sharedMemory, IntPtr location, IntPtr size, MemoryBlock owner)
+        private void UnmapViewInternal(IntPtr sharedMemory, IntPtr location, IntPtr size, MemoryBlock owner, bool updateProtection)
         {
             ulong startAddress = (ulong)location;
             ulong unmapSize = (ulong)size;
             ulong endAddress = startAddress + unmapSize;
 
-            var overlaps = Array.Empty<IntervalTreeNode<ulong, ulong>>();
+            var overlaps = new RangeNode<ulong>[InitialOverlapsSize];
             int count;
 
             lock (_mappings)
             {
-                count = _mappings.Get(startAddress, endAddress, ref overlaps);
+                count = _mappings.GetNodes(startAddress, endAddress, ref overlaps);
             }
 
             for (int index = 0; index < count; index++)
@@ -294,19 +301,14 @@ namespace Ryujinx.Memory.WindowsShared
 
                 if (IsMapped(overlap.Value))
                 {
-                    // Tree operations might modify the node start/end values, so save a copy before we modify the tree.
-                    ulong overlapStart = overlap.Start;
-                    ulong overlapEnd = overlap.End;
-                    ulong overlapValue = overlap.Value;
-
                     lock (_mappings)
                     {
                         _mappings.Remove(overlap);
-                        _mappings.Add(overlapStart, overlapEnd, ulong.MaxValue);
+                        _mappings.Add(new RangeNode<ulong>(overlap.Start, overlap.End, ulong.MaxValue));
                     }
 
-                    bool overlapStartsBefore = overlapStart < startAddress;
-                    bool overlapEndsAfter = overlapEnd > endAddress;
+                    bool overlapStartsBefore = overlap.Start < startAddress;
+                    bool overlapEndsAfter = overlap.End > endAddress;
 
                     if (overlapStartsBefore || overlapEndsAfter)
                     {
@@ -323,27 +325,27 @@ namespace Ryujinx.Memory.WindowsShared
                         {
                             partialUnmapState.PartialUnmapsCount++;
 
-                            if (!WindowsApi.UnmapViewOfFile2(WindowsApi.CurrentProcessHandle, (IntPtr)overlapStart, 2))
+                            if (!WindowsApi.UnmapViewOfFile2(WindowsApi.CurrentProcessHandle, (IntPtr)overlap.Start, 2))
                             {
                                 throw new WindowsApiException("UnmapViewOfFile2");
                             }
 
                             if (overlapStartsBefore)
                             {
-                                ulong remapSize = startAddress - overlapStart;
+                                ulong remapSize = startAddress - overlap.Start;
 
-                                MapViewInternal(sharedMemory, overlapValue, (IntPtr)overlapStart, (IntPtr)remapSize);
-                                RestoreRangeProtection(overlapStart, remapSize);
+                                MapViewInternal(sharedMemory, overlap.Value, (IntPtr)overlap.Start, (IntPtr)remapSize, updateProtection: false);
+                                RestoreRangeProtection(overlap.Start, remapSize);
                             }
 
                             if (overlapEndsAfter)
                             {
-                                ulong overlappedSize = endAddress - overlapStart;
-                                ulong remapBackingOffset = overlapValue + overlappedSize;
-                                ulong remapAddress = overlapStart + overlappedSize;
-                                ulong remapSize = overlapEnd - endAddress;
+                                ulong overlappedSize = endAddress - overlap.Start;
+                                ulong remapBackingOffset = overlap.Value + overlappedSize;
+                                ulong remapAddress = overlap.Start + overlappedSize;
+                                ulong remapSize = overlap.End - endAddress;
 
-                                MapViewInternal(sharedMemory, remapBackingOffset, (IntPtr)remapAddress, (IntPtr)remapSize);
+                                MapViewInternal(sharedMemory, remapBackingOffset, (IntPtr)remapAddress, (IntPtr)remapSize, updateProtection: false);
                                 RestoreRangeProtection(remapAddress, remapSize);
                             }
                         }
@@ -352,7 +354,7 @@ namespace Ryujinx.Memory.WindowsShared
                             partialUnmapLock.DowngradeFromWriterLock();
                         }
                     }
-                    else if (!WindowsApi.UnmapViewOfFile2(WindowsApi.CurrentProcessHandle, (IntPtr)overlapStart, 2))
+                    else if (!WindowsApi.UnmapViewOfFile2(WindowsApi.CurrentProcessHandle, (IntPtr)overlap.Start, 2))
                     {
                         throw new WindowsApiException("UnmapViewOfFile2");
                     }
@@ -360,7 +362,11 @@ namespace Ryujinx.Memory.WindowsShared
             }
 
             CoalesceForUnmap(startAddress, unmapSize, owner);
-            RemoveProtection(startAddress, unmapSize);
+
+            if (updateProtection)
+            {
+                UpdateProtection(startAddress, unmapSize, MemoryPermission.None);
+            }
         }
 
         /// <summary>
@@ -374,44 +380,58 @@ namespace Ryujinx.Memory.WindowsShared
             ulong endAddress = address + size;
             ulong blockAddress = (ulong)owner.Pointer;
             ulong blockEnd = blockAddress + owner.Size;
-            var overlaps = Array.Empty<IntervalTreeNode<ulong, ulong>>();
             int unmappedCount = 0;
 
             lock (_mappings)
             {
-                int count = _mappings.Get(
-                    Math.Max(address - MinimumPageSize, blockAddress),
-                    Math.Min(endAddress + MinimumPageSize, blockEnd), ref overlaps);
+                RangeNode<ulong> node = _mappings.GetNodeByKey(address);
 
-                if (count < 2)
+                if (node == null)
                 {
-                    // Nothing to coalesce if we only have 1 or no overlaps.
+                    // Nothing to coalesce if we have no overlaps.
                     return;
                 }
 
-                for (int index = 0; index < count; index++)
+                RangeNode<ulong> predecessor = node.Predecessor;
+                RangeNode<ulong> successor = null;
+
+                for (; node != null; node = successor)
                 {
-                    var overlap = overlaps[index];
+                    successor = node.Successor;
+                    var overlap = node;
 
                     if (!IsMapped(overlap.Value))
                     {
-                        if (address > overlap.Start)
-                        {
-                            address = overlap.Start;
-                        }
-
-                        if (endAddress < overlap.End)
-                        {
-                            endAddress = overlap.End;
-                        }
+                        address = Math.Min(address, overlap.Start);
+                        endAddress = Math.Max(endAddress, overlap.End);
 
                         _mappings.Remove(overlap);
-
                         unmappedCount++;
                     }
+
+                    if (node.End >= endAddress)
+                    {
+                        break;
+                    }
                 }
 
-                _mappings.Add(address, endAddress, ulong.MaxValue);
+                if (predecessor != null && !IsMapped(predecessor.Value) && predecessor.Start >= blockAddress)
+                {
+                    address = Math.Min(address, predecessor.Start);
+
+                    _mappings.Remove(predecessor);
+                    unmappedCount++;
+                }
+
+                if (successor != null && !IsMapped(successor.Value) && successor.End <= blockEnd)
+                {
+                    endAddress = Math.Max(endAddress, successor.End);
+
+                    _mappings.Remove(successor);
+                    unmappedCount++;
+                }
+
+                _mappings.Add(new RangeNode<ulong>(address, endAddress, ulong.MaxValue));
             }
 
             if (unmappedCount > 1)
@@ -462,60 +482,55 @@ namespace Ryujinx.Memory.WindowsShared
             ulong reprotectSize = (ulong)size;
             ulong endAddress = reprotectAddress + reprotectSize;
 
-            var overlaps = Array.Empty<IntervalTreeNode<ulong, ulong>>();
-            int count;
+            bool success = true;
 
             lock (_mappings)
             {
-                count = _mappings.Get(reprotectAddress, endAddress, ref overlaps);
-            }
+                RangeNode<ulong> node = _mappings.GetNodeByKey(reprotectAddress);
+                RangeNode<ulong> successorNode;
 
-            bool success = true;
-
-            for (int index = 0; index < count; index++)
-            {
-                var overlap = overlaps[index];
-
-                ulong mappedAddress = overlap.Start;
-                ulong mappedSize = overlap.End - overlap.Start;
-
-                if (mappedAddress < reprotectAddress)
+                for (; node != null; node = successorNode)
                 {
-                    ulong delta = reprotectAddress - mappedAddress;
-                    mappedAddress = reprotectAddress;
-                    mappedSize -= delta;
-                }
+                    successorNode = node.Successor;
+                    var overlap = node;
 
-                ulong mappedEndAddress = mappedAddress + mappedSize;
+                    ulong mappedAddress = overlap.Start;
+                    ulong mappedSize = overlap.End - overlap.Start;
 
-                if (mappedEndAddress > endAddress)
-                {
-                    ulong delta = mappedEndAddress - endAddress;
-                    mappedSize -= delta;
-                }
-
-                if (!WindowsApi.VirtualProtect((IntPtr)mappedAddress, (IntPtr)mappedSize, WindowsApi.GetProtection(permission), out _))
-                {
-                    if (throwOnError)
+                    if (mappedAddress < reprotectAddress)
                     {
-                        throw new WindowsApiException("VirtualProtect");
+                        ulong delta = reprotectAddress - mappedAddress;
+                        mappedAddress = reprotectAddress;
+                        mappedSize -= delta;
                     }
 
-                    success = false;
-                }
+                    ulong mappedEndAddress = mappedAddress + mappedSize;
 
-                // We only keep track of "non-standard" protections,
-                // that is, everything that is not just RW (which is the default when views are mapped).
-                if (permission == MemoryPermission.ReadAndWrite)
-                {
-                    RemoveProtection(mappedAddress, mappedSize);
-                }
-                else
-                {
-                    AddProtection(mappedAddress, mappedSize, permission);
+                    if (mappedEndAddress > endAddress)
+                    {
+                        ulong delta = mappedEndAddress - endAddress;
+                        mappedSize -= delta;
+                    }
+
+                    if (!WindowsApi.VirtualProtect((IntPtr)mappedAddress, (IntPtr)mappedSize, WindowsApi.GetProtection(permission), out _))
+                    {
+                        if (throwOnError)
+                        {
+                            throw new WindowsApiException("VirtualProtect");
+                        }
+
+                        success = false;
+                    }
+
+                    if (node.End >= endAddress)
+                    {
+                        break;
+                    }
                 }
             }
 
+            UpdateProtection(reprotectAddress, reprotectSize, permission);
+
             return success;
         }
 
@@ -564,29 +579,30 @@ namespace Ryujinx.Memory.WindowsShared
         /// <param name="address">Address of the protected region</param>
         /// <param name="size">Size of the protected region in bytes</param>
         /// <param name="permission">Memory permissions of the region</param>
-        private void AddProtection(ulong address, ulong size, MemoryPermission permission)
+        private void UpdateProtection(ulong address, ulong size, MemoryPermission permission)
         {
             ulong endAddress = address + size;
-            var overlaps = Array.Empty<IntervalTreeNode<ulong, MemoryPermission>>();
-            int count;
 
             lock (_protections)
             {
-                count = _protections.Get(address, endAddress, ref overlaps);
+                RangeNode<MemoryPermission> node = _protections.GetNodeByKey(address);
 
-                if (count == 1 &&
-                    overlaps[0].Start <= address &&
-                    overlaps[0].End >= endAddress &&
-                    overlaps[0].Value == permission)
+                if (node != null &&
+                    node.Start <= address &&
+                    node.End >= endAddress &&
+                    node.Value == permission)
                 {
                     return;
                 }
 
+                RangeNode<MemoryPermission> successorNode;
+
                 ulong startAddress = address;
 
-                for (int index = 0; index < count; index++)
+                for (; node != null; node = successorNode)
                 {
-                    var protection = overlaps[index];
+                    successorNode = node.Successor;
+                    var protection = node;
 
                     ulong protAddress = protection.Start;
                     ulong protEndAddress = protection.End;
@@ -594,7 +610,7 @@ namespace Ryujinx.Memory.WindowsShared
 
                     _protections.Remove(protection);
 
-                    if (protection.Value == permission)
+                    if (protPermission == permission)
                     {
                         if (startAddress > protAddress)
                         {
@@ -610,17 +626,22 @@ namespace Ryujinx.Memory.WindowsShared
                     {
                         if (startAddress > protAddress)
                         {
-                            _protections.Add(protAddress, startAddress, protPermission);
+                            _protections.Add(new RangeNode<MemoryPermission>(protAddress, startAddress, protPermission));
                         }
 
                         if (endAddress < protEndAddress)
                         {
-                            _protections.Add(endAddress, protEndAddress, protPermission);
+                            _protections.Add(new RangeNode<MemoryPermission>(endAddress, protEndAddress, protPermission));
                         }
                     }
+
+                    if (node.End >= endAddress)
+                    {
+                        break;
+                    }
                 }
 
-                _protections.Add(startAddress, endAddress, permission);
+                _protections.Add(new RangeNode<MemoryPermission>(startAddress, endAddress, permission));
             }
         }
 
@@ -632,16 +653,16 @@ namespace Ryujinx.Memory.WindowsShared
         private void RemoveProtection(ulong address, ulong size)
         {
             ulong endAddress = address + size;
-            var overlaps = Array.Empty<IntervalTreeNode<ulong, MemoryPermission>>();
-            int count;
 
             lock (_protections)
             {
-                count = _protections.Get(address, endAddress, ref overlaps);
+                RangeNode<MemoryPermission> node = _protections.GetNodeByKey(address);
+                RangeNode<MemoryPermission> successorNode;
 
-                for (int index = 0; index < count; index++)
+                for (; node != null; node = successorNode)
                 {
-                    var protection = overlaps[index];
+                    successorNode = node.Successor;
+                    var protection = node;
 
                     ulong protAddress = protection.Start;
                     ulong protEndAddress = protection.End;
@@ -651,12 +672,17 @@ namespace Ryujinx.Memory.WindowsShared
 
                     if (address > protAddress)
                     {
-                        _protections.Add(protAddress, address, protPermission);
+                        _protections.Add(new RangeNode<MemoryPermission>(protAddress, address, protPermission));
                     }
 
                     if (endAddress < protEndAddress)
                     {
-                        _protections.Add(endAddress, protEndAddress, protPermission);
+                        _protections.Add(new RangeNode<MemoryPermission>(endAddress, protEndAddress, protPermission));
+                    }
+
+                    if (node.End >= endAddress)
+                    {
+                        break;
                     }
                 }
             }
@@ -670,12 +696,12 @@ namespace Ryujinx.Memory.WindowsShared
         private void RestoreRangeProtection(ulong address, ulong size)
         {
             ulong endAddress = address + size;
-            var overlaps = Array.Empty<IntervalTreeNode<ulong, MemoryPermission>>();
+            var overlaps = new RangeNode<MemoryPermission>[InitialOverlapsSize];
             int count;
 
             lock (_protections)
             {
-                count = _protections.Get(address, endAddress, ref overlaps);
+                count = _protections.GetNodes(address, endAddress, ref overlaps);
             }
 
             ulong startAddress = address;
@@ -684,6 +710,12 @@ namespace Ryujinx.Memory.WindowsShared
             {
                 var protection = overlaps[index];
 
+                // If protection is R/W we don't need to reprotect as views are initially mapped as R/W.
+                if (protection.Value == MemoryPermission.ReadAndWrite)
+                {
+                    continue;
+                }
+
                 ulong protAddress = protection.Start;
                 ulong protEndAddress = protection.End;
 

Ryujinx.Tests/Cpu/CpuTest32.cs

@@ -456,6 +456,10 @@ namespace Ryujinx.Tests.Cpu
 
             Assert.Multiple(() =>
             {
+                Assert.That(_context.GetPstateFlag(PState.GE0Flag), Is.EqualTo((_unicornEmu.CPSR & (1u << 16)) != 0), "GE0Flag");
+                Assert.That(_context.GetPstateFlag(PState.GE1Flag), Is.EqualTo((_unicornEmu.CPSR & (1u << 17)) != 0), "GE1Flag");
+                Assert.That(_context.GetPstateFlag(PState.GE2Flag), Is.EqualTo((_unicornEmu.CPSR & (1u << 18)) != 0), "GE2Flag");
+                Assert.That(_context.GetPstateFlag(PState.GE3Flag), Is.EqualTo((_unicornEmu.CPSR & (1u << 19)) != 0), "GE3Flag");
                 Assert.That(_context.GetPstateFlag(PState.QFlag), Is.EqualTo(_unicornEmu.QFlag), "QFlag");
                 Assert.That(_context.GetPstateFlag(PState.VFlag), Is.EqualTo(_unicornEmu.OverflowFlag), "VFlag");
                 Assert.That(_context.GetPstateFlag(PState.CFlag), Is.EqualTo(_unicornEmu.CarryFlag), "CFlag");

Ryujinx.Tests/Cpu/CpuTestAlu32.cs

@@ -10,6 +10,21 @@ namespace Ryujinx.Tests.Cpu
 #if Alu32
 
 #region "ValueSource (Opcodes)"
+        private static uint[] _SU_H_AddSub_8_()
+        {
+            return new uint[]
+            {
+                0xe6100f90u, // SADD8  R0, R0, R0
+                0xe6100ff0u, // SSUB8  R0, R0, R0
+                0xe6300f90u, // SHADD8 R0, R0, R0
+                0xe6300ff0u, // SHSUB8 R0, R0, R0
+                0xe6500f90u, // UADD8  R0, R0, R0
+                0xe6500ff0u, // USUB8  R0, R0, R0
+                0xe6700f90u, // UHADD8 R0, R0, R0
+                0xe6700ff0u  // UHSUB8 R0, R0, R0
+            };
+        }
+
         private static uint[] _Ssat_Usat_()
         {
             return new uint[]
@@ -150,15 +165,14 @@ namespace Ryujinx.Tests.Cpu
         }
 
         [Test, Pairwise]
-        public void Uhadd8([Values(0u, 0xdu)] uint rd,
-                           [Values(1u)] uint rm,
-                           [Values(2u)] uint rn,
-                           [Random(RndCnt)] uint w0,
-                           [Random(RndCnt)] uint w1,
-                           [Random(RndCnt)] uint w2)
+        public void SU_H_AddSub_8([ValueSource("_SU_H_AddSub_8_")] uint opcode,
+                                  [Values(0u, 0xdu)] uint rd,
+                                  [Values(1u)] uint rm,
+                                  [Values(2u)] uint rn,
+                                  [Random(RndCnt)] uint w0,
+                                  [Random(RndCnt)] uint w1,
+                                  [Random(RndCnt)] uint w2)
         {
-            uint opcode = 0xE6700F90u; // UHADD8 R0, R0, R0
-
             opcode |= ((rm & 15) << 0) | ((rd & 15) << 12) | ((rn & 15) << 16);
 
             uint sp = TestContext.CurrentContext.Random.NextUInt();
@@ -169,20 +183,24 @@ namespace Ryujinx.Tests.Cpu
         }
 
         [Test, Pairwise]
-        public void Uhsub8([Values(0u, 0xdu)] uint rd,
-                           [Values(1u)] uint rm,
-                           [Values(2u)] uint rn,
-                           [Random(RndCnt)] uint w0,
-                           [Random(RndCnt)] uint w1,
-                           [Random(RndCnt)] uint w2)
+        public void Uadd8_Sel([Values(0u)] uint rd,
+                              [Values(1u)] uint rm,
+                              [Values(2u)] uint rn,
+                              [Random(RndCnt)] uint w0,
+                              [Random(RndCnt)] uint w1,
+                              [Random(RndCnt)] uint w2)
         {
-            uint opcode = 0xE6700FF0u; // UHSUB8 R0, R0, R0
+            uint opUadd8 = 0xE6500F90; // UADD8 R0, R0, R0
+            uint opSel   = 0xE6800FB0; // SEL R0, R0, R0
 
-            opcode |= ((rm & 15) << 0) | ((rd & 15) << 12) | ((rn & 15) << 16);
+            opUadd8  |= ((rm & 15) << 0) | ((rd & 15) << 12) | ((rn & 15) << 16);
+            opSel |= ((rm & 15) << 0) | ((rd & 15) << 12) | ((rn & 15) << 16);
 
-            uint sp = TestContext.CurrentContext.Random.NextUInt();
-
-            SingleOpcode(opcode, r0: w0, r1: w1, r2: w2, sp: sp);
+            SetContext(r0: w0, r1: w1, r2: w2);
+            Opcode(opUadd8);
+            Opcode(opSel);
+            Opcode(0xE12FFF1E); // BX LR
+            ExecuteOpcodes();
 
             CompareAgainstUnicorn();
         }

Ryujinx.Tests/Cpu/CpuTestSimdCvt32.cs

@@ -13,6 +13,16 @@ namespace Ryujinx.Tests.Cpu
 #if SimdCvt32
 
 #region "ValueSource (Opcodes)"
+        private static uint[] _Vrint_AMNP_V_F32_()
+        {
+            return new uint[]
+            {
+                0xf3ba0500u, // VRINTA.F32 Q0, Q0
+                0xf3ba0680u, // VRINTM.F32 Q0, Q0
+                0xf3ba0400u, // VRINTN.F32 Q0, Q0
+                0xf3ba0780u  // VRINTP.F32 Q0, Q0
+            };
+        }
 #endregion
 
 #region "ValueSource (Types)"
@@ -64,6 +74,47 @@ namespace Ryujinx.Tests.Cpu
             }
         }
 
+        private static IEnumerable<ulong> _2S_F_()
+        {
+            yield return 0xFF7FFFFFFF7FFFFFul; // -Max Normal    (float.MinValue)
+            yield return 0x8080000080800000ul; // -Min Normal
+            yield return 0x807FFFFF807FFFFFul; // -Max Subnormal
+            yield return 0x8000000180000001ul; // -Min Subnormal (-float.Epsilon)
+            yield return 0x7F7FFFFF7F7FFFFFul; // +Max Normal    (float.MaxValue)
+            yield return 0x0080000000800000ul; // +Min Normal
+            yield return 0x007FFFFF007FFFFFul; // +Max Subnormal
+            yield return 0x0000000100000001ul; // +Min Subnormal (float.Epsilon)
+
+            if (!NoZeros)
+            {
+                yield return 0x8000000080000000ul; // -Zero
+                yield return 0x0000000000000000ul; // +Zero
+            }
+
+            if (!NoInfs)
+            {
+                yield return 0xFF800000FF800000ul; // -Infinity
+                yield return 0x7F8000007F800000ul; // +Infinity
+            }
+
+            if (!NoNaNs)
+            {
+                yield return 0xFFC00000FFC00000ul; // -QNaN (all zeros payload) (float.NaN)
+                yield return 0xFFBFFFFFFFBFFFFFul; // -SNaN (all ones  payload)
+                yield return 0x7FC000007FC00000ul; // +QNaN (all zeros payload) (-float.NaN) (DefaultNaN)
+                yield return 0x7FBFFFFF7FBFFFFFul; // +SNaN (all ones  payload)
+            }
+
+            for (int cnt = 1; cnt <= RndCnt; cnt++)
+            {
+                ulong rnd1 = GenNormalS();
+                ulong rnd2 = GenSubnormalS();
+
+                yield return (rnd1 << 32) | rnd1;
+                yield return (rnd2 << 32) | rnd2;
+            }
+        }
+
         private static IEnumerable<ulong> _1D_F_()
         {
             yield return 0xFFEFFFFFFFFFFFFFul; // -Max Normal    (double.MinValue)
@@ -224,6 +275,35 @@ namespace Ryujinx.Tests.Cpu
             CompareAgainstUnicorn();
         }
 
+        [Test, Pairwise] [Explicit]
+        public void Vrint_AMNP_V_F32([ValueSource(nameof(_Vrint_AMNP_V_F32_))] uint opcode,
+                                     [Values(0u, 1u, 2u, 3u)] uint rd,
+                                     [Values(0u, 1u, 2u, 3u)] uint rm,
+                                     [ValueSource(nameof(_2S_F_))] ulong d0,
+                                     [ValueSource(nameof(_2S_F_))] ulong d1,
+                                     [ValueSource(nameof(_2S_F_))] ulong d2,
+                                     [ValueSource(nameof(_2S_F_))] ulong d3,
+                                     [Values] bool q)
+        {
+            if (q)
+            {
+                opcode |= 1 << 6;
+
+                rd >>= 1; rd <<= 1;
+                rm >>= 1; rm <<= 1;
+            }
+
+            opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
+            opcode |= ((rm & 0xf) << 0)  | ((rm & 0x10) << 1);
+
+            V128 v0 = MakeVectorE0E1(d0, d1);
+            V128 v1 = MakeVectorE0E1(d2, d3);
+
+            SingleOpcode(opcode, v0: v0, v1: v1);
+
+            CompareAgainstUnicorn();
+        }
+
         [Test, Pairwise, Description("VRINTX.F<size> <Sd>, <Sm>")]
         public void Vrintx_S([Values(0u, 1u)] uint rd,
                              [Values(0u, 1u)] uint rm,
@@ -253,7 +333,7 @@ namespace Ryujinx.Tests.Cpu
             }
 
             opcode |= ((size & 3) << 8);
-            
+
             int fpscr = (int)rMode << (int)Fpcr.RMode;
             SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, fpscr: fpscr);
 

Ryujinx.Tests/Cpu/CpuTestSimdMemory32.cs

@@ -12,7 +12,7 @@ namespace Ryujinx.Tests.Cpu
 #if SimdMemory32
         private const int RndCntImm = 2;
 
-        private uint[] LDSTModes =
+        private uint[] _ldStModes =
         {
             // LD1
             0b0111,
@@ -96,7 +96,7 @@ namespace Ryujinx.Tests.Cpu
                               [Values(0u, 13u)] uint rn,
                               [Values(1u, 13u, 15u)] uint rm,
                               [Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd,
-                              [Range(0u, 3u)] uint mode,
+                              [Range(0u, 10u)] uint mode,
                               [Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset)
         {
             var data = GenerateVectorSequence(0x1000);
@@ -104,7 +104,13 @@ namespace Ryujinx.Tests.Cpu
 
             uint opcode = 0xf4200000u; // VLD4.8 {D0, D1, D2, D3}, [R0], R0
 
-            opcode |= ((size & 3) << 6) | ((rn & 15) << 16) | (rm & 15) | (LDSTModes[mode] << 8);
+            if (mode > 3 && size == 3)
+            {
+                // A size of 3 is only valid for VLD1.
+                size = 2;
+            }
+
+            opcode |= ((size & 3) << 6) | ((rn & 15) << 16) | (rm & 15) | (_ldStModes[mode] << 8);
 
             opcode |= ((vd & 0x10) << 18);
             opcode |= ((vd & 0xf) << 12);
@@ -151,17 +157,23 @@ namespace Ryujinx.Tests.Cpu
                               [Values(0u, 13u)] uint rn,
                               [Values(1u, 13u, 15u)] uint rm,
                               [Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint vd,
-                              [Range(0u, 3u)] uint mode,
+                              [Range(0u, 10u)] uint mode,
                               [Values(0x0u)] [Random(0u, 0xffu, RndCntImm)] uint offset)
         {
             var data = GenerateVectorSequence(0x1000);
             SetWorkingMemory(0, data);
 
             (V128 vec1, V128 vec2, V128 vec3, V128 vec4) = GenerateTestVectors();
-            
+
             uint opcode = 0xf4000000u; // VST4.8 {D0, D1, D2, D3}, [R0], R0
 
-            opcode |= ((size & 3) << 6) | ((rn & 15) << 16) | (rm & 15) | (LDSTModes[mode] << 8);
+            if (mode > 3 && size == 3)
+            {
+                // A size of 3 is only valid for VST1.
+                size = 2;
+            }
+
+            opcode |= ((size & 3) << 6) | ((rn & 15) << 16) | (rm & 15) | (_ldStModes[mode] << 8);
 
             opcode |= ((vd & 0x10) << 18);
             opcode |= ((vd & 0xf) << 12);
@@ -183,7 +195,8 @@ namespace Ryujinx.Tests.Cpu
 
             uint opcode = 0xec100a00u; // VST4.8 {D0, D1, D2, D3}, [R0], R0
 
-            uint[] vldmModes = {
+            uint[] vldmModes =
+            {
                 // Note: 3rd 0 leaves a space for "D".
                 0b0100, // Increment after.
                 0b0101, // Increment after. (!)
@@ -240,7 +253,7 @@ namespace Ryujinx.Tests.Cpu
             {
                 opcode |= ((sd & 0x1) << 22);
                 opcode |= ((sd & 0x1e) << 11);
-            } 
+            }
             else
             {
                 opcode |= ((sd & 0x10) << 18);