Implement PLD and SUB (imm16) on T32, plus UADD8, SADD8, USUB8 and SSUB8 on both A32 and T32 (#3693 )

T32: Implement Asimd instructions (#3692 )
Fix bindless 1D textures having a buffer type on the shader (#3697 )
2022-09-13 19:51:40 -03:00 · 2022-09-13 18:25:37 -03:00 · 2022-09-13 08:53:55 +02:00 · 2022-09-13 08:24:09 +02:00 · 2022-09-13 07:59:38 +02:00 · 2022-09-11 15:58:15 +00:00
135 changed files with 3515 additions and 1446 deletions
--- a/ARMeilleure/Common/AddressTable.cs
+++ b/ARMeilleure/Common/AddressTable.cs
@@ -1,4 +1,4 @@
-using ARMeilleure.Diagnostics.EventSources;
+using ARMeilleure.Diagnostics;
 using System;
 using System.Collections.Generic;
 using System.Runtime.InteropServices;
@@ -218,7 +218,7 @@ namespace ARMeilleure.Common

            _pages.Add(page);

-            AddressTableEventSource.Log.Allocated(size, leaf);
+            TranslatorEventSource.Log.AddressTableAllocated(size, leaf);

            return page;
        }
--- a/ARMeilleure/Decoders/Decoder.cs
+++ b/ARMeilleure/Decoders/Decoder.cs
@@ -251,6 +251,13 @@ namespace ARMeilleure.Decoders
                return false;
            }

+            // Compare and branch instructions are always conditional.
+            if (opCode.Instruction.Name == InstName.Cbz ||
+                opCode.Instruction.Name == InstName.Cbnz)
+            {
+                return false;
+            }
+
            // Note: On ARM32, most instructions have conditional execution,
            // so there's no "Always" (unconditional) branch like on ARM64.
            // We need to check if the condition is "Always" instead.
--- a/ARMeilleure/Decoders/DecoderHelper.cs
+++ b/ARMeilleure/Decoders/DecoderHelper.cs
@@ -151,7 +151,7 @@ namespace ARMeilleure.Decoders

        public static bool VectorArgumentsInvalid(bool q, params int[] args)
        {
-            if (q) 
+            if (q)
            {
                for (int i = 0; i < args.Length; i++)
                {
--- a/ARMeilleure/Decoders/IOpCode32AluBf.cs
+++ b/ARMeilleure/Decoders/IOpCode32AluBf.cs
@@ -7,5 +7,8 @@

        int Msb { get; }
        int Lsb { get; }
+
+        int SourceMask => (int)(0xFFFFFFFF >> (31 - Msb));
+        int DestMask => SourceMask & (int)(0xFFFFFFFF << Lsb);
    }
 }
--- a/ARMeilleure/Decoders/IOpCode32AluImm16.cs
+++ b/ARMeilleure/Decoders/IOpCode32AluImm16.cs
@@ -0,0 +1,7 @@
+namespace ARMeilleure.Decoders
+{
+    interface IOpCode32AluImm16 : IOpCode32Alu
+    {
+        int Immediate { get; }
+    }
+}
--- a/ARMeilleure/Decoders/IOpCode32AluMla.cs
+++ b/ARMeilleure/Decoders/IOpCode32AluMla.cs
@@ -0,0 +1,11 @@
+namespace ARMeilleure.Decoders
+{
+    interface IOpCode32AluMla : IOpCode32AluReg
+    {
+        int Ra { get; }
+
+        bool NHigh { get; }
+        bool MHigh { get; }
+        bool R { get; }
+    }
+}
--- a/ARMeilleure/Decoders/IOpCode32AluUmull.cs
+++ b/ARMeilleure/Decoders/IOpCode32AluUmull.cs
@@ -0,0 +1,13 @@
+namespace ARMeilleure.Decoders
+{
+    interface IOpCode32AluUmull : IOpCode32, IOpCode32HasSetFlags
+    {
+        int RdLo { get; }
+        int RdHi { get; }
+        int Rn { get; }
+        int Rm { get; }
+
+        bool NHigh { get; }
+        bool MHigh { get; }
+    }
+}
--- a/ARMeilleure/Decoders/IOpCode32Mem.cs
+++ b/ARMeilleure/Decoders/IOpCode32Mem.cs
@@ -3,6 +3,7 @@ namespace ARMeilleure.Decoders
    interface IOpCode32Mem : IOpCode32
    {
        int Rt { get; }
+        int Rt2 => Rt | 1;
        int Rn { get; }

        bool WBack { get; }
--- a/ARMeilleure/Decoders/OpCode32.cs
+++ b/ARMeilleure/Decoders/OpCode32.cs
@@ -13,16 +13,13 @@ namespace ARMeilleure.Decoders
            Cond = (Condition)((uint)opCode >> 28);
        }

-        public bool IsThumb()
-        {
-            return this is OpCodeT16 || this is OpCodeT32;
-        }
+        public bool IsThumb { get; protected init; } = false;

        public uint GetPc()
        {
            // Due to backwards compatibility and legacy behavior of ARMv4 CPUs pipeline,
            // the PC actually points 2 instructions ahead.
-            if (IsThumb())
+            if (IsThumb)
            {
                // PC is ahead by 4 in thumb mode whether or not the current instruction
                // is 16 or 32 bit.
--- a/ARMeilleure/Decoders/OpCode32AluBf.cs
+++ b/ARMeilleure/Decoders/OpCode32AluBf.cs
@@ -6,12 +6,8 @@
        public int Rn { get; }

        public int Msb { get; }
-
        public int Lsb { get; }

-        public int SourceMask => (int)(0xFFFFFFFF >> (31 - Msb));
-        public int DestMask => SourceMask & (int)(0xFFFFFFFF << Lsb);
-
        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluBf(inst, address, opCode);

        public OpCode32AluBf(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
--- a/ARMeilleure/Decoders/OpCode32AluImm16.cs
+++ b/ARMeilleure/Decoders/OpCode32AluImm16.cs
@@ -1,6 +1,6 @@
 namespace ARMeilleure.Decoders
 {
-    class OpCode32AluImm16 : OpCode32Alu
+    class OpCode32AluImm16 : OpCode32Alu, IOpCode32AluImm16
    {
        public int Immediate { get; }

--- a/ARMeilleure/Decoders/OpCode32AluMla.cs
+++ b/ARMeilleure/Decoders/OpCode32AluMla.cs
@@ -1,6 +1,6 @@
 namespace ARMeilleure.Decoders
 {
-    class OpCode32AluMla : OpCode32, IOpCode32AluReg
+    class OpCode32AluMla : OpCode32, IOpCode32AluMla
    {
        public int Rn { get; }
        public int Rm { get; }
--- a/ARMeilleure/Decoders/OpCode32AluUmull.cs
+++ b/ARMeilleure/Decoders/OpCode32AluUmull.cs
@@ -1,6 +1,6 @@
 namespace ARMeilleure.Decoders
 {
-    class OpCode32AluUmull : OpCode32, IOpCode32HasSetFlags
+    class OpCode32AluUmull : OpCode32, IOpCode32AluUmull
    {
        public int RdLo { get; }
        public int RdHi { get; }
@@ -11,7 +11,6 @@
        public bool MHigh { get; }

        public bool? SetFlags { get; }
-        public DataOp DataOp { get; }

        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluUmull(inst, address, opCode);

@@ -26,7 +25,6 @@
            MHigh = ((opCode >> 6) & 0x1) == 1;

            SetFlags = ((opCode >> 20) & 0x1) != 0;
-            DataOp = DataOp.Arithmetic;
        }
    }
 }
--- a/ARMeilleure/Decoders/OpCode32Simd.cs
+++ b/ARMeilleure/Decoders/OpCode32Simd.cs
@@ -7,14 +7,15 @@
        public bool F { get; protected set; }
        public bool U { get; }

-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Simd(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Simd(inst, address, opCode, false);
+        public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32Simd(inst, address, opCode, true);

-        public OpCode32Simd(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32Simd(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
        {
            Size = (opCode >> 20) & 0x3;
            Q = ((opCode >> 6) & 0x1) != 0;
            F = ((opCode >> 10) & 0x1) != 0;
-            U = ((opCode >> 24) & 0x1) != 0;
+            U = ((opCode >> (isThumb ? 28 : 24)) & 0x1) != 0;
            Opc = (opCode >> 7) & 0x3;

            RegisterSize = Q ? RegisterSize.Simd128 : RegisterSize.Simd64;
--- a/ARMeilleure/Decoders/OpCode32SimdBase.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdBase.cs
@@ -47,6 +47,9 @@ namespace ARMeilleure.Decoders
            throw new InvalidOperationException();
        }

-        public OpCode32SimdBase(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
+        protected OpCode32SimdBase(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
+        {
+            IsThumb = isThumb;
+        }
    }
 }
--- a/ARMeilleure/Decoders/OpCode32SimdBinary.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdBinary.cs
@@ -5,9 +5,10 @@
    /// </summary>
    class OpCode32SimdBinary : OpCode32SimdReg
    {
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdBinary(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdBinary(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdBinary(inst, address, opCode, true);

-        public OpCode32SimdBinary(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdBinary(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
        {
            Size = 3;

--- a/ARMeilleure/Decoders/OpCode32SimdCmpZ.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdCmpZ.cs
@@ -2,9 +2,10 @@
 {
    class OpCode32SimdCmpZ : OpCode32Simd
    {
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCmpZ(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCmpZ(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCmpZ(inst, address, opCode, true);

-        public OpCode32SimdCmpZ(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdCmpZ(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
        {
            Size = (opCode >> 18) & 0x3;

--- a/ARMeilleure/Decoders/OpCode32SimdCvtFI.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdCvtFI.cs
@@ -2,9 +2,10 @@
 {
    class OpCode32SimdCvtFI : OpCode32SimdS
    {
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCvtFI(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCvtFI(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCvtFI(inst, address, opCode, true);

-        public OpCode32SimdCvtFI(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdCvtFI(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
        {
            Opc = (opCode >> 7) & 0x1;

--- a/ARMeilleure/Decoders/OpCode32SimdDupElem.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdDupElem.cs
@@ -4,9 +4,10 @@
    {
        public int Index { get; }

-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdDupElem(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdDupElem(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdDupElem(inst, address, opCode, true);

-        public OpCode32SimdDupElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdDupElem(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
        {
            var opc = (opCode >> 16) & 0xf;

--- a/ARMeilleure/Decoders/OpCode32SimdDupGP.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdDupGP.cs
@@ -7,10 +7,13 @@
        public int Rt { get; }
        public bool Q { get; }

-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdDupGP(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdDupGP(inst, address, opCode, false);
+        public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdDupGP(inst, address, opCode, true);

-        public OpCode32SimdDupGP(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdDupGP(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
        {
+            IsThumb = isThumb;
+
            Size = 2 - (((opCode >> 21) & 0x2) | ((opCode >> 5) & 0x1)); // B:E - 0 for 32, 16 then 8.
            if (Size == -1)
            {
--- a/ARMeilleure/Decoders/OpCode32SimdExt.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdExt.cs
@@ -4,9 +4,10 @@
    {
        public int Immediate { get; }

-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdExt(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdExt(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdExt(inst, address, opCode, true);

-        public OpCode32SimdExt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdExt(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
        {
            Immediate = (opCode >> 8) & 0xf;
            Size = 0;
--- a/ARMeilleure/Decoders/OpCode32SimdImm.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdImm.cs
@@ -6,9 +6,10 @@
        public long Immediate { get; }
        public int Elems => GetBytesCount() >> Size;

-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm(inst, address, opCode, false);
+        public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm(inst, address, opCode, true);

-        public OpCode32SimdImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdImm(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
        {
            Vd = (opCode >> 12) & 0xf;
            Vd |= (opCode >> 18) & 0x10;
@@ -22,7 +23,7 @@

            imm = ((uint)opCode >> 0) & 0xf;
            imm |= ((uint)opCode >> 12) & 0x70;
-            imm |= ((uint)opCode >> 17) & 0x80;
+            imm |= ((uint)opCode >> (isThumb ? 21 : 17)) & 0x80;

            (Immediate, Size) = OpCodeSimdHelper.GetSimdImmediateAndSize(cMode, op, imm);

--- a/ARMeilleure/Decoders/OpCode32SimdImm44.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdImm44.cs
@@ -7,10 +7,13 @@
        public int Size { get; }
        public int Elems { get; }

-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm44(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm44(inst, address, opCode, false);
+        public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm44(inst, address, opCode, true);

-        public OpCode32SimdImm44(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdImm44(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
        {
+            IsThumb = isThumb;
+
            Size = (opCode >> 8) & 0x3;

            bool single = Size != 3;
--- a/ARMeilleure/Decoders/OpCode32SimdLong.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdLong.cs
@@ -4,9 +4,10 @@
    {
        public bool U { get; }

-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdLong(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdLong(inst, address, opCode, false);
+        public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdLong(inst, address, opCode, true);

-        public OpCode32SimdLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdLong(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
        {
            int imm3h = (opCode >> 19) & 0x7;

@@ -18,7 +19,7 @@
                case 4: Size = 2; break;
            }

-            U = ((opCode >> 24) & 0x1) != 0;
+            U = ((opCode >> (isThumb ? 28 : 24)) & 0x1) != 0;

            RegisterSize = RegisterSize.Simd64;

--- a/ARMeilleure/Decoders/OpCode32SimdMemImm.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdMemImm.cs
@@ -8,10 +8,13 @@
        public bool Add { get; }
        public int Immediate { get; }

-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemImm(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemImm(inst, address, opCode, false);
+        public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemImm(inst, address, opCode, true);

-        public OpCode32SimdMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdMemImm(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
        {
+            IsThumb = isThumb;
+
            Immediate = opCode & 0xff;

            Rn = (opCode >> 16) & 0xf;
--- a/ARMeilleure/Decoders/OpCode32SimdMemMult.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdMemMult.cs
@@ -12,10 +12,13 @@
        public bool DoubleWidth { get; }
        public bool Add { get; }

-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemMult(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemMult(inst, address, opCode, false);
+        public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemMult(inst, address, opCode, true);

-        public OpCode32SimdMemMult(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdMemMult(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
        {
+            IsThumb = isThumb;
+
            Rn = (opCode >> 16) & 0xf;

            bool isLoad = (opCode & (1 << 20)) != 0;
--- a/ARMeilleure/Decoders/OpCode32SimdMemPair.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdMemPair.cs
@@ -1,11 +1,10 @@
 using ARMeilleure.State;
-using System;

 namespace ARMeilleure.Decoders
 {
    class OpCode32SimdMemPair : OpCode32, IOpCode32Simd
    {
-        private static int[] RegsMap =
+        private static int[] _regsMap =
        {
            1, 1, 4, 2,
            1, 1, 3, 1,
@@ -24,10 +23,13 @@ namespace ARMeilleure.Decoders
        public int Regs { get; }
        public int Increment { get; }

-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemPair(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemPair(inst, address, opCode, false);
+        public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemPair(inst, address, opCode, true);

-        public OpCode32SimdMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdMemPair(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
        {
+            IsThumb = isThumb;
+
            Vd = (opCode >> 12) & 0xf;
            Vd |= (opCode >> 18) & 0x10;

@@ -40,9 +42,9 @@ namespace ARMeilleure.Decoders
            WBack = Rm != RegisterAlias.Aarch32Pc;
            RegisterIndex = Rm != RegisterAlias.Aarch32Pc && Rm != RegisterAlias.Aarch32Sp;

-            Regs = RegsMap[(opCode >> 8) & 0xf];
+            Regs = _regsMap[(opCode >> 8) & 0xf];

-            Increment = Math.Min(Regs, ((opCode >> 8) & 0x1) + 1);
+            Increment = ((opCode >> 8) & 0x1) + 1;
        }
    }
 }
--- a/ARMeilleure/Decoders/OpCode32SimdMemSingle.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdMemSingle.cs
@@ -15,10 +15,13 @@ namespace ARMeilleure.Decoders
        public bool Replicate { get; }
        public int Increment { get; }

-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemSingle(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemSingle(inst, address, opCode, false);
+        public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemSingle(inst, address, opCode, true);

-        public OpCode32SimdMemSingle(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdMemSingle(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
        {
+            IsThumb = isThumb;
+
            Vd = (opCode >> 12) & 0xf;
            Vd |= (opCode >> 18) & 0x10;

--- a/ARMeilleure/Decoders/OpCode32SimdMovGp.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdMovGp.cs
@@ -11,10 +11,13 @@
        public int Opc1 { get; }
        public int Opc2 { get; }

-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGp(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGp(inst, address, opCode, false);
+        public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGp(inst, address, opCode, true);

-        public OpCode32SimdMovGp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdMovGp(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
        {
+            IsThumb = isThumb;
+
            // Which one is used is instruction dependant.
            Op = (opCode >> 20) & 0x1;

--- a/ARMeilleure/Decoders/OpCode32SimdMovGpDouble.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdMovGpDouble.cs
@@ -9,10 +9,13 @@
        public int Rt2 { get; }
        public int Op { get; }

-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpDouble(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpDouble(inst, address, opCode, false);
+        public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpDouble(inst, address, opCode, true);

-        public OpCode32SimdMovGpDouble(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdMovGpDouble(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
        {
+            IsThumb = isThumb;
+
            // Which one is used is instruction dependant.
            Op = (opCode >> 20) & 0x1;

--- a/ARMeilleure/Decoders/OpCode32SimdMovGpElem.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdMovGpElem.cs
@@ -11,10 +11,13 @@

        public int Index { get; }

-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpElem(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpElem(inst, address, opCode, false);
+        public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpElem(inst, address, opCode, true);

-        public OpCode32SimdMovGpElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdMovGpElem(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
        {
+            IsThumb = isThumb;
+
            Op = (opCode >> 20) & 0x1;
            U = ((opCode >> 23) & 1) != 0;

--- a/ARMeilleure/Decoders/OpCode32SimdMovn.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdMovn.cs
@@ -0,0 +1,13 @@
+namespace ARMeilleure.Decoders
+{
+    class OpCode32SimdMovn : OpCode32Simd
+    {
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovn(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovn(inst, address, opCode, true);
+
+        public OpCode32SimdMovn(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
+        {
+            Size = (opCode >> 18) & 0x3;
+        }
+    }
+}
--- a/ARMeilleure/Decoders/OpCode32SimdReg.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdReg.cs
@@ -8,9 +8,10 @@
        public int In => GetQuadwordSubindex(Vn) << (3 - Size);
        public int Fn => GetQuadwordSubindex(Vn) << (1 - (Size & 1));

-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdReg(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdReg(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdReg(inst, address, opCode, true);

-        public OpCode32SimdReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdReg(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
        {
            Vn = ((opCode >> 3) & 0x10) | ((opCode >> 16) & 0xf);

--- a/ARMeilleure/Decoders/OpCode32SimdRegElem.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdRegElem.cs
@@ -2,11 +2,12 @@
 {
    class OpCode32SimdRegElem : OpCode32SimdReg
    {
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElem(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElem(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElem(inst, address, opCode, true);

-        public OpCode32SimdRegElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdRegElem(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
        {
-            Q = ((opCode >> 24) & 0x1) != 0;
+            Q = ((opCode >> (isThumb ? 28 : 24)) & 0x1) != 0;
            F = ((opCode >> 8) & 0x1) != 0;
            Size = (opCode >> 20) & 0x3;

--- a/ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs
@@ -2,9 +2,10 @@
 {
    class OpCode32SimdRegElemLong : OpCode32SimdRegElem
    {
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElemLong(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElemLong(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElemLong(inst, address, opCode, true);

-        public OpCode32SimdRegElemLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdRegElemLong(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
        {
            Q = false;
            F = false;
--- a/ARMeilleure/Decoders/OpCode32SimdRegLong.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdRegLong.cs
@@ -4,9 +4,10 @@
    {
        public bool Polynomial { get; }

-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegLong(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegLong(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegLong(inst, address, opCode, true);

-        public OpCode32SimdRegLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdRegLong(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
        {
            Q = false;
            RegisterSize = RegisterSize.Simd64;
--- a/ARMeilleure/Decoders/OpCode32SimdRegS.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdRegS.cs
@@ -4,9 +4,10 @@
    {
        public int Vn { get; }

-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegS(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegS(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegS(inst, address, opCode, true);

-        public OpCode32SimdRegS(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdRegS(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
        {
            bool single = Size != 3;
            if (single)
--- a/ARMeilleure/Decoders/OpCode32SimdRegWide.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdRegWide.cs
@@ -2,9 +2,10 @@
 {
    class OpCode32SimdRegWide : OpCode32SimdReg
    {
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegWide(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegWide(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegWide(inst, address, opCode, true);

-        public OpCode32SimdRegWide(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdRegWide(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
        {
            Q = false;
            RegisterSize = RegisterSize.Simd64;
--- a/ARMeilleure/Decoders/OpCode32SimdRev.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdRev.cs
@@ -2,9 +2,10 @@
 {
    class OpCode32SimdRev : OpCode32SimdCmpZ
    {
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRev(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRev(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRev(inst, address, opCode, true);

-        public OpCode32SimdRev(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdRev(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
        {
            if (Opc + Size >= 3)
            {
--- a/ARMeilleure/Decoders/OpCode32SimdS.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdS.cs
@@ -8,10 +8,13 @@
        public int Opc2 { get; } // opc2 or RM (opc2<1:0>) [Vcvt, Vrint].
        public int Size { get; protected set; }

-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdS(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdS(inst, address, opCode, false);
+        public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdS(inst, address, opCode, true);

-        public OpCode32SimdS(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdS(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
        {
+            IsThumb = isThumb;
+
            Opc = (opCode >> 15) & 0x3;
            Opc2 = (opCode >> 16) & 0x7;

--- a/ARMeilleure/Decoders/OpCode32SimdSel.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdSel.cs
@@ -4,9 +4,10 @@
    {
        public OpCode32SimdSelMode Cc { get; }

-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSel(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSel(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSel(inst, address, opCode, true);

-        public OpCode32SimdSel(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdSel(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
        {
            Cc = (OpCode32SimdSelMode)((opCode >> 20) & 3);
        }
--- a/ARMeilleure/Decoders/OpCode32SimdShImm.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdShImm.cs
@@ -4,9 +4,10 @@
    {
        public int Shift { get; }

-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImm(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImm(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImm(inst, address, opCode, true);

-        public OpCode32SimdShImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdShImm(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
        {
            int imm6 = (opCode >> 16) & 0x3f;
            int limm6 = ((opCode >> 1) & 0x40) | imm6;
--- a/ARMeilleure/Decoders/OpCode32SimdShImmLong.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdShImmLong.cs
@@ -4,9 +4,10 @@
    {
        public int Shift { get; }

-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImmLong(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImmLong(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImmLong(inst, address, opCode, true);

-        public OpCode32SimdShImmLong(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdShImmLong(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
        {
            Q = false;
            RegisterSize = RegisterSize.Simd64;
--- a/ARMeilleure/Decoders/OpCode32SimdShImmNarrow.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdShImmNarrow.cs
@@ -2,8 +2,9 @@
 {
    class OpCode32SimdShImmNarrow : OpCode32SimdShImm
    {
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImmNarrow(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImmNarrow(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdShImmNarrow(inst, address, opCode, true);

-        public OpCode32SimdShImmNarrow(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
+        public OpCode32SimdShImmNarrow(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb) { }
    }
 }
--- a/ARMeilleure/Decoders/OpCode32SimdSpecial.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdSpecial.cs
@@ -5,10 +5,13 @@
        public int Rt { get; }
        public int Sreg { get; }

-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSpecial(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSpecial(inst, address, opCode, false);
+        public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSpecial(inst, address, opCode, true);

-        public OpCode32SimdSpecial(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdSpecial(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
        {
+            IsThumb = isThumb;
+
            Rt = (opCode >> 12) & 0xf;
            Sreg = (opCode >> 16) & 0xf;
        }
--- a/ARMeilleure/Decoders/OpCode32SimdSqrte.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdSqrte.cs
@@ -2,9 +2,10 @@
 {
    class OpCode32SimdSqrte : OpCode32Simd
    {
-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSqrte(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSqrte(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSqrte(inst, address, opCode, true);

-        public OpCode32SimdSqrte(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdSqrte(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
        {
            Size = (opCode >> 18) & 0x1;
            F = ((opCode >> 8) & 0x1) != 0;
--- a/ARMeilleure/Decoders/OpCode32SimdTbl.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdTbl.cs
@@ -4,9 +4,10 @@
    {
        public int Length { get; }

-        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdTbl(inst, address, opCode);
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdTbl(inst, address, opCode, false);
+        public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdTbl(inst, address, opCode, true);

-        public OpCode32SimdTbl(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        public OpCode32SimdTbl(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
        {
            Length = (opCode >> 8) & 3;
            Size = 0;
--- a/ARMeilleure/Decoders/OpCodeT16.cs
+++ b/ARMeilleure/Decoders/OpCodeT16.cs
@@ -8,6 +8,7 @@ namespace ARMeilleure.Decoders
        {
            Cond = Condition.Al;

+            IsThumb = true;
            OpCodeSizeInBytes = 2;
        }
    }
--- a/ARMeilleure/Decoders/OpCodeT16Adr.cs
+++ b/ARMeilleure/Decoders/OpCodeT16Adr.cs
@@ -4,14 +4,13 @@ namespace ARMeilleure.Decoders
    {
        public int Rd { get; }

-        public bool Add => true;
        public int Immediate { get; }

        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16Adr(inst, address, opCode);

        public OpCodeT16Adr(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
        {
-            Rd  = (opCode >> 8) & 7;
+            Rd = (opCode >> 8) & 7;

            int imm = (opCode & 0xff) << 2;
            Immediate = (int)(GetPc() & 0xfffffffc) + imm;
--- a/ARMeilleure/Decoders/OpCodeT32.cs
+++ b/ARMeilleure/Decoders/OpCodeT32.cs
@@ -8,6 +8,7 @@
        {
            Cond = Condition.Al;

+            IsThumb = true;
            OpCodeSizeInBytes = 4;
        }
    }
--- a/ARMeilleure/Decoders/OpCodeT32AluBf.cs
+++ b/ARMeilleure/Decoders/OpCodeT32AluBf.cs
@@ -0,0 +1,22 @@
+namespace ARMeilleure.Decoders
+{
+    class OpCodeT32AluBf : OpCodeT32, IOpCode32AluBf
+    {
+        public int Rd { get; }
+        public int Rn { get; }
+
+        public int Msb { get; }
+        public int Lsb { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32AluBf(inst, address, opCode);
+
+        public OpCodeT32AluBf(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        {
+            Rd = (opCode >> 8) & 0xf;
+            Rn = (opCode >> 16) & 0xf;
+
+            Msb = (opCode >> 0) & 0x1f;
+            Lsb = ((opCode >> 6) & 0x3) | ((opCode >> 10) & 0x1c);
+        }
+    }
+}
--- a/ARMeilleure/Decoders/OpCodeT32AluImm12.cs
+++ b/ARMeilleure/Decoders/OpCodeT32AluImm12.cs
@@ -0,0 +1,16 @@
+namespace ARMeilleure.Decoders
+{
+    class OpCodeT32AluImm12 : OpCodeT32Alu, IOpCode32AluImm
+    {
+        public int Immediate { get; }
+
+        public bool IsRotated => false;
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32AluImm12(inst, address, opCode);
+
+        public OpCodeT32AluImm12(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        {
+            Immediate = (opCode & 0xff) | ((opCode >> 4) & 0x700) | ((opCode >> 15) & 0x800);
+        }
+    }
+}
--- a/ARMeilleure/Decoders/OpCodeT32AluMla.cs
+++ b/ARMeilleure/Decoders/OpCodeT32AluMla.cs
@@ -0,0 +1,29 @@
+namespace ARMeilleure.Decoders
+{
+    class OpCodeT32AluMla : OpCodeT32, IOpCode32AluMla
+    {
+        public int Rn { get; }
+        public int Rm { get; }
+        public int Ra { get; }
+        public int Rd { get; }
+
+        public bool NHigh { get; }
+        public bool MHigh { get; }
+        public bool R { get; }
+        public bool? SetFlags => false;
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32AluMla(inst, address, opCode);
+
+        public OpCodeT32AluMla(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        {
+            Rm = (opCode >> 0) & 0xf;
+            Rd = (opCode >> 8) & 0xf;
+            Ra = (opCode >> 12) & 0xf;
+            Rn = (opCode >> 16) & 0xf;
+            R = (opCode & (1 << 4)) != 0;
+
+            MHigh = ((opCode >> 4) & 0x1) == 1;
+            NHigh = ((opCode >> 5) & 0x1) == 1;
+        }
+    }
+}
--- a/ARMeilleure/Decoders/OpCodeT32AluReg.cs
+++ b/ARMeilleure/Decoders/OpCodeT32AluReg.cs
@@ -0,0 +1,14 @@
+namespace ARMeilleure.Decoders
+{
+    class OpCodeT32AluReg : OpCodeT32Alu, IOpCode32AluReg
+    {
+        public int Rm { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32AluReg(inst, address, opCode);
+
+        public OpCodeT32AluReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        {
+            Rm = (opCode >> 0) & 0xf;
+        }
+    }
+}
--- a/ARMeilleure/Decoders/OpCodeT32AluUmull.cs
+++ b/ARMeilleure/Decoders/OpCodeT32AluUmull.cs
@@ -0,0 +1,28 @@
+namespace ARMeilleure.Decoders
+{
+    class OpCodeT32AluUmull : OpCodeT32, IOpCode32AluUmull
+    {
+        public int RdLo { get; }
+        public int RdHi { get; }
+        public int Rn { get; }
+        public int Rm { get; }
+
+        public bool NHigh { get; }
+        public bool MHigh { get; }
+
+        public bool? SetFlags => false;
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32AluUmull(inst, address, opCode);
+
+        public OpCodeT32AluUmull(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        {
+            Rm = (opCode >> 0) & 0xf;
+            RdHi = (opCode >> 8) & 0xf;
+            RdLo = (opCode >> 12) & 0xf;
+            Rn = (opCode >> 16) & 0xf;
+
+            MHigh = ((opCode >> 4) & 0x1) == 1;
+            NHigh = ((opCode >> 5) & 0x1) == 1;
+        }
+    }
+}
--- a/ARMeilleure/Decoders/OpCodeT32AluUx.cs
+++ b/ARMeilleure/Decoders/OpCodeT32AluUx.cs
@@ -0,0 +1,18 @@
+using ARMeilleure.State;
+
+namespace ARMeilleure.Decoders
+{
+    class OpCodeT32AluUx : OpCodeT32AluReg, IOpCode32AluUx
+    {
+        public int Rotate { get; }
+        public int RotateBits => Rotate * 8;
+        public bool Add => Rn != RegisterAlias.Aarch32Pc;
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32AluUx(inst, address, opCode);
+
+        public OpCodeT32AluUx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        {
+            Rotate = (opCode >> 4) & 0x3;
+        }
+    }
+}
--- a/ARMeilleure/Decoders/OpCodeT32BImm24.cs
+++ b/ARMeilleure/Decoders/OpCodeT32BImm24.cs
@@ -27,7 +27,7 @@ namespace ARMeilleure.Decoders
            int i2 = j2 ^ s ^ 1;

            int imm32 = imm11 | (imm10 << 11) | (i2 << 21) | (i1 << 22) | (s << 23);
-            imm32 = (imm32 << 9) >> 8;
+            imm32 = (imm32 << 8) >> 7;

            Immediate = pc + imm32;
        }
--- a/ARMeilleure/Decoders/OpCodeT32MemImm8D.cs
+++ b/ARMeilleure/Decoders/OpCodeT32MemImm8D.cs
@@ -23,7 +23,7 @@ namespace ARMeilleure.Decoders
            Add   = ((opCode >> 23) & 1) != 0;
            WBack = ((opCode >> 21) & 1) != 0;

-            Immediate = opCode & 0xff;
+            Immediate = (opCode & 0xff) << 2;

            IsLoad = ((opCode >> 20) & 1) != 0;
        }
--- a/ARMeilleure/Decoders/OpCodeT32MemLdEx.cs
+++ b/ARMeilleure/Decoders/OpCodeT32MemLdEx.cs
@@ -4,6 +4,7 @@ namespace ARMeilleure.Decoders
    {
        public int Rd => 0;
        public int Rt { get; }
+        public int Rt2 { get; }
        public int Rn { get; }

        public bool WBack => false;
@@ -17,6 +18,7 @@ namespace ARMeilleure.Decoders

        public OpCodeT32MemLdEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
        {
+            Rt2 = (opCode >> 8) & 0xf;
            Rt = (opCode >> 12) & 0xf;
            Rn = (opCode >> 16) & 0xf;
        }
--- a/ARMeilleure/Decoders/OpCodeT32MemStEx.cs
+++ b/ARMeilleure/Decoders/OpCodeT32MemStEx.cs
@@ -4,6 +4,7 @@ namespace ARMeilleure.Decoders
    {
        public int Rd { get; }
        public int Rt { get; }
+        public int Rt2 { get; }
        public int Rn { get; }

        public bool WBack => false;
@@ -18,6 +19,7 @@ namespace ARMeilleure.Decoders
        public OpCodeT32MemStEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
        {
            Rd = (opCode >> 0) & 0xf;
+            Rt2 = (opCode >> 8) & 0xf;
            Rt = (opCode >> 12) & 0xf;
            Rn = (opCode >> 16) & 0xf;
        }
--- a/ARMeilleure/Decoders/OpCodeT32MovImm16.cs
+++ b/ARMeilleure/Decoders/OpCodeT32MovImm16.cs
@@ -0,0 +1,16 @@
+namespace ARMeilleure.Decoders
+{
+    class OpCodeT32MovImm16 : OpCodeT32Alu, IOpCode32AluImm16
+    {
+        public int Immediate { get; }
+
+        public bool IsRotated => false;
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32MovImm16(inst, address, opCode);
+
+        public OpCodeT32MovImm16(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        {
+            Immediate = (opCode & 0xff) | ((opCode >> 4) & 0x700) | ((opCode >> 15) & 0x800) | ((opCode >> 4) & 0xf000);
+        }
+    }
+}
--- a/ARMeilleure/Decoders/OpCodeT32ShiftReg.cs
+++ b/ARMeilleure/Decoders/OpCodeT32ShiftReg.cs
@@ -0,0 +1,19 @@
+namespace ARMeilleure.Decoders
+{
+    class OpCodeT32ShiftReg : OpCodeT32Alu, IOpCode32AluRsReg
+    {
+        public int Rm => Rn;
+        public int Rs { get; }
+
+        public ShiftType ShiftType { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32ShiftReg(inst, address, opCode);
+
+        public OpCodeT32ShiftReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        {
+            Rs = (opCode >> 0) & 0xf;
+
+            ShiftType = (ShiftType)((opCode >> 21) & 3);
+        }
+    }
+}
--- a/ARMeilleure/Decoders/OpCodeT32Tb.cs
+++ b/ARMeilleure/Decoders/OpCodeT32Tb.cs
@@ -0,0 +1,16 @@
+namespace ARMeilleure.Decoders
+{
+    class OpCodeT32Tb : OpCodeT32, IOpCode32BReg
+    {
+        public int Rm { get; }
+        public int Rn { get; }
+
+        public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32Tb(inst, address, opCode);
+
+        public OpCodeT32Tb(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        {
+            Rm = (opCode >> 0) & 0xf;
+            Rn = (opCode >> 16) & 0xf;
+        }
+    }
+}
--- a/ARMeilleure/Decoders/OpCodeTable.cs
+++ b/ARMeilleure/Decoders/OpCodeTable.cs
@@ -727,11 +727,13 @@ namespace ARMeilleure.Decoders
            SetA32("<<<<0010111xxxxxxxxxxxxxxxxxxxxx", InstName.Rsc,     InstEmit32.Rsc,     OpCode32AluImm.Create);
            SetA32("<<<<0000111xxxxxxxxxxxxxxxx0xxxx", InstName.Rsc,     InstEmit32.Rsc,     OpCode32AluRsImm.Create);
            SetA32("<<<<0000111xxxxxxxxxxxxx0xx1xxxx", InstName.Rsc,     InstEmit32.Rsc,     OpCode32AluRsReg.Create);
+            SetA32("<<<<01100001xxxxxxxx11111001xxxx", InstName.Sadd8,   InstEmit32.Sadd8,   OpCode32AluReg.Create);
            SetA32("<<<<0010110xxxxxxxxxxxxxxxxxxxxx", InstName.Sbc,     InstEmit32.Sbc,     OpCode32AluImm.Create);
            SetA32("<<<<0000110xxxxxxxxxxxxxxxx0xxxx", InstName.Sbc,     InstEmit32.Sbc,     OpCode32AluRsImm.Create);
            SetA32("<<<<0000110xxxxxxxxxxxxx0xx1xxxx", InstName.Sbc,     InstEmit32.Sbc,     OpCode32AluRsReg.Create);
            SetA32("<<<<0111101xxxxxxxxxxxxxx101xxxx", InstName.Sbfx,    InstEmit32.Sbfx,    OpCode32AluBf.Create);
            SetA32("<<<<01110001xxxx1111xxxx0001xxxx", InstName.Sdiv,    InstEmit32.Sdiv,    OpCode32AluMla.Create);
+            SetA32("<<<<01101000xxxxxxxx11111011xxxx", InstName.Sel,     InstEmit32.Sel,     OpCode32AluReg.Create);
            SetA32("<<<<01100011xxxxxxxx11111001xxxx", InstName.Shadd8,  InstEmit32.Shadd8,  OpCode32AluReg.Create);
            SetA32("<<<<01100011xxxxxxxx11111111xxxx", InstName.Shsub8,  InstEmit32.Shsub8,  OpCode32AluReg.Create);
            SetA32("<<<<00010000xxxxxxxxxxxx1xx0xxxx", InstName.Smla__,  InstEmit32.Smla__,  OpCode32AluMla.Create);
@@ -745,6 +747,7 @@ namespace ARMeilleure.Decoders
            SetA32("<<<<00010010xxxx0000xxxx1x10xxxx", InstName.Smulw_,  InstEmit32.Smulw_,  OpCode32AluMla.Create);
            SetA32("<<<<0110101xxxxxxxxxxxxxxx01xxxx", InstName.Ssat,    InstEmit32.Ssat,    OpCode32Sat.Create);
            SetA32("<<<<01101010xxxxxxxx11110011xxxx", InstName.Ssat16,  InstEmit32.Ssat16,  OpCode32Sat16.Create);
+            SetA32("<<<<01100001xxxxxxxx11111111xxxx", InstName.Ssub8,   InstEmit32.Ssub8,   OpCode32AluReg.Create);
            SetA32("<<<<00011000xxxx111111001001xxxx", InstName.Stl,     InstEmit32.Stl,     OpCode32MemStEx.Create);
            SetA32("<<<<00011100xxxx111111001001xxxx", InstName.Stlb,    InstEmit32.Stlb,    OpCode32MemStEx.Create);
            SetA32("<<<<00011000xxxxxxxx11101001xxxx", InstName.Stlex,   InstEmit32.Stlex,   OpCode32MemStEx.Create);
@@ -779,6 +782,7 @@ namespace ARMeilleure.Decoders
            SetA32("<<<<00110001xxxx0000xxxxxxxxxxxx", InstName.Tst,     InstEmit32.Tst,     OpCode32AluImm.Create);
            SetA32("<<<<00010001xxxx0000xxxxxxx0xxxx", InstName.Tst,     InstEmit32.Tst,     OpCode32AluRsImm.Create);
            SetA32("<<<<00010001xxxx0000xxxx0xx1xxxx", InstName.Tst,     InstEmit32.Tst,     OpCode32AluRsReg.Create);
+            SetA32("<<<<01100101xxxxxxxx11111001xxxx", InstName.Uadd8,   InstEmit32.Uadd8,   OpCode32AluReg.Create);
            SetA32("<<<<0111111xxxxxxxxxxxxxx101xxxx", InstName.Ubfx,    InstEmit32.Ubfx,    OpCode32AluBf.Create);
            SetA32("<<<<01110011xxxx1111xxxx0001xxxx", InstName.Udiv,    InstEmit32.Udiv,    OpCode32AluMla.Create);
            SetA32("<<<<01100111xxxxxxxx11111001xxxx", InstName.Uhadd8,  InstEmit32.Uhadd8,  OpCode32AluReg.Create);
@@ -788,194 +792,234 @@ namespace ARMeilleure.Decoders
            SetA32("<<<<0000100xxxxxxxxxxxxx1001xxxx", InstName.Umull,   InstEmit32.Umull,   OpCode32AluUmull.Create);
            SetA32("<<<<0110111xxxxxxxxxxxxxxx01xxxx", InstName.Usat,    InstEmit32.Usat,    OpCode32Sat.Create);
            SetA32("<<<<01101110xxxxxxxx11110011xxxx", InstName.Usat16,  InstEmit32.Usat16,  OpCode32Sat16.Create);
+            SetA32("<<<<01100101xxxxxxxx11111111xxxx", InstName.Usub8,   InstEmit32.Usub8,   OpCode32AluReg.Create);
            SetA32("<<<<01101110xxxxxxxxxx000111xxxx", InstName.Uxtb,    InstEmit32.Uxtb,    OpCode32AluUx.Create);
            SetA32("<<<<01101100xxxxxxxxxx000111xxxx", InstName.Uxtb16,  InstEmit32.Uxtb16,  OpCode32AluUx.Create);
            SetA32("<<<<01101111xxxxxxxxxx000111xxxx", InstName.Uxth,    InstEmit32.Uxth,    OpCode32AluUx.Create);

-            // FP & SIMD
-            SetA32("111100111x110000xxx0001101x0xxx0", InstName.Aesd_V,      InstEmit32.Aesd_V,      OpCode32Simd.Create);
-            SetA32("111100111x110000xxx0001100x0xxx0", InstName.Aese_V,      InstEmit32.Aese_V,      OpCode32Simd.Create);
-            SetA32("111100111x110000xxx0001111x0xxx0", InstName.Aesimc_V,    InstEmit32.Aesimc_V,    OpCode32Simd.Create);
-            SetA32("111100111x110000xxx0001110x0xxx0", InstName.Aesmc_V,     InstEmit32.Aesmc_V,     OpCode32Simd.Create);
-            SetA32("111100110x00xxx0xxx01100x1x0xxx0", InstName.Sha256h_V,   InstEmit32.Sha256h_V,   OpCode32SimdReg.Create);
-            SetA32("111100110x01xxx0xxx01100x1x0xxx0", InstName.Sha256h2_V,  InstEmit32.Sha256h2_V,  OpCode32SimdReg.Create);
-            SetA32("111100111x111010xxx0001111x0xxx0", InstName.Sha256su0_V, InstEmit32.Sha256su0_V, OpCode32Simd.Create);
-            SetA32("111100110x10xxx0xxx01100x1x0xxx0", InstName.Sha256su1_V, InstEmit32.Sha256su1_V, OpCode32SimdReg.Create);
-            SetA32("1111001x0x<<xxxxxxxx0111xxx0xxxx", InstName.Vabd,        InstEmit32.Vabd_I,      OpCode32SimdReg.Create);
-            SetA32("1111001x1x<<xxxxxxxx0111x0x0xxxx", InstName.Vabdl,       InstEmit32.Vabdl_I,     OpCode32SimdRegLong.Create);
-            SetA32("<<<<11101x110000xxxx101x11x0xxxx", InstName.Vabs,        InstEmit32.Vabs_S,      OpCode32SimdS.Create);
-            SetA32("111100111x11<<01xxxx00110xx0xxxx", InstName.Vabs,        InstEmit32.Vabs_V,      OpCode32SimdCmpZ.Create);
-            SetA32("111100111x111001xxxx01110xx0xxxx", InstName.Vabs,        InstEmit32.Vabs_V,      OpCode32SimdCmpZ.Create);
-            SetA32("111100100xxxxxxxxxxx1000xxx0xxxx", InstName.Vadd,        InstEmit32.Vadd_I,      OpCode32SimdReg.Create);
-            SetA32("<<<<11100x11xxxxxxxx101xx0x0xxxx", InstName.Vadd,        InstEmit32.Vadd_S,      OpCode32SimdRegS.Create);
-            SetA32("111100100x00xxxxxxxx1101xxx0xxxx", InstName.Vadd,        InstEmit32.Vadd_V,      OpCode32SimdReg.Create);
-            SetA32("1111001x1x<<xxxxxxxx0000x0x0xxxx", InstName.Vaddl,       InstEmit32.Vaddl_I,     OpCode32SimdRegLong.Create);
-            SetA32("1111001x1x<<xxxxxxxx0001x0x0xxxx", InstName.Vaddw,       InstEmit32.Vaddw_I,     OpCode32SimdRegWide.Create);
-            SetA32("111100100x00xxxxxxxx0001xxx1xxxx", InstName.Vand,        InstEmit32.Vand_I,      OpCode32SimdBinary.Create);
-            SetA32("111100100x01xxxxxxxx0001xxx1xxxx", InstName.Vbic,        InstEmit32.Vbic_I,      OpCode32SimdBinary.Create);
-            SetA32("1111001x1x000xxxxxxx<<x10x11xxxx", InstName.Vbic,        InstEmit32.Vbic_II,     OpCode32SimdImm.Create);
-            SetA32("111100110x11xxxxxxxx0001xxx1xxxx", InstName.Vbif,        InstEmit32.Vbif,        OpCode32SimdBinary.Create);
-            SetA32("111100110x10xxxxxxxx0001xxx1xxxx", InstName.Vbit,        InstEmit32.Vbit,        OpCode32SimdBinary.Create);
-            SetA32("111100110x01xxxxxxxx0001xxx1xxxx", InstName.Vbsl,        InstEmit32.Vbsl,        OpCode32SimdBinary.Create);
-            SetA32("111100110x<<xxxxxxxx1000xxx1xxxx", InstName.Vceq,        InstEmit32.Vceq_I,      OpCode32SimdReg.Create);
-            SetA32("111100100x00xxxxxxxx1110xxx0xxxx", InstName.Vceq,        InstEmit32.Vceq_V,      OpCode32SimdReg.Create);
-            SetA32("111100111x11xx01xxxx0x010xx0xxxx", InstName.Vceq,        InstEmit32.Vceq_Z,      OpCode32SimdCmpZ.Create);
-            SetA32("1111001x0x<<xxxxxxxx0011xxx1xxxx", InstName.Vcge,        InstEmit32.Vcge_I,      OpCode32SimdReg.Create);
-            SetA32("111100110x00xxxxxxxx1110xxx0xxxx", InstName.Vcge,        InstEmit32.Vcge_V,      OpCode32SimdReg.Create);
-            SetA32("111100111x11xx01xxxx0x001xx0xxxx", InstName.Vcge,        InstEmit32.Vcge_Z,      OpCode32SimdCmpZ.Create);
-            SetA32("1111001x0x<<xxxxxxxx0011xxx0xxxx", InstName.Vcgt,        InstEmit32.Vcgt_I,      OpCode32SimdReg.Create);
-            SetA32("111100110x10xxxxxxxx1110xxx0xxxx", InstName.Vcgt,        InstEmit32.Vcgt_V,      OpCode32SimdReg.Create);
-            SetA32("111100111x11xx01xxxx0x000xx0xxxx", InstName.Vcgt,        InstEmit32.Vcgt_Z,      OpCode32SimdCmpZ.Create);
-            SetA32("111100111x11xx01xxxx0x011xx0xxxx", InstName.Vcle,        InstEmit32.Vcle_Z,      OpCode32SimdCmpZ.Create);
-            SetA32("111100111x11xx01xxxx0x100xx0xxxx", InstName.Vclt,        InstEmit32.Vclt_Z,      OpCode32SimdCmpZ.Create);
-            SetA32("<<<<11101x11010xxxxx101x01x0xxxx", InstName.Vcmp,        InstEmit32.Vcmp,        OpCode32SimdS.Create);
-            SetA32("<<<<11101x11010xxxxx101x11x0xxxx", InstName.Vcmpe,       InstEmit32.Vcmpe,       OpCode32SimdS.Create);
-            SetA32("111100111x110000xxxx01010xx0xxxx", InstName.Vcnt,        InstEmit32.Vcnt,        OpCode32SimdCmpZ.Create);
-            SetA32("<<<<11101x110111xxxx101x11x0xxxx", InstName.Vcvt,        InstEmit32.Vcvt_FD,     OpCode32SimdS.Create); // FP 32 and 64, scalar.
-            SetA32("<<<<11101x11110xxxxx101x11x0xxxx", InstName.Vcvt,        InstEmit32.Vcvt_FI,     OpCode32SimdCvtFI.Create); // FP32 to int.
-            SetA32("<<<<11101x111000xxxx101xx1x0xxxx", InstName.Vcvt,        InstEmit32.Vcvt_FI,     OpCode32SimdCvtFI.Create); // Int to FP32.
-            SetA32("111111101x1111xxxxxx101xx1x0xxxx", InstName.Vcvt,        InstEmit32.Vcvt_RM,     OpCode32SimdCvtFI.Create); // The many FP32 to int encodings (fp).
-            SetA32("111100111x111011xxxx011xxxx0xxxx", InstName.Vcvt,        InstEmit32.Vcvt_V,      OpCode32SimdCmpZ.Create); // FP and integer, vector.
-            SetA32("<<<<11101x00xxxxxxxx101xx0x0xxxx", InstName.Vdiv,        InstEmit32.Vdiv_S,      OpCode32SimdRegS.Create);
-            SetA32("<<<<11101xx0xxxxxxxx1011x0x10000", InstName.Vdup,        InstEmit32.Vdup,        OpCode32SimdDupGP.Create);
-            SetA32("111100111x11xxxxxxxx11000xx0xxxx", InstName.Vdup,        InstEmit32.Vdup_1,      OpCode32SimdDupElem.Create);
-            SetA32("111100110x00xxxxxxxx0001xxx1xxxx", InstName.Veor,        InstEmit32.Veor_I,      OpCode32SimdBinary.Create);
-            SetA32("111100101x11xxxxxxxxxxxxxxx0xxxx", InstName.Vext,        InstEmit32.Vext,        OpCode32SimdExt.Create);
-            SetA32("<<<<11101x10xxxxxxxx101xx0x0xxxx", InstName.Vfma,        InstEmit32.Vfma_S,      OpCode32SimdRegS.Create);
-            SetA32("111100100x00xxxxxxxx1100xxx1xxxx", InstName.Vfma,        InstEmit32.Vfma_V,      OpCode32SimdReg.Create);
-            SetA32("<<<<11101x10xxxxxxxx101xx1x0xxxx", InstName.Vfms,        InstEmit32.Vfms_S,      OpCode32SimdRegS.Create);
-            SetA32("111100100x10xxxxxxxx1100xxx1xxxx", InstName.Vfms,        InstEmit32.Vfms_V,      OpCode32SimdReg.Create);
-            SetA32("<<<<11101x01xxxxxxxx101xx1x0xxxx", InstName.Vfnma,       InstEmit32.Vfnma_S,     OpCode32SimdRegS.Create);
-            SetA32("<<<<11101x01xxxxxxxx101xx0x0xxxx", InstName.Vfnms,       InstEmit32.Vfnms_S,     OpCode32SimdRegS.Create);
-            SetA32("1111001x0x<<xxxxxxxx0000xxx0xxxx", InstName.Vhadd,       InstEmit32.Vhadd,       OpCode32SimdReg.Create);
-            SetA32("111101001x10xxxxxxxxxx00xxxxxxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemSingle.Create);
-            SetA32("111101000x10xxxxxxxx0111xxxxxxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemPair.Create); // Regs = 1.
-            SetA32("111101000x10xxxxxxxx1010xxxxxxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemPair.Create); // Regs = 2.
-            SetA32("111101000x10xxxxxxxx0110xxxxxxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemPair.Create); // Regs = 3.
-            SetA32("111101000x10xxxxxxxx0010xxxxxxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemPair.Create); // Regs = 4.
-            SetA32("111101001x10xxxxxxxxxx01xxxxxxxx", InstName.Vld2,        InstEmit32.Vld2,        OpCode32SimdMemSingle.Create);
-            SetA32("111101000x10xxxxxxxx100xxxxxxxxx", InstName.Vld2,        InstEmit32.Vld2,        OpCode32SimdMemPair.Create); // Regs = 1, inc = 1/2 (itype).
-            SetA32("111101000x10xxxxxxxx0011xxxxxxxx", InstName.Vld2,        InstEmit32.Vld2,        OpCode32SimdMemPair.Create); // Regs = 2, inc = 2.
-            SetA32("111101001x10xxxxxxxxxx10xxxxxxxx", InstName.Vld3,        InstEmit32.Vld3,        OpCode32SimdMemSingle.Create);
-            SetA32("111101000x10xxxxxxxx010xxxxxxxxx", InstName.Vld3,        InstEmit32.Vld3,        OpCode32SimdMemPair.Create); // Inc = 1/2 (itype).
-            SetA32("111101001x10xxxxxxxxxx11xxxxxxxx", InstName.Vld4,        InstEmit32.Vld4,        OpCode32SimdMemSingle.Create);
-            SetA32("111101000x10xxxxxxxx000xxxxxxxxx", InstName.Vld4,        InstEmit32.Vld4,        OpCode32SimdMemPair.Create); // Inc = 1/2 (itype).
-            SetA32("<<<<11001x01xxxxxxxx1011xxxxxxx0", InstName.Vldm,        InstEmit32.Vldm,        OpCode32SimdMemMult.Create);
-            SetA32("<<<<11001x11xxxxxxxx1011xxxxxxx0", InstName.Vldm,        InstEmit32.Vldm,        OpCode32SimdMemMult.Create);
-            SetA32("<<<<11010x11xxxxxxxx1011xxxxxxx0", InstName.Vldm,        InstEmit32.Vldm,        OpCode32SimdMemMult.Create);
-            SetA32("<<<<11001x01xxxxxxxx1010xxxxxxxx", InstName.Vldm,        InstEmit32.Vldm,        OpCode32SimdMemMult.Create);
-            SetA32("<<<<11001x11xxxxxxxx1010xxxxxxxx", InstName.Vldm,        InstEmit32.Vldm,        OpCode32SimdMemMult.Create);
-            SetA32("<<<<11010x11xxxxxxxx1010xxxxxxxx", InstName.Vldm,        InstEmit32.Vldm,        OpCode32SimdMemMult.Create);
-            SetA32("<<<<1101xx01xxxxxxxx101xxxxxxxxx", InstName.Vldr,        InstEmit32.Vldr,        OpCode32SimdMemImm.Create);
-            SetA32("1111001x0x<<xxxxxxxx0110xxx0xxxx", InstName.Vmax,        InstEmit32.Vmax_I,      OpCode32SimdReg.Create);
-            SetA32("111100100x00xxxxxxxx1111xxx0xxxx", InstName.Vmax,        InstEmit32.Vmax_V,      OpCode32SimdReg.Create);
-            SetA32("1111001x0x<<xxxxxxxx0110xxx1xxxx", InstName.Vmin,        InstEmit32.Vmin_I,      OpCode32SimdReg.Create);
-            SetA32("111100100x10xxxxxxxx1111xxx0xxxx", InstName.Vmin,        InstEmit32.Vmin_V,      OpCode32SimdReg.Create);
-            SetA32("111111101x00xxxxxxxx10>>x0x0xxxx", InstName.Vmaxnm,      InstEmit32.Vmaxnm_S,    OpCode32SimdRegS.Create);
-            SetA32("111100110x0xxxxxxxxx1111xxx1xxxx", InstName.Vmaxnm,      InstEmit32.Vmaxnm_V,    OpCode32SimdReg.Create);
-            SetA32("111111101x00xxxxxxxx10>>x1x0xxxx", InstName.Vminnm,      InstEmit32.Vminnm_S,    OpCode32SimdRegS.Create);
-            SetA32("111100110x1xxxxxxxxx1111xxx1xxxx", InstName.Vminnm,      InstEmit32.Vminnm_V,    OpCode32SimdReg.Create);
-            SetA32("1111001x1x<<xxxxxxxx000xx1x0xxxx", InstName.Vmla,        InstEmit32.Vmla_1,      OpCode32SimdRegElem.Create);
-            SetA32("111100100xxxxxxxxxxx1001xxx0xxxx", InstName.Vmla,        InstEmit32.Vmla_I,      OpCode32SimdReg.Create);
-            SetA32("<<<<11100x00xxxxxxxx101xx0x0xxxx", InstName.Vmla,        InstEmit32.Vmla_S,      OpCode32SimdRegS.Create);
-            SetA32("111100100x00xxxxxxxx1101xxx1xxxx", InstName.Vmla,        InstEmit32.Vmla_V,      OpCode32SimdReg.Create);
-            SetA32("1111001x1x<<xxxxxxxx010xx1x0xxxx", InstName.Vmls,        InstEmit32.Vmls_1,      OpCode32SimdRegElem.Create);
-            SetA32("<<<<11100x00xxxxxxxx101xx1x0xxxx", InstName.Vmls,        InstEmit32.Vmls_S,      OpCode32SimdRegS.Create);
-            SetA32("111100100x10xxxxxxxx1101xxx1xxxx", InstName.Vmls,        InstEmit32.Vmls_V,      OpCode32SimdReg.Create);
-            SetA32("111100110xxxxxxxxxxx1001xxx0xxxx", InstName.Vmls,        InstEmit32.Vmls_I,      OpCode32SimdReg.Create);
-            SetA32("1111001x1x<<xxxxxxx01010x0x0xxxx", InstName.Vmlsl,       InstEmit32.Vmlsl_I,     OpCode32SimdRegLong.Create);
-            SetA32("<<<<11100xx0xxxxxxxx1011xxx10000", InstName.Vmov,        InstEmit32.Vmov_G1,     OpCode32SimdMovGpElem.Create); // From gen purpose.
-            SetA32("<<<<1110xxx1xxxxxxxx1011xxx10000", InstName.Vmov,        InstEmit32.Vmov_G1,     OpCode32SimdMovGpElem.Create); // To gen purpose.
-            SetA32("<<<<1100010xxxxxxxxx101000x1xxxx", InstName.Vmov,        InstEmit32.Vmov_G2,     OpCode32SimdMovGpDouble.Create); // To/from gen purpose x2 and single precision x2.
-            SetA32("<<<<1100010xxxxxxxxx101100x1xxxx", InstName.Vmov,        InstEmit32.Vmov_GD,     OpCode32SimdMovGpDouble.Create); // To/from gen purpose x2 and double precision.
-            SetA32("<<<<1110000xxxxxxxxx1010x0010000", InstName.Vmov,        InstEmit32.Vmov_GS,     OpCode32SimdMovGp.Create); // To/from gen purpose and single precision.
-            SetA32("1111001x1x000xxxxxxx0xx00x01xxxx", InstName.Vmov,        InstEmit32.Vmov_I,      OpCode32SimdImm.Create); // D/Q vector I32.
-            SetA32("<<<<11101x11xxxxxxxx101x0000xxxx", InstName.Vmov,        InstEmit32.Vmov_I,      OpCode32SimdImm44.Create); // Scalar f16/32/64 based on size 01 10 11.
-            SetA32("1111001x1x000xxxxxxx10x00x01xxxx", InstName.Vmov,        InstEmit32.Vmov_I,      OpCode32SimdImm.Create); // D/Q I16.
-            SetA32("1111001x1x000xxxxxxx11xx0x01xxxx", InstName.Vmov,        InstEmit32.Vmov_I,      OpCode32SimdImm.Create); // D/Q (dt - from cmode).
-            SetA32("1111001x1x000xxxxxxx11100x11xxxx", InstName.Vmov,        InstEmit32.Vmov_I,      OpCode32SimdImm.Create); // D/Q I64.
-            SetA32("<<<<11101x110000xxxx101x01x0xxxx", InstName.Vmov,        InstEmit32.Vmov_S,      OpCode32SimdS.Create);
-            SetA32("1111001x1x001000xxx0101000x1xxxx", InstName.Vmovl,       InstEmit32.Vmovl,       OpCode32SimdLong.Create);
-            SetA32("1111001x1x010000xxx0101000x1xxxx", InstName.Vmovl,       InstEmit32.Vmovl,       OpCode32SimdLong.Create);
-            SetA32("1111001x1x100000xxx0101000x1xxxx", InstName.Vmovl,       InstEmit32.Vmovl,       OpCode32SimdLong.Create);
-            SetA32("111100111x11xx10xxxx001000x0xxx0", InstName.Vmovn,       InstEmit32.Vmovn,       OpCode32SimdCmpZ.Create);
-            SetA32("<<<<11101111xxxxxxxx101000010000", InstName.Vmrs,        InstEmit32.Vmrs,        OpCode32SimdSpecial.Create);
-            SetA32("<<<<11101110xxxxxxxx101000010000", InstName.Vmsr,        InstEmit32.Vmsr,        OpCode32SimdSpecial.Create);
-            SetA32("1111001x1x<<xxxxxxxx100xx1x0xxxx", InstName.Vmul,        InstEmit32.Vmul_1,      OpCode32SimdRegElem.Create);
-            SetA32("111100100x<<xxxxxxxx1001xxx1xxxx", InstName.Vmul,        InstEmit32.Vmul_I,      OpCode32SimdReg.Create);
-            SetA32("111100110x00xxxxxxxx1001xxx1xxxx", InstName.Vmul,        InstEmit32.Vmul_I,      OpCode32SimdReg.Create);
-            SetA32("<<<<11100x10xxxxxxxx101xx0x0xxxx", InstName.Vmul,        InstEmit32.Vmul_S,      OpCode32SimdRegS.Create);
-            SetA32("111100110x00xxxxxxxx1101xxx1xxxx", InstName.Vmul,        InstEmit32.Vmul_V,      OpCode32SimdReg.Create);
-            SetA32("1111001x1x<<xxxxxxx01010x1x0xxxx", InstName.Vmull,       InstEmit32.Vmull_1,     OpCode32SimdRegElemLong.Create);
-            SetA32("1111001x1x<<xxxxxxx01100x0x0xxxx", InstName.Vmull,       InstEmit32.Vmull_I,     OpCode32SimdRegLong.Create);
-            SetA32("111100101xx0xxxxxxx01110x0x0xxxx", InstName.Vmull,       InstEmit32.Vmull_I,     OpCode32SimdRegLong.Create); // P8/P64
-            SetA32("111100111x110000xxxx01011xx0xxxx", InstName.Vmvn,        InstEmit32.Vmvn_I,      OpCode32SimdBinary.Create);
-            SetA32("1111001x1x000xxxxxxx0xx00x11xxxx", InstName.Vmvn,        InstEmit32.Vmvn_II,     OpCode32SimdImm.Create); // D/Q vector I32.
-            SetA32("1111001x1x000xxxxxxx10x00x11xxxx", InstName.Vmvn,        InstEmit32.Vmvn_II,     OpCode32SimdImm.Create);
-            SetA32("1111001x1x000xxxxxxx110x0x11xxxx", InstName.Vmvn,        InstEmit32.Vmvn_II,     OpCode32SimdImm.Create);
-            SetA32("<<<<11101x110001xxxx101x01x0xxxx", InstName.Vneg,        InstEmit32.Vneg_S,      OpCode32SimdS.Create);
-            SetA32("111100111x11<<01xxxx00111xx0xxxx", InstName.Vneg,        InstEmit32.Vneg_V,      OpCode32SimdCmpZ.Create);
-            SetA32("111100111x111001xxxx01111xx0xxxx", InstName.Vneg,        InstEmit32.Vneg_V,      OpCode32SimdCmpZ.Create);
-            SetA32("<<<<11100x01xxxxxxxx101xx1x0xxxx", InstName.Vnmla,       InstEmit32.Vnmla_S,     OpCode32SimdRegS.Create);
-            SetA32("<<<<11100x01xxxxxxxx101xx0x0xxxx", InstName.Vnmls,       InstEmit32.Vnmls_S,     OpCode32SimdRegS.Create);
-            SetA32("<<<<11100x10xxxxxxxx101xx1x0xxxx", InstName.Vnmul,       InstEmit32.Vnmul_S,     OpCode32SimdRegS.Create);
-            SetA32("111100100x11xxxxxxxx0001xxx1xxxx", InstName.Vorn,        InstEmit32.Vorn_I,      OpCode32SimdBinary.Create);
-            SetA32("111100100x10xxxxxxxx0001xxx1xxxx", InstName.Vorr,        InstEmit32.Vorr_I,      OpCode32SimdBinary.Create);
-            SetA32("1111001x1x000xxxxxxx<<x10x01xxxx", InstName.Vorr,        InstEmit32.Vorr_II,     OpCode32SimdImm.Create);
-            SetA32("111100100x<<xxxxxxxx1011x0x1xxxx", InstName.Vpadd,       InstEmit32.Vpadd_I,     OpCode32SimdReg.Create);
-            SetA32("111100110x00xxxxxxxx1101x0x0xxxx", InstName.Vpadd,       InstEmit32.Vpadd_V,     OpCode32SimdReg.Create);
-            SetA32("1111001x0x<<xxxxxxxx1010x0x0xxxx", InstName.Vpmax,       InstEmit32.Vpmax_I,     OpCode32SimdReg.Create);
-            SetA32("111100110x00xxxxxxxx1111x0x0xxxx", InstName.Vpmax,       InstEmit32.Vpmax_V,     OpCode32SimdReg.Create);
-            SetA32("1111001x0x<<xxxxxxxx1010x0x1xxxx", InstName.Vpmin,       InstEmit32.Vpmin_I,     OpCode32SimdReg.Create);
-            SetA32("111100110x10xxxxxxxx1111x0x0xxxx", InstName.Vpmin,       InstEmit32.Vpmin_V,     OpCode32SimdReg.Create);
-            SetA32("1111001x1x>>>xxxxxxx100101x1xxx0", InstName.Vqrshrn,     InstEmit32.Vqrshrn,     OpCode32SimdShImmNarrow.Create);
-            SetA32("111100111x>>>xxxxxxx100001x1xxx0", InstName.Vqrshrun,    InstEmit32.Vqrshrun,    OpCode32SimdShImmNarrow.Create);
-            SetA32("1111001x1x>>>xxxxxxx100100x1xxx0", InstName.Vqshrn,      InstEmit32.Vqshrn,      OpCode32SimdShImmNarrow.Create);
-            SetA32("111100111x111011xxxx010x0xx0xxxx", InstName.Vrecpe,      InstEmit32.Vrecpe,      OpCode32SimdSqrte.Create);
-            SetA32("111100100x00xxxxxxxx1111xxx1xxxx", InstName.Vrecps,      InstEmit32.Vrecps,      OpCode32SimdReg.Create);
-            SetA32("111100111x11xx00xxxx000<<xx0xxxx", InstName.Vrev,        InstEmit32.Vrev,        OpCode32SimdRev.Create);
-            SetA32("111111101x1110xxxxxx101x01x0xxxx", InstName.Vrint,       InstEmit32.Vrint_RM,    OpCode32SimdS.Create);
-            SetA32("<<<<11101x110110xxxx101x11x0xxxx", InstName.Vrint,       InstEmit32.Vrint_Z,     OpCode32SimdS.Create);
-            SetA32("<<<<11101x110111xxxx101x01x0xxxx", InstName.Vrintx,      InstEmit32.Vrintx_S,    OpCode32SimdS.Create);
-            SetA32("1111001x1x>>>xxxxxxx0010>xx1xxxx", InstName.Vrshr,       InstEmit32.Vrshr,       OpCode32SimdShImm.Create);
-            SetA32("111100111x111011xxxx010x1xx0xxxx", InstName.Vrsqrte,     InstEmit32.Vrsqrte,     OpCode32SimdSqrte.Create);
-            SetA32("111100100x10xxxxxxxx1111xxx1xxxx", InstName.Vrsqrts,     InstEmit32.Vrsqrts,     OpCode32SimdReg.Create);
-            SetA32("111111100xxxxxxxxxxx101xx0x0xxxx", InstName.Vsel,        InstEmit32.Vsel,        OpCode32SimdSel.Create);
-            SetA32("111100101x>>>xxxxxxx0101>xx1xxxx", InstName.Vshl,        InstEmit32.Vshl,        OpCode32SimdShImm.Create);
-            SetA32("1111001x0xxxxxxxxxxx0100xxx0xxxx", InstName.Vshl,        InstEmit32.Vshl_I,      OpCode32SimdReg.Create);
-            SetA32("1111001x1x>>>xxxxxxx101000x1xxxx", InstName.Vshll,       InstEmit32.Vshll,       OpCode32SimdShImmLong.Create); // A1 encoding.
-            SetA32("1111001x1x>>>xxxxxxx0000>xx1xxxx", InstName.Vshr,        InstEmit32.Vshr,        OpCode32SimdShImm.Create);
-            SetA32("111100101x>>>xxxxxxx100000x1xxx0", InstName.Vshrn,       InstEmit32.Vshrn,       OpCode32SimdShImmNarrow.Create);
-            SetA32("<<<<11101x110001xxxx101x11x0xxxx", InstName.Vsqrt,       InstEmit32.Vsqrt_S,     OpCode32SimdS.Create);
-            SetA32("1111001x1x>>>xxxxxxx0001>xx1xxxx", InstName.Vsra,        InstEmit32.Vsra,        OpCode32SimdShImm.Create);
-            SetA32("111101001x00xxxxxxxx<<00xxxxxxxx", InstName.Vst1,        InstEmit32.Vst1,        OpCode32SimdMemSingle.Create);
-            SetA32("111101000x00xxxxxxxx0111xxxxxxxx", InstName.Vst1,        InstEmit32.Vst1,        OpCode32SimdMemPair.Create); // Regs = 1.
-            SetA32("111101000x00xxxxxxxx1010xxxxxxxx", InstName.Vst1,        InstEmit32.Vst1,        OpCode32SimdMemPair.Create); // Regs = 2.
-            SetA32("111101000x00xxxxxxxx0110xxxxxxxx", InstName.Vst1,        InstEmit32.Vst1,        OpCode32SimdMemPair.Create); // Regs = 3.
-            SetA32("111101000x00xxxxxxxx0010xxxxxxxx", InstName.Vst1,        InstEmit32.Vst1,        OpCode32SimdMemPair.Create); // Regs = 4.
-            SetA32("111101001x00xxxxxxxx<<01xxxxxxxx", InstName.Vst2,        InstEmit32.Vst2,        OpCode32SimdMemSingle.Create);
-            SetA32("111101000x00xxxxxxxx100xxxxxxxxx", InstName.Vst2,        InstEmit32.Vst2,        OpCode32SimdMemPair.Create); // Regs = 1, inc = 1/2 (itype).
-            SetA32("111101000x00xxxxxxxx0011xxxxxxxx", InstName.Vst2,        InstEmit32.Vst2,        OpCode32SimdMemPair.Create); // Regs = 2, inc = 2.
-            SetA32("111101001x00xxxxxxxx<<10xxxxxxxx", InstName.Vst3,        InstEmit32.Vst3,        OpCode32SimdMemSingle.Create);
-            SetA32("111101000x00xxxxxxxx010xxxxxxxxx", InstName.Vst3,        InstEmit32.Vst3,        OpCode32SimdMemPair.Create); // Inc = 1/2 (itype).
-            SetA32("111101001x00xxxxxxxx<<11xxxxxxxx", InstName.Vst4,        InstEmit32.Vst4,        OpCode32SimdMemSingle.Create);
-            SetA32("111101000x00xxxxxxxx000xxxxxxxxx", InstName.Vst4,        InstEmit32.Vst4,        OpCode32SimdMemPair.Create); // Inc = 1/2 (itype).
-            SetA32("<<<<11001x00xxxxxxxx1011xxxxxxx0", InstName.Vstm,        InstEmit32.Vstm,        OpCode32SimdMemMult.Create);
-            SetA32("<<<<11001x10xxxxxxxx1011xxxxxxx0", InstName.Vstm,        InstEmit32.Vstm,        OpCode32SimdMemMult.Create);
-            SetA32("<<<<11010x10xxxxxxxx1011xxxxxxx0", InstName.Vstm,        InstEmit32.Vstm,        OpCode32SimdMemMult.Create);
-            SetA32("<<<<11001x00xxxxxxxx1010xxxxxxxx", InstName.Vstm,        InstEmit32.Vstm,        OpCode32SimdMemMult.Create);
-            SetA32("<<<<11001x10xxxxxxxx1010xxxxxxxx", InstName.Vstm,        InstEmit32.Vstm,        OpCode32SimdMemMult.Create);
-            SetA32("<<<<11010x10xxxxxxxx1010xxxxxxxx", InstName.Vstm,        InstEmit32.Vstm,        OpCode32SimdMemMult.Create);
-            SetA32("<<<<1101xx00xxxxxxxx101xxxxxxxxx", InstName.Vstr,        InstEmit32.Vstr,        OpCode32SimdMemImm.Create);
-            SetA32("111100110xxxxxxxxxxx1000xxx0xxxx", InstName.Vsub,        InstEmit32.Vsub_I,      OpCode32SimdReg.Create);
-            SetA32("<<<<11100x11xxxxxxxx101xx1x0xxxx", InstName.Vsub,        InstEmit32.Vsub_S,      OpCode32SimdRegS.Create);
-            SetA32("111100100x10xxxxxxxx1101xxx0xxxx", InstName.Vsub,        InstEmit32.Vsub_V,      OpCode32SimdReg.Create);
-            SetA32("1111001x1x<<xxxxxxxx0011x0x0xxxx", InstName.Vsubw,       InstEmit32.Vsubw_I,     OpCode32SimdRegWide.Create);
-            SetA32("111100111x11xxxxxxxx10xxxxx0xxxx", InstName.Vtbl,        InstEmit32.Vtbl,        OpCode32SimdTbl.Create);
-            SetA32("111100111x11<<10xxxx00001xx0xxxx", InstName.Vtrn,        InstEmit32.Vtrn,        OpCode32SimdCmpZ.Create);
-            SetA32("111100100x<<xxxxxxxx1000xxx1xxxx", InstName.Vtst,        InstEmit32.Vtst,        OpCode32SimdReg.Create);
-            SetA32("111100111x11<<10xxxx00010xx0xxxx", InstName.Vuzp,        InstEmit32.Vuzp,        OpCode32SimdCmpZ.Create);
-            SetA32("111100111x11<<10xxxx00011xx0xxxx", InstName.Vzip,        InstEmit32.Vzip,        OpCode32SimdCmpZ.Create);
+            // VFP
+            SetVfp("<<<<11101x110000xxxx101x11x0xxxx", InstName.Vabs,   InstEmit32.Vabs_S,   OpCode32SimdS.Create,           OpCode32SimdS.CreateT32);
+            SetVfp("<<<<11100x11xxxxxxxx101xx0x0xxxx", InstName.Vadd,   InstEmit32.Vadd_S,   OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+            SetVfp("<<<<11101x11010xxxxx101x01x0xxxx", InstName.Vcmp,   InstEmit32.Vcmp,     OpCode32SimdS.Create,           OpCode32SimdS.CreateT32);
+            SetVfp("<<<<11101x11010xxxxx101x11x0xxxx", InstName.Vcmpe,  InstEmit32.Vcmpe,    OpCode32SimdS.Create,           OpCode32SimdS.CreateT32);
+            SetVfp("<<<<11101x110111xxxx101x11x0xxxx", InstName.Vcvt,   InstEmit32.Vcvt_FD,  OpCode32SimdS.Create,           OpCode32SimdS.CreateT32); // FP 32 and 64, scalar.
+            SetVfp("<<<<11101x11110xxxxx101x11x0xxxx", InstName.Vcvt,   InstEmit32.Vcvt_FI,  OpCode32SimdCvtFI.Create,       OpCode32SimdCvtFI.CreateT32); // FP32 to int.
+            SetVfp("<<<<11101x111000xxxx101xx1x0xxxx", InstName.Vcvt,   InstEmit32.Vcvt_FI,  OpCode32SimdCvtFI.Create,       OpCode32SimdCvtFI.CreateT32); // Int to FP32.
+            SetVfp("111111101x1111xxxxxx101xx1x0xxxx", InstName.Vcvt,   InstEmit32.Vcvt_RM,  OpCode32SimdCvtFI.Create,       OpCode32SimdCvtFI.CreateT32); // The many FP32 to int encodings (fp).
+            SetVfp("<<<<11101x00xxxxxxxx101xx0x0xxxx", InstName.Vdiv,   InstEmit32.Vdiv_S,   OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+            SetVfp("<<<<11101xx0xxxxxxxx1011x0x10000", InstName.Vdup,   InstEmit32.Vdup,     OpCode32SimdDupGP.Create,       OpCode32SimdDupGP.CreateT32);
+            SetVfp("<<<<11101x10xxxxxxxx101xx0x0xxxx", InstName.Vfma,   InstEmit32.Vfma_S,   OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+            SetVfp("<<<<11101x10xxxxxxxx101xx1x0xxxx", InstName.Vfms,   InstEmit32.Vfms_S,   OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+            SetVfp("<<<<11101x01xxxxxxxx101xx1x0xxxx", InstName.Vfnma,  InstEmit32.Vfnma_S,  OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+            SetVfp("<<<<11101x01xxxxxxxx101xx0x0xxxx", InstName.Vfnms,  InstEmit32.Vfnms_S,  OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+            SetVfp("<<<<11001x01xxxxxxxx1011xxxxxxx0", InstName.Vldm,   InstEmit32.Vldm,     OpCode32SimdMemMult.Create,     OpCode32SimdMemMult.CreateT32);
+            SetVfp("<<<<11001x11xxxxxxxx1011xxxxxxx0", InstName.Vldm,   InstEmit32.Vldm,     OpCode32SimdMemMult.Create,     OpCode32SimdMemMult.CreateT32);
+            SetVfp("<<<<11010x11xxxxxxxx1011xxxxxxx0", InstName.Vldm,   InstEmit32.Vldm,     OpCode32SimdMemMult.Create,     OpCode32SimdMemMult.CreateT32);
+            SetVfp("<<<<11001x01xxxxxxxx1010xxxxxxxx", InstName.Vldm,   InstEmit32.Vldm,     OpCode32SimdMemMult.Create,     OpCode32SimdMemMult.CreateT32);
+            SetVfp("<<<<11001x11xxxxxxxx1010xxxxxxxx", InstName.Vldm,   InstEmit32.Vldm,     OpCode32SimdMemMult.Create,     OpCode32SimdMemMult.CreateT32);
+            SetVfp("<<<<11010x11xxxxxxxx1010xxxxxxxx", InstName.Vldm,   InstEmit32.Vldm,     OpCode32SimdMemMult.Create,     OpCode32SimdMemMult.CreateT32);
+            SetVfp("<<<<1101xx01xxxxxxxx101xxxxxxxxx", InstName.Vldr,   InstEmit32.Vldr,     OpCode32SimdMemImm.Create,      OpCode32SimdMemImm.CreateT32);
+            SetVfp("111111101x00xxxxxxxx10>>x0x0xxxx", InstName.Vmaxnm, InstEmit32.Vmaxnm_S, OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+            SetVfp("111111101x00xxxxxxxx10>>x1x0xxxx", InstName.Vminnm, InstEmit32.Vminnm_S, OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+            SetVfp("<<<<11100x00xxxxxxxx101xx0x0xxxx", InstName.Vmla,   InstEmit32.Vmla_S,   OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+            SetVfp("<<<<11100x00xxxxxxxx101xx1x0xxxx", InstName.Vmls,   InstEmit32.Vmls_S,   OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+            SetVfp("<<<<11100xx0xxxxxxxx1011xxx10000", InstName.Vmov,   InstEmit32.Vmov_G1,  OpCode32SimdMovGpElem.Create,   OpCode32SimdMovGpElem.CreateT32); // From gen purpose.
+            SetVfp("<<<<1110xxx1xxxxxxxx1011xxx10000", InstName.Vmov,   InstEmit32.Vmov_G1,  OpCode32SimdMovGpElem.Create,   OpCode32SimdMovGpElem.CreateT32); // To gen purpose.
+            SetVfp("<<<<1100010xxxxxxxxx101000x1xxxx", InstName.Vmov,   InstEmit32.Vmov_G2,  OpCode32SimdMovGpDouble.Create, OpCode32SimdMovGpDouble.CreateT32); // To/from gen purpose x2 and single precision x2.
+            SetVfp("<<<<1100010xxxxxxxxx101100x1xxxx", InstName.Vmov,   InstEmit32.Vmov_GD,  OpCode32SimdMovGpDouble.Create, OpCode32SimdMovGpDouble.CreateT32); // To/from gen purpose x2 and double precision.
+            SetVfp("<<<<1110000xxxxxxxxx1010x0010000", InstName.Vmov,   InstEmit32.Vmov_GS,  OpCode32SimdMovGp.Create,       OpCode32SimdMovGp.CreateT32); // To/from gen purpose and single precision.
+            SetVfp("<<<<11101x11xxxxxxxx101x0000xxxx", InstName.Vmov,   InstEmit32.Vmov_I,   OpCode32SimdImm44.Create,       OpCode32SimdImm44.CreateT32); // Scalar f16/32/64 based on size 01 10 11.
+            SetVfp("<<<<11101x110000xxxx101x01x0xxxx", InstName.Vmov,   InstEmit32.Vmov_S,   OpCode32SimdS.Create,           OpCode32SimdS.CreateT32);
+            SetVfp("<<<<11101111xxxxxxxx101000010000", InstName.Vmrs,   InstEmit32.Vmrs,     OpCode32SimdSpecial.Create,     OpCode32SimdSpecial.CreateT32);
+            SetVfp("<<<<11101110xxxxxxxx101000010000", InstName.Vmsr,   InstEmit32.Vmsr,     OpCode32SimdSpecial.Create,     OpCode32SimdSpecial.CreateT32);
+            SetVfp("<<<<11100x10xxxxxxxx101xx0x0xxxx", InstName.Vmul,   InstEmit32.Vmul_S,   OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+            SetVfp("<<<<11101x110001xxxx101x01x0xxxx", InstName.Vneg,   InstEmit32.Vneg_S,   OpCode32SimdS.Create,           OpCode32SimdS.CreateT32);
+            SetVfp("<<<<11100x01xxxxxxxx101xx1x0xxxx", InstName.Vnmla,  InstEmit32.Vnmla_S,  OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+            SetVfp("<<<<11100x01xxxxxxxx101xx0x0xxxx", InstName.Vnmls,  InstEmit32.Vnmls_S,  OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+            SetVfp("<<<<11100x10xxxxxxxx101xx1x0xxxx", InstName.Vnmul,  InstEmit32.Vnmul_S,  OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+            SetVfp("111111101x1110xxxxxx101x01x0xxxx", InstName.Vrint,  InstEmit32.Vrint_RM, OpCode32SimdS.Create,           OpCode32SimdS.CreateT32);
+            SetVfp("<<<<11101x110110xxxx101x11x0xxxx", InstName.Vrint,  InstEmit32.Vrint_Z,  OpCode32SimdS.Create,           OpCode32SimdS.CreateT32);
+            SetVfp("<<<<11101x110111xxxx101x01x0xxxx", InstName.Vrintx, InstEmit32.Vrintx_S, OpCode32SimdS.Create,           OpCode32SimdS.CreateT32);
+            SetVfp("<<<<11101x110001xxxx101x11x0xxxx", InstName.Vsqrt,  InstEmit32.Vsqrt_S,  OpCode32SimdS.Create,           OpCode32SimdS.CreateT32);
+            SetVfp("111111100xxxxxxxxxxx101xx0x0xxxx", InstName.Vsel,   InstEmit32.Vsel,     OpCode32SimdSel.Create,         OpCode32SimdSel.CreateT32);
+            SetVfp("<<<<11001x00xxxxxxxx1011xxxxxxx0", InstName.Vstm,   InstEmit32.Vstm,     OpCode32SimdMemMult.Create,     OpCode32SimdMemMult.CreateT32);
+            SetVfp("<<<<11001x10xxxxxxxx1011xxxxxxx0", InstName.Vstm,   InstEmit32.Vstm,     OpCode32SimdMemMult.Create,     OpCode32SimdMemMult.CreateT32);
+            SetVfp("<<<<11010x10xxxxxxxx1011xxxxxxx0", InstName.Vstm,   InstEmit32.Vstm,     OpCode32SimdMemMult.Create,     OpCode32SimdMemMult.CreateT32);
+            SetVfp("<<<<11001x00xxxxxxxx1010xxxxxxxx", InstName.Vstm,   InstEmit32.Vstm,     OpCode32SimdMemMult.Create,     OpCode32SimdMemMult.CreateT32);
+            SetVfp("<<<<11001x10xxxxxxxx1010xxxxxxxx", InstName.Vstm,   InstEmit32.Vstm,     OpCode32SimdMemMult.Create,     OpCode32SimdMemMult.CreateT32);
+            SetVfp("<<<<11010x10xxxxxxxx1010xxxxxxxx", InstName.Vstm,   InstEmit32.Vstm,     OpCode32SimdMemMult.Create,     OpCode32SimdMemMult.CreateT32);
+            SetVfp("<<<<1101xx00xxxxxxxx101xxxxxxxxx", InstName.Vstr,   InstEmit32.Vstr,     OpCode32SimdMemImm.Create,      OpCode32SimdMemImm.CreateT32);
+            SetVfp("<<<<11100x11xxxxxxxx101xx1x0xxxx", InstName.Vsub,   InstEmit32.Vsub_S,   OpCode32SimdRegS.Create,        OpCode32SimdRegS.CreateT32);
+
+            // ASIMD
+            SetAsimd("111100111x110000xxx0001101x0xxx0", InstName.Aesd_V,      InstEmit32.Aesd_V,      OpCode32Simd.Create,            OpCode32Simd.CreateT32);
+            SetAsimd("111100111x110000xxx0001100x0xxx0", InstName.Aese_V,      InstEmit32.Aese_V,      OpCode32Simd.Create,            OpCode32Simd.CreateT32);
+            SetAsimd("111100111x110000xxx0001111x0xxx0", InstName.Aesimc_V,    InstEmit32.Aesimc_V,    OpCode32Simd.Create,            OpCode32Simd.CreateT32);
+            SetAsimd("111100111x110000xxx0001110x0xxx0", InstName.Aesmc_V,     InstEmit32.Aesmc_V,     OpCode32Simd.Create,            OpCode32Simd.CreateT32);
+            SetAsimd("111100110x00xxx0xxx01100x1x0xxx0", InstName.Sha256h_V,   InstEmit32.Sha256h_V,   OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100110x01xxx0xxx01100x1x0xxx0", InstName.Sha256h2_V,  InstEmit32.Sha256h2_V,  OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100111x111010xxx0001111x0xxx0", InstName.Sha256su0_V, InstEmit32.Sha256su0_V, OpCode32Simd.Create,            OpCode32Simd.CreateT32);
+            SetAsimd("111100110x10xxx0xxx01100x1x0xxx0", InstName.Sha256su1_V, InstEmit32.Sha256su1_V, OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("1111001x0x<<xxxxxxxx0111xxx0xxxx", InstName.Vabd,        InstEmit32.Vabd_I,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("1111001x1x<<xxxxxxxx0111x0x0xxxx", InstName.Vabdl,       InstEmit32.Vabdl_I,     OpCode32SimdRegLong.Create,     OpCode32SimdRegLong.CreateT32);
+            SetAsimd("111100111x11<<01xxxx00110xx0xxxx", InstName.Vabs,        InstEmit32.Vabs_V,      OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("111100111x111001xxxx01110xx0xxxx", InstName.Vabs,        InstEmit32.Vabs_V,      OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("111100100xxxxxxxxxxx1000xxx0xxxx", InstName.Vadd,        InstEmit32.Vadd_I,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100100x00xxxxxxxx1101xxx0xxxx", InstName.Vadd,        InstEmit32.Vadd_V,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("1111001x1x<<xxxxxxx00000x0x0xxxx", InstName.Vaddl,       InstEmit32.Vaddl_I,     OpCode32SimdRegLong.Create,     OpCode32SimdRegLong.CreateT32);
+            SetAsimd("1111001x1x<<xxxxxxx00001x0x0xxxx", InstName.Vaddw,       InstEmit32.Vaddw_I,     OpCode32SimdRegWide.Create,     OpCode32SimdRegWide.CreateT32);
+            SetAsimd("111100100x00xxxxxxxx0001xxx1xxxx", InstName.Vand,        InstEmit32.Vand_I,      OpCode32SimdBinary.Create,      OpCode32SimdBinary.CreateT32);
+            SetAsimd("111100100x01xxxxxxxx0001xxx1xxxx", InstName.Vbic,        InstEmit32.Vbic_I,      OpCode32SimdBinary.Create,      OpCode32SimdBinary.CreateT32);
+            SetAsimd("1111001x1x000xxxxxxx<<x10x11xxxx", InstName.Vbic,        InstEmit32.Vbic_II,     OpCode32SimdImm.Create,         OpCode32SimdImm.CreateT32);
+            SetAsimd("111100110x11xxxxxxxx0001xxx1xxxx", InstName.Vbif,        InstEmit32.Vbif,        OpCode32SimdBinary.Create,      OpCode32SimdBinary.CreateT32);
+            SetAsimd("111100110x10xxxxxxxx0001xxx1xxxx", InstName.Vbit,        InstEmit32.Vbit,        OpCode32SimdBinary.Create,      OpCode32SimdBinary.CreateT32);
+            SetAsimd("111100110x01xxxxxxxx0001xxx1xxxx", InstName.Vbsl,        InstEmit32.Vbsl,        OpCode32SimdBinary.Create,      OpCode32SimdBinary.CreateT32);
+            SetAsimd("111100110x<<xxxxxxxx1000xxx1xxxx", InstName.Vceq,        InstEmit32.Vceq_I,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100100x00xxxxxxxx1110xxx0xxxx", InstName.Vceq,        InstEmit32.Vceq_V,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100111x11xx01xxxx0x010xx0xxxx", InstName.Vceq,        InstEmit32.Vceq_Z,      OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("1111001x0x<<xxxxxxxx0011xxx1xxxx", InstName.Vcge,        InstEmit32.Vcge_I,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100110x00xxxxxxxx1110xxx0xxxx", InstName.Vcge,        InstEmit32.Vcge_V,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100111x11xx01xxxx0x001xx0xxxx", InstName.Vcge,        InstEmit32.Vcge_Z,      OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("1111001x0x<<xxxxxxxx0011xxx0xxxx", InstName.Vcgt,        InstEmit32.Vcgt_I,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100110x10xxxxxxxx1110xxx0xxxx", InstName.Vcgt,        InstEmit32.Vcgt_V,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100111x11xx01xxxx0x000xx0xxxx", InstName.Vcgt,        InstEmit32.Vcgt_Z,      OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("111100111x11xx01xxxx0x011xx0xxxx", InstName.Vcle,        InstEmit32.Vcle_Z,      OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("111100111x11xx01xxxx0x100xx0xxxx", InstName.Vclt,        InstEmit32.Vclt_Z,      OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("111100111x110000xxxx01010xx0xxxx", InstName.Vcnt,        InstEmit32.Vcnt,        OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("111100111x111011xxxx011xxxx0xxxx", InstName.Vcvt,        InstEmit32.Vcvt_V,      OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32); // FP and integer, vector.
+            SetAsimd("111100111x11xxxxxxxx11000xx0xxxx", InstName.Vdup,        InstEmit32.Vdup_1,      OpCode32SimdDupElem.Create,     OpCode32SimdDupElem.CreateT32);
+            SetAsimd("111100110x00xxxxxxxx0001xxx1xxxx", InstName.Veor,        InstEmit32.Veor_I,      OpCode32SimdBinary.Create,      OpCode32SimdBinary.CreateT32);
+            SetAsimd("111100101x11xxxxxxxxxxxxxxx0xxxx", InstName.Vext,        InstEmit32.Vext,        OpCode32SimdExt.Create,         OpCode32SimdExt.CreateT32);
+            SetAsimd("111100100x00xxxxxxxx1100xxx1xxxx", InstName.Vfma,        InstEmit32.Vfma_V,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100100x10xxxxxxxx1100xxx1xxxx", InstName.Vfms,        InstEmit32.Vfms_V,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("1111001x0x<<xxxxxxxx0000xxx0xxxx", InstName.Vhadd,       InstEmit32.Vhadd,       OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111101001x10xxxxxxxx0000xxx0xxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x10xxxxxxxx0100xx0xxxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x10xxxxxxxx1000x000xxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x10xxxxxxxx1000x011xxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x10xxxxxxxx110000x0xxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x10xxxxxxxx110001xxxxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x10xxxxxxxx110010xxxxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101000x10xxxxxxxx0111xx0xxxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Regs = 1.
+            SetAsimd("111101000x10xxxxxxxx1010xx<<xxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Regs = 2.
+            SetAsimd("111101000x10xxxxxxxx0110xx0xxxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Regs = 3.
+            SetAsimd("111101000x10xxxxxxxx0010xxxxxxxx", InstName.Vld1,        InstEmit32.Vld1,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Regs = 4.
+            SetAsimd("111101001x10xxxxxxxx0x01xxxxxxxx", InstName.Vld2,        InstEmit32.Vld2,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x10xxxxxxxx1001xx0xxxxx", InstName.Vld2,        InstEmit32.Vld2,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x10xxxxxxxx1101<<xxxxxx", InstName.Vld2,        InstEmit32.Vld2,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101000x10xxxxxxxx100x<<0xxxxx", InstName.Vld2,        InstEmit32.Vld2,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Regs = 1, inc = 1/2 (itype).
+            SetAsimd("111101000x10xxxxxxxx100x<<10xxxx", InstName.Vld2,        InstEmit32.Vld2,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Regs = 1, inc = 1/2 (itype).
+            SetAsimd("111101000x10xxxxxxxx0011<<xxxxxx", InstName.Vld2,        InstEmit32.Vld2,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Regs = 2, inc = 2.
+            SetAsimd("111101001x10xxxxxxxx0x10xxx0xxxx", InstName.Vld3,        InstEmit32.Vld3,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x10xxxxxxxx1010xx00xxxx", InstName.Vld3,        InstEmit32.Vld3,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x10xxxxxxxx1110<<x0xxxx", InstName.Vld3,        InstEmit32.Vld3,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101000x10xxxxxxxx010x<<0xxxxx", InstName.Vld3,        InstEmit32.Vld3,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Inc = 1/2 (itype).
+            SetAsimd("111101001x10xxxxxxxx0x11xxxxxxxx", InstName.Vld4,        InstEmit32.Vld4,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x10xxxxxxxx1011xx<<xxxx", InstName.Vld4,        InstEmit32.Vld4,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x10xxxxxxxx1111<<x>xxxx", InstName.Vld4,        InstEmit32.Vld4,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101000x10xxxxxxxx000x<<xxxxxx", InstName.Vld4,        InstEmit32.Vld4,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Inc = 1/2 (itype).
+            SetAsimd("1111001x0x<<xxxxxxxx0110xxx0xxxx", InstName.Vmax,        InstEmit32.Vmax_I,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100100x00xxxxxxxx1111xxx0xxxx", InstName.Vmax,        InstEmit32.Vmax_V,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("1111001x0x<<xxxxxxxx0110xxx1xxxx", InstName.Vmin,        InstEmit32.Vmin_I,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100100x10xxxxxxxx1111xxx0xxxx", InstName.Vmin,        InstEmit32.Vmin_V,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100110x0xxxxxxxxx1111xxx1xxxx", InstName.Vmaxnm,      InstEmit32.Vmaxnm_V,    OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100110x1xxxxxxxxx1111xxx1xxxx", InstName.Vminnm,      InstEmit32.Vminnm_V,    OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("1111001x1x<<xxxxxxxx000xx1x0xxxx", InstName.Vmla,        InstEmit32.Vmla_1,      OpCode32SimdRegElem.Create,     OpCode32SimdRegElem.CreateT32);
+            SetAsimd("111100100xxxxxxxxxxx1001xxx0xxxx", InstName.Vmla,        InstEmit32.Vmla_I,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100100x00xxxxxxxx1101xxx1xxxx", InstName.Vmla,        InstEmit32.Vmla_V,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("1111001x1x<<xxxxxxx01000x0x0xxxx", InstName.Vmlal,       InstEmit32.Vmlal_I,     OpCode32SimdRegLong.Create,     OpCode32SimdRegLong.CreateT32);
+            SetAsimd("1111001x1x<<xxxxxxxx010xx1x0xxxx", InstName.Vmls,        InstEmit32.Vmls_1,      OpCode32SimdRegElem.Create,     OpCode32SimdRegElem.CreateT32);
+            SetAsimd("111100100x10xxxxxxxx1101xxx1xxxx", InstName.Vmls,        InstEmit32.Vmls_V,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100110xxxxxxxxxxx1001xxx0xxxx", InstName.Vmls,        InstEmit32.Vmls_I,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("1111001x1x<<xxxxxxx01010x0x0xxxx", InstName.Vmlsl,       InstEmit32.Vmlsl_I,     OpCode32SimdRegLong.Create,     OpCode32SimdRegLong.CreateT32);
+            SetAsimd("1111001x1x000xxxxxxx0xx00x01xxxx", InstName.Vmov,        InstEmit32.Vmov_I,      OpCode32SimdImm.Create,         OpCode32SimdImm.CreateT32); // D/Q vector I32.
+            SetAsimd("1111001x1x000xxxxxxx10x00x01xxxx", InstName.Vmov,        InstEmit32.Vmov_I,      OpCode32SimdImm.Create,         OpCode32SimdImm.CreateT32); // D/Q I16.
+            SetAsimd("1111001x1x000xxxxxxx11xx0x01xxxx", InstName.Vmov,        InstEmit32.Vmov_I,      OpCode32SimdImm.Create,         OpCode32SimdImm.CreateT32); // D/Q (dt - from cmode).
+            SetAsimd("1111001x1x000xxxxxxx11100x11xxxx", InstName.Vmov,        InstEmit32.Vmov_I,      OpCode32SimdImm.Create,         OpCode32SimdImm.CreateT32); // D/Q I64.
+            SetAsimd("1111001x1x001000xxx0101000x1xxxx", InstName.Vmovl,       InstEmit32.Vmovl,       OpCode32SimdLong.Create,        OpCode32SimdLong.CreateT32);
+            SetAsimd("1111001x1x010000xxx0101000x1xxxx", InstName.Vmovl,       InstEmit32.Vmovl,       OpCode32SimdLong.Create,        OpCode32SimdLong.CreateT32);
+            SetAsimd("1111001x1x100000xxx0101000x1xxxx", InstName.Vmovl,       InstEmit32.Vmovl,       OpCode32SimdLong.Create,        OpCode32SimdLong.CreateT32);
+            SetAsimd("111100111x11<<10xxxx001000x0xxx0", InstName.Vmovn,       InstEmit32.Vmovn,       OpCode32SimdMovn.Create,        OpCode32SimdMovn.CreateT32);
+            SetAsimd("1111001x1x<<xxxxxxxx100xx1x0xxxx", InstName.Vmul,        InstEmit32.Vmul_1,      OpCode32SimdRegElem.Create,     OpCode32SimdRegElem.CreateT32);
+            SetAsimd("111100100x<<xxxxxxxx1001xxx1xxxx", InstName.Vmul,        InstEmit32.Vmul_I,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100110x00xxxxxxxx1001xxx1xxxx", InstName.Vmul,        InstEmit32.Vmul_I,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100110x00xxxxxxxx1101xxx1xxxx", InstName.Vmul,        InstEmit32.Vmul_V,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("1111001x1x<<xxxxxxx01010x1x0xxxx", InstName.Vmull,       InstEmit32.Vmull_1,     OpCode32SimdRegElemLong.Create, OpCode32SimdRegElemLong.CreateT32);
+            SetAsimd("1111001x1x<<xxxxxxx01100x0x0xxxx", InstName.Vmull,       InstEmit32.Vmull_I,     OpCode32SimdRegLong.Create,     OpCode32SimdRegLong.CreateT32);
+            SetAsimd("111100101xx0xxxxxxx01110x0x0xxxx", InstName.Vmull,       InstEmit32.Vmull_I,     OpCode32SimdRegLong.Create,     OpCode32SimdRegLong.CreateT32); // P8/P64
+            SetAsimd("111100111x110000xxxx01011xx0xxxx", InstName.Vmvn,        InstEmit32.Vmvn_I,      OpCode32SimdBinary.Create,      OpCode32SimdBinary.CreateT32);
+            SetAsimd("1111001x1x000xxxxxxx0xx00x11xxxx", InstName.Vmvn,        InstEmit32.Vmvn_II,     OpCode32SimdImm.Create,         OpCode32SimdImm.CreateT32); // D/Q vector I32.
+            SetAsimd("1111001x1x000xxxxxxx10x00x11xxxx", InstName.Vmvn,        InstEmit32.Vmvn_II,     OpCode32SimdImm.Create,         OpCode32SimdImm.CreateT32);
+            SetAsimd("1111001x1x000xxxxxxx110x0x11xxxx", InstName.Vmvn,        InstEmit32.Vmvn_II,     OpCode32SimdImm.Create,         OpCode32SimdImm.CreateT32);
+            SetAsimd("111100111x11<<01xxxx00111xx0xxxx", InstName.Vneg,        InstEmit32.Vneg_V,      OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("111100111x111001xxxx01111xx0xxxx", InstName.Vneg,        InstEmit32.Vneg_V,      OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("111100100x11xxxxxxxx0001xxx1xxxx", InstName.Vorn,        InstEmit32.Vorn_I,      OpCode32SimdBinary.Create,      OpCode32SimdBinary.CreateT32);
+            SetAsimd("111100100x10xxxxxxxx0001xxx1xxxx", InstName.Vorr,        InstEmit32.Vorr_I,      OpCode32SimdBinary.Create,      OpCode32SimdBinary.CreateT32);
+            SetAsimd("1111001x1x000xxxxxxx<<x10x01xxxx", InstName.Vorr,        InstEmit32.Vorr_II,     OpCode32SimdImm.Create,         OpCode32SimdImm.CreateT32);
+            SetAsimd("111100100x<<xxxxxxxx1011x0x1xxxx", InstName.Vpadd,       InstEmit32.Vpadd_I,     OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100110x00xxxxxxxx1101x0x0xxxx", InstName.Vpadd,       InstEmit32.Vpadd_V,     OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100111x11<<00xxxx0010xxx0xxxx", InstName.Vpaddl,      InstEmit32.Vpaddl,      OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("1111001x0x<<xxxxxxxx1010x0x0xxxx", InstName.Vpmax,       InstEmit32.Vpmax_I,     OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100110x00xxxxxxxx1111x0x0xxxx", InstName.Vpmax,       InstEmit32.Vpmax_V,     OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("1111001x0x<<xxxxxxxx1010x0x1xxxx", InstName.Vpmin,       InstEmit32.Vpmin_I,     OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100110x10xxxxxxxx1111x0x0xxxx", InstName.Vpmin,       InstEmit32.Vpmin_V,     OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("1111001x0xxxxxxxxxxx0000xxx1xxxx", InstName.Vqadd,       InstEmit32.Vqadd,       OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100100x01xxxxxxxx1011xxx0xxxx", InstName.Vqdmulh,     InstEmit32.Vqdmulh,     OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100100x10xxxxxxxx1011xxx0xxxx", InstName.Vqdmulh,     InstEmit32.Vqdmulh,     OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100111x11<<10xxxx00101xx0xxx0", InstName.Vqmovn,      InstEmit32.Vqmovn,      OpCode32SimdMovn.Create,        OpCode32SimdMovn.CreateT32);
+            SetAsimd("111100111x11<<10xxxx001001x0xxx0", InstName.Vqmovun,     InstEmit32.Vqmovun,     OpCode32SimdMovn.Create,        OpCode32SimdMovn.CreateT32);
+            SetAsimd("1111001x1x>>>xxxxxxx100101x1xxx0", InstName.Vqrshrn,     InstEmit32.Vqrshrn,     OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32);
+            SetAsimd("111100111x>>>xxxxxxx100001x1xxx0", InstName.Vqrshrun,    InstEmit32.Vqrshrun,    OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32);
+            SetAsimd("1111001x1x>>>xxxxxxx100100x1xxx0", InstName.Vqshrn,      InstEmit32.Vqshrn,      OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32);
+            SetAsimd("111100111x>>>xxxxxxx100000x1xxx0", InstName.Vqshrun,     InstEmit32.Vqshrun,     OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32);
+            SetAsimd("1111001x0xxxxxxxxxxx0010xxx1xxxx", InstName.Vqsub,       InstEmit32.Vqsub,       OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100111x111011xxxx010x0xx0xxxx", InstName.Vrecpe,      InstEmit32.Vrecpe,      OpCode32SimdSqrte.Create,       OpCode32SimdSqrte.CreateT32);
+            SetAsimd("111100100x00xxxxxxxx1111xxx1xxxx", InstName.Vrecps,      InstEmit32.Vrecps,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100111x11xx00xxxx000<<xx0xxxx", InstName.Vrev,        InstEmit32.Vrev,        OpCode32SimdRev.Create,         OpCode32SimdRev.CreateT32);
+            SetAsimd("1111001x0x<<xxxxxxxx0001xxx0xxxx", InstName.Vrhadd,      InstEmit32.Vrhadd,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100111x111010xxxx01010xx0xxxx", InstName.Vrinta,      InstEmit32.Vrinta_V,    OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("111100111x111010xxxx01101xx0xxxx", InstName.Vrintm,      InstEmit32.Vrintm_V,    OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("111100111x111010xxxx01000xx0xxxx", InstName.Vrintn,      InstEmit32.Vrintn_V,    OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("111100111x111010xxxx01111xx0xxxx", InstName.Vrintp,      InstEmit32.Vrintp_V,    OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("1111001x1x>>>xxxxxxx0010>xx1xxxx", InstName.Vrshr,       InstEmit32.Vrshr,       OpCode32SimdShImm.Create,       OpCode32SimdShImm.CreateT32);
+            SetAsimd("111100101x>>>xxxxxxx100001x1xxx0", InstName.Vrshrn,      InstEmit32.Vrshrn,      OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32);
+            SetAsimd("111100111x111011xxxx010x1xx0xxxx", InstName.Vrsqrte,     InstEmit32.Vrsqrte,     OpCode32SimdSqrte.Create,       OpCode32SimdSqrte.CreateT32);
+            SetAsimd("111100100x10xxxxxxxx1111xxx1xxxx", InstName.Vrsqrts,     InstEmit32.Vrsqrts,     OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("1111001x1x>>>xxxxxxx0011>xx1xxxx", InstName.Vrsra,       InstEmit32.Vrsra,       OpCode32SimdShImm.Create,       OpCode32SimdShImm.CreateT32);
+            SetAsimd("111100101x>>>xxxxxxx0101>xx1xxxx", InstName.Vshl,        InstEmit32.Vshl,        OpCode32SimdShImm.Create,       OpCode32SimdShImm.CreateT32);
+            SetAsimd("1111001x0xxxxxxxxxxx0100xxx0xxxx", InstName.Vshl,        InstEmit32.Vshl_I,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("1111001x1x>>>xxxxxxx101000x1xxxx", InstName.Vshll,       InstEmit32.Vshll,       OpCode32SimdShImmLong.Create,   OpCode32SimdShImmLong.CreateT32); // A1 encoding.
+            SetAsimd("1111001x1x>>>xxxxxxx0000>xx1xxxx", InstName.Vshr,        InstEmit32.Vshr,        OpCode32SimdShImm.Create,       OpCode32SimdShImm.CreateT32);
+            SetAsimd("111100101x>>>xxxxxxx100000x1xxx0", InstName.Vshrn,       InstEmit32.Vshrn,       OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32);
+            SetAsimd("1111001x1x>>>xxxxxxx0001>xx1xxxx", InstName.Vsra,        InstEmit32.Vsra,        OpCode32SimdShImm.Create,       OpCode32SimdShImm.CreateT32);
+            SetAsimd("111101001x00xxxxxxxx0000xxx0xxxx", InstName.Vst1,        InstEmit32.Vst1,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x00xxxxxxxx0100xx0xxxxx", InstName.Vst1,        InstEmit32.Vst1,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x00xxxxxxxx1000x000xxxx", InstName.Vst1,        InstEmit32.Vst1,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x00xxxxxxxx1000x011xxxx", InstName.Vst1,        InstEmit32.Vst1,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101000x00xxxxxxxx0111xx0xxxxx", InstName.Vst1,        InstEmit32.Vst1,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Regs = 1.
+            SetAsimd("111101000x00xxxxxxxx1010xx<<xxxx", InstName.Vst1,        InstEmit32.Vst1,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Regs = 2.
+            SetAsimd("111101000x00xxxxxxxx0110xx0xxxxx", InstName.Vst1,        InstEmit32.Vst1,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Regs = 3.
+            SetAsimd("111101000x00xxxxxxxx0010xxxxxxxx", InstName.Vst1,        InstEmit32.Vst1,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Regs = 4.
+            SetAsimd("111101001x00xxxxxxxx0x01xxxxxxxx", InstName.Vst2,        InstEmit32.Vst2,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x00xxxxxxxx1001xx0xxxxx", InstName.Vst2,        InstEmit32.Vst2,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101000x00xxxxxxxx100x<<0xxxxx", InstName.Vst2,        InstEmit32.Vst2,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Regs = 1, inc = 1/2 (itype).
+            SetAsimd("111101000x00xxxxxxxx100x<<10xxxx", InstName.Vst2,        InstEmit32.Vst2,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Regs = 1, inc = 1/2 (itype).
+            SetAsimd("111101000x00xxxxxxxx0011<<xxxxxx", InstName.Vst2,        InstEmit32.Vst2,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Regs = 2, inc = 2.
+            SetAsimd("111101001x00xxxxxxxx0x10xxx0xxxx", InstName.Vst3,        InstEmit32.Vst3,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x00xxxxxxxx1010xx00xxxx", InstName.Vst3,        InstEmit32.Vst3,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101000x00xxxxxxxx010x<<0xxxxx", InstName.Vst3,        InstEmit32.Vst3,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Inc = 1/2 (itype).
+            SetAsimd("111101001x00xxxxxxxx0x11xxxxxxxx", InstName.Vst4,        InstEmit32.Vst4,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101001x00xxxxxxxx1011xx<<xxxx", InstName.Vst4,        InstEmit32.Vst4,        OpCode32SimdMemSingle.Create,   OpCode32SimdMemSingle.CreateT32);
+            SetAsimd("111101000x00xxxxxxxx000x<<xxxxxx", InstName.Vst4,        InstEmit32.Vst4,        OpCode32SimdMemPair.Create,     OpCode32SimdMemPair.CreateT32); // Inc = 1/2 (itype).
+            SetAsimd("111100110xxxxxxxxxxx1000xxx0xxxx", InstName.Vsub,        InstEmit32.Vsub_I,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100100x10xxxxxxxx1101xxx0xxxx", InstName.Vsub,        InstEmit32.Vsub_V,      OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("1111001x1x<<xxxxxxx00010x0x0xxxx", InstName.Vsubl,       InstEmit32.Vsubl_I,     OpCode32SimdRegLong.Create,     OpCode32SimdRegLong.CreateT32);
+            SetAsimd("1111001x1x<<xxxxxxx00011x0x0xxxx", InstName.Vsubw,       InstEmit32.Vsubw_I,     OpCode32SimdRegWide.Create,     OpCode32SimdRegWide.CreateT32);
+            SetAsimd("111100111x11xxxxxxxx10xxxxx0xxxx", InstName.Vtbl,        InstEmit32.Vtbl,        OpCode32SimdTbl.Create,         OpCode32SimdTbl.CreateT32);
+            SetAsimd("111100111x11<<10xxxx00001xx0xxxx", InstName.Vtrn,        InstEmit32.Vtrn,        OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("111100100x<<xxxxxxxx1000xxx1xxxx", InstName.Vtst,        InstEmit32.Vtst,        OpCode32SimdReg.Create,         OpCode32SimdReg.CreateT32);
+            SetAsimd("111100111x11<<10xxxx00010xx0xxxx", InstName.Vuzp,        InstEmit32.Vuzp,        OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
+            SetAsimd("111100111x11<<10xxxx00011xx0xxxx", InstName.Vzip,        InstEmit32.Vzip,        OpCode32SimdCmpZ.Create,        OpCode32SimdCmpZ.CreateT32);
 #endregion

 #region "OpCode Table (AArch32, T16)"
@@ -1008,7 +1052,7 @@ namespace ARMeilleure.Decoders
            SetT16("01000101xxxxxxxx", InstName.Cmp,    InstEmit32.Cmp,     OpCodeT16AluRegHigh.Create);
            SetT16("01000110xxxxxxxx", InstName.Mov,    InstEmit32.Mov,     OpCodeT16AluRegHigh.Create);
            SetT16("010001110xxxx000", InstName.Bx,     InstEmit32.Bx,      OpCodeT16BReg.Create);
-            SetT16("010001111xxxx000", InstName.Blx,    InstEmit32.Blx,     OpCodeT16BReg.Create);
+            SetT16("010001111xxxx000", InstName.Blx,    InstEmit32.Blxr,    OpCodeT16BReg.Create);
            SetT16("01001xxxxxxxxxxx", InstName.Ldr,    InstEmit32.Ldr,     OpCodeT16MemLit.Create);
            SetT16("0101000xxxxxxxxx", InstName.Str,    InstEmit32.Str,     OpCodeT16MemReg.Create);
            SetT16("0101001xxxxxxxxx", InstName.Strh,   InstEmit32.Strh,    OpCodeT16MemReg.Create);
@@ -1056,74 +1100,148 @@ namespace ARMeilleure.Decoders
            SetT32("11110x01010xxxxx0xxxxxxxxxxxxxxx", InstName.Adc,      InstEmit32.Adc,      OpCodeT32AluImm.Create);
            SetT32("11101011000<xxxx0xxx<<<<xxxxxxxx", InstName.Add,      InstEmit32.Add,      OpCodeT32AluRsImm.Create);
            SetT32("11110x01000<xxxx0xxx<<<<xxxxxxxx", InstName.Add,      InstEmit32.Add,      OpCodeT32AluImm.Create);
+            SetT32("11110x100000xxxx0xxxxxxxxxxxxxxx", InstName.Add,      InstEmit32.Add,      OpCodeT32AluImm12.Create);
            SetT32("11101010000<xxxx0xxx<<<<xxxxxxxx", InstName.And,      InstEmit32.And,      OpCodeT32AluRsImm.Create);
            SetT32("11110x00000<xxxx0xxx<<<<xxxxxxxx", InstName.And,      InstEmit32.And,      OpCodeT32AluImm.Create);
            SetT32("11110x<<<xxxxxxx10x0xxxxxxxxxxxx", InstName.B,        InstEmit32.B,        OpCodeT32BImm20.Create);
            SetT32("11110xxxxxxxxxxx10x1xxxxxxxxxxxx", InstName.B,        InstEmit32.B,        OpCodeT32BImm24.Create);
+            SetT32("11110011011011110xxxxxxxxx0xxxxx", InstName.Bfc,      InstEmit32.Bfc,      OpCodeT32AluBf.Create);
+            SetT32("111100110110<<<<0xxxxxxxxx0xxxxx", InstName.Bfi,      InstEmit32.Bfi,      OpCodeT32AluBf.Create);
            SetT32("11101010001xxxxx0xxxxxxxxxxxxxxx", InstName.Bic,      InstEmit32.Bic,      OpCodeT32AluRsImm.Create);
            SetT32("11110x00001xxxxx0xxxxxxxxxxxxxxx", InstName.Bic,      InstEmit32.Bic,      OpCodeT32AluImm.Create);
            SetT32("11110xxxxxxxxxxx11x1xxxxxxxxxxxx", InstName.Bl,       InstEmit32.Bl,       OpCodeT32BImm24.Create);
            SetT32("11110xxxxxxxxxxx11x0xxxxxxxxxxx0", InstName.Blx,      InstEmit32.Blx,      OpCodeT32BImm24.Create);
+            SetT32("111110101011xxxx1111xxxx1000xxxx", InstName.Clz,      InstEmit32.Clz,      OpCodeT32AluReg.Create);
            SetT32("111010110001xxxx0xxx1111xxxxxxxx", InstName.Cmn,      InstEmit32.Cmn,      OpCodeT32AluRsImm.Create);
            SetT32("11110x010001xxxx0xxx1111xxxxxxxx", InstName.Cmn,      InstEmit32.Cmn,      OpCodeT32AluImm.Create);
            SetT32("111010111011xxxx0xxx1111xxxxxxxx", InstName.Cmp,      InstEmit32.Cmp,      OpCodeT32AluRsImm.Create);
            SetT32("11110x011011xxxx0xxx1111xxxxxxxx", InstName.Cmp,      InstEmit32.Cmp,      OpCodeT32AluImm.Create);
            SetT32("11101010100<xxxx0xxx<<<<xxxxxxxx", InstName.Eor,      InstEmit32.Eor,      OpCodeT32AluRsImm.Create);
            SetT32("11110x00100<xxxx0xxx<<<<xxxxxxxx", InstName.Eor,      InstEmit32.Eor,      OpCodeT32AluImm.Create);
+            SetT32("111010001101xxxxxxxx111110101111", InstName.Lda,      InstEmit32.Lda,      OpCodeT32MemLdEx.Create);
+            SetT32("111010001101xxxxxxxx111110001111", InstName.Ldab,     InstEmit32.Ldab,     OpCodeT32MemLdEx.Create);
            SetT32("111010001101xxxxxxxx111111101111", InstName.Ldaex,    InstEmit32.Ldaex,    OpCodeT32MemLdEx.Create);
+            SetT32("111010001101xxxxxxxx111111001111", InstName.Ldaexb,   InstEmit32.Ldaexb,   OpCodeT32MemLdEx.Create);
+            SetT32("111010001101xxxxxxxxxxxx11111111", InstName.Ldaexd,   InstEmit32.Ldaexd,   OpCodeT32MemLdEx.Create);
+            SetT32("111010001101xxxxxxxx111111011111", InstName.Ldaexh,   InstEmit32.Ldaexh,   OpCodeT32MemLdEx.Create);
+            SetT32("111010001101xxxxxxxx111110011111", InstName.Ldah,     InstEmit32.Ldah,     OpCodeT32MemLdEx.Create);
            SetT32("1110100010x1xxxxxxxxxxxxxxxxxxxx", InstName.Ldm,      InstEmit32.Ldm,      OpCodeT32MemMult.Create);
            SetT32("1110100100x1xxxxxxxxxxxxxxxxxxxx", InstName.Ldm,      InstEmit32.Ldm,      OpCodeT32MemMult.Create);
-            SetT32("111110000101xxxx<<<<10x1xxxxxxxx", InstName.Ldr,      InstEmit32.Ldr,      OpCodeT32MemImm8.Create);
-            SetT32("111110000101xxxx<<<<1100xxxxxxxx", InstName.Ldr,      InstEmit32.Ldr,      OpCodeT32MemImm8.Create);
-            SetT32("111110000101xxxx<<<<11x1xxxxxxxx", InstName.Ldr,      InstEmit32.Ldr,      OpCodeT32MemImm8.Create);
+            SetT32("111110000101xxxxxxxx10x1xxxxxxxx", InstName.Ldr,      InstEmit32.Ldr,      OpCodeT32MemImm8.Create);
+            SetT32("111110000101xxxxxxxx1100xxxxxxxx", InstName.Ldr,      InstEmit32.Ldr,      OpCodeT32MemImm8.Create);
+            SetT32("111110000101xxxxxxxx11x1xxxxxxxx", InstName.Ldr,      InstEmit32.Ldr,      OpCodeT32MemImm8.Create);
            SetT32("111110001101xxxxxxxxxxxxxxxxxxxx", InstName.Ldr,      InstEmit32.Ldr,      OpCodeT32MemImm12.Create);
            SetT32("111110000101<<<<xxxx000000xxxxxx", InstName.Ldr,      InstEmit32.Ldr,      OpCodeT32MemRsImm.Create);
-            SetT32("111110000001xxxx<<<<10x1xxxxxxxx", InstName.Ldrb,     InstEmit32.Ldrb,     OpCodeT32MemImm8.Create);
+            SetT32("111110000001xxxxxxxx10x1xxxxxxxx", InstName.Ldrb,     InstEmit32.Ldrb,     OpCodeT32MemImm8.Create);
            SetT32("111110000001xxxx<<<<1100xxxxxxxx", InstName.Ldrb,     InstEmit32.Ldrb,     OpCodeT32MemImm8.Create);
-            SetT32("111110000001xxxx<<<<11x1xxxxxxxx", InstName.Ldrb,     InstEmit32.Ldrb,     OpCodeT32MemImm8.Create);
-            SetT32("111110001001xxxxxxxxxxxxxxxxxxxx", InstName.Ldrb,     InstEmit32.Ldrb,     OpCodeT32MemImm12.Create);
-            SetT32("1110100>x1>1<<<<xxxxxxxxxxxxxxxx", InstName.Ldrd,     InstEmit32.Ldrd,     OpCodeT32MemImm8D.Create);
-            SetT32("111110000011xxxx<<<<10x1xxxxxxxx", InstName.Ldrh,     InstEmit32.Ldrh,     OpCodeT32MemImm8.Create);
+            SetT32("111110000001xxxxxxxx11x1xxxxxxxx", InstName.Ldrb,     InstEmit32.Ldrb,     OpCodeT32MemImm8.Create);
+            SetT32("111110001001xxxx<<<<xxxxxxxxxxxx", InstName.Ldrb,     InstEmit32.Ldrb,     OpCodeT32MemImm12.Create);
+            SetT32("111110000001xxxx<<<<000000xxxxxx", InstName.Ldrb,     InstEmit32.Ldrb,     OpCodeT32MemRsImm.Create);
+            SetT32("11101000x111<<<<xxxxxxxxxxxxxxxx", InstName.Ldrd,     InstEmit32.Ldrd,     OpCodeT32MemImm8D.Create);
+            SetT32("11101001x1x1<<<<xxxxxxxxxxxxxxxx", InstName.Ldrd,     InstEmit32.Ldrd,     OpCodeT32MemImm8D.Create);
+            SetT32("111110000011xxxxxxxx10x1xxxxxxxx", InstName.Ldrh,     InstEmit32.Ldrh,     OpCodeT32MemImm8.Create);
            SetT32("111110000011xxxx<<<<1100xxxxxxxx", InstName.Ldrh,     InstEmit32.Ldrh,     OpCodeT32MemImm8.Create);
-            SetT32("111110000011xxxx<<<<11x1xxxxxxxx", InstName.Ldrh,     InstEmit32.Ldrh,     OpCodeT32MemImm8.Create);
-            SetT32("111110001011xxxxxxxxxxxxxxxxxxxx", InstName.Ldrh,     InstEmit32.Ldrh,     OpCodeT32MemImm12.Create);
-            SetT32("111110010001xxxx<<<<10x1xxxxxxxx", InstName.Ldrsb,    InstEmit32.Ldrsb,    OpCodeT32MemImm8.Create);
+            SetT32("111110000011xxxxxxxx11x1xxxxxxxx", InstName.Ldrh,     InstEmit32.Ldrh,     OpCodeT32MemImm8.Create);
+            SetT32("111110001011xxxx<<<<xxxxxxxxxxxx", InstName.Ldrh,     InstEmit32.Ldrh,     OpCodeT32MemImm12.Create);
+            SetT32("111110000011xxxx<<<<000000xxxxxx", InstName.Ldrh,     InstEmit32.Ldrh,     OpCodeT32MemRsImm.Create);
+            SetT32("111110010001xxxxxxxx10x1xxxxxxxx", InstName.Ldrsb,    InstEmit32.Ldrsb,    OpCodeT32MemImm8.Create);
            SetT32("111110010001xxxx<<<<1100xxxxxxxx", InstName.Ldrsb,    InstEmit32.Ldrsb,    OpCodeT32MemImm8.Create);
-            SetT32("111110010001xxxx<<<<11x1xxxxxxxx", InstName.Ldrsb,    InstEmit32.Ldrsb,    OpCodeT32MemImm8.Create);
-            SetT32("111110011001xxxxxxxxxxxxxxxxxxxx", InstName.Ldrsb,    InstEmit32.Ldrsb,    OpCodeT32MemImm12.Create);
-            SetT32("111110010011xxxx<<<<10x1xxxxxxxx", InstName.Ldrsh,    InstEmit32.Ldrsh,    OpCodeT32MemImm8.Create);
+            SetT32("111110010001xxxxxxxx11x1xxxxxxxx", InstName.Ldrsb,    InstEmit32.Ldrsb,    OpCodeT32MemImm8.Create);
+            SetT32("111110011001xxxx<<<<xxxxxxxxxxxx", InstName.Ldrsb,    InstEmit32.Ldrsb,    OpCodeT32MemImm12.Create);
+            SetT32("111110010001xxxx<<<<000000xxxxxx", InstName.Ldrsb,    InstEmit32.Ldrsb,    OpCodeT32MemRsImm.Create);
+            SetT32("111110010011xxxxxxxx10x1xxxxxxxx", InstName.Ldrsh,    InstEmit32.Ldrsh,    OpCodeT32MemImm8.Create);
            SetT32("111110010011xxxx<<<<1100xxxxxxxx", InstName.Ldrsh,    InstEmit32.Ldrsh,    OpCodeT32MemImm8.Create);
-            SetT32("111110010011xxxx<<<<11x1xxxxxxxx", InstName.Ldrsh,    InstEmit32.Ldrsh,    OpCodeT32MemImm8.Create);
-            SetT32("111110011011xxxxxxxxxxxxxxxxxxxx", InstName.Ldrsh,    InstEmit32.Ldrsh,    OpCodeT32MemImm12.Create);
+            SetT32("111110010011xxxxxxxx11x1xxxxxxxx", InstName.Ldrsh,    InstEmit32.Ldrsh,    OpCodeT32MemImm8.Create);
+            SetT32("111110011011xxxx<<<<xxxxxxxxxxxx", InstName.Ldrsh,    InstEmit32.Ldrsh,    OpCodeT32MemImm12.Create);
+            SetT32("111110010011xxxx<<<<000000xxxxxx", InstName.Ldrsh,    InstEmit32.Ldrsh,    OpCodeT32MemRsImm.Create);
+            SetT32("111110110000xxxx<<<<xxxx0000xxxx", InstName.Mla,      InstEmit32.Mla,      OpCodeT32AluMla.Create);
+            SetT32("111110110000xxxxxxxxxxxx0001xxxx", InstName.Mls,      InstEmit32.Mls,      OpCodeT32AluMla.Create);
            SetT32("11101010010x11110xxxxxxxxxxxxxxx", InstName.Mov,      InstEmit32.Mov,      OpCodeT32AluRsImm.Create);
+            SetT32("111110100xxxxxxx1111xxxx0000xxxx", InstName.Mov,      InstEmit32.Mov,      OpCodeT32ShiftReg.Create);
            SetT32("11110x00010x11110xxxxxxxxxxxxxxx", InstName.Mov,      InstEmit32.Mov,      OpCodeT32AluImm.Create);
+            SetT32("11110x100100xxxx0xxxxxxxxxxxxxxx", InstName.Mov,      InstEmit32.Mov,      OpCodeT32MovImm16.Create);
+            SetT32("11110x101100xxxx0xxxxxxxxxxxxxxx", InstName.Movt,     InstEmit32.Movt,     OpCodeT32MovImm16.Create);
+            SetT32("111110110000xxxx1111xxxx0000xxxx", InstName.Mul,      InstEmit32.Mul,      OpCodeT32AluMla.Create);
            SetT32("11101010011x11110xxxxxxxxxxxxxxx", InstName.Mvn,      InstEmit32.Mvn,      OpCodeT32AluRsImm.Create);
            SetT32("11110x00011x11110xxxxxxxxxxxxxxx", InstName.Mvn,      InstEmit32.Mvn,      OpCodeT32AluImm.Create);
+            SetT32("11110011101011111000000000000000", InstName.Nop,      InstEmit32.Nop,      OpCodeT32.Create);
            SetT32("11101010011x<<<<0xxxxxxxxxxxxxxx", InstName.Orn,      InstEmit32.Orn,      OpCodeT32AluRsImm.Create);
            SetT32("11110x00011x<<<<0xxxxxxxxxxxxxxx", InstName.Orn,      InstEmit32.Orn,      OpCodeT32AluImm.Create);
            SetT32("11101010010x<<<<0xxxxxxxxxxxxxxx", InstName.Orr,      InstEmit32.Orr,      OpCodeT32AluRsImm.Create);
            SetT32("11110x00010x<<<<0xxxxxxxxxxxxxxx", InstName.Orr,      InstEmit32.Orr,      OpCodeT32AluImm.Create);
+            SetT32("1111100010x1xxxx1111xxxxxxxxxxxx", InstName.Pld,      InstEmit32.Nop,      OpCodeT32.Create);
+            SetT32("1111100000x1xxxx11111100xxxxxxxx", InstName.Pld,      InstEmit32.Nop,      OpCodeT32.Create);
+            SetT32("1111100000x1xxxx1111000000xxxxxx", InstName.Pld,      InstEmit32.Nop,      OpCodeT32.Create);
            SetT32("11101011110xxxxx0xxxxxxxxxxxxxxx", InstName.Rsb,      InstEmit32.Rsb,      OpCodeT32AluRsImm.Create);
            SetT32("11110x01110xxxxx0xxxxxxxxxxxxxxx", InstName.Rsb,      InstEmit32.Rsb,      OpCodeT32AluImm.Create);
+            SetT32("111110101000xxxx1111xxxx0000xxxx", InstName.Sadd8,    InstEmit32.Sadd8,    OpCodeT32AluReg.Create);
            SetT32("11101011011xxxxx0xxxxxxxxxxxxxxx", InstName.Sbc,      InstEmit32.Sbc,      OpCodeT32AluRsImm.Create);
            SetT32("11110x01011xxxxx0xxxxxxxxxxxxxxx", InstName.Sbc,      InstEmit32.Sbc,      OpCodeT32AluImm.Create);
+            SetT32("111100110100xxxx0xxxxxxxxx0xxxxx", InstName.Sbfx,     InstEmit32.Sbfx,     OpCodeT32AluBf.Create);
+            SetT32("111110111001xxxx1111xxxx1111xxxx", InstName.Sdiv,     InstEmit32.Sdiv,     OpCodeT32AluMla.Create);
+            SetT32("111110101010xxxx1111xxxx1000xxxx", InstName.Sel,      InstEmit32.Sel,      OpCodeT32AluReg.Create);
+            SetT32("111110101000xxxx1111xxxx0010xxxx", InstName.Shadd8,   InstEmit32.Shadd8,   OpCodeT32AluReg.Create);
+            SetT32("111110101100xxxx1111xxxx0010xxxx", InstName.Shsub8,   InstEmit32.Shsub8,   OpCodeT32AluReg.Create);
+            SetT32("111110110001xxxx<<<<xxxx00xxxxxx", InstName.Smla__,   InstEmit32.Smla__,   OpCodeT32AluMla.Create);
+            SetT32("111110111100xxxxxxxxxxxx0000xxxx", InstName.Smlal,    InstEmit32.Smlal,    OpCodeT32AluUmull.Create);
+            SetT32("111110111100xxxxxxxxxxxx10xxxxxx", InstName.Smlal__,  InstEmit32.Smlal__,  OpCodeT32AluUmull.Create);
+            SetT32("111110110011xxxx<<<<xxxx000xxxxx", InstName.Smlaw_,   InstEmit32.Smlaw_,   OpCodeT32AluMla.Create);
+            SetT32("111110110101xxxx<<<<xxxx000xxxxx", InstName.Smmla,    InstEmit32.Smmla,    OpCodeT32AluMla.Create);
+            SetT32("111110110110xxxxxxxxxxxx000xxxxx", InstName.Smmls,    InstEmit32.Smmls,    OpCodeT32AluMla.Create);
+            SetT32("111110110001xxxx1111xxxx00xxxxxx", InstName.Smul__,   InstEmit32.Smul__,   OpCodeT32AluMla.Create);
+            SetT32("111110111000xxxxxxxxxxxx0000xxxx", InstName.Smull,    InstEmit32.Smull,    OpCodeT32AluUmull.Create);
+            SetT32("111110110011xxxx1111xxxx000xxxxx", InstName.Smulw_,   InstEmit32.Smulw_,   OpCodeT32AluMla.Create);
+            SetT32("111110101100xxxx1111xxxx0000xxxx", InstName.Ssub8,    InstEmit32.Ssub8,    OpCodeT32AluReg.Create);
+            SetT32("111010001100xxxxxxxx111110101111", InstName.Stl,      InstEmit32.Stl,      OpCodeT32MemStEx.Create);
+            SetT32("111010001100xxxxxxxx111110001111", InstName.Stlb,     InstEmit32.Stlb,     OpCodeT32MemStEx.Create);
            SetT32("111010001100xxxxxxxx11111110xxxx", InstName.Stlex,    InstEmit32.Stlex,    OpCodeT32MemStEx.Create);
+            SetT32("111010001100xxxxxxxx11111100xxxx", InstName.Stlexb,   InstEmit32.Stlexb,   OpCodeT32MemStEx.Create);
+            SetT32("111010001100xxxxxxxxxxxx1111xxxx", InstName.Stlexd,   InstEmit32.Stlexd,   OpCodeT32MemStEx.Create);
+            SetT32("111010001100xxxxxxxx11111101xxxx", InstName.Stlexh,   InstEmit32.Stlexh,   OpCodeT32MemStEx.Create);
+            SetT32("111010001100xxxxxxxx111110011111", InstName.Stlh,     InstEmit32.Stlh,     OpCodeT32MemStEx.Create);
            SetT32("1110100010x0xxxx0xxxxxxxxxxxxxxx", InstName.Stm,      InstEmit32.Stm,      OpCodeT32MemMult.Create);
            SetT32("1110100100x0xxxx0xxxxxxxxxxxxxxx", InstName.Stm,      InstEmit32.Stm,      OpCodeT32MemMult.Create);
-            SetT32("111110000100xxxxxxxx1<<>xxxxxxxx", InstName.Str,      InstEmit32.Str,      OpCodeT32MemImm8.Create);
-            SetT32("111110001100xxxxxxxxxxxxxxxxxxxx", InstName.Str,      InstEmit32.Str,      OpCodeT32MemImm12.Create);
+            SetT32("111110000100<<<<xxxx10x1xxxxxxxx", InstName.Str,      InstEmit32.Str,      OpCodeT32MemImm8.Create);
+            SetT32("111110000100<<<<xxxx1100xxxxxxxx", InstName.Str,      InstEmit32.Str,      OpCodeT32MemImm8.Create);
+            SetT32("111110000100<<<<xxxx11x1xxxxxxxx", InstName.Str,      InstEmit32.Str,      OpCodeT32MemImm8.Create);
+            SetT32("111110001100<<<<xxxxxxxxxxxxxxxx", InstName.Str,      InstEmit32.Str,      OpCodeT32MemImm12.Create);
            SetT32("111110000100<<<<xxxx000000xxxxxx", InstName.Str,      InstEmit32.Str,      OpCodeT32MemRsImm.Create);
-            SetT32("111110000000xxxxxxxx1<<>xxxxxxxx", InstName.Strb,     InstEmit32.Strb,     OpCodeT32MemImm8.Create);
-            SetT32("111110001000xxxxxxxxxxxxxxxxxxxx", InstName.Strb,     InstEmit32.Strb,     OpCodeT32MemImm12.Create);
-            SetT32("1110100>x1>0<<<<xxxxxxxxxxxxxxxx", InstName.Strd,     InstEmit32.Strd,     OpCodeT32MemImm8D.Create);
-            SetT32("111110000010xxxxxxxx1<<>xxxxxxxx", InstName.Strh,     InstEmit32.Strh,     OpCodeT32MemImm8.Create);
-            SetT32("111110001010xxxxxxxxxxxxxxxxxxxx", InstName.Strh,     InstEmit32.Strh,     OpCodeT32MemImm12.Create);
+            SetT32("111110000000<<<<xxxx10x1xxxxxxxx", InstName.Strb,     InstEmit32.Strb,     OpCodeT32MemImm8.Create);
+            SetT32("111110000000<<<<xxxx1100xxxxxxxx", InstName.Strb,     InstEmit32.Strb,     OpCodeT32MemImm8.Create);
+            SetT32("111110000000<<<<xxxx11x1xxxxxxxx", InstName.Strb,     InstEmit32.Strb,     OpCodeT32MemImm8.Create);
+            SetT32("111110001000<<<<xxxxxxxxxxxxxxxx", InstName.Strb,     InstEmit32.Strb,     OpCodeT32MemImm12.Create);
+            SetT32("111110000000<<<<xxxx000000xxxxxx", InstName.Strb,     InstEmit32.Strb,     OpCodeT32MemRsImm.Create);
+            SetT32("11101000x110<<<<xxxxxxxxxxxxxxxx", InstName.Strd,     InstEmit32.Strd,     OpCodeT32MemImm8D.Create);
+            SetT32("11101001x1x0<<<<xxxxxxxxxxxxxxxx", InstName.Strd,     InstEmit32.Strd,     OpCodeT32MemImm8D.Create);
+            SetT32("111110000010<<<<xxxx10x1xxxxxxxx", InstName.Strh,     InstEmit32.Strh,     OpCodeT32MemImm8.Create);
+            SetT32("111110000010<<<<xxxx1100xxxxxxxx", InstName.Strh,     InstEmit32.Strh,     OpCodeT32MemImm8.Create);
+            SetT32("111110000010<<<<xxxx11x1xxxxxxxx", InstName.Strh,     InstEmit32.Strh,     OpCodeT32MemImm8.Create);
+            SetT32("111110001010<<<<xxxxxxxxxxxxxxxx", InstName.Strh,     InstEmit32.Strh,     OpCodeT32MemImm12.Create);
+            SetT32("111110000010<<<<xxxx000000xxxxxx", InstName.Strh,     InstEmit32.Strh,     OpCodeT32MemRsImm.Create);
            SetT32("11101011101<xxxx0xxx<<<<xxxxxxxx", InstName.Sub,      InstEmit32.Sub,      OpCodeT32AluRsImm.Create);
            SetT32("11110x01101<xxxx0xxx<<<<xxxxxxxx", InstName.Sub,      InstEmit32.Sub,      OpCodeT32AluImm.Create);
+            SetT32("11110x101010xxxx0xxxxxxxxxxxxxxx", InstName.Sub,      InstEmit32.Sub,      OpCodeT32AluImm12.Create);
+            SetT32("111110100100xxxx1111xxxx10xxxxxx", InstName.Sxtb,     InstEmit32.Sxtb,     OpCodeT32AluUx.Create);
+            SetT32("111110100010xxxx1111xxxx10xxxxxx", InstName.Sxtb16,   InstEmit32.Sxtb16,   OpCodeT32AluUx.Create);
+            SetT32("111110100000xxxx1111xxxx10xxxxxx", InstName.Sxth,     InstEmit32.Sxth,     OpCodeT32AluUx.Create);
+            SetT32("111010001101xxxx111100000000xxxx", InstName.Tbb,      InstEmit32.Tbb,      OpCodeT32Tb.Create);
+            SetT32("111010001101xxxx111100000001xxxx", InstName.Tbh,      InstEmit32.Tbh,      OpCodeT32Tb.Create);
            SetT32("111010101001xxxx0xxx1111xxxxxxxx", InstName.Teq,      InstEmit32.Teq,      OpCodeT32AluRsImm.Create);
            SetT32("11110x001001xxxx0xxx1111xxxxxxxx", InstName.Teq,      InstEmit32.Teq,      OpCodeT32AluImm.Create);
            SetT32("111010100001xxxx0xxx1111xxxxxxxx", InstName.Tst,      InstEmit32.Tst,      OpCodeT32AluRsImm.Create);
            SetT32("11110x000001xxxx0xxx1111xxxxxxxx", InstName.Tst,      InstEmit32.Tst,      OpCodeT32AluImm.Create);
+            SetT32("111110101000xxxx1111xxxx0100xxxx", InstName.Uadd8,    InstEmit32.Uadd8,    OpCodeT32AluReg.Create);
+            SetT32("111100111100xxxx0xxxxxxxxx0xxxxx", InstName.Ubfx,     InstEmit32.Ubfx,     OpCodeT32AluBf.Create);
+            SetT32("111110111011xxxx1111xxxx1111xxxx", InstName.Udiv,     InstEmit32.Udiv,     OpCodeT32AluMla.Create);
+            SetT32("111110101000xxxx1111xxxx0110xxxx", InstName.Uhadd8,   InstEmit32.Uhadd8,   OpCodeT32AluReg.Create);
+            SetT32("111110101100xxxx1111xxxx0110xxxx", InstName.Uhsub8,   InstEmit32.Uhsub8,   OpCodeT32AluReg.Create);
+            SetT32("111110111110xxxxxxxxxxxx0110xxxx", InstName.Umaal,    InstEmit32.Umaal,    OpCodeT32AluUmull.Create);
+            SetT32("111110111110xxxxxxxxxxxx0000xxxx", InstName.Umlal,    InstEmit32.Umlal,    OpCodeT32AluUmull.Create);
+            SetT32("111110111010xxxxxxxxxxxx0000xxxx", InstName.Umull,    InstEmit32.Umull,    OpCodeT32AluUmull.Create);
+            SetT32("111110101100xxxx1111xxxx0100xxxx", InstName.Usub8,    InstEmit32.Usub8,    OpCodeT32AluReg.Create);
+            SetT32("111110100101xxxx1111xxxx10xxxxxx", InstName.Uxtb,     InstEmit32.Uxtb,     OpCodeT32AluUx.Create);
+            SetT32("111110100011xxxx1111xxxx10xxxxxx", InstName.Uxtb16,   InstEmit32.Uxtb16,   OpCodeT32AluUx.Create);
+            SetT32("111110100001xxxx1111xxxx10xxxxxx", InstName.Uxth,     InstEmit32.Uxth,     OpCodeT32AluUx.Create);
 #endregion

            FillFastLookupTable(InstA32FastLookup, AllInstA32, ToFastLookupIndexA);
@@ -1180,6 +1298,46 @@ namespace ARMeilleure.Decoders
            Set(reversedEncoding, AllInstT32, new InstDescriptor(name, emitter), reversedMakeOp);
        }

+        private static void SetVfp(string encoding, InstName name, InstEmitter emitter, MakeOp makeOpA32, MakeOp makeOpT32)
+        {
+            SetA32(encoding, name, emitter, makeOpA32);
+
+            string thumbEncoding = encoding;
+            if (thumbEncoding.StartsWith("<<<<"))
+            {
+                thumbEncoding = "1110" + thumbEncoding.Substring(4);
+            }
+            SetT32(thumbEncoding, name, emitter, makeOpT32);
+        }
+
+        private static void SetAsimd(string encoding, InstName name, InstEmitter emitter, MakeOp makeOpA32, MakeOp makeOpT32)
+        {
+            SetA32(encoding, name, emitter, makeOpA32);
+
+            string thumbEncoding = encoding;
+            if (thumbEncoding.StartsWith("11110100"))
+            {
+                thumbEncoding = "11111001" + encoding.Substring(8);
+            }
+            else if (thumbEncoding.StartsWith("1111001x"))
+            {
+                thumbEncoding = "111x1111" + encoding.Substring(8);
+            }
+            else if (thumbEncoding.StartsWith("11110010"))
+            {
+                thumbEncoding = "11101111" + encoding.Substring(8);
+            }
+            else if (thumbEncoding.StartsWith("11110011"))
+            {
+                thumbEncoding = "11111111" + encoding.Substring(8);
+            }
+            else
+            {
+                throw new ArgumentException("Invalid ASIMD instruction encoding");
+            }
+            SetT32(thumbEncoding, name, emitter, makeOpT32);
+        }
+
        private static void SetA64(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp)
        {
            Set(encoding, AllInstA64, new InstDescriptor(name, emitter), makeOp);
--- a/ARMeilleure/Diagnostics/EventSources/AddressTableEventSource.cs
+++ b/ARMeilleure/Diagnostics/EventSources/AddressTableEventSource.cs
@@ -1,51 +0,0 @@
-using System.Diagnostics.Tracing;
-
-namespace ARMeilleure.Diagnostics.EventSources
-{
-    [EventSource(Name = "ARMeilleure")]
-    class AddressTableEventSource : EventSource
-    {
-        public static readonly AddressTableEventSource Log = new();
-
-        private ulong _size;
-        private ulong _leafSize;
-        private PollingCounter _sizeCounter;
-        private PollingCounter _leafSizeCounter;
-
-        public AddressTableEventSource()
-        {
-            _sizeCounter = new PollingCounter("addr-tab-alloc", this, () => _size / 1024d / 1024d)
-            {
-                DisplayName = "AddressTable Total Bytes Allocated",
-                DisplayUnits = "MB"
-            };
-
-            _leafSizeCounter = new PollingCounter("addr-tab-leaf-alloc", this, () => _leafSize / 1024d / 1024d)
-            {
-                DisplayName = "AddressTable Total Leaf Bytes Allocated",
-                DisplayUnits = "MB"
-            };
-        }
-
-        public void Allocated(int bytes, bool leaf)
-        {
-            _size += (uint)bytes;
-
-            if (leaf)
-            {
-                _leafSize += (uint)bytes;
-            }
-        }
-
-        protected override void Dispose(bool disposing)
-        {
-            _leafSizeCounter.Dispose();
-            _leafSizeCounter = null;
-
-            _sizeCounter.Dispose();
-            _sizeCounter = null;
-
-            base.Dispose(disposing);
-        }
-    }
-}
--- a/ARMeilleure/Diagnostics/TranslatorEventSource.cs
+++ b/ARMeilleure/Diagnostics/TranslatorEventSource.cs
@@ -0,0 +1,67 @@
+using System.Diagnostics.Tracing;
+using System.Threading;
+
+namespace ARMeilleure.Diagnostics
+{
+    [EventSource(Name = "ARMeilleure")]
+    class TranslatorEventSource : EventSource
+    {
+        public static readonly TranslatorEventSource Log = new();
+
+        private int _rejitQueue;
+        private ulong _funcTabSize;
+        private ulong _funcTabLeafSize;
+        private PollingCounter _rejitQueueCounter;
+        private PollingCounter _funcTabSizeCounter;
+        private PollingCounter _funcTabLeafSizeCounter;
+
+        public TranslatorEventSource()
+        {
+            _rejitQueueCounter = new PollingCounter("rejit-queue-length", this, () => _rejitQueue)
+            {
+                DisplayName = "Rejit Queue Length"
+            };
+
+            _funcTabSizeCounter = new PollingCounter("addr-tab-alloc", this, () => _funcTabSize / 1024d / 1024d)
+            {
+                DisplayName = "AddressTable Total Bytes Allocated",
+                DisplayUnits = "MB"
+            };
+
+            _funcTabLeafSizeCounter = new PollingCounter("addr-tab-leaf-alloc", this, () => _funcTabLeafSize / 1024d / 1024d)
+            {
+                DisplayName = "AddressTable Total Leaf Bytes Allocated",
+                DisplayUnits = "MB"
+            };
+        }
+
+        public void RejitQueueAdd(int count)
+        {
+            Interlocked.Add(ref _rejitQueue, count);
+        }
+
+        public void AddressTableAllocated(int bytes, bool leaf)
+        {
+            _funcTabSize += (uint)bytes;
+
+            if (leaf)
+            {
+                _funcTabLeafSize += (uint)bytes;
+            }
+        }
+
+        protected override void Dispose(bool disposing)
+        {
+            _rejitQueueCounter.Dispose();
+            _rejitQueueCounter = null;
+
+            _funcTabLeafSizeCounter.Dispose();
+            _funcTabLeafSizeCounter = null;
+
+            _funcTabSizeCounter.Dispose();
+            _funcTabSizeCounter = null;
+
+            base.Dispose(disposing);
+        }
+    }
+}
--- a/ARMeilleure/Instructions/InstEmitAlu32.cs
+++ b/ARMeilleure/Instructions/InstEmitAlu32.cs
@@ -74,7 +74,7 @@ namespace ARMeilleure.Instructions

        public static void Bfc(ArmEmitterContext context)
        {
-            OpCode32AluBf op = (OpCode32AluBf)context.CurrOp;
+            IOpCode32AluBf op = (IOpCode32AluBf)context.CurrOp;

            Operand d = GetIntA32(context, op.Rd);
            Operand res = context.BitwiseAnd(d, Const(~op.DestMask));
@@ -84,7 +84,7 @@ namespace ARMeilleure.Instructions

        public static void Bfi(ArmEmitterContext context)
        {
-            OpCode32AluBf op = (OpCode32AluBf)context.CurrOp;
+            IOpCode32AluBf op = (IOpCode32AluBf)context.CurrOp;

            Operand n = GetIntA32(context, op.Rn);
            Operand d = GetIntA32(context, op.Rd);
@@ -185,7 +185,7 @@ namespace ARMeilleure.Instructions

        public static void Movt(ArmEmitterContext context)
        {
-            OpCode32AluImm16 op = (OpCode32AluImm16)context.CurrOp;
+            IOpCode32AluImm16 op = (IOpCode32AluImm16)context.CurrOp;

            Operand d = GetIntA32(context, op.Rd);
            Operand imm = Const(op.Immediate << 16); // Immeditate value as top halfword.
@@ -363,6 +363,11 @@ namespace ARMeilleure.Instructions
            EmitAluStore(context, res);
        }

+        public static void Sadd8(ArmEmitterContext context)
+        {
+            EmitAddSub8(context, add: true, unsigned: false);
+        }
+
        public static void Sbc(ArmEmitterContext context)
        {
            IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
@@ -389,7 +394,7 @@ namespace ARMeilleure.Instructions

        public static void Sbfx(ArmEmitterContext context)
        {
-            OpCode32AluBf op = (OpCode32AluBf)context.CurrOp;
+            IOpCode32AluBf op = (IOpCode32AluBf)context.CurrOp;

            var msb = op.Lsb + op.Msb; // For this instruction, the msb is actually a width.

@@ -401,17 +406,38 @@ namespace ARMeilleure.Instructions

        public static void Sdiv(ArmEmitterContext context)
        {
-            EmitDiv(context, false);
+            EmitDiv(context, unsigned: false);
+        }
+
+        public static void Sel(ArmEmitterContext context)
+        {
+            IOpCode32AluReg op = (IOpCode32AluReg)context.CurrOp;
+
+            Operand n = GetIntA32(context, op.Rn);
+            Operand m = GetIntA32(context, op.Rm);
+
+            Operand ge0 = context.ZeroExtend8(OperandType.I32, context.Negate(GetFlag(PState.GE0Flag)));
+            Operand ge1 = context.ZeroExtend8(OperandType.I32, context.Negate(GetFlag(PState.GE1Flag)));
+            Operand ge2 = context.ZeroExtend8(OperandType.I32, context.Negate(GetFlag(PState.GE2Flag)));
+            Operand ge3 = context.Negate(GetFlag(PState.GE3Flag));
+
+            Operand mask = context.BitwiseOr(ge0, context.ShiftLeft(ge1, Const(8)));
+            mask = context.BitwiseOr(mask, context.ShiftLeft(ge2, Const(16)));
+            mask = context.BitwiseOr(mask, context.ShiftLeft(ge3, Const(24)));
+
+            Operand res = context.BitwiseOr(context.BitwiseAnd(n, mask), context.BitwiseAnd(m, context.BitwiseNot(mask)));
+
+            SetIntA32(context, op.Rd, res);
        }

        public static void Shadd8(ArmEmitterContext context)
        {
-            EmitHadd8(context, false);
+            EmitHadd8(context, unsigned: false);
        }

        public static void Shsub8(ArmEmitterContext context)
        {
-            EmitHsub8(context, false);
+            EmitHsub8(context, unsigned: false);
        }

        public static void Ssat(ArmEmitterContext context)
@@ -428,6 +454,11 @@ namespace ARMeilleure.Instructions
            EmitSat16(context, -(1 << op.SatImm), (1 << op.SatImm) - 1);
        }

+        public static void Ssub8(ArmEmitterContext context)
+        {
+            EmitAddSub8(context, add: false, unsigned: false);
+        }
+
        public static void Sub(ArmEmitterContext context)
        {
            IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
@@ -482,9 +513,14 @@ namespace ARMeilleure.Instructions
            EmitNZFlagsCheck(context, res);
        }

+        public static void Uadd8(ArmEmitterContext context)
+        {
+            EmitAddSub8(context, add: true, unsigned: true);
+        }
+
        public static void Ubfx(ArmEmitterContext context)
        {
-            OpCode32AluBf op = (OpCode32AluBf)context.CurrOp;
+            IOpCode32AluBf op = (IOpCode32AluBf)context.CurrOp;

            var msb = op.Lsb + op.Msb; // For this instruction, the msb is actually a width.

@@ -496,17 +532,17 @@ namespace ARMeilleure.Instructions

        public static void Udiv(ArmEmitterContext context)
        {
-            EmitDiv(context, true);
+            EmitDiv(context, unsigned: true);
        }

        public static void Uhadd8(ArmEmitterContext context)
        {
-            EmitHadd8(context, true);
+            EmitHadd8(context, unsigned: true);
        }

        public static void Uhsub8(ArmEmitterContext context)
        {
-            EmitHsub8(context, true);
+            EmitHsub8(context, unsigned: true);
        }

        public static void Usat(ArmEmitterContext context)
@@ -523,6 +559,11 @@ namespace ARMeilleure.Instructions
            EmitSat16(context, 0, (1 << op.SatImm) - 1);
        }

+        public static void Usub8(ArmEmitterContext context)
+        {
+            EmitAddSub8(context, add: false, unsigned: true);
+        }
+
        public static void Uxtb(ArmEmitterContext context)
        {
            EmitSignExtend(context, false, 8);
@@ -678,9 +719,40 @@ namespace ARMeilleure.Instructions
            context.MarkLabel(lblEnd);
        }

+        private static void EmitAddSub8(ArmEmitterContext context, bool add, bool unsigned)
+        {
+            IOpCode32AluReg op = (IOpCode32AluReg)context.CurrOp;
+
+            Operand n = GetIntA32(context, op.Rn);
+            Operand m = GetIntA32(context, op.Rm);
+
+            Operand res = Const(0);
+
+            for (int byteSel = 0; byteSel < 4; byteSel++)
+            {
+                Operand shift = Const(byteSel * 8);
+
+                Operand nByte = context.ShiftRightUI(n, shift);
+                Operand mByte = context.ShiftRightUI(m, shift);
+
+                nByte = unsigned ? context.ZeroExtend8(OperandType.I32, nByte) : context.SignExtend8(OperandType.I32, nByte);
+                mByte = unsigned ? context.ZeroExtend8(OperandType.I32, mByte) : context.SignExtend8(OperandType.I32, mByte);
+
+                Operand resByte = add ? context.Add(nByte, mByte) : context.Subtract(nByte, mByte);
+
+                res = context.BitwiseOr(res, context.ShiftLeft(context.ZeroExtend8(OperandType.I32, resByte), shift));
+
+                SetFlag(context, PState.GE0Flag + byteSel, unsigned && add
+                    ? context.ShiftRightUI(resByte, Const(8))
+                    : context.ShiftRightUI(context.BitwiseNot(resByte), Const(31)));
+            }
+
+            SetIntA32(context, op.Rd, res);
+        }
+
        private static void EmitHadd8(ArmEmitterContext context, bool unsigned)
        {
-            OpCode32AluReg op = (OpCode32AluReg)context.CurrOp;
+            IOpCode32AluReg op = (IOpCode32AluReg)context.CurrOp;

            Operand m = GetIntA32(context, op.Rm);
            Operand n = GetIntA32(context, op.Rn);
@@ -710,7 +782,7 @@ namespace ARMeilleure.Instructions

        private static void EmitHsub8(ArmEmitterContext context, bool unsigned)
        {
-            OpCode32AluReg op = (OpCode32AluReg)context.CurrOp;
+            IOpCode32AluReg op = (IOpCode32AluReg)context.CurrOp;

            Operand m = GetIntA32(context, op.Rm);
            Operand n = GetIntA32(context, op.Rn);
--- a/ARMeilleure/Instructions/InstEmitAluHelper.cs
+++ b/ARMeilleure/Instructions/InstEmitAluHelper.cs
@@ -128,7 +128,7 @@ namespace ARMeilleure.Instructions
        {
            Debug.Assert(value.Type == OperandType.I32);

-            if (((OpCode32)context.CurrOp).IsThumb())
+            if (((OpCode32)context.CurrOp).IsThumb)
            {
                bool isReturn = IsA32Return(context);
                if (!isReturn)
@@ -205,7 +205,7 @@ namespace ARMeilleure.Instructions
                    return Const(op.Immediate);
                }

-                case OpCode32AluImm16 op: return Const(op.Immediate);
+                case IOpCode32AluImm16 op: return Const(op.Immediate);

                case IOpCode32AluRsImm op: return GetMShiftedByImmediate(context, op, setCarry);
                case IOpCode32AluRsReg op: return GetMShiftedByReg(context, op, setCarry);
--- a/ARMeilleure/Instructions/InstEmitFlow32.cs
+++ b/ARMeilleure/Instructions/InstEmitFlow32.cs
@@ -34,7 +34,7 @@ namespace ARMeilleure.Instructions

            uint pc = op.GetPc();

-            bool isThumb = ((OpCode32)context.CurrOp).IsThumb();
+            bool isThumb = ((OpCode32)context.CurrOp).IsThumb;

            uint currentPc = isThumb
                ? pc | 1
@@ -61,7 +61,7 @@ namespace ARMeilleure.Instructions
            Operand addr = context.Copy(GetIntA32(context, op.Rm));
            Operand bitOne = context.BitwiseAnd(addr, Const(1));

-            bool isThumb = ((OpCode32)context.CurrOp).IsThumb();
+            bool isThumb = ((OpCode32)context.CurrOp).IsThumb;

            uint currentPc = isThumb
                ? (pc - 2) | 1
@@ -107,5 +107,30 @@ namespace ARMeilleure.Instructions

            context.SetIfThenBlockState(op.IfThenBlockConds);
        }
+
+        public static void Tbb(ArmEmitterContext context) => EmitTb(context, halfword: false);
+        public static void Tbh(ArmEmitterContext context)  => EmitTb(context, halfword: true);
+
+        private static void EmitTb(ArmEmitterContext context, bool halfword)
+        {
+            OpCodeT32Tb op = (OpCodeT32Tb)context.CurrOp;
+
+            Operand halfwords;
+
+            if (halfword)
+            {
+                Operand address = context.Add(GetIntA32(context, op.Rn), context.ShiftLeft(GetIntA32(context, op.Rm), Const(1)));
+                halfwords = InstEmitMemoryHelper.EmitReadInt(context, address, 1);
+            }
+            else
+            {
+                Operand address = context.Add(GetIntA32(context, op.Rn), GetIntA32(context, op.Rm));
+                halfwords = InstEmitMemoryHelper.EmitReadIntAligned(context, address, 0);
+            }
+
+            Operand targetAddress = context.Add(Const((int)op.GetPc()), context.ShiftLeft(halfwords, Const(1)));
+
+            EmitVirtualJump(context, targetAddress, isReturn: false);
+        }
    }
 }
--- a/ARMeilleure/Instructions/InstEmitMemory32.cs
+++ b/ARMeilleure/Instructions/InstEmitMemory32.cs
@@ -204,15 +204,15 @@ namespace ARMeilleure.Instructions

                    context.BranchIfTrue(lblBigEndian, GetFlag(PState.EFlag));

-                    Load(op.Rt,     0, WordSizeLog2);
-                    Load(op.Rt | 1, 4, WordSizeLog2);
+                    Load(op.Rt, 0, WordSizeLog2);
+                    Load(op.Rt2, 4, WordSizeLog2);

                    context.Branch(lblEnd);

                    context.MarkLabel(lblBigEndian);

-                    Load(op.Rt | 1, 0, WordSizeLog2);
-                    Load(op.Rt,     4, WordSizeLog2);
+                    Load(op.Rt2, 0, WordSizeLog2);
+                    Load(op.Rt, 4, WordSizeLog2);

                    context.MarkLabel(lblEnd);
                }
@@ -237,15 +237,15 @@ namespace ARMeilleure.Instructions

                    context.BranchIfTrue(lblBigEndian, GetFlag(PState.EFlag));

-                    Store(op.Rt,     0, WordSizeLog2);
-                    Store(op.Rt | 1, 4, WordSizeLog2);
+                    Store(op.Rt, 0, WordSizeLog2);
+                    Store(op.Rt2, 4, WordSizeLog2);

                    context.Branch(lblEnd);

                    context.MarkLabel(lblBigEndian);

-                    Store(op.Rt | 1, 0, WordSizeLog2);
-                    Store(op.Rt,     4, WordSizeLog2);
+                    Store(op.Rt2, 0, WordSizeLog2);
+                    Store(op.Rt, 4, WordSizeLog2);

                    context.MarkLabel(lblEnd);
                }
--- a/ARMeilleure/Instructions/InstEmitMemoryEx32.cs
+++ b/ARMeilleure/Instructions/InstEmitMemoryEx32.cs
@@ -172,13 +172,13 @@ namespace ARMeilleure.Instructions
                    context.BranchIfTrue(lblBigEndian, GetFlag(PState.EFlag));

                    SetIntA32(context, op.Rt, valueLow);
-                    SetIntA32(context, op.Rt | 1, valueHigh);
+                    SetIntA32(context, op.Rt2, valueHigh);

                    context.Branch(lblEnd);

                    context.MarkLabel(lblBigEndian);

-                    SetIntA32(context, op.Rt | 1, valueLow);
+                    SetIntA32(context, op.Rt2, valueLow);
                    SetIntA32(context, op.Rt, valueHigh);

                    context.MarkLabel(lblEnd);
@@ -195,7 +195,7 @@ namespace ARMeilleure.Instructions
                    // Split the result into 2 words (based on endianness)

                    Operand lo = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rt));
-                    Operand hi = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rt | 1));
+                    Operand hi = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rt2));

                    Operand lblBigEndian = Label();
                    Operand lblEnd = Label();
--- a/ARMeilleure/Instructions/InstEmitMemoryHelper.cs
+++ b/ARMeilleure/Instructions/InstEmitMemoryHelper.cs
@@ -123,6 +123,41 @@ namespace ARMeilleure.Instructions
                   context.CurrOp is OpCodeSimdMemSs);
        }

+        public static Operand EmitReadInt(ArmEmitterContext context, Operand address, int size)
+        {
+            Operand temp = context.AllocateLocal(size == 3 ? OperandType.I64 : OperandType.I32);
+
+            Operand lblSlowPath = Label();
+            Operand lblEnd      = Label();
+
+            Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: false, size);
+
+            Operand value = default;
+
+            switch (size)
+            {
+                case 0: value = context.Load8 (physAddr);                  break;
+                case 1: value = context.Load16(physAddr);                  break;
+                case 2: value = context.Load  (OperandType.I32, physAddr); break;
+                case 3: value = context.Load  (OperandType.I64, physAddr); break;
+            }
+
+            context.Copy(temp, value);
+
+            if (!context.Memory.Type.IsHostMapped())
+            {
+                context.Branch(lblEnd);
+
+                context.MarkLabel(lblSlowPath, BasicBlockFrequency.Cold);
+
+                context.Copy(temp, EmitReadIntFallback(context, address, size));
+
+                context.MarkLabel(lblEnd);
+            }
+
+            return temp;
+        }
+
        private static void EmitReadInt(ArmEmitterContext context, Operand address, int rt, int size)
        {
            Operand lblSlowPath = Label();
@@ -419,6 +454,11 @@ namespace ARMeilleure.Instructions
        }

        private static void EmitReadIntFallback(ArmEmitterContext context, Operand address, int rt, int size)
+        {
+            SetInt(context, rt, EmitReadIntFallback(context, address, size));
+        }
+
+        private static Operand EmitReadIntFallback(ArmEmitterContext context, Operand address, int size)
        {
            MethodInfo info = null;

@@ -430,7 +470,7 @@ namespace ARMeilleure.Instructions
                case 3: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt64)); break;
            }

-            SetInt(context, rt, context.Call(info, address));
+            return context.Call(info, address);
        }

        private static void EmitReadVectorFallback(
--- a/ARMeilleure/Instructions/InstEmitMul32.cs
+++ b/ARMeilleure/Instructions/InstEmitMul32.cs
@@ -25,7 +25,7 @@ namespace ARMeilleure.Instructions

        public static void Mla(ArmEmitterContext context)
        {
-            OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
+            IOpCode32AluMla op = (IOpCode32AluMla)context.CurrOp;

            Operand n = GetAluN(context);
            Operand m = GetAluM(context);
@@ -43,7 +43,7 @@ namespace ARMeilleure.Instructions

        public static void Mls(ArmEmitterContext context)
        {
-            OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
+            IOpCode32AluMla op = (IOpCode32AluMla)context.CurrOp;

            Operand n = GetAluN(context);
            Operand m = GetAluM(context);
@@ -71,7 +71,7 @@ namespace ARMeilleure.Instructions

        private static void EmitSmmul(ArmEmitterContext context, MullFlags flags)
        {
-            OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
+            IOpCode32AluMla op = (IOpCode32AluMla)context.CurrOp;

            Operand n = context.SignExtend32(OperandType.I64, GetIntA32(context, op.Rn));
            Operand m = context.SignExtend32(OperandType.I64, GetIntA32(context, op.Rm));
@@ -99,7 +99,7 @@ namespace ARMeilleure.Instructions

        public static void Smla__(ArmEmitterContext context)
        {
-            OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
+            IOpCode32AluMla op = (IOpCode32AluMla)context.CurrOp;

            Operand n = GetIntA32(context, op.Rn);
            Operand m = GetIntA32(context, op.Rm);
@@ -142,7 +142,7 @@ namespace ARMeilleure.Instructions

        public static void Smlal__(ArmEmitterContext context)
        {
-            OpCode32AluUmull op = (OpCode32AluUmull)context.CurrOp;
+            IOpCode32AluUmull op = (IOpCode32AluUmull)context.CurrOp;

            Operand n = GetIntA32(context, op.Rn);
            Operand m = GetIntA32(context, op.Rm);
@@ -180,7 +180,7 @@ namespace ARMeilleure.Instructions

        public static void Smlaw_(ArmEmitterContext context)
        {
-            OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
+            IOpCode32AluMla op = (IOpCode32AluMla)context.CurrOp;

            Operand n = GetIntA32(context, op.Rn);
            Operand m = GetIntA32(context, op.Rm);
@@ -210,7 +210,7 @@ namespace ARMeilleure.Instructions

        public static void Smul__(ArmEmitterContext context)
        {
-            OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
+            IOpCode32AluMla op = (IOpCode32AluMla)context.CurrOp;

            Operand n = GetIntA32(context, op.Rn);
            Operand m = GetIntA32(context, op.Rm);
@@ -240,7 +240,7 @@ namespace ARMeilleure.Instructions

        public static void Smull(ArmEmitterContext context)
        {
-            OpCode32AluUmull op = (OpCode32AluUmull)context.CurrOp;
+            IOpCode32AluUmull op = (IOpCode32AluUmull)context.CurrOp;

            Operand n = context.SignExtend32(OperandType.I64, GetIntA32(context, op.Rn));
            Operand m = context.SignExtend32(OperandType.I64, GetIntA32(context, op.Rm));
@@ -261,7 +261,7 @@ namespace ARMeilleure.Instructions

        public static void Smulw_(ArmEmitterContext context)
        {
-            OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
+            IOpCode32AluMla op = (IOpCode32AluMla)context.CurrOp;

            Operand n = GetIntA32(context, op.Rn);
            Operand m = GetIntA32(context, op.Rm);
@@ -285,7 +285,7 @@ namespace ARMeilleure.Instructions

        public static void Umaal(ArmEmitterContext context)
        {
-            OpCode32AluUmull op = (OpCode32AluUmull)context.CurrOp;
+            IOpCode32AluUmull op = (IOpCode32AluUmull)context.CurrOp;

            Operand n   = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rn));
            Operand m   = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rm));
@@ -310,7 +310,7 @@ namespace ARMeilleure.Instructions

        public static void Umull(ArmEmitterContext context)
        {
-            OpCode32AluUmull op = (OpCode32AluUmull)context.CurrOp;
+            IOpCode32AluUmull op = (IOpCode32AluUmull)context.CurrOp;

            Operand n = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rn));
            Operand m = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rm));
@@ -331,7 +331,7 @@ namespace ARMeilleure.Instructions

        private static void EmitMlal(ArmEmitterContext context, bool signed)
        {
-            OpCode32AluUmull op = (OpCode32AluUmull)context.CurrOp;
+            IOpCode32AluUmull op = (IOpCode32AluUmull)context.CurrOp;

            Operand n = GetIntA32(context, op.Rn);
            Operand m = GetIntA32(context, op.Rm);
--- a/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs
+++ b/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs
@@ -777,6 +777,13 @@ namespace ARMeilleure.Instructions
            }
        }

+        public static void Vmlal_I(ArmEmitterContext context)
+        {
+            OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
+
+            EmitVectorTernaryLongOpI32(context, (d, n, m) => context.Add(d, context.Multiply(n, m)), !op.U);
+        }
+
        public static void Vmls_S(ArmEmitterContext context)
        {
            if (Optimizations.FastFP && Optimizations.UseSse2)
@@ -992,6 +999,13 @@ namespace ARMeilleure.Instructions
            }
        }

+        public static void Vpaddl(ArmEmitterContext context)
+        {
+            OpCode32Simd op = (OpCode32Simd)context.CurrOp;
+
+            EmitVectorPairwiseLongOpI32(context, (op1, op2) => context.Add(op1, op2), (op.Opc & 1) == 0);
+        }
+
        public static void Vpmax_V(ArmEmitterContext context)
        {
            if (Optimizations.FastFP && Optimizations.UseSse2)
@@ -1014,7 +1028,7 @@ namespace ARMeilleure.Instructions
            }
            else
            {
-                EmitVectorPairwiseOpI32(context, (op1, op2) => 
+                EmitVectorPairwiseOpI32(context, (op1, op2) =>
                {
                    Operand greater = op.U ? context.ICompareGreaterUI(op1, op2) : context.ICompareGreater(op1, op2);
                    return context.ConditionalSelect(greater, op1, op2);
@@ -1052,6 +1066,62 @@ namespace ARMeilleure.Instructions
            }
        }

+        public static void Vqadd(ArmEmitterContext context)
+        {
+            OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
+
+            EmitSaturatingAddSubBinaryOp(context, add: true, !op.U);
+        }
+
+        public static void Vqdmulh(ArmEmitterContext context)
+        {
+            OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
+            int eSize = 8 << op.Size;
+
+            EmitVectorBinaryOpI32(context, (op1, op2) =>
+            {
+                if (op.Size == 2)
+                {
+                    op1 = context.SignExtend32(OperandType.I64, op1);
+                    op2 = context.SignExtend32(OperandType.I64, op2);
+                }
+
+                Operand res = context.Multiply(op1, op2);
+                res = context.ShiftRightSI(res, Const(eSize - 1));
+                res = EmitSatQ(context, res, eSize, signedSrc: true, signedDst: true);
+
+                if (op.Size == 2)
+                {
+                    res = context.ConvertI64ToI32(res);
+                }
+
+                return res;
+            }, signed: true);
+        }
+
+        public static void Vqmovn(ArmEmitterContext context)
+        {
+            OpCode32SimdMovn op = (OpCode32SimdMovn)context.CurrOp;
+
+            bool signed = !op.Q;
+
+            EmitVectorUnaryNarrowOp32(context, (op1) => EmitSatQ(context, op1, 8 << op.Size, signed, signed), signed);
+        }
+
+        public static void Vqmovun(ArmEmitterContext context)
+        {
+            OpCode32SimdMovn op = (OpCode32SimdMovn)context.CurrOp;
+
+            EmitVectorUnaryNarrowOp32(context, (op1) => EmitSatQ(context, op1, 8 << op.Size, signedSrc: true, signedDst: false), signed: true);
+        }
+
+        public static void Vqsub(ArmEmitterContext context)
+        {
+            OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
+
+            EmitSaturatingAddSubBinaryOp(context, add: false, !op.U);
+        }
+
        public static void Vrev(ArmEmitterContext context)
        {
            OpCode32SimdRev op = (OpCode32SimdRev)context.CurrOp;
@@ -1202,6 +1272,30 @@ namespace ARMeilleure.Instructions
            }
        }

+        public static void Vrhadd(ArmEmitterContext context)
+        {
+            OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
+
+            EmitVectorBinaryOpI32(context, (op1, op2) =>
+            {
+                if (op.Size == 2)
+                {
+                    op1 = context.ZeroExtend32(OperandType.I64, op1);
+                    op2 = context.ZeroExtend32(OperandType.I64, op2);
+                }
+
+                Operand res = context.Add(context.Add(op1, op2), Const(op1.Type, 1L));
+                res = context.ShiftRightUI(res, Const(1));
+
+                if (op.Size == 2)
+                {
+                    res = context.ConvertI64ToI32(res);
+                }
+
+                return res;
+            }, !op.U);
+        }
+
        public static void Vrsqrte(ArmEmitterContext context)
        {
            OpCode32SimdSqrte op = (OpCode32SimdSqrte)context.CurrOp;
@@ -1349,6 +1443,13 @@ namespace ARMeilleure.Instructions
            }
        }

+        public static void Vsubl_I(ArmEmitterContext context)
+        {
+            OpCode32SimdRegLong op = (OpCode32SimdRegLong)context.CurrOp;
+
+            EmitVectorBinaryLongOpI32(context, (op1, op2) => context.Subtract(op1, op2), !op.U);
+        }
+
        public static void Vsubw_I(ArmEmitterContext context)
        {
            OpCode32SimdRegWide op = (OpCode32SimdRegWide)context.CurrOp;
@@ -1356,6 +1457,46 @@ namespace ARMeilleure.Instructions
            EmitVectorBinaryWideOpI32(context, (op1, op2) => context.Subtract(op1, op2), !op.U);
        }

+        private static void EmitSaturatingAddSubBinaryOp(ArmEmitterContext context, bool add, bool signed)
+        {
+            OpCode32Simd op = (OpCode32Simd)context.CurrOp;
+
+            EmitVectorBinaryOpI32(context, (ne, me) =>
+            {
+                if (op.Size <= 2)
+                {
+                    if (op.Size == 2)
+                    {
+                        ne = signed ? context.SignExtend32(OperandType.I64, ne) : context.ZeroExtend32(OperandType.I64, ne);
+                        me = signed ? context.SignExtend32(OperandType.I64, me) : context.ZeroExtend32(OperandType.I64, me);
+                    }
+
+                    Operand res = add ? context.Add(ne, me) : context.Subtract(ne, me);
+
+                    res = EmitSatQ(context, res, 8 << op.Size, signedSrc: true, signed);
+
+                    if (op.Size == 2)
+                    {
+                        res = context.ConvertI64ToI32(res);
+                    }
+
+                    return res;
+                }
+                else if (add) /* if (op.Size == 3) */
+                {
+                    return signed
+                        ? EmitBinarySignedSatQAdd(context, ne, me)
+                        : EmitBinaryUnsignedSatQAdd(context, ne, me);
+                }
+                else /* if (sub) */
+                {
+                    return signed
+                        ? EmitBinarySignedSatQSub(context, ne, me)
+                        : EmitBinaryUnsignedSatQSub(context, ne, me);
+                }
+            }, signed);
+        }
+
        private static void EmitSse41MaxMinNumOpF32(ArmEmitterContext context, bool isMaxNum, bool scalar)
        {
            IOpCode32Simd op = (IOpCode32Simd)context.CurrOp;
--- a/ARMeilleure/Instructions/InstEmitSimdCvt32.cs
+++ b/ARMeilleure/Instructions/InstEmitSimdCvt32.cs
@@ -323,6 +323,60 @@ namespace ARMeilleure.Instructions
            }
        }

+        // VRINTA (vector).
+        public static void Vrinta_V(ArmEmitterContext context)
+        {
+            EmitVectorUnaryOpF32(context, (m) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, m));
+        }
+
+        // VRINTM (vector).
+        public static void Vrintm_V(ArmEmitterContext context)
+        {
+            if (Optimizations.UseSse2)
+            {
+                EmitVectorUnaryOpSimd32(context, (m) =>
+                {
+                    return context.AddIntrinsic(Intrinsic.X86Roundps, m, Const(X86GetRoundControl(FPRoundingMode.TowardsMinusInfinity)));
+                });
+            }
+            else
+            {
+                EmitVectorUnaryOpF32(context, (m) => EmitUnaryMathCall(context, nameof(Math.Floor), m));
+            }
+        }
+
+        // VRINTN (vector).
+        public static void Vrintn_V(ArmEmitterContext context)
+        {
+            if (Optimizations.UseSse2)
+            {
+                EmitVectorUnaryOpSimd32(context, (m) =>
+                {
+                    return context.AddIntrinsic(Intrinsic.X86Roundps, m, Const(X86GetRoundControl(FPRoundingMode.ToNearest)));
+                });
+            }
+            else
+            {
+                EmitVectorUnaryOpF32(context, (m) => EmitRoundMathCall(context, MidpointRounding.ToEven, m));
+            }
+        }
+
+        // VRINTP (vector).
+        public static void Vrintp_V(ArmEmitterContext context)
+        {
+            if (Optimizations.UseSse2)
+            {
+                EmitVectorUnaryOpSimd32(context, (m) =>
+                {
+                    return context.AddIntrinsic(Intrinsic.X86Roundps, m, Const(X86GetRoundControl(FPRoundingMode.TowardsPlusInfinity)));
+                });
+            }
+            else
+            {
+                EmitVectorUnaryOpF32(context, (m) => EmitUnaryMathCall(context, nameof(Math.Ceiling), m));
+            }
+        }
+
        // VRINTZ (floating-point).
        public static void Vrint_Z(ArmEmitterContext context)
        {
--- a/ARMeilleure/Instructions/InstEmitSimdHelper.cs
+++ b/ARMeilleure/Instructions/InstEmitSimdHelper.cs
@@ -1281,7 +1281,7 @@ namespace ARMeilleure.Instructions

        public static void EmitSseOrAvxExitFtzAndDazModesOpF(ArmEmitterContext context, Operand isTrue = default)
        {
-            isTrue = isTrue == default 
+            isTrue = isTrue == default
                ? context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetFpcrFz)))
                : isTrue;

@@ -1612,7 +1612,7 @@ namespace ARMeilleure.Instructions
        }

        // long BinarySignedSatQAdd(long op1, long op2);
-        private static Operand EmitBinarySignedSatQAdd(ArmEmitterContext context, Operand op1, Operand op2)
+        public static Operand EmitBinarySignedSatQAdd(ArmEmitterContext context, Operand op1, Operand op2)
        {
            Debug.Assert(op1.Type == OperandType.I64 && op2.Type == OperandType.I64);

@@ -1639,7 +1639,7 @@ namespace ARMeilleure.Instructions
        }

        // ulong BinaryUnsignedSatQAdd(ulong op1, ulong op2);
-        private static Operand EmitBinaryUnsignedSatQAdd(ArmEmitterContext context, Operand op1, Operand op2)
+        public static Operand EmitBinaryUnsignedSatQAdd(ArmEmitterContext context, Operand op1, Operand op2)
        {
            Debug.Assert(op1.Type == OperandType.I64 && op2.Type == OperandType.I64);

@@ -1660,7 +1660,7 @@ namespace ARMeilleure.Instructions
        }

        // long BinarySignedSatQSub(long op1, long op2);
-        private static Operand EmitBinarySignedSatQSub(ArmEmitterContext context, Operand op1, Operand op2)
+        public static Operand EmitBinarySignedSatQSub(ArmEmitterContext context, Operand op1, Operand op2)
        {
            Debug.Assert(op1.Type == OperandType.I64 && op2.Type == OperandType.I64);

@@ -1687,7 +1687,7 @@ namespace ARMeilleure.Instructions
        }

        // ulong BinaryUnsignedSatQSub(ulong op1, ulong op2);
-        private static Operand EmitBinaryUnsignedSatQSub(ArmEmitterContext context, Operand op1, Operand op2)
+        public static Operand EmitBinaryUnsignedSatQSub(ArmEmitterContext context, Operand op1, Operand op2)
        {
            Debug.Assert(op1.Type == OperandType.I64 && op2.Type == OperandType.I64);

--- a/ARMeilleure/Instructions/InstEmitSimdHelper32.cs
+++ b/ARMeilleure/Instructions/InstEmitSimdHelper32.cs
@@ -219,6 +219,25 @@ namespace ARMeilleure.Instructions

        // Integer

+        public static void EmitVectorUnaryAccumulateOpI32(ArmEmitterContext context, Func1I emit, bool signed)
+        {
+            OpCode32Simd op = (OpCode32Simd)context.CurrOp;
+
+            Operand res = GetVecA32(op.Qd);
+
+            int elems = op.GetBytesCount() >> op.Size;
+
+            for (int index = 0; index < elems; index++)
+            {
+                Operand de = EmitVectorExtract32(context, op.Qd, op.Id + index, op.Size, signed);
+                Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, signed);
+
+                res = EmitVectorInsert(context, res, context.Add(de, emit(me)), op.Id + index, op.Size);
+            }
+
+            context.Copy(GetVecA32(op.Qd), res);
+        }
+
        public static void EmitVectorUnaryOpI32(ArmEmitterContext context, Func1I emit, bool signed)
        {
            OpCode32Simd op = (OpCode32Simd)context.CurrOp;
@@ -385,6 +404,18 @@ namespace ARMeilleure.Instructions
            EmitVectorUnaryOpI32(context, emit, true);
        }

+        public static void EmitVectorUnaryOpSx32(ArmEmitterContext context, Func1I emit, bool accumulate)
+        {
+            if (accumulate)
+            {
+                EmitVectorUnaryAccumulateOpI32(context, emit, true);
+            }
+            else
+            {
+                EmitVectorUnaryOpI32(context, emit, true);
+            }
+        }
+
        public static void EmitVectorBinaryOpSx32(ArmEmitterContext context, Func2I emit)
        {
            EmitVectorBinaryOpI32(context, emit, true);
@@ -400,6 +431,18 @@ namespace ARMeilleure.Instructions
            EmitVectorUnaryOpI32(context, emit, false);
        }

+        public static void EmitVectorUnaryOpZx32(ArmEmitterContext context, Func1I emit, bool accumulate)
+        {
+            if (accumulate)
+            {
+                EmitVectorUnaryAccumulateOpI32(context, emit, false);
+            }
+            else
+            {
+                EmitVectorUnaryOpI32(context, emit, false);
+            }
+        }
+
        public static void EmitVectorBinaryOpZx32(ArmEmitterContext context, Func2I emit)
        {
            EmitVectorBinaryOpI32(context, emit, false);
@@ -592,6 +635,34 @@ namespace ARMeilleure.Instructions
            context.Copy(GetVecA32(op.Qd), res);
        }

+        public static void EmitVectorPairwiseLongOpI32(ArmEmitterContext context, Func2I emit, bool signed)
+        {
+            OpCode32Simd op = (OpCode32Simd)context.CurrOp;
+
+            int elems = (op.Q ? 16 : 8) >> op.Size;
+            int pairs = elems >> 1;
+            int id = (op.Vd & 1) * pairs;
+
+            Operand res = GetVecA32(op.Qd);
+
+            for (int index = 0; index < pairs; index++)
+            {
+                int pairIndex = index << 1;
+                Operand m1 = EmitVectorExtract32(context, op.Qm, op.Im + pairIndex, op.Size, signed);
+                Operand m2 = EmitVectorExtract32(context, op.Qm, op.Im + pairIndex + 1, op.Size, signed);
+
+                if (op.Size == 2)
+                {
+                    m1 = signed ? context.SignExtend32(OperandType.I64, m1) : context.ZeroExtend32(OperandType.I64, m1);
+                    m2 = signed ? context.SignExtend32(OperandType.I64, m2) : context.ZeroExtend32(OperandType.I64, m2);
+                }
+
+                res = EmitVectorInsert(context, res, emit(m1, m2), id + index, op.Size + 1);
+            }
+
+            context.Copy(GetVecA32(op.Qd), res);
+        }
+
        // Narrow

        public static void EmitVectorUnaryNarrowOp32(ArmEmitterContext context, Func1I emit, bool signed = false)
--- a/ARMeilleure/Instructions/InstEmitSimdMemory32.cs
+++ b/ARMeilleure/Instructions/InstEmitSimdMemory32.cs
@@ -67,7 +67,7 @@ namespace ARMeilleure.Instructions

                for (int i = 0; i < count; i++)
                {
-                    // Write an element from a double simd register.
+                    // Accesses an element from a double simd register.
                    Operand address = context.Add(n, Const(offset));
                    if (eBytes == 8)
                    {
@@ -131,6 +131,7 @@ namespace ARMeilleure.Instructions
            {
                OpCode32SimdMemPair op = (OpCode32SimdMemPair)context.CurrOp;

+                int increment = count > 1 ? op.Increment : 1;
                int eBytes = 1 << op.Size;

                Operand n = context.Copy(GetIntA32(context, op.Rn));
@@ -144,7 +145,7 @@ namespace ARMeilleure.Instructions
                        int elemD = d + reg;
                        for (int i = 0; i < count; i++)
                        {
-                            // Write an element from a double simd register
+                            // Accesses an element from a double simd register,
                            // add ebytes for each element.
                            Operand address = context.Add(n, Const(offset));
                            int index = ((elemD & 1) << (3 - op.Size)) + elem;
@@ -161,7 +162,6 @@ namespace ARMeilleure.Instructions
                            }
                            else
                            {
-
                                if (load)
                                {
                                    EmitLoadSimd(context, address, GetVecA32(elemD >> 1), elemD >> 1, index, op.Size);
@@ -173,7 +173,7 @@ namespace ARMeilleure.Instructions
                            }

                            offset += eBytes;
-                            elemD += op.Increment;
+                            elemD += increment;
                        }
                    }
                }
--- a/ARMeilleure/Instructions/InstEmitSimdShift32.cs
+++ b/ARMeilleure/Instructions/InstEmitSimdShift32.cs
@@ -33,64 +33,24 @@ namespace ARMeilleure.Instructions
            EmitShrImmSaturatingNarrowOp(context, op.U ? ShrImmSaturatingNarrowFlags.VectorZxZx : ShrImmSaturatingNarrowFlags.VectorSxSx);
        }

+        public static void Vqshrun(ArmEmitterContext context)
+        {
+            EmitShrImmSaturatingNarrowOp(context, ShrImmSaturatingNarrowFlags.VectorSxZx);
+        }
+
        public static void Vrshr(ArmEmitterContext context)
        {
-            OpCode32SimdShImm op = (OpCode32SimdShImm)context.CurrOp;
-            int shift = GetImmShr(op);
-            long roundConst = 1L << (shift - 1);
+            EmitRoundShrImmOp(context, accumulate: false);
+        }

-            if (op.U)
-            {
-                if (op.Size < 2)
-                {
-                    EmitVectorUnaryOpZx32(context, (op1) =>
-                    {
-                        op1 = context.Add(op1, Const(op1.Type, roundConst));
+        public static void Vrshrn(ArmEmitterContext context)
+        {
+            EmitRoundShrImmNarrowOp(context, signed: false);
+        }

-                        return context.ShiftRightUI(op1, Const(shift));
-                    });
-                }
-                else if (op.Size == 2)
-                {
-                    EmitVectorUnaryOpZx32(context, (op1) =>
-                    {
-                        op1 = context.ZeroExtend32(OperandType.I64, op1);
-                        op1 = context.Add(op1, Const(op1.Type, roundConst));
-
-                        return context.ConvertI64ToI32(context.ShiftRightUI(op1, Const(shift)));
-                    });
-                }
-                else /* if (op.Size == 3) */
-                {
-                    EmitVectorUnaryOpZx32(context, (op1) => EmitShrImm64(context, op1, signed: false, roundConst, shift));
-                }
-            }
-            else
-            {
-                if (op.Size < 2)
-                {
-                    EmitVectorUnaryOpSx32(context, (op1) =>
-                    {
-                        op1 = context.Add(op1, Const(op1.Type, roundConst));
-
-                        return context.ShiftRightSI(op1, Const(shift));
-                    });
-                }
-                else if (op.Size == 2)
-                {
-                    EmitVectorUnaryOpSx32(context, (op1) =>
-                    {
-                        op1 = context.SignExtend32(OperandType.I64, op1);
-                        op1 = context.Add(op1, Const(op1.Type, roundConst));
-
-                        return context.ConvertI64ToI32(context.ShiftRightSI(op1, Const(shift)));
-                    });
-                }
-                else /* if (op.Size == 3) */
-                {
-                    EmitVectorUnaryOpZx32(context, (op1) => EmitShrImm64(context, op1, signed: true, roundConst, shift));
-                }
-            }
+        public static void Vrsra(ArmEmitterContext context)
+        {
+            EmitRoundShrImmOp(context, accumulate: true);
        }

        public static void Vshl(ArmEmitterContext context)
@@ -191,6 +151,89 @@ namespace ARMeilleure.Instructions
            }
        }

+        public static void EmitRoundShrImmOp(ArmEmitterContext context, bool accumulate)
+        {
+            OpCode32SimdShImm op = (OpCode32SimdShImm)context.CurrOp;
+            int shift = GetImmShr(op);
+            long roundConst = 1L << (shift - 1);
+
+            if (op.U)
+            {
+                if (op.Size < 2)
+                {
+                    EmitVectorUnaryOpZx32(context, (op1) =>
+                    {
+                        op1 = context.Add(op1, Const(op1.Type, roundConst));
+
+                        return context.ShiftRightUI(op1, Const(shift));
+                    }, accumulate);
+                }
+                else if (op.Size == 2)
+                {
+                    EmitVectorUnaryOpZx32(context, (op1) =>
+                    {
+                        op1 = context.ZeroExtend32(OperandType.I64, op1);
+                        op1 = context.Add(op1, Const(op1.Type, roundConst));
+
+                        return context.ConvertI64ToI32(context.ShiftRightUI(op1, Const(shift)));
+                    }, accumulate);
+                }
+                else /* if (op.Size == 3) */
+                {
+                    EmitVectorUnaryOpZx32(context, (op1) => EmitShrImm64(context, op1, signed: false, roundConst, shift), accumulate);
+                }
+            }
+            else
+            {
+                if (op.Size < 2)
+                {
+                    EmitVectorUnaryOpSx32(context, (op1) =>
+                    {
+                        op1 = context.Add(op1, Const(op1.Type, roundConst));
+
+                        return context.ShiftRightSI(op1, Const(shift));
+                    }, accumulate);
+                }
+                else if (op.Size == 2)
+                {
+                    EmitVectorUnaryOpSx32(context, (op1) =>
+                    {
+                        op1 = context.SignExtend32(OperandType.I64, op1);
+                        op1 = context.Add(op1, Const(op1.Type, roundConst));
+
+                        return context.ConvertI64ToI32(context.ShiftRightSI(op1, Const(shift)));
+                    }, accumulate);
+                }
+                else /* if (op.Size == 3) */
+                {
+                    EmitVectorUnaryOpZx32(context, (op1) => EmitShrImm64(context, op1, signed: true, roundConst, shift), accumulate);
+                }
+            }
+        }
+
+        private static void EmitRoundShrImmNarrowOp(ArmEmitterContext context, bool signed)
+        {
+            OpCode32SimdShImm op = (OpCode32SimdShImm)context.CurrOp;
+
+            int shift = GetImmShr(op);
+            long roundConst = 1L << (shift - 1);
+
+            EmitVectorUnaryNarrowOp32(context, (op1) =>
+            {
+                if (op.Size <= 1)
+                {
+                    op1 = context.Add(op1, Const(op1.Type, roundConst));
+                    op1 = signed ? context.ShiftRightSI(op1, Const(shift)) : context.ShiftRightUI(op1, Const(shift));
+                }
+                else /* if (op.Size == 2 && round) */
+                {
+                    op1 = EmitShrImm64(context, op1, signed, roundConst, shift); // shift <= 32
+                }
+
+                return op1;
+            }, signed);
+        }
+
        private static Operand EmitShlRegOp(ArmEmitterContext context, Operand op, Operand shiftLsB, int size, bool unsigned)
        {
            if (shiftLsB.Type == OperandType.I64)
@@ -289,7 +332,7 @@ namespace ARMeilleure.Instructions
                    op1 = EmitShrImm64(context, op1, signedSrc, roundConst, shift); // shift <= 32
                }

-                return EmitSatQ(context, op1, 8 << op.Size, signedDst);
+                return EmitSatQ(context, op1, 8 << op.Size, signedSrc, signedDst);
            }, signedSrc);
        }

@@ -313,15 +356,20 @@ namespace ARMeilleure.Instructions
            return context.Call(info, value, Const(roundConst), Const(shift));
        }

-        private static Operand EmitSatQ(ArmEmitterContext context, Operand value, int eSize, bool signed)
+        private static Operand EmitSatQ(ArmEmitterContext context, Operand value, int eSize, bool signedSrc, bool signedDst)
        {
            Debug.Assert(eSize <= 32);

-            long intMin = signed ? -(1L << (eSize - 1)) : 0;
-            long intMax = signed ? (1L << (eSize - 1)) - 1 : (1L << eSize) - 1;
+            long intMin = signedDst ? -(1L << (eSize - 1)) : 0;
+            long intMax = signedDst ? (1L << (eSize - 1)) - 1 : (1L << eSize) - 1;

-            Operand gt = context.ICompareGreater(value, Const(value.Type, intMax));
-            Operand lt = context.ICompareLess(value, Const(value.Type, intMin));
+            Operand gt = signedSrc
+                ? context.ICompareGreater(value, Const(value.Type, intMax))
+                : context.ICompareGreaterUI(value, Const(value.Type, intMax));
+
+            Operand lt = signedSrc
+                ? context.ICompareLess(value, Const(value.Type, intMin))
+                : context.ICompareLessUI(value, Const(value.Type, intMin));

            value = context.ConditionalSelect(gt, Const(value.Type, intMax), value);
            value = context.ConditionalSelect(lt, Const(value.Type, intMin), value);
--- a/ARMeilleure/Instructions/InstEmitSystem32.cs
+++ b/ARMeilleure/Instructions/InstEmitSystem32.cs
@@ -16,18 +16,13 @@ namespace ARMeilleure.Instructions
        {
            OpCode32System op = (OpCode32System)context.CurrOp;

-            if (op.Coproc != 15)
+            if (op.Coproc != 15 || op.Opc1 != 0)
            {
                InstEmit.Und(context);

                return;
            }

-            if (op.Opc1 != 0)
-            {
-                throw new NotImplementedException($"Unknown MRC Opc1 0x{op.Opc1:X16} at 0x{op.Address:X16}.");
-            }
-
            MethodInfo info;

            switch (op.CRn)
@@ -35,7 +30,7 @@ namespace ARMeilleure.Instructions
                case 13: // Process and Thread Info.
                    if (op.CRm != 0)
                    {
-                        throw new NotImplementedException($"Unknown MRC CRm 0x{op.CRm:X16} at 0x{op.Address:X16}.");
+                        throw new NotImplementedException($"Unknown MRC CRm 0x{op.CRm:X} at 0x{op.Address:X} (0x{op.RawOpCode:X}).");
                    }

                    switch (op.Opc2)
@@ -44,7 +39,7 @@ namespace ARMeilleure.Instructions
                            info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetTpidrEl032)); break;

                        default:
-                            throw new NotImplementedException($"Unknown MRC Opc2 0x{op.Opc2:X16} at 0x{op.Address:X16}.");
+                            throw new NotImplementedException($"Unknown MRC Opc2 0x{op.Opc2:X} at 0x{op.Address:X} (0x{op.RawOpCode:X}).");
                    }

                    break;
@@ -59,11 +54,11 @@ namespace ARMeilleure.Instructions
                                    return; // No-op.

                                default:
-                                    throw new NotImplementedException($"Unknown MRC Opc2 0x{op.Opc2:X16} at 0x{op.Address:X16}.");
+                                    throw new NotImplementedException($"Unknown MRC Opc2 0x{op.Opc2:X16} at 0x{op.Address:X16} (0x{op.RawOpCode:X}).");
                            }

                        default:
-                            throw new NotImplementedException($"Unknown MRC CRm 0x{op.CRm:X16} at 0x{op.Address:X16}.");
+                            throw new NotImplementedException($"Unknown MRC CRm 0x{op.CRm:X16} at 0x{op.Address:X16} (0x{op.RawOpCode:X}).");
                    }

                default:
@@ -77,18 +72,13 @@ namespace ARMeilleure.Instructions
        {
            OpCode32System op = (OpCode32System)context.CurrOp;

-            if (op.Coproc != 15)
+            if (op.Coproc != 15 || op.Opc1 != 0)
            {
                InstEmit.Und(context);

                return;
            }

-            if (op.Opc1 != 0)
-            {
-                throw new NotImplementedException($"Unknown MRC Opc1 0x{op.Opc1:X16} at 0x{op.Address:X16}.");
-            }
-
            MethodInfo info;

            switch (op.CRn)
@@ -96,7 +86,7 @@ namespace ARMeilleure.Instructions
                case 13: // Process and Thread Info.
                    if (op.CRm != 0)
                    {
-                        throw new NotImplementedException($"Unknown MRC CRm 0x{op.CRm:X16} at 0x{op.Address:X16}.");
+                        throw new NotImplementedException($"Unknown MRC CRm 0x{op.CRm:X} at 0x{op.Address:X} (0x{op.RawOpCode:X}).");
                    }

                    switch (op.Opc2)
@@ -108,13 +98,13 @@ namespace ARMeilleure.Instructions
                            info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetTpidr32)); break;

                        default:
-                            throw new NotImplementedException($"Unknown MRC Opc2 0x{op.Opc2:X16} at 0x{op.Address:X16}.");
+                            throw new NotImplementedException($"Unknown MRC Opc2 0x{op.Opc2:X} at 0x{op.Address:X} (0x{op.RawOpCode:X}).");
                    }

                    break;

                default:
-                    throw new NotImplementedException($"Unknown MRC 0x{op.RawOpCode:X8} at 0x{op.Address:X16}.");
+                    throw new NotImplementedException($"Unknown MRC 0x{op.RawOpCode:X} at 0x{op.Address:X}.");
            }

            if (op.Rt == RegisterAlias.Aarch32Pc)
@@ -154,13 +144,13 @@ namespace ARMeilleure.Instructions
                            info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntpctEl0)); break;

                        default:
-                            throw new NotImplementedException($"Unknown MRRC Opc1 0x{opc:X16} at 0x{op.Address:X16}.");
+                            throw new NotImplementedException($"Unknown MRRC Opc1 0x{opc:X} at 0x{op.Address:X} (0x{op.RawOpCode:X}).");
                    }

                    break;

                default:
-                    throw new NotImplementedException($"Unknown MRRC 0x{op.RawOpCode:X8} at 0x{op.Address:X16}.");
+                    throw new NotImplementedException($"Unknown MRRC 0x{op.RawOpCode:X} at 0x{op.Address:X}.");
            }

            Operand result = context.Call(info);
@@ -265,7 +255,7 @@ namespace ARMeilleure.Instructions
                case 0b1000: // FPEXC
                    throw new NotImplementedException("Supervisor Only");
                default:
-                    throw new NotImplementedException($"Unknown VMRS 0x{op.RawOpCode:X8} at 0x{op.Address:X16}.");
+                    throw new NotImplementedException($"Unknown VMRS 0x{op.RawOpCode:X} at 0x{op.Address:X}.");
            }
        }

@@ -288,7 +278,7 @@ namespace ARMeilleure.Instructions
                case 0b1000: // FPEXC
                    throw new NotImplementedException("Supervisor Only");
                default:
-                    throw new NotImplementedException($"Unknown VMSR 0x{op.RawOpCode:X8} at 0x{op.Address:X16}.");
+                    throw new NotImplementedException($"Unknown VMSR 0x{op.RawOpCode:X} at 0x{op.Address:X}.");
            }
        }

--- a/ARMeilleure/Instructions/InstName.cs
+++ b/ARMeilleure/Instructions/InstName.cs
@@ -81,6 +81,7 @@ namespace ARMeilleure.Instructions
        Sbcs,
        Sbfm,
        Sdiv,
+        Sel,
        Shsub8,
        Smaddl,
        Smsubl,
@@ -519,6 +520,7 @@ namespace ARMeilleure.Instructions
        Revsh,
        Rsb,
        Rsc,
+        Sadd8,
        Sbfx,
        Shadd8,
        Smla__,
@@ -529,6 +531,7 @@ namespace ARMeilleure.Instructions
        Smmls,
        Smul__,
        Smmul,
+        Ssub8,
        Stl,
        Stlb,
        Stlex,
@@ -545,9 +548,12 @@ namespace ARMeilleure.Instructions
        Strexh,
        Strh,
        Sxtb16,
+        Tbb,
+        Tbh,
        Teq,
        Trap,
        Tst,
+        Uadd8,
        Ubfx,
        Uhadd8,
        Uhsub8,
@@ -556,6 +562,7 @@ namespace ARMeilleure.Instructions
        Umull,
        Usat,
        Usat16,
+        Usub8,
        Uxtb,
        Uxtb16,
        Uxth,
@@ -601,6 +608,7 @@ namespace ARMeilleure.Instructions
        Vmin,
        Vminnm,
        Vmla,
+        Vmlal,
        Vmls,
        Vmlsl,
        Vmov,
@@ -618,15 +626,28 @@ namespace ARMeilleure.Instructions
        Vorn,
        Vorr,
        Vpadd,
+        Vpaddl,
        Vpmax,
        Vpmin,
+        Vqadd,
+        Vqdmulh,
+        Vqmovn,
+        Vqmovun,
        Vqrshrn,
        Vqrshrun,
        Vqshrn,
+        Vqshrun,
+        Vqsub,
        Vrev,
+        Vrhadd,
        Vrint,
+        Vrinta,
+        Vrintm,
+        Vrintn,
+        Vrintp,
        Vrintx,
        Vrshr,
+        Vrshrn,
        Vsel,
        Vshl,
        Vshll,
@@ -643,8 +664,10 @@ namespace ARMeilleure.Instructions
        Vrecps,
        Vrsqrte,
        Vrsqrts,
+        Vrsra,
        Vsra,
        Vsub,
+        Vsubl,
        Vsubw,
        Vtbl,
        Vtrn,
--- a/ARMeilleure/State/PState.cs
+++ b/ARMeilleure/State/PState.cs
@@ -4,6 +4,10 @@ namespace ARMeilleure.State
    {
        TFlag = 5,
        EFlag = 9,
+        GE0Flag = 16,
+        GE1Flag = 17,
+        GE2Flag = 18,
+        GE3Flag = 19,
        QFlag = 27,
        VFlag = 28,
        CFlag = 29,
--- a/ARMeilleure/Translation/PTC/Ptc.cs
+++ b/ARMeilleure/Translation/PTC/Ptc.cs
@@ -27,7 +27,7 @@ namespace ARMeilleure.Translation.PTC
        private const string OuterHeaderMagicString = "PTCohd\0\0";
        private const string InnerHeaderMagicString = "PTCihd\0\0";

-        private const uint InternalVersion = 3666; //! To be incremented manually for each change to the ARMeilleure project.
+        private const uint InternalVersion = 3695; //! To be incremented manually for each change to the ARMeilleure project.

        private const string ActualDir = "0";
        private const string BackupDir = "1";
--- a/ARMeilleure/Translation/Translator.cs
+++ b/ARMeilleure/Translation/Translator.cs
@@ -44,15 +44,11 @@ namespace ARMeilleure.Translation
        private readonly IJitMemoryAllocator _allocator;
        private readonly ConcurrentQueue<KeyValuePair<ulong, TranslatedFunction>> _oldFuncs;

-        private readonly ConcurrentDictionary<ulong, object> _backgroundSet;
-        private readonly ConcurrentStack<RejitRequest> _backgroundStack;
-        private readonly AutoResetEvent _backgroundTranslatorEvent;
-        private readonly ReaderWriterLock _backgroundTranslatorLock;
-
        internal TranslatorCache<TranslatedFunction> Functions { get; }
        internal AddressTable<ulong> FunctionTable { get; }
        internal EntryTable<uint> CountTable { get; }
        internal TranslatorStubs Stubs { get; }
+        internal TranslatorQueue Queue { get; }
        internal IMemoryManager Memory { get; }

        private volatile int _threadCount;
@@ -67,10 +63,7 @@ namespace ARMeilleure.Translation

            _oldFuncs = new ConcurrentQueue<KeyValuePair<ulong, TranslatedFunction>>();

-            _backgroundSet = new ConcurrentDictionary<ulong, object>();
-            _backgroundStack = new ConcurrentStack<RejitRequest>();
-            _backgroundTranslatorEvent = new AutoResetEvent(false);
-            _backgroundTranslatorLock = new ReaderWriterLock();
+            Queue = new TranslatorQueue();

            JitCache.Initialize(allocator);

@@ -87,43 +80,6 @@ namespace ARMeilleure.Translation
            }
        }

-        private void TranslateStackedSubs()
-        {
-            while (_threadCount != 0)
-            {
-                _backgroundTranslatorLock.AcquireReaderLock(Timeout.Infinite);
-
-                if (_backgroundStack.TryPop(out RejitRequest request) &&
-                    _backgroundSet.TryRemove(request.Address, out _))
-                {
-                    TranslatedFunction func = Translate(request.Address, request.Mode, highCq: true);
-
-                    Functions.AddOrUpdate(request.Address, func.GuestSize, func, (key, oldFunc) =>
-                    {
-                        EnqueueForDeletion(key, oldFunc);
-                        return func;
-                    });
-
-                    if (PtcProfiler.Enabled)
-                    {
-                        PtcProfiler.UpdateEntry(request.Address, request.Mode, highCq: true);
-                    }
-
-                    RegisterFunction(request.Address, func);
-
-                    _backgroundTranslatorLock.ReleaseReaderLock();
-                }
-                else
-                {
-                    _backgroundTranslatorLock.ReleaseReaderLock();
-                    _backgroundTranslatorEvent.WaitOne();
-                }
-            }
-
-             // Wake up any other background translator threads, to encourage them to exit.
-            _backgroundTranslatorEvent.Set();
-        }
-
        public void Execute(State.ExecutionContext context, ulong address)
        {
            if (Interlocked.Increment(ref _threadCount) == 1)
@@ -155,7 +111,7 @@ namespace ARMeilleure.Translation
                {
                    bool last = i != 0 && i == unboundedThreadCount - 1;

-                    Thread backgroundTranslatorThread = new Thread(TranslateStackedSubs)
+                    Thread backgroundTranslatorThread = new Thread(BackgroundTranslate)
                    {
                        Name = "CPU.BackgroundTranslatorThread." + i,
                        Priority = last ? ThreadPriority.Lowest : ThreadPriority.Normal
@@ -186,10 +142,9 @@ namespace ARMeilleure.Translation

            if (Interlocked.Decrement(ref _threadCount) == 0)
            {
-                _backgroundTranslatorEvent.Set();
-
                ClearJitCache();

+                Queue.Dispose();
                Stubs.Dispose();
                FunctionTable.Dispose();
                CountTable.Dispose();
@@ -317,6 +272,27 @@ namespace ARMeilleure.Translation
            return new TranslatedFunction(func, counter, funcSize, highCq);
        }

+        private void BackgroundTranslate()
+        {
+            while (_threadCount != 0 && Queue.TryDequeue(out RejitRequest request))
+            {
+                TranslatedFunction func = Translate(request.Address, request.Mode, highCq: true);
+
+                Functions.AddOrUpdate(request.Address, func.GuestSize, func, (key, oldFunc) =>
+                {
+                    EnqueueForDeletion(key, oldFunc);
+                    return func;
+                });
+
+                if (PtcProfiler.Enabled)
+                {
+                    PtcProfiler.UpdateEntry(request.Address, request.Mode, highCq: true);
+                }
+
+                RegisterFunction(request.Address, func);
+            }
+        }
+
        private struct Range
        {
            public ulong Start { get; }
@@ -504,11 +480,7 @@ namespace ARMeilleure.Translation

        internal void EnqueueForRejit(ulong guestAddress, ExecutionMode mode)
        {
-            if (_backgroundSet.TryAdd(guestAddress, null))
-            {
-                _backgroundStack.Push(new RejitRequest(guestAddress, mode));
-                _backgroundTranslatorEvent.Set();
-            }
+            Queue.Enqueue(guestAddress, mode);
        }

        private void EnqueueForDeletion(ulong guestAddress, TranslatedFunction func)
@@ -542,26 +514,23 @@ namespace ARMeilleure.Translation

        private void ClearRejitQueue(bool allowRequeue)
        {
-            _backgroundTranslatorLock.AcquireWriterLock(Timeout.Infinite);
-
-            if (allowRequeue)
+            if (!allowRequeue)
            {
-                while (_backgroundStack.TryPop(out var request))
+                Queue.Clear();
+
+                return;
+            }
+
+            lock (Queue.Sync)
+            {
+                while (Queue.Count > 0 && Queue.TryDequeue(out RejitRequest request))
                {
                    if (Functions.TryGetValue(request.Address, out var func) && func.CallCounter != null)
                    {
                        Volatile.Write(ref func.CallCounter.Value, 0);
                    }
-
-                    _backgroundSet.TryRemove(request.Address, out _);
                }
            }
-            else
-            {
-                _backgroundStack.Clear();
-            }
-
-            _backgroundTranslatorLock.ReleaseWriterLock();
        }
    }
 }
--- a/ARMeilleure/Translation/TranslatorQueue.cs
+++ b/ARMeilleure/Translation/TranslatorQueue.cs
@@ -0,0 +1,121 @@
+using ARMeilleure.Diagnostics;
+using ARMeilleure.State;
+using System;
+using System.Collections.Generic;
+using System.Threading;
+
+namespace ARMeilleure.Translation
+{
+    /// <summary>
+    /// Represents a queue of <see cref="RejitRequest"/>.
+    /// </summary>
+    /// <remarks>
+    /// This does not necessarily behave like a queue, i.e: a FIFO collection.
+    /// </remarks>
+    sealed class TranslatorQueue : IDisposable
+    {
+        private bool _disposed;
+        private readonly Stack<RejitRequest> _requests;
+        private readonly HashSet<ulong> _requestAddresses;
+
+        /// <summary>
+        /// Gets the object used to synchronize access to the <see cref="TranslatorQueue"/>.
+        /// </summary>
+        public object Sync { get; }
+
+        /// <summary>
+        /// Gets the number of requests in the <see cref="TranslatorQueue"/>.
+        /// </summary>
+        public int Count => _requests.Count;
+
+        /// <summary>
+        /// Initializes a new instance of the <see cref="TranslatorQueue"/> class.
+        /// </summary>
+        public TranslatorQueue()
+        {
+            Sync = new object();
+
+            _requests = new Stack<RejitRequest>();
+            _requestAddresses = new HashSet<ulong>();
+        }
+
+        /// <summary>
+        /// Enqueues a request with the specified <paramref name="address"/> and <paramref name="mode"/>.
+        /// </summary>
+        /// <param name="address">Address of request</param>
+        /// <param name="mode"><see cref="ExecutionMode"/> of request</param>
+        public void Enqueue(ulong address, ExecutionMode mode)
+        {
+            lock (Sync)
+            {
+                if (_requestAddresses.Add(address))
+                {
+                    _requests.Push(new RejitRequest(address, mode));
+
+                    TranslatorEventSource.Log.RejitQueueAdd(1);
+
+                    Monitor.Pulse(Sync);
+                }
+            }
+        }
+
+        /// <summary>
+        /// Tries to dequeue a <see cref="RejitRequest"/>. This will block the thread until a <see cref="RejitRequest"/>
+        /// is enqueued or the <see cref="TranslatorQueue"/> is disposed.
+        /// </summary>
+        /// <param name="result"><see cref="RejitRequest"/> dequeued</param>
+        /// <returns><see langword="true"/> on success; otherwise <see langword="false"/></returns>
+        public bool TryDequeue(out RejitRequest result)
+        {
+            while (!_disposed)
+            {
+                lock (Sync)
+                {
+                    if (_requests.TryPop(out result))
+                    {
+                        _requestAddresses.Remove(result.Address);
+
+                        TranslatorEventSource.Log.RejitQueueAdd(-1);
+
+                        return true;
+                    }
+
+                    Monitor.Wait(Sync);
+                }
+            }
+
+            result = default;
+
+            return false;
+        }
+
+        /// <summary>
+        /// Clears the <see cref="TranslatorQueue"/>.
+        /// </summary>
+        public void Clear()
+        {
+            lock (Sync)
+            {
+                TranslatorEventSource.Log.RejitQueueAdd(-_requests.Count);
+
+                _requests.Clear();
+                _requestAddresses.Clear();
+
+                Monitor.PulseAll(Sync);
+            }
+        }
+
+        /// <summary>
+        /// Releases all resources used by the <see cref="TranslatorQueue"/> instance.
+        /// </summary>
+        public void Dispose()
+        {
+            if (!_disposed)
+            {
+                _disposed = true;
+
+                Clear();
+            }
+        }
+    }
+}
--- a/README.md
+++ b/README.md
@@ -36,8 +36,8 @@

 ## Compatibility

-As of January 2022, Ryujinx has been tested on approximately 3,500 titles; over 3,200 boot past menus and into gameplay, with roughly 2,500 of those being considered playable.
-You can check out the compatibility list [here](https://github.com/Ryujinx/Ryujinx-Games-List/issues). Anyone is free to submit an updated test on an existing game entry; simply follow the new issue template and testing guidelines, or post as a reply to the applicable game issue. Use the search function to see if a game has been tested already!
+As of September 2022, Ryujinx has been tested on approximately 3,600 titles; over 3,400 boot past menus and into gameplay, with roughly 2,700 of those being considered playable. You can check out the compatibility list [here](https://github.com/Ryujinx/Ryujinx-Games-List/issues).  
+Anyone is free to submit a new game test or update an existing game test entry; simply follow the new issue template and testing guidelines, or post as a reply to the applicable game issue. Use the search function to see if a game has been tested already!

 ## Usage

@@ -118,11 +118,11 @@ If you'd like to support the project financially, Ryujinx has an active Patreon
    <img src="https://images.squarespace-cdn.com/content/v1/560c1d39e4b0b4fae0c9cf2a/1567548955044-WVD994WZP76EWF15T0L3/Patreon+Button.png?format=500w" width="150">
 </a>

-All the developers working on the project do so on their free time, but the project has several expenses:
+All developers working on the project do so in their free time, but the project has several expenses:
 * Hackable Nintendo Switch consoles to reverse-engineer the hardware
 * Additional computer hardware for testing purposes (e.g. GPUs to diagnose graphical bugs, etc.)
-* Licenses for various software development tools (e.g. Jetbrains, LDN servers, IDA)
-* Web hosting and infrastructure maintenance
+* Licenses for various software development tools (e.g. Jetbrains, IDA)
+* Web hosting and infrastructure maintenance (e.g. LDN servers)

 All funds received through Patreon are considered a donation to support the project. Patrons receive early access to progress reports and exclusive access to developer interviews.

--- a/Ryujinx.Audio/Renderer/Server/AudioRenderSystem.cs
+++ b/Ryujinx.Audio/Renderer/Server/AudioRenderSystem.cs
@@ -55,7 +55,6 @@ namespace Ryujinx.Audio.Renderer.Server
        private uint _processHandle;
        private ulong _appletResourceId;

-        private WritableRegion _workBufferRegion;
        private MemoryHandle _workBufferMemoryPin;

        private Memory<float> _mixBuffer;
@@ -98,7 +97,15 @@ namespace Ryujinx.Audio.Renderer.Server
            _sessionId = 0;
        }

-        public ResultCode Initialize(ref AudioRendererConfiguration parameter, uint processHandle, CpuAddress workBuffer, ulong workBufferSize, int sessionId, ulong appletResourceId, IVirtualMemoryManager memoryManager)
+        public ResultCode Initialize(
+            ref AudioRendererConfiguration parameter,
+            uint processHandle,
+            Memory<byte> workBufferMemory,
+            CpuAddress workBuffer,
+            ulong workBufferSize,
+            int sessionId,
+            ulong appletResourceId,
+            IVirtualMemoryManager memoryManager)
        {
            if (!BehaviourContext.CheckValidRevision(parameter.Revision))
            {
@@ -134,11 +141,10 @@ namespace Ryujinx.Audio.Renderer.Server

            WorkBufferAllocator workBufferAllocator;

-            _workBufferRegion = MemoryManager.GetWritableRegion(workBuffer, (int)workBufferSize);
-            _workBufferRegion.Memory.Span.Fill(0);
-            _workBufferMemoryPin = _workBufferRegion.Memory.Pin();
+            workBufferMemory.Span.Fill(0);
+            _workBufferMemoryPin = workBufferMemory.Pin();

-            workBufferAllocator = new WorkBufferAllocator(_workBufferRegion.Memory);
+            workBufferAllocator = new WorkBufferAllocator(workBufferMemory);

            PoolMapper poolMapper = new PoolMapper(processHandle, false);
            poolMapper.InitializeSystemPool(ref _dspMemoryPoolState, workBuffer, workBufferSize);
@@ -841,7 +847,6 @@ namespace Ryujinx.Audio.Renderer.Server
                _manager.Unregister(this);
                _terminationEvent.Dispose();
                _workBufferMemoryPin.Dispose();
-                _workBufferRegion.Dispose();

                if (MemoryManager is IRefCounted rc)
                {
--- a/Ryujinx.Audio/Renderer/Server/AudioRendererManager.cs
+++ b/Ryujinx.Audio/Renderer/Server/AudioRendererManager.cs
@@ -305,13 +305,34 @@ namespace Ryujinx.Audio.Renderer.Server
        /// <param name="workBufferSize">The guest work buffer size.</param>
        /// <param name="processHandle">The process handle of the application.</param>
        /// <returns>A <see cref="ResultCode"/> reporting an error or a success.</returns>
-        public ResultCode OpenAudioRenderer(out AudioRenderSystem renderer, IVirtualMemoryManager memoryManager, ref AudioRendererConfiguration parameter, ulong appletResourceUserId, ulong workBufferAddress, ulong workBufferSize, uint processHandle, float volume)
+        public ResultCode OpenAudioRenderer(
+            out AudioRenderSystem renderer,
+            IVirtualMemoryManager memoryManager,
+            ref AudioRendererConfiguration parameter,
+            ulong appletResourceUserId,
+            ulong workBufferAddress,
+            ulong workBufferSize,
+            uint processHandle,
+            float volume)
        {
            int sessionId = AcquireSessionId();

            AudioRenderSystem audioRenderer = new AudioRenderSystem(this, _sessionsSystemEvent[sessionId]);

-            ResultCode result = audioRenderer.Initialize(ref parameter, processHandle, workBufferAddress, workBufferSize, sessionId, appletResourceUserId, memoryManager);
+            // TODO: Eventually, we should try to use the guest supplied work buffer instead of allocating
+            // our own. However, it was causing problems on some applications that would unmap the memory
+            // before the audio renderer was fully disposed.
+            Memory<byte> workBufferMemory = GC.AllocateArray<byte>((int)workBufferSize, pinned: true);
+
+            ResultCode result = audioRenderer.Initialize(
+                ref parameter,
+                processHandle,
+                workBufferMemory,
+                workBufferAddress,
+                workBufferSize,
+                sessionId,
+                appletResourceUserId,
+                memoryManager);

            if (result == ResultCode.Success)
            {
--- a/Ryujinx.Common/Collections/IntrusiveRedBlackTreeNode.cs
+++ b/Ryujinx.Common/Collections/IntrusiveRedBlackTreeNode.cs
@@ -5,10 +5,10 @@ namespace Ryujinx.Common.Collections
    /// </summary>
    public class IntrusiveRedBlackTreeNode<T> where T : IntrusiveRedBlackTreeNode<T>
    {
-        public bool Color = true;
-        public T Left;
-        public T Right;
-        public T Parent;
+        internal bool Color = true;
+        internal T Left;
+        internal T Right;
+        internal T Parent;

        public T Predecessor => IntrusiveRedBlackTreeImpl<T>.PredecessorOf((T)this);
        public T Successor => IntrusiveRedBlackTreeImpl<T>.SuccessorOf((T)this);
--- a/Ryujinx.Cpu/Jit/MemoryManagerHostMapped.cs
+++ b/Ryujinx.Cpu/Jit/MemoryManagerHostMapped.cs
@@ -274,7 +274,8 @@ namespace Ryujinx.Cpu.Jit
        /// <inheritdoc/>
        public void Write(ulong va, ReadOnlySpan<byte> data)
        {
-            try {
+            try
+            {
                SignalMemoryTracking(va, (ulong)data.Length, write: true);

                _addressSpaceMirror.Write(va, data);
--- a/Ryujinx.Graphics.GAL/Capabilities.cs
+++ b/Ryujinx.Graphics.GAL/Capabilities.cs
@@ -26,6 +26,7 @@ namespace Ryujinx.Graphics.GAL
        public readonly bool SupportsNonConstantTextureOffset;
        public readonly bool SupportsShaderBallot;
        public readonly bool SupportsTextureShadowLod;
+        public readonly bool SupportsViewportIndex;
        public readonly bool SupportsViewportSwizzle;
        public readonly bool SupportsIndirectParameters;

@@ -59,6 +60,7 @@ namespace Ryujinx.Graphics.GAL
            bool supportsNonConstantTextureOffset,
            bool supportsShaderBallot,
            bool supportsTextureShadowLod,
+            bool supportsViewportIndex,
            bool supportsViewportSwizzle,
            bool supportsIndirectParameters,
            uint maximumUniformBuffersPerStage,
@@ -89,6 +91,7 @@ namespace Ryujinx.Graphics.GAL
            SupportsNonConstantTextureOffset = supportsNonConstantTextureOffset;
            SupportsShaderBallot = supportsShaderBallot;
            SupportsTextureShadowLod = supportsTextureShadowLod;
+            SupportsViewportIndex = supportsViewportIndex;
            SupportsViewportSwizzle = supportsViewportSwizzle;
            SupportsIndirectParameters = supportsIndirectParameters;
            MaximumUniformBuffersPerStage = maximumUniformBuffersPerStage;
--- a/Ryujinx.Graphics.GAL/Format.cs
+++ b/Ryujinx.Graphics.GAL/Format.cs
@@ -151,6 +151,190 @@ namespace Ryujinx.Graphics.GAL

    public static class FormatExtensions
    {
+        /// <summary>
+        /// The largest scalar size for a buffer format.
+        /// </summary>
+        public const int MaxBufferFormatScalarSize = 4;
+
+        /// <summary>
+        /// Gets the byte size for a single component of this format, or its packed size.
+        /// </summary>
+        /// <param name="format">Texture format</param>
+        /// <returns>Byte size for a single component, or packed size</returns>
+        public static int GetScalarSize(this Format format)
+        {
+            switch (format)
+            {
+                case Format.R8Unorm:
+                case Format.R8Snorm:
+                case Format.R8Uint:
+                case Format.R8Sint:
+                case Format.R8G8Unorm:
+                case Format.R8G8Snorm:
+                case Format.R8G8Uint:
+                case Format.R8G8Sint:
+                case Format.R8G8B8Unorm:
+                case Format.R8G8B8Snorm:
+                case Format.R8G8B8Uint:
+                case Format.R8G8B8Sint:
+                case Format.R8G8B8A8Unorm:
+                case Format.R8G8B8A8Snorm:
+                case Format.R8G8B8A8Uint:
+                case Format.R8G8B8A8Sint:
+                case Format.R8G8B8A8Srgb:
+                case Format.R4G4Unorm:
+                case Format.R8Uscaled:
+                case Format.R8Sscaled:
+                case Format.R8G8Uscaled:
+                case Format.R8G8Sscaled:
+                case Format.R8G8B8Uscaled:
+                case Format.R8G8B8Sscaled:
+                case Format.R8G8B8A8Uscaled:
+                case Format.R8G8B8A8Sscaled:
+                case Format.B8G8R8A8Unorm:
+                case Format.B8G8R8A8Srgb:
+                    return 1;
+
+                case Format.R16Float:
+                case Format.R16Unorm:
+                case Format.R16Snorm:
+                case Format.R16Uint:
+                case Format.R16Sint:
+                case Format.R16G16Float:
+                case Format.R16G16Unorm:
+                case Format.R16G16Snorm:
+                case Format.R16G16Uint:
+                case Format.R16G16Sint:
+                case Format.R16G16B16Float:
+                case Format.R16G16B16Unorm:
+                case Format.R16G16B16Snorm:
+                case Format.R16G16B16Uint:
+                case Format.R16G16B16Sint:
+                case Format.R16G16B16A16Float:
+                case Format.R16G16B16A16Unorm:
+                case Format.R16G16B16A16Snorm:
+                case Format.R16G16B16A16Uint:
+                case Format.R16G16B16A16Sint:
+                case Format.R4G4B4A4Unorm:
+                case Format.R5G5B5X1Unorm:
+                case Format.R5G5B5A1Unorm:
+                case Format.R5G6B5Unorm:
+                case Format.R16Uscaled:
+                case Format.R16Sscaled:
+                case Format.R16G16Uscaled:
+                case Format.R16G16Sscaled:
+                case Format.R16G16B16Uscaled:
+                case Format.R16G16B16Sscaled:
+                case Format.R16G16B16A16Uscaled:
+                case Format.R16G16B16A16Sscaled:
+                case Format.B5G6R5Unorm:
+                case Format.B5G5R5A1Unorm:
+                case Format.A1B5G5R5Unorm:
+                    return 2;
+
+                case Format.R32Float:
+                case Format.R32Uint:
+                case Format.R32Sint:
+                case Format.R32G32Float:
+                case Format.R32G32Uint:
+                case Format.R32G32Sint:
+                case Format.R32G32B32Float:
+                case Format.R32G32B32Uint:
+                case Format.R32G32B32Sint:
+                case Format.R32G32B32A32Float:
+                case Format.R32G32B32A32Uint:
+                case Format.R32G32B32A32Sint:
+                case Format.R10G10B10A2Unorm:
+                case Format.R10G10B10A2Uint:
+                case Format.R11G11B10Float:
+                case Format.R9G9B9E5Float:
+                case Format.R32Uscaled:
+                case Format.R32Sscaled:
+                case Format.R32G32Uscaled:
+                case Format.R32G32Sscaled:
+                case Format.R32G32B32Uscaled:
+                case Format.R32G32B32Sscaled:
+                case Format.R32G32B32A32Uscaled:
+                case Format.R32G32B32A32Sscaled:
+                case Format.R10G10B10A2Snorm:
+                case Format.R10G10B10A2Sint:
+                case Format.R10G10B10A2Uscaled:
+                case Format.R10G10B10A2Sscaled:
+                    return 4;
+
+                case Format.S8Uint:
+                    return 1;
+                case Format.D16Unorm:
+                    return 2;
+                case Format.S8UintD24Unorm:
+                case Format.D32Float:
+                case Format.D24UnormS8Uint:
+                    return 4;
+                case Format.D32FloatS8Uint:
+                    return 8;
+
+                case Format.Bc1RgbaUnorm:
+                case Format.Bc1RgbaSrgb:
+                    return 8;
+
+                case Format.Bc2Unorm:
+                case Format.Bc3Unorm:
+                case Format.Bc2Srgb:
+                case Format.Bc3Srgb:
+                case Format.Bc4Unorm:
+                case Format.Bc4Snorm:
+                case Format.Bc5Unorm:
+                case Format.Bc5Snorm:
+                case Format.Bc7Unorm:
+                case Format.Bc7Srgb:
+                case Format.Bc6HSfloat:
+                case Format.Bc6HUfloat:
+                    return 16;
+
+                case Format.Etc2RgbUnorm:
+                case Format.Etc2RgbPtaUnorm:
+                case Format.Etc2RgbSrgb:
+                case Format.Etc2RgbPtaSrgb:
+                    return 8;
+
+                case Format.Etc2RgbaUnorm:
+                case Format.Etc2RgbaSrgb:
+                    return 16;
+
+                case Format.Astc4x4Unorm:
+                case Format.Astc5x4Unorm:
+                case Format.Astc5x5Unorm:
+                case Format.Astc6x5Unorm:
+                case Format.Astc6x6Unorm:
+                case Format.Astc8x5Unorm:
+                case Format.Astc8x6Unorm:
+                case Format.Astc8x8Unorm:
+                case Format.Astc10x5Unorm:
+                case Format.Astc10x6Unorm:
+                case Format.Astc10x8Unorm:
+                case Format.Astc10x10Unorm:
+                case Format.Astc12x10Unorm:
+                case Format.Astc12x12Unorm:
+                case Format.Astc4x4Srgb:
+                case Format.Astc5x4Srgb:
+                case Format.Astc5x5Srgb:
+                case Format.Astc6x5Srgb:
+                case Format.Astc6x6Srgb:
+                case Format.Astc8x5Srgb:
+                case Format.Astc8x6Srgb:
+                case Format.Astc8x8Srgb:
+                case Format.Astc10x5Srgb:
+                case Format.Astc10x6Srgb:
+                case Format.Astc10x8Srgb:
+                case Format.Astc10x10Srgb:
+                case Format.Astc12x10Srgb:
+                case Format.Astc12x12Srgb:
+                    return 16;
+            }
+
+            return 1;
+        }
+
        /// <summary>
        /// Checks if the texture format is valid to use as image format.
        /// </summary>
--- a/Ryujinx.Graphics.Gpu/Engine/Threed/SemaphoreUpdater.cs
+++ b/Ryujinx.Graphics.Gpu/Engine/Threed/SemaphoreUpdater.cs
@@ -1,4 +1,5 @@
 using Ryujinx.Graphics.GAL;
+using System;

 namespace Ryujinx.Graphics.Gpu.Engine.Threed
 {
@@ -151,10 +152,21 @@ namespace Ryujinx.Graphics.Gpu.Engine.Threed

            ulong ticks = _context.GetTimestamp();

+            float divisor = type switch
+            {
+                ReportCounterType.SamplesPassed => _channel.TextureManager.RenderTargetScale * _channel.TextureManager.RenderTargetScale,
+                _ => 1f
+            };
+
            ICounterEvent counter = null;

            void resultHandler(object evt, ulong result)
            {
+                if (divisor != 1f)
+                {
+                    result = (ulong)MathF.Ceiling(result / divisor);
+                }
+
                CounterData counterData = new CounterData
                {
                    Counter = result,
--- a/Ryujinx.Graphics.Gpu/Image/TextureBindingsManager.cs
+++ b/Ryujinx.Graphics.Gpu/Image/TextureBindingsManager.cs
@@ -47,6 +47,7 @@ namespace Ryujinx.Graphics.Gpu.Image

            public int TextureHandle;
            public int SamplerHandle;
+            public Format ImageFormat;
            public int InvalidatedSequence;
            public Texture CachedTexture;
            public Sampler CachedSampler;
@@ -564,6 +565,9 @@ namespace Ryujinx.Graphics.Gpu.Image
                    // Buffers are frequently re-created to accomodate larger data, so we need to re-bind
                    // to ensure we're not using a old buffer that was already deleted.
                    _channel.BufferManager.SetBufferTextureStorage(stage, hostTexture, texture.Range.GetSubRange(0).Address, texture.Size, bindingInfo, bindingInfo.Format, false);
+
+                    // Cache is not used for buffer texture, it must always rebind.
+                    state.CachedTexture = null;
                }
                else
                {
@@ -659,14 +663,16 @@ namespace Ryujinx.Graphics.Gpu.Image
                        cachedTexture?.SignalModified();
                    }

-                    if ((usageFlags & TextureUsageFlags.NeedsScaleValue) != 0 &&
-                        UpdateScale(state.CachedTexture, usageFlags, scaleIndex, stage))
+                    Format format = bindingInfo.Format == 0 ? cachedTexture.Format : bindingInfo.Format;
+
+                    if (state.ImageFormat != format ||
+                        ((usageFlags & TextureUsageFlags.NeedsScaleValue) != 0 &&
+                        UpdateScale(state.CachedTexture, usageFlags, scaleIndex, stage)))
                    {
                        ITexture hostTextureRebind = state.CachedTexture.GetTargetTexture(bindingInfo.Target);

-                        Format format = bindingInfo.Format == 0 ? cachedTexture.Format : bindingInfo.Format;
-
                        state.Texture = hostTextureRebind;
+                        state.ImageFormat = format;

                        _context.Renderer.Pipeline.SetImage(bindingInfo.Binding, hostTextureRebind, format);
                    }
@@ -696,6 +702,9 @@ namespace Ryujinx.Graphics.Gpu.Image
                    }

                    _channel.BufferManager.SetBufferTextureStorage(stage, hostTexture, texture.Range.GetSubRange(0).Address, texture.Size, bindingInfo, format, true);
+
+                    // Cache is not used for buffer texture, it must always rebind.
+                    state.CachedTexture = null;
                }
                else
                {
@@ -721,6 +730,8 @@ namespace Ryujinx.Graphics.Gpu.Image
                            format = texture.Format;
                        }

+                        state.ImageFormat = format;
+
                        _context.Renderer.Pipeline.SetImage(bindingInfo.Binding, hostTexture, format);
                    }

--- a/Ryujinx.Graphics.Gpu/Shader/DiskCache/DiskCacheHostStorage.cs
+++ b/Ryujinx.Graphics.Gpu/Shader/DiskCache/DiskCacheHostStorage.cs
@@ -22,7 +22,7 @@ namespace Ryujinx.Graphics.Gpu.Shader.DiskCache
        private const ushort FileFormatVersionMajor = 1;
        private const ushort FileFormatVersionMinor = 2;
        private const uint FileFormatVersionPacked = ((uint)FileFormatVersionMajor << 16) | FileFormatVersionMinor;
-        private const uint CodeGenVersion = 3672;
+        private const uint CodeGenVersion = 3697;

        private const string SharedTocFileName = "shared.toc";
        private const string SharedDataFileName = "shared.data";
@@ -827,4 +827,4 @@ namespace Ryujinx.Graphics.Gpu.Shader.DiskCache
            }
        }
    }
-}
+}
--- a/Ryujinx.Graphics.Gpu/Shader/GpuAccessorBase.cs
+++ b/Ryujinx.Graphics.Gpu/Shader/GpuAccessorBase.cs
@@ -134,6 +134,8 @@ namespace Ryujinx.Graphics.Gpu.Shader

        public bool QueryHostSupportsTextureShadowLod() => _context.Capabilities.SupportsTextureShadowLod;

+        public bool QueryHostSupportsViewportIndex() => _context.Capabilities.SupportsViewportIndex;
+
        /// <summary>
        /// Converts a packed Maxwell texture format to the shader translator texture format.
        /// </summary>
--- a/Ryujinx.Graphics.OpenGL/OpenGLRenderer.cs
+++ b/Ryujinx.Graphics.OpenGL/OpenGLRenderer.cs
@@ -120,6 +120,7 @@ namespace Ryujinx.Graphics.OpenGL
                supportsNonConstantTextureOffset: HwCapabilities.SupportsNonConstantTextureOffset,
                supportsShaderBallot: HwCapabilities.SupportsShaderBallot,
                supportsTextureShadowLod: HwCapabilities.SupportsTextureShadowLod,
+                supportsViewportIndex: true,
                supportsViewportSwizzle: HwCapabilities.SupportsViewportSwizzle,
                supportsIndirectParameters: HwCapabilities.SupportsIndirectParameters,
                maximumUniformBuffersPerStage: 13, // TODO: Avoid hardcoding those limits here and get from driver?
--- a/Ryujinx.Graphics.Shader/IGpuAccessor.cs
+++ b/Ryujinx.Graphics.Shader/IGpuAccessor.cs
@@ -267,6 +267,15 @@ namespace Ryujinx.Graphics.Shader
            return true;
        }

+        /// <summary>
+        /// Queries host GPU shader viewport index output support.
+        /// </summary>
+        /// <returns>True if the GPU and driver supports shader viewport index output, false otherwise</returns>
+        bool QueryHostSupportsViewportIndex()
+        {
+            return true;
+        }
+
        /// <summary>
        /// Queries the point size from the GPU state, used when it is not explicitly set on the shader.
        /// </summary>
--- a/Ryujinx.Graphics.Shader/Instructions/InstEmitTexture.cs
+++ b/Ryujinx.Graphics.Shader/Instructions/InstEmitTexture.cs
@@ -16,7 +16,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
            { 0b0111, 0b1011, 0b1101, 0b1110, 0b1111, 0b0000, 0b0000, 0b0000 }
        };

-        private const bool Sample1DAs2D = true;
+        public const bool Sample1DAs2D = true;

        private enum TexsType
        {
--- a/Ryujinx.Graphics.Shader/IntermediateRepresentation/Operation.cs
+++ b/Ryujinx.Graphics.Shader/IntermediateRepresentation/Operation.cs
@@ -180,6 +180,18 @@ namespace Ryujinx.Graphics.Shader.IntermediateRepresentation
            _sources[index] = source;
        }

+        public void InsertSource(int index, Operand source)
+        {
+            Operand[] newSources = new Operand[_sources.Length + 1];
+
+            Array.Copy(_sources, 0, newSources, 0, index);
+            Array.Copy(_sources, index, newSources, index + 1, _sources.Length - index);
+
+            newSources[index] = source;
+
+            _sources = newSources;
+        }
+
        protected void RemoveSource(int index)
        {
            SetSource(index, null);
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
gdkchan	8e119a1e96	Implement PLD and SUB (imm16) on T32, plus UADD8, SADD8, USUB8 and SSUB8 on both A32 and T32 (#3693 )	2022-09-13 19:51:40 -03:00
merry	e05bf90af6	T32: Implement Asimd instructions (#3692 )	2022-09-13 18:25:37 -03:00
gdkchan	66f16f4392	Fix bindless 1D textures having a buffer type on the shader (#3697 ) * Fix bindless 1D textures having a buffer type on the shader * Shader cache version bump	2022-09-13 08:53:55 +02:00
gdkchan	729ff5337c	Fix increment on Arm32 NEON VLDn/VSTn instructions with regs > 1 (#3695 ) * Fix increment on Arm32 NEON VLDn/VSTn instructions with regs > 1 * PPTC version bump * PR feedback	2022-09-13 08:24:09 +02:00
gdkchan	2492e7e808	Fix R4G4B4A4 format on Vulkan (#3696 )	2022-09-13 07:59:38 +02:00
riperiperi	36172ab43b	Scale SamplesPassed counter by RT scale on report (#3680 ) * Scale SamplesPassed counter by RT scale on report Adds a scale factor for samples passed counter report based on the render target scale at the time. This ensures that when a game reads this counter, it appears similar to the result at 1x. This doesn't cover cases where the the render target scale changes during the queried draws, though that might be better to handle along with other scope related issues in a future rework of counters. Games generally don't count for occlusion queries over render target changes anyways. Fixes an issue in the Splatoon games where the special charge would scale too quickly at high res, points at the end of the game would be broken (but still provide a correct winner), and playing at a low res would make it impossible to swim in ink. May also affect LOD scaling in The Witcher 3. * Update Ryujinx.Graphics.Gpu/Engine/Threed/SemaphoreUpdater.cs Co-authored-by: gdkchan <gab.dark.100@gmail.com> Co-authored-by: gdkchan <gab.dark.100@gmail.com>	2022-09-11 15:58:15 +00:00
gdkchan	4d69286a9c	Implement VRINT (vector) Arm32 NEON instructions (#3691 )	2022-09-11 15:44:27 +00:00
merry	1529e6cf0d	T32: Add Vfp instructions (#3690 )	2022-09-10 23:03:14 -03:00
gdkchan	f468db7602	Implement Thumb (32-bit) memory (ordered), multiply, extension and bitfield instructions (#3687 ) * Implement Thumb (32-bit) memory (ordered), multiply and bitfield instructions * Remove public from interface * Fix T32 BL immediate and implement signed and unsigned extend instructions	2022-09-10 22:51:00 -03:00
gdk	c5f1d1749a	Revert address space mirror changes	2022-09-10 16:23:49 +02:00
gdk	7dd69f2d0e	Allocation free tree lookup	2022-09-10 16:23:49 +02:00
gdk	c646638680	Update several methods to use GetNode directly and avoid array allocations	2022-09-10 16:23:49 +02:00
gdk	65f2a82b97	Optimize PlaceholderManager.UnreserveRange	2022-09-10 16:23:49 +02:00
gdk	93dd6d525a	Fix potential issue with partial unmap We must also do the unmap operation with the RWLock, otherwise faults on the unmapped region will cause crashes and the whole thing becomes pointless	2022-09-10 16:23:49 +02:00
gdk	96d4ad952c	Fix reprotection regression	2022-09-10 16:23:49 +02:00
gdk	6a07f80b76	Make RBTree node fields internal again Prevents someone from accidentaly messing with them and leaving the tree in a invalid state	2022-09-10 16:23:49 +02:00
gdk	22214ac664	Delete unused code	2022-09-10 16:23:49 +02:00
gdk	45e520a27c	Rewrite PlaceholderManager4KB to use intrusive RBTree, and to coalesce free placeholders Also make the other placeholder manager use intrusive RBTree, allows the IntervalTree that was added just for this to be deleted	2022-09-10 16:23:49 +02:00
gdk	5b5810a46a	Defer address space mirror mapping and use it only if strictly needed	2022-09-10 16:23:49 +02:00
gdkchan	619ac86bd0	Do not output ViewportIndex on SPIR-V if GPU does not support it (#3644 ) * Do not output ViewportIndex on SPIR-V if GPU does not support it * Bump shader cache version	2022-09-10 13:20:23 +00:00
EmulationFanatic	7a1ab71c73	Update README.MD verbiage and compatibility	2022-09-10 15:07:37 +02:00
riperiperi	dc4ba3993b	Rebind textures if format changes or they're buffer textures	2022-09-10 14:12:50 +02:00
gdkchan	81f1a4dc31	Allocate work buffer for audio renderer instead of using guest supplied memory (#3276 ) * Allocate work buffer for audio renderer instead of using guest supplied memory * Typo * Use GC.AllocateArray to allocate pinned array	2022-09-10 01:16:24 +00:00
gdkchan	c64524a240	Add ADD (zx imm12), NOP, MOV (rs), LDA, TBB, TBH, MOV (zx imm16) and CLZ thumb instructions (#3683 ) * Add ADD (zx imm12), NOP, MOV (register shifted), LDA, TBB, TBH, MOV (zx imm16) and CLZ thumb instructions, fix LDRD, STRD, CBZ, CBNZ and BLX (reg) * Bump PPTC version	2022-09-09 22:09:11 -03:00
gdkchan	db45688aa8	Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions (#3677 ) * Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPADDL, VSUBL, VQDMULH and VMLAL Arm32 NEON instructions * PPTC version * Fix VQADD/VQSUB * Improve MRC/MCR handling and exception messages In case data is being recompiled as code, we don't want to throw at emit stage, instead we should only throw if it actually tries to execute	2022-09-09 21:47:38 -03:00
riperiperi	c6d82209ab	Restride vertex buffer when stride causes attributes to misalign in Vulkan. (#3679 ) * Vertex Buffer Alignment part 1 * Update CacheByRange * Add Stride Change compute shader, fix storage buffers in helpers * An AMD exclusive * Reword * Change rules - stride conversion when attrs misalign * Fix stupid mistake * Fix background pipeline compile * Improve a few things. * Fix some feedback * Address Feedback (the shader binary didn't change when i changed the source to use the subgroup size) * Fix bug where rewritten buffer would be disposed instantly.	2022-09-08 20:30:19 -03:00
FICTURE7	ee1825219b	Clean up rejit queue (#2751 )	2022-09-08 20:14:08 -03:00