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2
.github/ISSUE_TEMPLATE/bug_report.md
vendored
2
.github/ISSUE_TEMPLATE/bug_report.md
vendored
@@ -1,6 +1,6 @@
|
||||
---
|
||||
name: Bug Report
|
||||
about: Something doesn't work correctly in Ryujinx.
|
||||
about: Something doesn't work correctly in Ryujinx. Note that game-specific issues should be instead posted on the Game Compatibility List at https://github.com/Ryujinx/Ryujinx-Games-List, unless it is a provable regression.
|
||||
#assignees:
|
||||
---
|
||||
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
using ARMeilleure.Diagnostics.EventSources;
|
||||
using ARMeilleure.Diagnostics;
|
||||
using System;
|
||||
using System.Collections.Generic;
|
||||
using System.Runtime.InteropServices;
|
||||
@@ -218,7 +218,7 @@ namespace ARMeilleure.Common
|
||||
|
||||
_pages.Add(page);
|
||||
|
||||
AddressTableEventSource.Log.Allocated(size, leaf);
|
||||
TranslatorEventSource.Log.AddressTableAllocated(size, leaf);
|
||||
|
||||
return page;
|
||||
}
|
||||
|
||||
@@ -251,6 +251,13 @@ namespace ARMeilleure.Decoders
|
||||
return false;
|
||||
}
|
||||
|
||||
// Compare and branch instructions are always conditional.
|
||||
if (opCode.Instruction.Name == InstName.Cbz ||
|
||||
opCode.Instruction.Name == InstName.Cbnz)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
// Note: On ARM32, most instructions have conditional execution,
|
||||
// so there's no "Always" (unconditional) branch like on ARM64.
|
||||
// We need to check if the condition is "Always" instead.
|
||||
|
||||
@@ -151,7 +151,7 @@ namespace ARMeilleure.Decoders
|
||||
|
||||
public static bool VectorArgumentsInvalid(bool q, params int[] args)
|
||||
{
|
||||
if (q)
|
||||
if (q)
|
||||
{
|
||||
for (int i = 0; i < args.Length; i++)
|
||||
{
|
||||
|
||||
@@ -7,5 +7,8 @@
|
||||
|
||||
int Msb { get; }
|
||||
int Lsb { get; }
|
||||
|
||||
int SourceMask => (int)(0xFFFFFFFF >> (31 - Msb));
|
||||
int DestMask => SourceMask & (int)(0xFFFFFFFF << Lsb);
|
||||
}
|
||||
}
|
||||
|
||||
7
ARMeilleure/Decoders/IOpCode32AluImm16.cs
Normal file
7
ARMeilleure/Decoders/IOpCode32AluImm16.cs
Normal file
@@ -0,0 +1,7 @@
|
||||
namespace ARMeilleure.Decoders
|
||||
{
|
||||
interface IOpCode32AluImm16 : IOpCode32Alu
|
||||
{
|
||||
int Immediate { get; }
|
||||
}
|
||||
}
|
||||
11
ARMeilleure/Decoders/IOpCode32AluMla.cs
Normal file
11
ARMeilleure/Decoders/IOpCode32AluMla.cs
Normal file
@@ -0,0 +1,11 @@
|
||||
namespace ARMeilleure.Decoders
|
||||
{
|
||||
interface IOpCode32AluMla : IOpCode32AluReg
|
||||
{
|
||||
int Ra { get; }
|
||||
|
||||
bool NHigh { get; }
|
||||
bool MHigh { get; }
|
||||
bool R { get; }
|
||||
}
|
||||
}
|
||||
13
ARMeilleure/Decoders/IOpCode32AluUmull.cs
Normal file
13
ARMeilleure/Decoders/IOpCode32AluUmull.cs
Normal file
@@ -0,0 +1,13 @@
|
||||
namespace ARMeilleure.Decoders
|
||||
{
|
||||
interface IOpCode32AluUmull : IOpCode32, IOpCode32HasSetFlags
|
||||
{
|
||||
int RdLo { get; }
|
||||
int RdHi { get; }
|
||||
int Rn { get; }
|
||||
int Rm { get; }
|
||||
|
||||
bool NHigh { get; }
|
||||
bool MHigh { get; }
|
||||
}
|
||||
}
|
||||
@@ -3,6 +3,7 @@ namespace ARMeilleure.Decoders
|
||||
interface IOpCode32Mem : IOpCode32
|
||||
{
|
||||
int Rt { get; }
|
||||
int Rt2 => Rt | 1;
|
||||
int Rn { get; }
|
||||
|
||||
bool WBack { get; }
|
||||
|
||||
@@ -13,16 +13,13 @@ namespace ARMeilleure.Decoders
|
||||
Cond = (Condition)((uint)opCode >> 28);
|
||||
}
|
||||
|
||||
public bool IsThumb()
|
||||
{
|
||||
return this is OpCodeT16 || this is OpCodeT32;
|
||||
}
|
||||
public bool IsThumb { get; protected init; } = false;
|
||||
|
||||
public uint GetPc()
|
||||
{
|
||||
// Due to backwards compatibility and legacy behavior of ARMv4 CPUs pipeline,
|
||||
// the PC actually points 2 instructions ahead.
|
||||
if (IsThumb())
|
||||
if (IsThumb)
|
||||
{
|
||||
// PC is ahead by 4 in thumb mode whether or not the current instruction
|
||||
// is 16 or 32 bit.
|
||||
|
||||
@@ -6,12 +6,8 @@
|
||||
public int Rn { get; }
|
||||
|
||||
public int Msb { get; }
|
||||
|
||||
public int Lsb { get; }
|
||||
|
||||
public int SourceMask => (int)(0xFFFFFFFF >> (31 - Msb));
|
||||
public int DestMask => SourceMask & (int)(0xFFFFFFFF << Lsb);
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluBf(inst, address, opCode);
|
||||
|
||||
public OpCode32AluBf(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
namespace ARMeilleure.Decoders
|
||||
{
|
||||
class OpCode32AluImm16 : OpCode32Alu
|
||||
class OpCode32AluImm16 : OpCode32Alu, IOpCode32AluImm16
|
||||
{
|
||||
public int Immediate { get; }
|
||||
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
namespace ARMeilleure.Decoders
|
||||
{
|
||||
class OpCode32AluMla : OpCode32, IOpCode32AluReg
|
||||
class OpCode32AluMla : OpCode32, IOpCode32AluMla
|
||||
{
|
||||
public int Rn { get; }
|
||||
public int Rm { get; }
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
namespace ARMeilleure.Decoders
|
||||
{
|
||||
class OpCode32AluUmull : OpCode32, IOpCode32HasSetFlags
|
||||
class OpCode32AluUmull : OpCode32, IOpCode32AluUmull
|
||||
{
|
||||
public int RdLo { get; }
|
||||
public int RdHi { get; }
|
||||
@@ -11,7 +11,6 @@
|
||||
public bool MHigh { get; }
|
||||
|
||||
public bool? SetFlags { get; }
|
||||
public DataOp DataOp { get; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluUmull(inst, address, opCode);
|
||||
|
||||
@@ -26,7 +25,6 @@
|
||||
MHigh = ((opCode >> 6) & 0x1) == 1;
|
||||
|
||||
SetFlags = ((opCode >> 20) & 0x1) != 0;
|
||||
DataOp = DataOp.Arithmetic;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -2,9 +2,10 @@
|
||||
{
|
||||
class OpCode32SimdCvtFI : OpCode32SimdS
|
||||
{
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCvtFI(inst, address, opCode);
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCvtFI(inst, address, opCode, false);
|
||||
public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCvtFI(inst, address, opCode, true);
|
||||
|
||||
public OpCode32SimdCvtFI(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
public OpCode32SimdCvtFI(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
|
||||
{
|
||||
Opc = (opCode >> 7) & 0x1;
|
||||
|
||||
|
||||
@@ -7,10 +7,13 @@
|
||||
public int Rt { get; }
|
||||
public bool Q { get; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdDupGP(inst, address, opCode);
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdDupGP(inst, address, opCode, false);
|
||||
public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdDupGP(inst, address, opCode, true);
|
||||
|
||||
public OpCode32SimdDupGP(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
public OpCode32SimdDupGP(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
|
||||
{
|
||||
IsThumb = isThumb;
|
||||
|
||||
Size = 2 - (((opCode >> 21) & 0x2) | ((opCode >> 5) & 0x1)); // B:E - 0 for 32, 16 then 8.
|
||||
if (Size == -1)
|
||||
{
|
||||
|
||||
@@ -7,10 +7,13 @@
|
||||
public int Size { get; }
|
||||
public int Elems { get; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm44(inst, address, opCode);
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm44(inst, address, opCode, false);
|
||||
public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm44(inst, address, opCode, true);
|
||||
|
||||
public OpCode32SimdImm44(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
public OpCode32SimdImm44(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
|
||||
{
|
||||
IsThumb = isThumb;
|
||||
|
||||
Size = (opCode >> 8) & 0x3;
|
||||
|
||||
bool single = Size != 3;
|
||||
|
||||
@@ -8,10 +8,13 @@
|
||||
public bool Add { get; }
|
||||
public int Immediate { get; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemImm(inst, address, opCode);
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemImm(inst, address, opCode, false);
|
||||
public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemImm(inst, address, opCode, true);
|
||||
|
||||
public OpCode32SimdMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
public OpCode32SimdMemImm(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
|
||||
{
|
||||
IsThumb = isThumb;
|
||||
|
||||
Immediate = opCode & 0xff;
|
||||
|
||||
Rn = (opCode >> 16) & 0xf;
|
||||
|
||||
@@ -12,10 +12,13 @@
|
||||
public bool DoubleWidth { get; }
|
||||
public bool Add { get; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemMult(inst, address, opCode);
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemMult(inst, address, opCode, false);
|
||||
public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMemMult(inst, address, opCode, true);
|
||||
|
||||
public OpCode32SimdMemMult(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
public OpCode32SimdMemMult(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
|
||||
{
|
||||
IsThumb = isThumb;
|
||||
|
||||
Rn = (opCode >> 16) & 0xf;
|
||||
|
||||
bool isLoad = (opCode & (1 << 20)) != 0;
|
||||
|
||||
@@ -1,11 +1,10 @@
|
||||
using ARMeilleure.State;
|
||||
using System;
|
||||
|
||||
namespace ARMeilleure.Decoders
|
||||
{
|
||||
class OpCode32SimdMemPair : OpCode32, IOpCode32Simd
|
||||
{
|
||||
private static int[] RegsMap =
|
||||
private static int[] _regsMap =
|
||||
{
|
||||
1, 1, 4, 2,
|
||||
1, 1, 3, 1,
|
||||
@@ -40,9 +39,9 @@ namespace ARMeilleure.Decoders
|
||||
WBack = Rm != RegisterAlias.Aarch32Pc;
|
||||
RegisterIndex = Rm != RegisterAlias.Aarch32Pc && Rm != RegisterAlias.Aarch32Sp;
|
||||
|
||||
Regs = RegsMap[(opCode >> 8) & 0xf];
|
||||
Regs = _regsMap[(opCode >> 8) & 0xf];
|
||||
|
||||
Increment = Math.Min(Regs, ((opCode >> 8) & 0x1) + 1);
|
||||
Increment = ((opCode >> 8) & 0x1) + 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -11,10 +11,13 @@
|
||||
public int Opc1 { get; }
|
||||
public int Opc2 { get; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGp(inst, address, opCode);
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGp(inst, address, opCode, false);
|
||||
public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGp(inst, address, opCode, true);
|
||||
|
||||
public OpCode32SimdMovGp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
public OpCode32SimdMovGp(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
|
||||
{
|
||||
IsThumb = isThumb;
|
||||
|
||||
// Which one is used is instruction dependant.
|
||||
Op = (opCode >> 20) & 0x1;
|
||||
|
||||
|
||||
@@ -9,10 +9,13 @@
|
||||
public int Rt2 { get; }
|
||||
public int Op { get; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpDouble(inst, address, opCode);
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpDouble(inst, address, opCode, false);
|
||||
public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpDouble(inst, address, opCode, true);
|
||||
|
||||
public OpCode32SimdMovGpDouble(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
public OpCode32SimdMovGpDouble(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
|
||||
{
|
||||
IsThumb = isThumb;
|
||||
|
||||
// Which one is used is instruction dependant.
|
||||
Op = (opCode >> 20) & 0x1;
|
||||
|
||||
|
||||
@@ -11,10 +11,13 @@
|
||||
|
||||
public int Index { get; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpElem(inst, address, opCode);
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpElem(inst, address, opCode, false);
|
||||
public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovGpElem(inst, address, opCode, true);
|
||||
|
||||
public OpCode32SimdMovGpElem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
public OpCode32SimdMovGpElem(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
|
||||
{
|
||||
IsThumb = isThumb;
|
||||
|
||||
Op = (opCode >> 20) & 0x1;
|
||||
U = ((opCode >> 23) & 1) != 0;
|
||||
|
||||
|
||||
12
ARMeilleure/Decoders/OpCode32SimdMovn.cs
Normal file
12
ARMeilleure/Decoders/OpCode32SimdMovn.cs
Normal file
@@ -0,0 +1,12 @@
|
||||
namespace ARMeilleure.Decoders
|
||||
{
|
||||
class OpCode32SimdMovn : OpCode32Simd
|
||||
{
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdMovn(inst, address, opCode);
|
||||
|
||||
public OpCode32SimdMovn(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
Size = (opCode >> 18) & 0x3;
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -4,9 +4,10 @@
|
||||
{
|
||||
public int Vn { get; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegS(inst, address, opCode);
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegS(inst, address, opCode, false);
|
||||
public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegS(inst, address, opCode, true);
|
||||
|
||||
public OpCode32SimdRegS(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
public OpCode32SimdRegS(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
|
||||
{
|
||||
bool single = Size != 3;
|
||||
if (single)
|
||||
|
||||
@@ -8,10 +8,13 @@
|
||||
public int Opc2 { get; } // opc2 or RM (opc2<1:0>) [Vcvt, Vrint].
|
||||
public int Size { get; protected set; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdS(inst, address, opCode);
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdS(inst, address, opCode, false);
|
||||
public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdS(inst, address, opCode, true);
|
||||
|
||||
public OpCode32SimdS(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
public OpCode32SimdS(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
|
||||
{
|
||||
IsThumb = isThumb;
|
||||
|
||||
Opc = (opCode >> 15) & 0x3;
|
||||
Opc2 = (opCode >> 16) & 0x7;
|
||||
|
||||
|
||||
@@ -4,9 +4,10 @@
|
||||
{
|
||||
public OpCode32SimdSelMode Cc { get; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSel(inst, address, opCode);
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSel(inst, address, opCode, false);
|
||||
public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSel(inst, address, opCode, true);
|
||||
|
||||
public OpCode32SimdSel(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
public OpCode32SimdSel(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
|
||||
{
|
||||
Cc = (OpCode32SimdSelMode)((opCode >> 20) & 3);
|
||||
}
|
||||
|
||||
@@ -5,10 +5,13 @@
|
||||
public int Rt { get; }
|
||||
public int Sreg { get; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSpecial(inst, address, opCode);
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSpecial(inst, address, opCode, false);
|
||||
public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdSpecial(inst, address, opCode, true);
|
||||
|
||||
public OpCode32SimdSpecial(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
public OpCode32SimdSpecial(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
|
||||
{
|
||||
IsThumb = isThumb;
|
||||
|
||||
Rt = (opCode >> 12) & 0xf;
|
||||
Sreg = (opCode >> 16) & 0xf;
|
||||
}
|
||||
|
||||
@@ -8,6 +8,7 @@ namespace ARMeilleure.Decoders
|
||||
{
|
||||
Cond = Condition.Al;
|
||||
|
||||
IsThumb = true;
|
||||
OpCodeSizeInBytes = 2;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -4,14 +4,13 @@ namespace ARMeilleure.Decoders
|
||||
{
|
||||
public int Rd { get; }
|
||||
|
||||
public bool Add => true;
|
||||
public int Immediate { get; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16Adr(inst, address, opCode);
|
||||
|
||||
public OpCodeT16Adr(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
Rd = (opCode >> 8) & 7;
|
||||
Rd = (opCode >> 8) & 7;
|
||||
|
||||
int imm = (opCode & 0xff) << 2;
|
||||
Immediate = (int)(GetPc() & 0xfffffffc) + imm;
|
||||
|
||||
@@ -8,6 +8,7 @@
|
||||
{
|
||||
Cond = Condition.Al;
|
||||
|
||||
IsThumb = true;
|
||||
OpCodeSizeInBytes = 4;
|
||||
}
|
||||
}
|
||||
|
||||
22
ARMeilleure/Decoders/OpCodeT32AluBf.cs
Normal file
22
ARMeilleure/Decoders/OpCodeT32AluBf.cs
Normal file
@@ -0,0 +1,22 @@
|
||||
namespace ARMeilleure.Decoders
|
||||
{
|
||||
class OpCodeT32AluBf : OpCodeT32, IOpCode32AluBf
|
||||
{
|
||||
public int Rd { get; }
|
||||
public int Rn { get; }
|
||||
|
||||
public int Msb { get; }
|
||||
public int Lsb { get; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32AluBf(inst, address, opCode);
|
||||
|
||||
public OpCodeT32AluBf(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
Rd = (opCode >> 8) & 0xf;
|
||||
Rn = (opCode >> 16) & 0xf;
|
||||
|
||||
Msb = (opCode >> 0) & 0x1f;
|
||||
Lsb = ((opCode >> 6) & 0x3) | ((opCode >> 10) & 0x1c);
|
||||
}
|
||||
}
|
||||
}
|
||||
16
ARMeilleure/Decoders/OpCodeT32AluImm12.cs
Normal file
16
ARMeilleure/Decoders/OpCodeT32AluImm12.cs
Normal file
@@ -0,0 +1,16 @@
|
||||
namespace ARMeilleure.Decoders
|
||||
{
|
||||
class OpCodeT32AluImm12 : OpCodeT32Alu, IOpCode32AluImm
|
||||
{
|
||||
public int Immediate { get; }
|
||||
|
||||
public bool IsRotated => false;
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32AluImm12(inst, address, opCode);
|
||||
|
||||
public OpCodeT32AluImm12(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
Immediate = (opCode & 0xff) | ((opCode >> 4) & 0x700) | ((opCode >> 15) & 0x800);
|
||||
}
|
||||
}
|
||||
}
|
||||
29
ARMeilleure/Decoders/OpCodeT32AluMla.cs
Normal file
29
ARMeilleure/Decoders/OpCodeT32AluMla.cs
Normal file
@@ -0,0 +1,29 @@
|
||||
namespace ARMeilleure.Decoders
|
||||
{
|
||||
class OpCodeT32AluMla : OpCodeT32, IOpCode32AluMla
|
||||
{
|
||||
public int Rn { get; }
|
||||
public int Rm { get; }
|
||||
public int Ra { get; }
|
||||
public int Rd { get; }
|
||||
|
||||
public bool NHigh { get; }
|
||||
public bool MHigh { get; }
|
||||
public bool R { get; }
|
||||
public bool? SetFlags => false;
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32AluMla(inst, address, opCode);
|
||||
|
||||
public OpCodeT32AluMla(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
Rm = (opCode >> 0) & 0xf;
|
||||
Rd = (opCode >> 8) & 0xf;
|
||||
Ra = (opCode >> 12) & 0xf;
|
||||
Rn = (opCode >> 16) & 0xf;
|
||||
R = (opCode & (1 << 4)) != 0;
|
||||
|
||||
MHigh = ((opCode >> 4) & 0x1) == 1;
|
||||
NHigh = ((opCode >> 5) & 0x1) == 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
14
ARMeilleure/Decoders/OpCodeT32AluReg.cs
Normal file
14
ARMeilleure/Decoders/OpCodeT32AluReg.cs
Normal file
@@ -0,0 +1,14 @@
|
||||
namespace ARMeilleure.Decoders
|
||||
{
|
||||
class OpCodeT32AluReg : OpCodeT32Alu, IOpCode32AluReg
|
||||
{
|
||||
public int Rm { get; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32AluReg(inst, address, opCode);
|
||||
|
||||
public OpCodeT32AluReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
Rm = (opCode >> 0) & 0xf;
|
||||
}
|
||||
}
|
||||
}
|
||||
28
ARMeilleure/Decoders/OpCodeT32AluUmull.cs
Normal file
28
ARMeilleure/Decoders/OpCodeT32AluUmull.cs
Normal file
@@ -0,0 +1,28 @@
|
||||
namespace ARMeilleure.Decoders
|
||||
{
|
||||
class OpCodeT32AluUmull : OpCodeT32, IOpCode32AluUmull
|
||||
{
|
||||
public int RdLo { get; }
|
||||
public int RdHi { get; }
|
||||
public int Rn { get; }
|
||||
public int Rm { get; }
|
||||
|
||||
public bool NHigh { get; }
|
||||
public bool MHigh { get; }
|
||||
|
||||
public bool? SetFlags => false;
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32AluUmull(inst, address, opCode);
|
||||
|
||||
public OpCodeT32AluUmull(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
Rm = (opCode >> 0) & 0xf;
|
||||
RdHi = (opCode >> 8) & 0xf;
|
||||
RdLo = (opCode >> 12) & 0xf;
|
||||
Rn = (opCode >> 16) & 0xf;
|
||||
|
||||
MHigh = ((opCode >> 4) & 0x1) == 1;
|
||||
NHigh = ((opCode >> 5) & 0x1) == 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
18
ARMeilleure/Decoders/OpCodeT32AluUx.cs
Normal file
18
ARMeilleure/Decoders/OpCodeT32AluUx.cs
Normal file
@@ -0,0 +1,18 @@
|
||||
using ARMeilleure.State;
|
||||
|
||||
namespace ARMeilleure.Decoders
|
||||
{
|
||||
class OpCodeT32AluUx : OpCodeT32AluReg, IOpCode32AluUx
|
||||
{
|
||||
public int Rotate { get; }
|
||||
public int RotateBits => Rotate * 8;
|
||||
public bool Add => Rn != RegisterAlias.Aarch32Pc;
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32AluUx(inst, address, opCode);
|
||||
|
||||
public OpCodeT32AluUx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
Rotate = (opCode >> 4) & 0x3;
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -27,7 +27,7 @@ namespace ARMeilleure.Decoders
|
||||
int i2 = j2 ^ s ^ 1;
|
||||
|
||||
int imm32 = imm11 | (imm10 << 11) | (i2 << 21) | (i1 << 22) | (s << 23);
|
||||
imm32 = (imm32 << 9) >> 8;
|
||||
imm32 = (imm32 << 8) >> 7;
|
||||
|
||||
Immediate = pc + imm32;
|
||||
}
|
||||
|
||||
@@ -23,7 +23,7 @@ namespace ARMeilleure.Decoders
|
||||
Add = ((opCode >> 23) & 1) != 0;
|
||||
WBack = ((opCode >> 21) & 1) != 0;
|
||||
|
||||
Immediate = opCode & 0xff;
|
||||
Immediate = (opCode & 0xff) << 2;
|
||||
|
||||
IsLoad = ((opCode >> 20) & 1) != 0;
|
||||
}
|
||||
|
||||
@@ -4,6 +4,7 @@ namespace ARMeilleure.Decoders
|
||||
{
|
||||
public int Rd => 0;
|
||||
public int Rt { get; }
|
||||
public int Rt2 { get; }
|
||||
public int Rn { get; }
|
||||
|
||||
public bool WBack => false;
|
||||
@@ -17,6 +18,7 @@ namespace ARMeilleure.Decoders
|
||||
|
||||
public OpCodeT32MemLdEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
Rt2 = (opCode >> 8) & 0xf;
|
||||
Rt = (opCode >> 12) & 0xf;
|
||||
Rn = (opCode >> 16) & 0xf;
|
||||
}
|
||||
|
||||
@@ -4,6 +4,7 @@ namespace ARMeilleure.Decoders
|
||||
{
|
||||
public int Rd { get; }
|
||||
public int Rt { get; }
|
||||
public int Rt2 { get; }
|
||||
public int Rn { get; }
|
||||
|
||||
public bool WBack => false;
|
||||
@@ -18,6 +19,7 @@ namespace ARMeilleure.Decoders
|
||||
public OpCodeT32MemStEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
Rd = (opCode >> 0) & 0xf;
|
||||
Rt2 = (opCode >> 8) & 0xf;
|
||||
Rt = (opCode >> 12) & 0xf;
|
||||
Rn = (opCode >> 16) & 0xf;
|
||||
}
|
||||
|
||||
16
ARMeilleure/Decoders/OpCodeT32MovImm16.cs
Normal file
16
ARMeilleure/Decoders/OpCodeT32MovImm16.cs
Normal file
@@ -0,0 +1,16 @@
|
||||
namespace ARMeilleure.Decoders
|
||||
{
|
||||
class OpCodeT32MovImm16 : OpCodeT32Alu, IOpCode32AluImm16
|
||||
{
|
||||
public int Immediate { get; }
|
||||
|
||||
public bool IsRotated => false;
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32MovImm16(inst, address, opCode);
|
||||
|
||||
public OpCodeT32MovImm16(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
Immediate = (opCode & 0xff) | ((opCode >> 4) & 0x700) | ((opCode >> 15) & 0x800) | ((opCode >> 4) & 0xf000);
|
||||
}
|
||||
}
|
||||
}
|
||||
19
ARMeilleure/Decoders/OpCodeT32ShiftReg.cs
Normal file
19
ARMeilleure/Decoders/OpCodeT32ShiftReg.cs
Normal file
@@ -0,0 +1,19 @@
|
||||
namespace ARMeilleure.Decoders
|
||||
{
|
||||
class OpCodeT32ShiftReg : OpCodeT32Alu, IOpCode32AluRsReg
|
||||
{
|
||||
public int Rm => Rn;
|
||||
public int Rs { get; }
|
||||
|
||||
public ShiftType ShiftType { get; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32ShiftReg(inst, address, opCode);
|
||||
|
||||
public OpCodeT32ShiftReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
Rs = (opCode >> 0) & 0xf;
|
||||
|
||||
ShiftType = (ShiftType)((opCode >> 21) & 3);
|
||||
}
|
||||
}
|
||||
}
|
||||
16
ARMeilleure/Decoders/OpCodeT32Tb.cs
Normal file
16
ARMeilleure/Decoders/OpCodeT32Tb.cs
Normal file
@@ -0,0 +1,16 @@
|
||||
namespace ARMeilleure.Decoders
|
||||
{
|
||||
class OpCodeT32Tb : OpCodeT32, IOpCode32BReg
|
||||
{
|
||||
public int Rm { get; }
|
||||
public int Rn { get; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32Tb(inst, address, opCode);
|
||||
|
||||
public OpCodeT32Tb(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
Rm = (opCode >> 0) & 0xf;
|
||||
Rn = (opCode >> 16) & 0xf;
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -792,7 +792,61 @@ namespace ARMeilleure.Decoders
|
||||
SetA32("<<<<01101100xxxxxxxxxx000111xxxx", InstName.Uxtb16, InstEmit32.Uxtb16, OpCode32AluUx.Create);
|
||||
SetA32("<<<<01101111xxxxxxxxxx000111xxxx", InstName.Uxth, InstEmit32.Uxth, OpCode32AluUx.Create);
|
||||
|
||||
// FP & SIMD
|
||||
// VFP
|
||||
SetVfp("<<<<11101x110000xxxx101x11x0xxxx", InstName.Vabs, InstEmit32.Vabs_S, OpCode32SimdS.Create, OpCode32SimdS.CreateT32);
|
||||
SetVfp("<<<<11100x11xxxxxxxx101xx0x0xxxx", InstName.Vadd, InstEmit32.Vadd_S, OpCode32SimdRegS.Create, OpCode32SimdRegS.CreateT32);
|
||||
SetVfp("<<<<11101x11010xxxxx101x01x0xxxx", InstName.Vcmp, InstEmit32.Vcmp, OpCode32SimdS.Create, OpCode32SimdS.CreateT32);
|
||||
SetVfp("<<<<11101x11010xxxxx101x11x0xxxx", InstName.Vcmpe, InstEmit32.Vcmpe, OpCode32SimdS.Create, OpCode32SimdS.CreateT32);
|
||||
SetVfp("<<<<11101x110111xxxx101x11x0xxxx", InstName.Vcvt, InstEmit32.Vcvt_FD, OpCode32SimdS.Create, OpCode32SimdS.CreateT32); // FP 32 and 64, scalar.
|
||||
SetVfp("<<<<11101x11110xxxxx101x11x0xxxx", InstName.Vcvt, InstEmit32.Vcvt_FI, OpCode32SimdCvtFI.Create, OpCode32SimdCvtFI.CreateT32); // FP32 to int.
|
||||
SetVfp("<<<<11101x111000xxxx101xx1x0xxxx", InstName.Vcvt, InstEmit32.Vcvt_FI, OpCode32SimdCvtFI.Create, OpCode32SimdCvtFI.CreateT32); // Int to FP32.
|
||||
SetVfp("111111101x1111xxxxxx101xx1x0xxxx", InstName.Vcvt, InstEmit32.Vcvt_RM, OpCode32SimdCvtFI.Create, OpCode32SimdCvtFI.CreateT32); // The many FP32 to int encodings (fp).
|
||||
SetVfp("<<<<11101x00xxxxxxxx101xx0x0xxxx", InstName.Vdiv, InstEmit32.Vdiv_S, OpCode32SimdRegS.Create, OpCode32SimdRegS.CreateT32);
|
||||
SetVfp("<<<<11101xx0xxxxxxxx1011x0x10000", InstName.Vdup, InstEmit32.Vdup, OpCode32SimdDupGP.Create, OpCode32SimdDupGP.CreateT32);
|
||||
SetVfp("<<<<11101x10xxxxxxxx101xx0x0xxxx", InstName.Vfma, InstEmit32.Vfma_S, OpCode32SimdRegS.Create, OpCode32SimdRegS.CreateT32);
|
||||
SetVfp("<<<<11101x10xxxxxxxx101xx1x0xxxx", InstName.Vfms, InstEmit32.Vfms_S, OpCode32SimdRegS.Create, OpCode32SimdRegS.CreateT32);
|
||||
SetVfp("<<<<11101x01xxxxxxxx101xx1x0xxxx", InstName.Vfnma, InstEmit32.Vfnma_S, OpCode32SimdRegS.Create, OpCode32SimdRegS.CreateT32);
|
||||
SetVfp("<<<<11101x01xxxxxxxx101xx0x0xxxx", InstName.Vfnms, InstEmit32.Vfnms_S, OpCode32SimdRegS.Create, OpCode32SimdRegS.CreateT32);
|
||||
SetVfp("<<<<11001x01xxxxxxxx1011xxxxxxx0", InstName.Vldm, InstEmit32.Vldm, OpCode32SimdMemMult.Create, OpCode32SimdMemMult.CreateT32);
|
||||
SetVfp("<<<<11001x11xxxxxxxx1011xxxxxxx0", InstName.Vldm, InstEmit32.Vldm, OpCode32SimdMemMult.Create, OpCode32SimdMemMult.CreateT32);
|
||||
SetVfp("<<<<11010x11xxxxxxxx1011xxxxxxx0", InstName.Vldm, InstEmit32.Vldm, OpCode32SimdMemMult.Create, OpCode32SimdMemMult.CreateT32);
|
||||
SetVfp("<<<<11001x01xxxxxxxx1010xxxxxxxx", InstName.Vldm, InstEmit32.Vldm, OpCode32SimdMemMult.Create, OpCode32SimdMemMult.CreateT32);
|
||||
SetVfp("<<<<11001x11xxxxxxxx1010xxxxxxxx", InstName.Vldm, InstEmit32.Vldm, OpCode32SimdMemMult.Create, OpCode32SimdMemMult.CreateT32);
|
||||
SetVfp("<<<<11010x11xxxxxxxx1010xxxxxxxx", InstName.Vldm, InstEmit32.Vldm, OpCode32SimdMemMult.Create, OpCode32SimdMemMult.CreateT32);
|
||||
SetVfp("<<<<1101xx01xxxxxxxx101xxxxxxxxx", InstName.Vldr, InstEmit32.Vldr, OpCode32SimdMemImm.Create, OpCode32SimdMemImm.CreateT32);
|
||||
SetVfp("111111101x00xxxxxxxx10>>x0x0xxxx", InstName.Vmaxnm, InstEmit32.Vmaxnm_S, OpCode32SimdRegS.Create, OpCode32SimdRegS.CreateT32);
|
||||
SetVfp("111111101x00xxxxxxxx10>>x1x0xxxx", InstName.Vminnm, InstEmit32.Vminnm_S, OpCode32SimdRegS.Create, OpCode32SimdRegS.CreateT32);
|
||||
SetVfp("<<<<11100x00xxxxxxxx101xx0x0xxxx", InstName.Vmla, InstEmit32.Vmla_S, OpCode32SimdRegS.Create, OpCode32SimdRegS.CreateT32);
|
||||
SetVfp("<<<<11100x00xxxxxxxx101xx1x0xxxx", InstName.Vmls, InstEmit32.Vmls_S, OpCode32SimdRegS.Create, OpCode32SimdRegS.CreateT32);
|
||||
SetVfp("<<<<11100xx0xxxxxxxx1011xxx10000", InstName.Vmov, InstEmit32.Vmov_G1, OpCode32SimdMovGpElem.Create, OpCode32SimdMovGpElem.CreateT32); // From gen purpose.
|
||||
SetVfp("<<<<1110xxx1xxxxxxxx1011xxx10000", InstName.Vmov, InstEmit32.Vmov_G1, OpCode32SimdMovGpElem.Create, OpCode32SimdMovGpElem.CreateT32); // To gen purpose.
|
||||
SetVfp("<<<<1100010xxxxxxxxx101000x1xxxx", InstName.Vmov, InstEmit32.Vmov_G2, OpCode32SimdMovGpDouble.Create, OpCode32SimdMovGpDouble.CreateT32); // To/from gen purpose x2 and single precision x2.
|
||||
SetVfp("<<<<1100010xxxxxxxxx101100x1xxxx", InstName.Vmov, InstEmit32.Vmov_GD, OpCode32SimdMovGpDouble.Create, OpCode32SimdMovGpDouble.CreateT32); // To/from gen purpose x2 and double precision.
|
||||
SetVfp("<<<<1110000xxxxxxxxx1010x0010000", InstName.Vmov, InstEmit32.Vmov_GS, OpCode32SimdMovGp.Create, OpCode32SimdMovGp.CreateT32); // To/from gen purpose and single precision.
|
||||
SetVfp("<<<<11101x11xxxxxxxx101x0000xxxx", InstName.Vmov, InstEmit32.Vmov_I, OpCode32SimdImm44.Create, OpCode32SimdImm44.CreateT32); // Scalar f16/32/64 based on size 01 10 11.
|
||||
SetVfp("<<<<11101x110000xxxx101x01x0xxxx", InstName.Vmov, InstEmit32.Vmov_S, OpCode32SimdS.Create, OpCode32SimdS.CreateT32);
|
||||
SetVfp("<<<<11101111xxxxxxxx101000010000", InstName.Vmrs, InstEmit32.Vmrs, OpCode32SimdSpecial.Create, OpCode32SimdSpecial.CreateT32);
|
||||
SetVfp("<<<<11101110xxxxxxxx101000010000", InstName.Vmsr, InstEmit32.Vmsr, OpCode32SimdSpecial.Create, OpCode32SimdSpecial.CreateT32);
|
||||
SetVfp("<<<<11100x10xxxxxxxx101xx0x0xxxx", InstName.Vmul, InstEmit32.Vmul_S, OpCode32SimdRegS.Create, OpCode32SimdRegS.CreateT32);
|
||||
SetVfp("<<<<11101x110001xxxx101x01x0xxxx", InstName.Vneg, InstEmit32.Vneg_S, OpCode32SimdS.Create, OpCode32SimdS.CreateT32);
|
||||
SetVfp("<<<<11100x01xxxxxxxx101xx1x0xxxx", InstName.Vnmla, InstEmit32.Vnmla_S, OpCode32SimdRegS.Create, OpCode32SimdRegS.CreateT32);
|
||||
SetVfp("<<<<11100x01xxxxxxxx101xx0x0xxxx", InstName.Vnmls, InstEmit32.Vnmls_S, OpCode32SimdRegS.Create, OpCode32SimdRegS.CreateT32);
|
||||
SetVfp("<<<<11100x10xxxxxxxx101xx1x0xxxx", InstName.Vnmul, InstEmit32.Vnmul_S, OpCode32SimdRegS.Create, OpCode32SimdRegS.CreateT32);
|
||||
SetVfp("111111101x1110xxxxxx101x01x0xxxx", InstName.Vrint, InstEmit32.Vrint_RM, OpCode32SimdS.Create, OpCode32SimdS.CreateT32);
|
||||
SetVfp("<<<<11101x110110xxxx101x11x0xxxx", InstName.Vrint, InstEmit32.Vrint_Z, OpCode32SimdS.Create, OpCode32SimdS.CreateT32);
|
||||
SetVfp("<<<<11101x110111xxxx101x01x0xxxx", InstName.Vrintx, InstEmit32.Vrintx_S, OpCode32SimdS.Create, OpCode32SimdS.CreateT32);
|
||||
SetVfp("<<<<11101x110001xxxx101x11x0xxxx", InstName.Vsqrt, InstEmit32.Vsqrt_S, OpCode32SimdS.Create, OpCode32SimdS.CreateT32);
|
||||
SetVfp("111111100xxxxxxxxxxx101xx0x0xxxx", InstName.Vsel, InstEmit32.Vsel, OpCode32SimdSel.Create, OpCode32SimdSel.CreateT32);
|
||||
SetVfp("<<<<11001x00xxxxxxxx1011xxxxxxx0", InstName.Vstm, InstEmit32.Vstm, OpCode32SimdMemMult.Create, OpCode32SimdMemMult.CreateT32);
|
||||
SetVfp("<<<<11001x10xxxxxxxx1011xxxxxxx0", InstName.Vstm, InstEmit32.Vstm, OpCode32SimdMemMult.Create, OpCode32SimdMemMult.CreateT32);
|
||||
SetVfp("<<<<11010x10xxxxxxxx1011xxxxxxx0", InstName.Vstm, InstEmit32.Vstm, OpCode32SimdMemMult.Create, OpCode32SimdMemMult.CreateT32);
|
||||
SetVfp("<<<<11001x00xxxxxxxx1010xxxxxxxx", InstName.Vstm, InstEmit32.Vstm, OpCode32SimdMemMult.Create, OpCode32SimdMemMult.CreateT32);
|
||||
SetVfp("<<<<11001x10xxxxxxxx1010xxxxxxxx", InstName.Vstm, InstEmit32.Vstm, OpCode32SimdMemMult.Create, OpCode32SimdMemMult.CreateT32);
|
||||
SetVfp("<<<<11010x10xxxxxxxx1010xxxxxxxx", InstName.Vstm, InstEmit32.Vstm, OpCode32SimdMemMult.Create, OpCode32SimdMemMult.CreateT32);
|
||||
SetVfp("<<<<1101xx00xxxxxxxx101xxxxxxxxx", InstName.Vstr, InstEmit32.Vstr, OpCode32SimdMemImm.Create, OpCode32SimdMemImm.CreateT32);
|
||||
SetVfp("<<<<11100x11xxxxxxxx101xx1x0xxxx", InstName.Vsub, InstEmit32.Vsub_S, OpCode32SimdRegS.Create, OpCode32SimdRegS.CreateT32);
|
||||
|
||||
// ASIMD
|
||||
SetA32("111100111x110000xxx0001101x0xxx0", InstName.Aesd_V, InstEmit32.Aesd_V, OpCode32Simd.Create);
|
||||
SetA32("111100111x110000xxx0001100x0xxx0", InstName.Aese_V, InstEmit32.Aese_V, OpCode32Simd.Create);
|
||||
SetA32("111100111x110000xxx0001111x0xxx0", InstName.Aesimc_V, InstEmit32.Aesimc_V, OpCode32Simd.Create);
|
||||
@@ -803,14 +857,12 @@ namespace ARMeilleure.Decoders
|
||||
SetA32("111100110x10xxx0xxx01100x1x0xxx0", InstName.Sha256su1_V, InstEmit32.Sha256su1_V, OpCode32SimdReg.Create);
|
||||
SetA32("1111001x0x<<xxxxxxxx0111xxx0xxxx", InstName.Vabd, InstEmit32.Vabd_I, OpCode32SimdReg.Create);
|
||||
SetA32("1111001x1x<<xxxxxxxx0111x0x0xxxx", InstName.Vabdl, InstEmit32.Vabdl_I, OpCode32SimdRegLong.Create);
|
||||
SetA32("<<<<11101x110000xxxx101x11x0xxxx", InstName.Vabs, InstEmit32.Vabs_S, OpCode32SimdS.Create);
|
||||
SetA32("111100111x11<<01xxxx00110xx0xxxx", InstName.Vabs, InstEmit32.Vabs_V, OpCode32SimdCmpZ.Create);
|
||||
SetA32("111100111x111001xxxx01110xx0xxxx", InstName.Vabs, InstEmit32.Vabs_V, OpCode32SimdCmpZ.Create);
|
||||
SetA32("111100100xxxxxxxxxxx1000xxx0xxxx", InstName.Vadd, InstEmit32.Vadd_I, OpCode32SimdReg.Create);
|
||||
SetA32("<<<<11100x11xxxxxxxx101xx0x0xxxx", InstName.Vadd, InstEmit32.Vadd_S, OpCode32SimdRegS.Create);
|
||||
SetA32("111100100x00xxxxxxxx1101xxx0xxxx", InstName.Vadd, InstEmit32.Vadd_V, OpCode32SimdReg.Create);
|
||||
SetA32("1111001x1x<<xxxxxxxx0000x0x0xxxx", InstName.Vaddl, InstEmit32.Vaddl_I, OpCode32SimdRegLong.Create);
|
||||
SetA32("1111001x1x<<xxxxxxxx0001x0x0xxxx", InstName.Vaddw, InstEmit32.Vaddw_I, OpCode32SimdRegWide.Create);
|
||||
SetA32("1111001x1x<<xxxxxxx00000x0x0xxxx", InstName.Vaddl, InstEmit32.Vaddl_I, OpCode32SimdRegLong.Create);
|
||||
SetA32("1111001x1x<<xxxxxxx00001x0x0xxxx", InstName.Vaddw, InstEmit32.Vaddw_I, OpCode32SimdRegWide.Create);
|
||||
SetA32("111100100x00xxxxxxxx0001xxx1xxxx", InstName.Vand, InstEmit32.Vand_I, OpCode32SimdBinary.Create);
|
||||
SetA32("111100100x01xxxxxxxx0001xxx1xxxx", InstName.Vbic, InstEmit32.Vbic_I, OpCode32SimdBinary.Create);
|
||||
SetA32("1111001x1x000xxxxxxx<<x10x11xxxx", InstName.Vbic, InstEmit32.Vbic_II, OpCode32SimdImm.Create);
|
||||
@@ -828,83 +880,64 @@ namespace ARMeilleure.Decoders
|
||||
SetA32("111100111x11xx01xxxx0x000xx0xxxx", InstName.Vcgt, InstEmit32.Vcgt_Z, OpCode32SimdCmpZ.Create);
|
||||
SetA32("111100111x11xx01xxxx0x011xx0xxxx", InstName.Vcle, InstEmit32.Vcle_Z, OpCode32SimdCmpZ.Create);
|
||||
SetA32("111100111x11xx01xxxx0x100xx0xxxx", InstName.Vclt, InstEmit32.Vclt_Z, OpCode32SimdCmpZ.Create);
|
||||
SetA32("<<<<11101x11010xxxxx101x01x0xxxx", InstName.Vcmp, InstEmit32.Vcmp, OpCode32SimdS.Create);
|
||||
SetA32("<<<<11101x11010xxxxx101x11x0xxxx", InstName.Vcmpe, InstEmit32.Vcmpe, OpCode32SimdS.Create);
|
||||
SetA32("111100111x110000xxxx01010xx0xxxx", InstName.Vcnt, InstEmit32.Vcnt, OpCode32SimdCmpZ.Create);
|
||||
SetA32("<<<<11101x110111xxxx101x11x0xxxx", InstName.Vcvt, InstEmit32.Vcvt_FD, OpCode32SimdS.Create); // FP 32 and 64, scalar.
|
||||
SetA32("<<<<11101x11110xxxxx101x11x0xxxx", InstName.Vcvt, InstEmit32.Vcvt_FI, OpCode32SimdCvtFI.Create); // FP32 to int.
|
||||
SetA32("<<<<11101x111000xxxx101xx1x0xxxx", InstName.Vcvt, InstEmit32.Vcvt_FI, OpCode32SimdCvtFI.Create); // Int to FP32.
|
||||
SetA32("111111101x1111xxxxxx101xx1x0xxxx", InstName.Vcvt, InstEmit32.Vcvt_RM, OpCode32SimdCvtFI.Create); // The many FP32 to int encodings (fp).
|
||||
SetA32("111100111x111011xxxx011xxxx0xxxx", InstName.Vcvt, InstEmit32.Vcvt_V, OpCode32SimdCmpZ.Create); // FP and integer, vector.
|
||||
SetA32("<<<<11101x00xxxxxxxx101xx0x0xxxx", InstName.Vdiv, InstEmit32.Vdiv_S, OpCode32SimdRegS.Create);
|
||||
SetA32("<<<<11101xx0xxxxxxxx1011x0x10000", InstName.Vdup, InstEmit32.Vdup, OpCode32SimdDupGP.Create);
|
||||
SetA32("111100111x11xxxxxxxx11000xx0xxxx", InstName.Vdup, InstEmit32.Vdup_1, OpCode32SimdDupElem.Create);
|
||||
SetA32("111100110x00xxxxxxxx0001xxx1xxxx", InstName.Veor, InstEmit32.Veor_I, OpCode32SimdBinary.Create);
|
||||
SetA32("111100101x11xxxxxxxxxxxxxxx0xxxx", InstName.Vext, InstEmit32.Vext, OpCode32SimdExt.Create);
|
||||
SetA32("<<<<11101x10xxxxxxxx101xx0x0xxxx", InstName.Vfma, InstEmit32.Vfma_S, OpCode32SimdRegS.Create);
|
||||
SetA32("111100100x00xxxxxxxx1100xxx1xxxx", InstName.Vfma, InstEmit32.Vfma_V, OpCode32SimdReg.Create);
|
||||
SetA32("<<<<11101x10xxxxxxxx101xx1x0xxxx", InstName.Vfms, InstEmit32.Vfms_S, OpCode32SimdRegS.Create);
|
||||
SetA32("111100100x10xxxxxxxx1100xxx1xxxx", InstName.Vfms, InstEmit32.Vfms_V, OpCode32SimdReg.Create);
|
||||
SetA32("<<<<11101x01xxxxxxxx101xx1x0xxxx", InstName.Vfnma, InstEmit32.Vfnma_S, OpCode32SimdRegS.Create);
|
||||
SetA32("<<<<11101x01xxxxxxxx101xx0x0xxxx", InstName.Vfnms, InstEmit32.Vfnms_S, OpCode32SimdRegS.Create);
|
||||
SetA32("1111001x0x<<xxxxxxxx0000xxx0xxxx", InstName.Vhadd, InstEmit32.Vhadd, OpCode32SimdReg.Create);
|
||||
SetA32("111101001x10xxxxxxxxxx00xxxxxxxx", InstName.Vld1, InstEmit32.Vld1, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101000x10xxxxxxxx0111xxxxxxxx", InstName.Vld1, InstEmit32.Vld1, OpCode32SimdMemPair.Create); // Regs = 1.
|
||||
SetA32("111101000x10xxxxxxxx1010xxxxxxxx", InstName.Vld1, InstEmit32.Vld1, OpCode32SimdMemPair.Create); // Regs = 2.
|
||||
SetA32("111101000x10xxxxxxxx0110xxxxxxxx", InstName.Vld1, InstEmit32.Vld1, OpCode32SimdMemPair.Create); // Regs = 3.
|
||||
SetA32("111101001x10xxxxxxxx0000xxx0xxxx", InstName.Vld1, InstEmit32.Vld1, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101001x10xxxxxxxx0100xx0xxxxx", InstName.Vld1, InstEmit32.Vld1, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101001x10xxxxxxxx1000x000xxxx", InstName.Vld1, InstEmit32.Vld1, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101001x10xxxxxxxx1000x011xxxx", InstName.Vld1, InstEmit32.Vld1, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101001x10xxxxxxxx110000x0xxxx", InstName.Vld1, InstEmit32.Vld1, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101001x10xxxxxxxx110001xxxxxx", InstName.Vld1, InstEmit32.Vld1, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101001x10xxxxxxxx110010xxxxxx", InstName.Vld1, InstEmit32.Vld1, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101000x10xxxxxxxx0111xx0xxxxx", InstName.Vld1, InstEmit32.Vld1, OpCode32SimdMemPair.Create); // Regs = 1.
|
||||
SetA32("111101000x10xxxxxxxx1010xx<<xxxx", InstName.Vld1, InstEmit32.Vld1, OpCode32SimdMemPair.Create); // Regs = 2.
|
||||
SetA32("111101000x10xxxxxxxx0110xx0xxxxx", InstName.Vld1, InstEmit32.Vld1, OpCode32SimdMemPair.Create); // Regs = 3.
|
||||
SetA32("111101000x10xxxxxxxx0010xxxxxxxx", InstName.Vld1, InstEmit32.Vld1, OpCode32SimdMemPair.Create); // Regs = 4.
|
||||
SetA32("111101001x10xxxxxxxxxx01xxxxxxxx", InstName.Vld2, InstEmit32.Vld2, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101000x10xxxxxxxx100xxxxxxxxx", InstName.Vld2, InstEmit32.Vld2, OpCode32SimdMemPair.Create); // Regs = 1, inc = 1/2 (itype).
|
||||
SetA32("111101000x10xxxxxxxx0011xxxxxxxx", InstName.Vld2, InstEmit32.Vld2, OpCode32SimdMemPair.Create); // Regs = 2, inc = 2.
|
||||
SetA32("111101001x10xxxxxxxxxx10xxxxxxxx", InstName.Vld3, InstEmit32.Vld3, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101000x10xxxxxxxx010xxxxxxxxx", InstName.Vld3, InstEmit32.Vld3, OpCode32SimdMemPair.Create); // Inc = 1/2 (itype).
|
||||
SetA32("111101001x10xxxxxxxxxx11xxxxxxxx", InstName.Vld4, InstEmit32.Vld4, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101000x10xxxxxxxx000xxxxxxxxx", InstName.Vld4, InstEmit32.Vld4, OpCode32SimdMemPair.Create); // Inc = 1/2 (itype).
|
||||
SetA32("<<<<11001x01xxxxxxxx1011xxxxxxx0", InstName.Vldm, InstEmit32.Vldm, OpCode32SimdMemMult.Create);
|
||||
SetA32("<<<<11001x11xxxxxxxx1011xxxxxxx0", InstName.Vldm, InstEmit32.Vldm, OpCode32SimdMemMult.Create);
|
||||
SetA32("<<<<11010x11xxxxxxxx1011xxxxxxx0", InstName.Vldm, InstEmit32.Vldm, OpCode32SimdMemMult.Create);
|
||||
SetA32("<<<<11001x01xxxxxxxx1010xxxxxxxx", InstName.Vldm, InstEmit32.Vldm, OpCode32SimdMemMult.Create);
|
||||
SetA32("<<<<11001x11xxxxxxxx1010xxxxxxxx", InstName.Vldm, InstEmit32.Vldm, OpCode32SimdMemMult.Create);
|
||||
SetA32("<<<<11010x11xxxxxxxx1010xxxxxxxx", InstName.Vldm, InstEmit32.Vldm, OpCode32SimdMemMult.Create);
|
||||
SetA32("<<<<1101xx01xxxxxxxx101xxxxxxxxx", InstName.Vldr, InstEmit32.Vldr, OpCode32SimdMemImm.Create);
|
||||
SetA32("111101001x10xxxxxxxx0x01xxxxxxxx", InstName.Vld2, InstEmit32.Vld2, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101001x10xxxxxxxx1001xx0xxxxx", InstName.Vld2, InstEmit32.Vld2, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101001x10xxxxxxxx1101<<xxxxxx", InstName.Vld2, InstEmit32.Vld2, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101000x10xxxxxxxx100x<<0xxxxx", InstName.Vld2, InstEmit32.Vld2, OpCode32SimdMemPair.Create); // Regs = 1, inc = 1/2 (itype).
|
||||
SetA32("111101000x10xxxxxxxx100x<<10xxxx", InstName.Vld2, InstEmit32.Vld2, OpCode32SimdMemPair.Create); // Regs = 1, inc = 1/2 (itype).
|
||||
SetA32("111101000x10xxxxxxxx0011<<xxxxxx", InstName.Vld2, InstEmit32.Vld2, OpCode32SimdMemPair.Create); // Regs = 2, inc = 2.
|
||||
SetA32("111101001x10xxxxxxxx0x10xxx0xxxx", InstName.Vld3, InstEmit32.Vld3, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101001x10xxxxxxxx1010xx00xxxx", InstName.Vld3, InstEmit32.Vld3, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101001x10xxxxxxxx1110<<x0xxxx", InstName.Vld3, InstEmit32.Vld3, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101000x10xxxxxxxx010x<<0xxxxx", InstName.Vld3, InstEmit32.Vld3, OpCode32SimdMemPair.Create); // Inc = 1/2 (itype).
|
||||
SetA32("111101001x10xxxxxxxx0x11xxxxxxxx", InstName.Vld4, InstEmit32.Vld4, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101001x10xxxxxxxx1011xx<<xxxx", InstName.Vld4, InstEmit32.Vld4, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101001x10xxxxxxxx1111<<x>xxxx", InstName.Vld4, InstEmit32.Vld4, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101000x10xxxxxxxx000x<<xxxxxx", InstName.Vld4, InstEmit32.Vld4, OpCode32SimdMemPair.Create); // Inc = 1/2 (itype).
|
||||
SetA32("1111001x0x<<xxxxxxxx0110xxx0xxxx", InstName.Vmax, InstEmit32.Vmax_I, OpCode32SimdReg.Create);
|
||||
SetA32("111100100x00xxxxxxxx1111xxx0xxxx", InstName.Vmax, InstEmit32.Vmax_V, OpCode32SimdReg.Create);
|
||||
SetA32("1111001x0x<<xxxxxxxx0110xxx1xxxx", InstName.Vmin, InstEmit32.Vmin_I, OpCode32SimdReg.Create);
|
||||
SetA32("111100100x10xxxxxxxx1111xxx0xxxx", InstName.Vmin, InstEmit32.Vmin_V, OpCode32SimdReg.Create);
|
||||
SetA32("111111101x00xxxxxxxx10>>x0x0xxxx", InstName.Vmaxnm, InstEmit32.Vmaxnm_S, OpCode32SimdRegS.Create);
|
||||
SetA32("111100110x0xxxxxxxxx1111xxx1xxxx", InstName.Vmaxnm, InstEmit32.Vmaxnm_V, OpCode32SimdReg.Create);
|
||||
SetA32("111111101x00xxxxxxxx10>>x1x0xxxx", InstName.Vminnm, InstEmit32.Vminnm_S, OpCode32SimdRegS.Create);
|
||||
SetA32("111100110x1xxxxxxxxx1111xxx1xxxx", InstName.Vminnm, InstEmit32.Vminnm_V, OpCode32SimdReg.Create);
|
||||
SetA32("1111001x1x<<xxxxxxxx000xx1x0xxxx", InstName.Vmla, InstEmit32.Vmla_1, OpCode32SimdRegElem.Create);
|
||||
SetA32("111100100xxxxxxxxxxx1001xxx0xxxx", InstName.Vmla, InstEmit32.Vmla_I, OpCode32SimdReg.Create);
|
||||
SetA32("<<<<11100x00xxxxxxxx101xx0x0xxxx", InstName.Vmla, InstEmit32.Vmla_S, OpCode32SimdRegS.Create);
|
||||
SetA32("111100100x00xxxxxxxx1101xxx1xxxx", InstName.Vmla, InstEmit32.Vmla_V, OpCode32SimdReg.Create);
|
||||
SetA32("1111001x1x<<xxxxxxx01000x0x0xxxx", InstName.Vmlal, InstEmit32.Vmlal_I, OpCode32SimdRegLong.Create);
|
||||
SetA32("1111001x1x<<xxxxxxxx010xx1x0xxxx", InstName.Vmls, InstEmit32.Vmls_1, OpCode32SimdRegElem.Create);
|
||||
SetA32("<<<<11100x00xxxxxxxx101xx1x0xxxx", InstName.Vmls, InstEmit32.Vmls_S, OpCode32SimdRegS.Create);
|
||||
SetA32("111100100x10xxxxxxxx1101xxx1xxxx", InstName.Vmls, InstEmit32.Vmls_V, OpCode32SimdReg.Create);
|
||||
SetA32("111100110xxxxxxxxxxx1001xxx0xxxx", InstName.Vmls, InstEmit32.Vmls_I, OpCode32SimdReg.Create);
|
||||
SetA32("1111001x1x<<xxxxxxx01010x0x0xxxx", InstName.Vmlsl, InstEmit32.Vmlsl_I, OpCode32SimdRegLong.Create);
|
||||
SetA32("<<<<11100xx0xxxxxxxx1011xxx10000", InstName.Vmov, InstEmit32.Vmov_G1, OpCode32SimdMovGpElem.Create); // From gen purpose.
|
||||
SetA32("<<<<1110xxx1xxxxxxxx1011xxx10000", InstName.Vmov, InstEmit32.Vmov_G1, OpCode32SimdMovGpElem.Create); // To gen purpose.
|
||||
SetA32("<<<<1100010xxxxxxxxx101000x1xxxx", InstName.Vmov, InstEmit32.Vmov_G2, OpCode32SimdMovGpDouble.Create); // To/from gen purpose x2 and single precision x2.
|
||||
SetA32("<<<<1100010xxxxxxxxx101100x1xxxx", InstName.Vmov, InstEmit32.Vmov_GD, OpCode32SimdMovGpDouble.Create); // To/from gen purpose x2 and double precision.
|
||||
SetA32("<<<<1110000xxxxxxxxx1010x0010000", InstName.Vmov, InstEmit32.Vmov_GS, OpCode32SimdMovGp.Create); // To/from gen purpose and single precision.
|
||||
SetA32("1111001x1x000xxxxxxx0xx00x01xxxx", InstName.Vmov, InstEmit32.Vmov_I, OpCode32SimdImm.Create); // D/Q vector I32.
|
||||
SetA32("<<<<11101x11xxxxxxxx101x0000xxxx", InstName.Vmov, InstEmit32.Vmov_I, OpCode32SimdImm44.Create); // Scalar f16/32/64 based on size 01 10 11.
|
||||
SetA32("1111001x1x000xxxxxxx10x00x01xxxx", InstName.Vmov, InstEmit32.Vmov_I, OpCode32SimdImm.Create); // D/Q I16.
|
||||
SetA32("1111001x1x000xxxxxxx11xx0x01xxxx", InstName.Vmov, InstEmit32.Vmov_I, OpCode32SimdImm.Create); // D/Q (dt - from cmode).
|
||||
SetA32("1111001x1x000xxxxxxx11100x11xxxx", InstName.Vmov, InstEmit32.Vmov_I, OpCode32SimdImm.Create); // D/Q I64.
|
||||
SetA32("<<<<11101x110000xxxx101x01x0xxxx", InstName.Vmov, InstEmit32.Vmov_S, OpCode32SimdS.Create);
|
||||
SetA32("1111001x1x001000xxx0101000x1xxxx", InstName.Vmovl, InstEmit32.Vmovl, OpCode32SimdLong.Create);
|
||||
SetA32("1111001x1x010000xxx0101000x1xxxx", InstName.Vmovl, InstEmit32.Vmovl, OpCode32SimdLong.Create);
|
||||
SetA32("1111001x1x100000xxx0101000x1xxxx", InstName.Vmovl, InstEmit32.Vmovl, OpCode32SimdLong.Create);
|
||||
SetA32("111100111x11xx10xxxx001000x0xxx0", InstName.Vmovn, InstEmit32.Vmovn, OpCode32SimdCmpZ.Create);
|
||||
SetA32("<<<<11101111xxxxxxxx101000010000", InstName.Vmrs, InstEmit32.Vmrs, OpCode32SimdSpecial.Create);
|
||||
SetA32("<<<<11101110xxxxxxxx101000010000", InstName.Vmsr, InstEmit32.Vmsr, OpCode32SimdSpecial.Create);
|
||||
SetA32("111100111x11<<10xxxx001000x0xxx0", InstName.Vmovn, InstEmit32.Vmovn, OpCode32SimdMovn.Create);
|
||||
SetA32("1111001x1x<<xxxxxxxx100xx1x0xxxx", InstName.Vmul, InstEmit32.Vmul_1, OpCode32SimdRegElem.Create);
|
||||
SetA32("111100100x<<xxxxxxxx1001xxx1xxxx", InstName.Vmul, InstEmit32.Vmul_I, OpCode32SimdReg.Create);
|
||||
SetA32("111100110x00xxxxxxxx1001xxx1xxxx", InstName.Vmul, InstEmit32.Vmul_I, OpCode32SimdReg.Create);
|
||||
SetA32("<<<<11100x10xxxxxxxx101xx0x0xxxx", InstName.Vmul, InstEmit32.Vmul_S, OpCode32SimdRegS.Create);
|
||||
SetA32("111100110x00xxxxxxxx1101xxx1xxxx", InstName.Vmul, InstEmit32.Vmul_V, OpCode32SimdReg.Create);
|
||||
SetA32("1111001x1x<<xxxxxxx01010x1x0xxxx", InstName.Vmull, InstEmit32.Vmull_1, OpCode32SimdRegElemLong.Create);
|
||||
SetA32("1111001x1x<<xxxxxxx01100x0x0xxxx", InstName.Vmull, InstEmit32.Vmull_I, OpCode32SimdRegLong.Create);
|
||||
@@ -913,64 +946,70 @@ namespace ARMeilleure.Decoders
|
||||
SetA32("1111001x1x000xxxxxxx0xx00x11xxxx", InstName.Vmvn, InstEmit32.Vmvn_II, OpCode32SimdImm.Create); // D/Q vector I32.
|
||||
SetA32("1111001x1x000xxxxxxx10x00x11xxxx", InstName.Vmvn, InstEmit32.Vmvn_II, OpCode32SimdImm.Create);
|
||||
SetA32("1111001x1x000xxxxxxx110x0x11xxxx", InstName.Vmvn, InstEmit32.Vmvn_II, OpCode32SimdImm.Create);
|
||||
SetA32("<<<<11101x110001xxxx101x01x0xxxx", InstName.Vneg, InstEmit32.Vneg_S, OpCode32SimdS.Create);
|
||||
SetA32("111100111x11<<01xxxx00111xx0xxxx", InstName.Vneg, InstEmit32.Vneg_V, OpCode32SimdCmpZ.Create);
|
||||
SetA32("111100111x111001xxxx01111xx0xxxx", InstName.Vneg, InstEmit32.Vneg_V, OpCode32SimdCmpZ.Create);
|
||||
SetA32("<<<<11100x01xxxxxxxx101xx1x0xxxx", InstName.Vnmla, InstEmit32.Vnmla_S, OpCode32SimdRegS.Create);
|
||||
SetA32("<<<<11100x01xxxxxxxx101xx0x0xxxx", InstName.Vnmls, InstEmit32.Vnmls_S, OpCode32SimdRegS.Create);
|
||||
SetA32("<<<<11100x10xxxxxxxx101xx1x0xxxx", InstName.Vnmul, InstEmit32.Vnmul_S, OpCode32SimdRegS.Create);
|
||||
SetA32("111100100x11xxxxxxxx0001xxx1xxxx", InstName.Vorn, InstEmit32.Vorn_I, OpCode32SimdBinary.Create);
|
||||
SetA32("111100100x10xxxxxxxx0001xxx1xxxx", InstName.Vorr, InstEmit32.Vorr_I, OpCode32SimdBinary.Create);
|
||||
SetA32("1111001x1x000xxxxxxx<<x10x01xxxx", InstName.Vorr, InstEmit32.Vorr_II, OpCode32SimdImm.Create);
|
||||
SetA32("111100100x<<xxxxxxxx1011x0x1xxxx", InstName.Vpadd, InstEmit32.Vpadd_I, OpCode32SimdReg.Create);
|
||||
SetA32("111100110x00xxxxxxxx1101x0x0xxxx", InstName.Vpadd, InstEmit32.Vpadd_V, OpCode32SimdReg.Create);
|
||||
SetA32("111100111x11<<00xxxx0010xxx0xxxx", InstName.Vpaddl, InstEmit32.Vpaddl, OpCode32SimdCmpZ.Create);
|
||||
SetA32("1111001x0x<<xxxxxxxx1010x0x0xxxx", InstName.Vpmax, InstEmit32.Vpmax_I, OpCode32SimdReg.Create);
|
||||
SetA32("111100110x00xxxxxxxx1111x0x0xxxx", InstName.Vpmax, InstEmit32.Vpmax_V, OpCode32SimdReg.Create);
|
||||
SetA32("1111001x0x<<xxxxxxxx1010x0x1xxxx", InstName.Vpmin, InstEmit32.Vpmin_I, OpCode32SimdReg.Create);
|
||||
SetA32("111100110x10xxxxxxxx1111x0x0xxxx", InstName.Vpmin, InstEmit32.Vpmin_V, OpCode32SimdReg.Create);
|
||||
SetA32("1111001x0xxxxxxxxxxx0000xxx1xxxx", InstName.Vqadd, InstEmit32.Vqadd, OpCode32SimdReg.Create);
|
||||
SetA32("111100100x01xxxxxxxx1011xxx0xxxx", InstName.Vqdmulh, InstEmit32.Vqdmulh, OpCode32SimdReg.Create);
|
||||
SetA32("111100100x10xxxxxxxx1011xxx0xxxx", InstName.Vqdmulh, InstEmit32.Vqdmulh, OpCode32SimdReg.Create);
|
||||
SetA32("111100111x11<<10xxxx00101xx0xxx0", InstName.Vqmovn, InstEmit32.Vqmovn, OpCode32SimdMovn.Create);
|
||||
SetA32("111100111x11<<10xxxx001001x0xxx0", InstName.Vqmovun, InstEmit32.Vqmovun, OpCode32SimdMovn.Create);
|
||||
SetA32("1111001x1x>>>xxxxxxx100101x1xxx0", InstName.Vqrshrn, InstEmit32.Vqrshrn, OpCode32SimdShImmNarrow.Create);
|
||||
SetA32("111100111x>>>xxxxxxx100001x1xxx0", InstName.Vqrshrun, InstEmit32.Vqrshrun, OpCode32SimdShImmNarrow.Create);
|
||||
SetA32("1111001x1x>>>xxxxxxx100100x1xxx0", InstName.Vqshrn, InstEmit32.Vqshrn, OpCode32SimdShImmNarrow.Create);
|
||||
SetA32("111100111x>>>xxxxxxx100000x1xxx0", InstName.Vqshrun, InstEmit32.Vqshrun, OpCode32SimdShImmNarrow.Create);
|
||||
SetA32("1111001x0xxxxxxxxxxx0010xxx1xxxx", InstName.Vqsub, InstEmit32.Vqsub, OpCode32SimdReg.Create);
|
||||
SetA32("111100111x111011xxxx010x0xx0xxxx", InstName.Vrecpe, InstEmit32.Vrecpe, OpCode32SimdSqrte.Create);
|
||||
SetA32("111100100x00xxxxxxxx1111xxx1xxxx", InstName.Vrecps, InstEmit32.Vrecps, OpCode32SimdReg.Create);
|
||||
SetA32("111100111x11xx00xxxx000<<xx0xxxx", InstName.Vrev, InstEmit32.Vrev, OpCode32SimdRev.Create);
|
||||
SetA32("111111101x1110xxxxxx101x01x0xxxx", InstName.Vrint, InstEmit32.Vrint_RM, OpCode32SimdS.Create);
|
||||
SetA32("<<<<11101x110110xxxx101x11x0xxxx", InstName.Vrint, InstEmit32.Vrint_Z, OpCode32SimdS.Create);
|
||||
SetA32("<<<<11101x110111xxxx101x01x0xxxx", InstName.Vrintx, InstEmit32.Vrintx_S, OpCode32SimdS.Create);
|
||||
SetA32("1111001x0x<<xxxxxxxx0001xxx0xxxx", InstName.Vrhadd, InstEmit32.Vrhadd, OpCode32SimdReg.Create);
|
||||
SetA32("111100111x111010xxxx01010xx0xxxx", InstName.Vrinta, InstEmit32.Vrinta_V, OpCode32SimdCmpZ.Create);
|
||||
SetA32("111100111x111010xxxx01101xx0xxxx", InstName.Vrintm, InstEmit32.Vrintm_V, OpCode32SimdCmpZ.Create);
|
||||
SetA32("111100111x111010xxxx01000xx0xxxx", InstName.Vrintn, InstEmit32.Vrintn_V, OpCode32SimdCmpZ.Create);
|
||||
SetA32("111100111x111010xxxx01111xx0xxxx", InstName.Vrintp, InstEmit32.Vrintp_V, OpCode32SimdCmpZ.Create);
|
||||
SetA32("1111001x1x>>>xxxxxxx0010>xx1xxxx", InstName.Vrshr, InstEmit32.Vrshr, OpCode32SimdShImm.Create);
|
||||
SetA32("111100101x>>>xxxxxxx100001x1xxx0", InstName.Vrshrn, InstEmit32.Vrshrn, OpCode32SimdShImmNarrow.Create);
|
||||
SetA32("111100111x111011xxxx010x1xx0xxxx", InstName.Vrsqrte, InstEmit32.Vrsqrte, OpCode32SimdSqrte.Create);
|
||||
SetA32("111100100x10xxxxxxxx1111xxx1xxxx", InstName.Vrsqrts, InstEmit32.Vrsqrts, OpCode32SimdReg.Create);
|
||||
SetA32("111111100xxxxxxxxxxx101xx0x0xxxx", InstName.Vsel, InstEmit32.Vsel, OpCode32SimdSel.Create);
|
||||
SetA32("1111001x1x>>>xxxxxxx0011>xx1xxxx", InstName.Vrsra, InstEmit32.Vrsra, OpCode32SimdShImm.Create);
|
||||
SetA32("111100101x>>>xxxxxxx0101>xx1xxxx", InstName.Vshl, InstEmit32.Vshl, OpCode32SimdShImm.Create);
|
||||
SetA32("1111001x0xxxxxxxxxxx0100xxx0xxxx", InstName.Vshl, InstEmit32.Vshl_I, OpCode32SimdReg.Create);
|
||||
SetA32("1111001x1x>>>xxxxxxx101000x1xxxx", InstName.Vshll, InstEmit32.Vshll, OpCode32SimdShImmLong.Create); // A1 encoding.
|
||||
SetA32("1111001x1x>>>xxxxxxx0000>xx1xxxx", InstName.Vshr, InstEmit32.Vshr, OpCode32SimdShImm.Create);
|
||||
SetA32("111100101x>>>xxxxxxx100000x1xxx0", InstName.Vshrn, InstEmit32.Vshrn, OpCode32SimdShImmNarrow.Create);
|
||||
SetA32("<<<<11101x110001xxxx101x11x0xxxx", InstName.Vsqrt, InstEmit32.Vsqrt_S, OpCode32SimdS.Create);
|
||||
SetA32("1111001x1x>>>xxxxxxx0001>xx1xxxx", InstName.Vsra, InstEmit32.Vsra, OpCode32SimdShImm.Create);
|
||||
SetA32("111101001x00xxxxxxxx<<00xxxxxxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101000x00xxxxxxxx0111xxxxxxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemPair.Create); // Regs = 1.
|
||||
SetA32("111101000x00xxxxxxxx1010xxxxxxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemPair.Create); // Regs = 2.
|
||||
SetA32("111101000x00xxxxxxxx0110xxxxxxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemPair.Create); // Regs = 3.
|
||||
SetA32("111101001x00xxxxxxxx0000xxx0xxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101001x00xxxxxxxx0100xx0xxxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101001x00xxxxxxxx1000x000xxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101001x00xxxxxxxx1000x011xxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101000x00xxxxxxxx0111xx0xxxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemPair.Create); // Regs = 1.
|
||||
SetA32("111101000x00xxxxxxxx1010xx<<xxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemPair.Create); // Regs = 2.
|
||||
SetA32("111101000x00xxxxxxxx0110xx0xxxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemPair.Create); // Regs = 3.
|
||||
SetA32("111101000x00xxxxxxxx0010xxxxxxxx", InstName.Vst1, InstEmit32.Vst1, OpCode32SimdMemPair.Create); // Regs = 4.
|
||||
SetA32("111101001x00xxxxxxxx<<01xxxxxxxx", InstName.Vst2, InstEmit32.Vst2, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101000x00xxxxxxxx100xxxxxxxxx", InstName.Vst2, InstEmit32.Vst2, OpCode32SimdMemPair.Create); // Regs = 1, inc = 1/2 (itype).
|
||||
SetA32("111101000x00xxxxxxxx0011xxxxxxxx", InstName.Vst2, InstEmit32.Vst2, OpCode32SimdMemPair.Create); // Regs = 2, inc = 2.
|
||||
SetA32("111101001x00xxxxxxxx<<10xxxxxxxx", InstName.Vst3, InstEmit32.Vst3, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101000x00xxxxxxxx010xxxxxxxxx", InstName.Vst3, InstEmit32.Vst3, OpCode32SimdMemPair.Create); // Inc = 1/2 (itype).
|
||||
SetA32("111101001x00xxxxxxxx<<11xxxxxxxx", InstName.Vst4, InstEmit32.Vst4, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101000x00xxxxxxxx000xxxxxxxxx", InstName.Vst4, InstEmit32.Vst4, OpCode32SimdMemPair.Create); // Inc = 1/2 (itype).
|
||||
SetA32("<<<<11001x00xxxxxxxx1011xxxxxxx0", InstName.Vstm, InstEmit32.Vstm, OpCode32SimdMemMult.Create);
|
||||
SetA32("<<<<11001x10xxxxxxxx1011xxxxxxx0", InstName.Vstm, InstEmit32.Vstm, OpCode32SimdMemMult.Create);
|
||||
SetA32("<<<<11010x10xxxxxxxx1011xxxxxxx0", InstName.Vstm, InstEmit32.Vstm, OpCode32SimdMemMult.Create);
|
||||
SetA32("<<<<11001x00xxxxxxxx1010xxxxxxxx", InstName.Vstm, InstEmit32.Vstm, OpCode32SimdMemMult.Create);
|
||||
SetA32("<<<<11001x10xxxxxxxx1010xxxxxxxx", InstName.Vstm, InstEmit32.Vstm, OpCode32SimdMemMult.Create);
|
||||
SetA32("<<<<11010x10xxxxxxxx1010xxxxxxxx", InstName.Vstm, InstEmit32.Vstm, OpCode32SimdMemMult.Create);
|
||||
SetA32("<<<<1101xx00xxxxxxxx101xxxxxxxxx", InstName.Vstr, InstEmit32.Vstr, OpCode32SimdMemImm.Create);
|
||||
SetA32("111101001x00xxxxxxxx0x01xxxxxxxx", InstName.Vst2, InstEmit32.Vst2, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101001x00xxxxxxxx1001xx0xxxxx", InstName.Vst2, InstEmit32.Vst2, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101000x00xxxxxxxx100x<<0xxxxx", InstName.Vst2, InstEmit32.Vst2, OpCode32SimdMemPair.Create); // Regs = 1, inc = 1/2 (itype).
|
||||
SetA32("111101000x00xxxxxxxx100x<<10xxxx", InstName.Vst2, InstEmit32.Vst2, OpCode32SimdMemPair.Create); // Regs = 1, inc = 1/2 (itype).
|
||||
SetA32("111101000x00xxxxxxxx0011<<xxxxxx", InstName.Vst2, InstEmit32.Vst2, OpCode32SimdMemPair.Create); // Regs = 2, inc = 2.
|
||||
SetA32("111101001x00xxxxxxxx0x10xxx0xxxx", InstName.Vst3, InstEmit32.Vst3, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101001x00xxxxxxxx1010xx00xxxx", InstName.Vst3, InstEmit32.Vst3, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101000x00xxxxxxxx010x<<0xxxxx", InstName.Vst3, InstEmit32.Vst3, OpCode32SimdMemPair.Create); // Inc = 1/2 (itype).
|
||||
SetA32("111101001x00xxxxxxxx0x11xxxxxxxx", InstName.Vst4, InstEmit32.Vst4, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101001x00xxxxxxxx1011xx<<xxxx", InstName.Vst4, InstEmit32.Vst4, OpCode32SimdMemSingle.Create);
|
||||
SetA32("111101000x00xxxxxxxx000x<<xxxxxx", InstName.Vst4, InstEmit32.Vst4, OpCode32SimdMemPair.Create); // Inc = 1/2 (itype).
|
||||
SetA32("111100110xxxxxxxxxxx1000xxx0xxxx", InstName.Vsub, InstEmit32.Vsub_I, OpCode32SimdReg.Create);
|
||||
SetA32("<<<<11100x11xxxxxxxx101xx1x0xxxx", InstName.Vsub, InstEmit32.Vsub_S, OpCode32SimdRegS.Create);
|
||||
SetA32("111100100x10xxxxxxxx1101xxx0xxxx", InstName.Vsub, InstEmit32.Vsub_V, OpCode32SimdReg.Create);
|
||||
SetA32("1111001x1x<<xxxxxxxx0011x0x0xxxx", InstName.Vsubw, InstEmit32.Vsubw_I, OpCode32SimdRegWide.Create);
|
||||
SetA32("1111001x1x<<xxxxxxx00010x0x0xxxx", InstName.Vsubl, InstEmit32.Vsubl_I, OpCode32SimdRegLong.Create);
|
||||
SetA32("1111001x1x<<xxxxxxx00011x0x0xxxx", InstName.Vsubw, InstEmit32.Vsubw_I, OpCode32SimdRegWide.Create);
|
||||
SetA32("111100111x11xxxxxxxx10xxxxx0xxxx", InstName.Vtbl, InstEmit32.Vtbl, OpCode32SimdTbl.Create);
|
||||
SetA32("111100111x11<<10xxxx00001xx0xxxx", InstName.Vtrn, InstEmit32.Vtrn, OpCode32SimdCmpZ.Create);
|
||||
SetA32("111100100x<<xxxxxxxx1000xxx1xxxx", InstName.Vtst, InstEmit32.Vtst, OpCode32SimdReg.Create);
|
||||
@@ -1008,7 +1047,7 @@ namespace ARMeilleure.Decoders
|
||||
SetT16("01000101xxxxxxxx", InstName.Cmp, InstEmit32.Cmp, OpCodeT16AluRegHigh.Create);
|
||||
SetT16("01000110xxxxxxxx", InstName.Mov, InstEmit32.Mov, OpCodeT16AluRegHigh.Create);
|
||||
SetT16("010001110xxxx000", InstName.Bx, InstEmit32.Bx, OpCodeT16BReg.Create);
|
||||
SetT16("010001111xxxx000", InstName.Blx, InstEmit32.Blx, OpCodeT16BReg.Create);
|
||||
SetT16("010001111xxxx000", InstName.Blx, InstEmit32.Blxr, OpCodeT16BReg.Create);
|
||||
SetT16("01001xxxxxxxxxxx", InstName.Ldr, InstEmit32.Ldr, OpCodeT16MemLit.Create);
|
||||
SetT16("0101000xxxxxxxxx", InstName.Str, InstEmit32.Str, OpCodeT16MemReg.Create);
|
||||
SetT16("0101001xxxxxxxxx", InstName.Strh, InstEmit32.Strh, OpCodeT16MemReg.Create);
|
||||
@@ -1056,49 +1095,71 @@ namespace ARMeilleure.Decoders
|
||||
SetT32("11110x01010xxxxx0xxxxxxxxxxxxxxx", InstName.Adc, InstEmit32.Adc, OpCodeT32AluImm.Create);
|
||||
SetT32("11101011000<xxxx0xxx<<<<xxxxxxxx", InstName.Add, InstEmit32.Add, OpCodeT32AluRsImm.Create);
|
||||
SetT32("11110x01000<xxxx0xxx<<<<xxxxxxxx", InstName.Add, InstEmit32.Add, OpCodeT32AluImm.Create);
|
||||
SetT32("11110x100000xxxx0xxxxxxxxxxxxxxx", InstName.Add, InstEmit32.Add, OpCodeT32AluImm12.Create);
|
||||
SetT32("11101010000<xxxx0xxx<<<<xxxxxxxx", InstName.And, InstEmit32.And, OpCodeT32AluRsImm.Create);
|
||||
SetT32("11110x00000<xxxx0xxx<<<<xxxxxxxx", InstName.And, InstEmit32.And, OpCodeT32AluImm.Create);
|
||||
SetT32("11110x<<<xxxxxxx10x0xxxxxxxxxxxx", InstName.B, InstEmit32.B, OpCodeT32BImm20.Create);
|
||||
SetT32("11110xxxxxxxxxxx10x1xxxxxxxxxxxx", InstName.B, InstEmit32.B, OpCodeT32BImm24.Create);
|
||||
SetT32("11110011011011110xxxxxxxxx0xxxxx", InstName.Bfc, InstEmit32.Bfc, OpCodeT32AluBf.Create);
|
||||
SetT32("111100110110<<<<0xxxxxxxxx0xxxxx", InstName.Bfi, InstEmit32.Bfi, OpCodeT32AluBf.Create);
|
||||
SetT32("11101010001xxxxx0xxxxxxxxxxxxxxx", InstName.Bic, InstEmit32.Bic, OpCodeT32AluRsImm.Create);
|
||||
SetT32("11110x00001xxxxx0xxxxxxxxxxxxxxx", InstName.Bic, InstEmit32.Bic, OpCodeT32AluImm.Create);
|
||||
SetT32("11110xxxxxxxxxxx11x1xxxxxxxxxxxx", InstName.Bl, InstEmit32.Bl, OpCodeT32BImm24.Create);
|
||||
SetT32("11110xxxxxxxxxxx11x0xxxxxxxxxxx0", InstName.Blx, InstEmit32.Blx, OpCodeT32BImm24.Create);
|
||||
SetT32("111110101011xxxx1111xxxx1000xxxx", InstName.Clz, InstEmit32.Clz, OpCodeT32AluReg.Create);
|
||||
SetT32("111010110001xxxx0xxx1111xxxxxxxx", InstName.Cmn, InstEmit32.Cmn, OpCodeT32AluRsImm.Create);
|
||||
SetT32("11110x010001xxxx0xxx1111xxxxxxxx", InstName.Cmn, InstEmit32.Cmn, OpCodeT32AluImm.Create);
|
||||
SetT32("111010111011xxxx0xxx1111xxxxxxxx", InstName.Cmp, InstEmit32.Cmp, OpCodeT32AluRsImm.Create);
|
||||
SetT32("11110x011011xxxx0xxx1111xxxxxxxx", InstName.Cmp, InstEmit32.Cmp, OpCodeT32AluImm.Create);
|
||||
SetT32("11101010100<xxxx0xxx<<<<xxxxxxxx", InstName.Eor, InstEmit32.Eor, OpCodeT32AluRsImm.Create);
|
||||
SetT32("11110x00100<xxxx0xxx<<<<xxxxxxxx", InstName.Eor, InstEmit32.Eor, OpCodeT32AluImm.Create);
|
||||
SetT32("111010001101xxxxxxxx111110101111", InstName.Lda, InstEmit32.Lda, OpCodeT32MemLdEx.Create);
|
||||
SetT32("111010001101xxxxxxxx111110001111", InstName.Ldab, InstEmit32.Ldab, OpCodeT32MemLdEx.Create);
|
||||
SetT32("111010001101xxxxxxxx111111101111", InstName.Ldaex, InstEmit32.Ldaex, OpCodeT32MemLdEx.Create);
|
||||
SetT32("111010001101xxxxxxxx111111001111", InstName.Ldaexb, InstEmit32.Ldaexb, OpCodeT32MemLdEx.Create);
|
||||
SetT32("111010001101xxxxxxxxxxxx11111111", InstName.Ldaexd, InstEmit32.Ldaexd, OpCodeT32MemLdEx.Create);
|
||||
SetT32("111010001101xxxxxxxx111111011111", InstName.Ldaexh, InstEmit32.Ldaexh, OpCodeT32MemLdEx.Create);
|
||||
SetT32("111010001101xxxxxxxx111110011111", InstName.Ldah, InstEmit32.Ldah, OpCodeT32MemLdEx.Create);
|
||||
SetT32("1110100010x1xxxxxxxxxxxxxxxxxxxx", InstName.Ldm, InstEmit32.Ldm, OpCodeT32MemMult.Create);
|
||||
SetT32("1110100100x1xxxxxxxxxxxxxxxxxxxx", InstName.Ldm, InstEmit32.Ldm, OpCodeT32MemMult.Create);
|
||||
SetT32("111110000101xxxx<<<<10x1xxxxxxxx", InstName.Ldr, InstEmit32.Ldr, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110000101xxxx<<<<1100xxxxxxxx", InstName.Ldr, InstEmit32.Ldr, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110000101xxxx<<<<11x1xxxxxxxx", InstName.Ldr, InstEmit32.Ldr, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110000101xxxxxxxx10x1xxxxxxxx", InstName.Ldr, InstEmit32.Ldr, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110000101xxxxxxxx1100xxxxxxxx", InstName.Ldr, InstEmit32.Ldr, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110000101xxxxxxxx11x1xxxxxxxx", InstName.Ldr, InstEmit32.Ldr, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110001101xxxxxxxxxxxxxxxxxxxx", InstName.Ldr, InstEmit32.Ldr, OpCodeT32MemImm12.Create);
|
||||
SetT32("111110000101<<<<xxxx000000xxxxxx", InstName.Ldr, InstEmit32.Ldr, OpCodeT32MemRsImm.Create);
|
||||
SetT32("111110000001xxxx<<<<10x1xxxxxxxx", InstName.Ldrb, InstEmit32.Ldrb, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110000001xxxx<<<<1100xxxxxxxx", InstName.Ldrb, InstEmit32.Ldrb, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110000001xxxx<<<<11x1xxxxxxxx", InstName.Ldrb, InstEmit32.Ldrb, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110000001xxxxxxxx10x1xxxxxxxx", InstName.Ldrb, InstEmit32.Ldrb, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110000001xxxxxxxx1100xxxxxxxx", InstName.Ldrb, InstEmit32.Ldrb, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110000001xxxxxxxx11x1xxxxxxxx", InstName.Ldrb, InstEmit32.Ldrb, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110001001xxxxxxxxxxxxxxxxxxxx", InstName.Ldrb, InstEmit32.Ldrb, OpCodeT32MemImm12.Create);
|
||||
SetT32("1110100>x1>1<<<<xxxxxxxxxxxxxxxx", InstName.Ldrd, InstEmit32.Ldrd, OpCodeT32MemImm8D.Create);
|
||||
SetT32("111110000011xxxx<<<<10x1xxxxxxxx", InstName.Ldrh, InstEmit32.Ldrh, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110000011xxxx<<<<1100xxxxxxxx", InstName.Ldrh, InstEmit32.Ldrh, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110000011xxxx<<<<11x1xxxxxxxx", InstName.Ldrh, InstEmit32.Ldrh, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110000001xxxx<<<<000000xxxxxx", InstName.Ldrb, InstEmit32.Ldrb, OpCodeT32MemRsImm.Create);
|
||||
SetT32("11101000x111<<<<xxxxxxxxxxxxxxxx", InstName.Ldrd, InstEmit32.Ldrd, OpCodeT32MemImm8D.Create);
|
||||
SetT32("11101001x1x1<<<<xxxxxxxxxxxxxxxx", InstName.Ldrd, InstEmit32.Ldrd, OpCodeT32MemImm8D.Create);
|
||||
SetT32("111110000011xxxxxxxx10x1xxxxxxxx", InstName.Ldrh, InstEmit32.Ldrh, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110000011xxxxxxxx1100xxxxxxxx", InstName.Ldrh, InstEmit32.Ldrh, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110000011xxxxxxxx11x1xxxxxxxx", InstName.Ldrh, InstEmit32.Ldrh, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110001011xxxxxxxxxxxxxxxxxxxx", InstName.Ldrh, InstEmit32.Ldrh, OpCodeT32MemImm12.Create);
|
||||
SetT32("111110010001xxxx<<<<10x1xxxxxxxx", InstName.Ldrsb, InstEmit32.Ldrsb, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110010001xxxx<<<<1100xxxxxxxx", InstName.Ldrsb, InstEmit32.Ldrsb, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110010001xxxx<<<<11x1xxxxxxxx", InstName.Ldrsb, InstEmit32.Ldrsb, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110000011xxxx<<<<000000xxxxxx", InstName.Ldrh, InstEmit32.Ldrh, OpCodeT32MemRsImm.Create);
|
||||
SetT32("111110010001xxxxxxxx10x1xxxxxxxx", InstName.Ldrsb, InstEmit32.Ldrsb, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110010001xxxxxxxx1100xxxxxxxx", InstName.Ldrsb, InstEmit32.Ldrsb, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110010001xxxxxxxx11x1xxxxxxxx", InstName.Ldrsb, InstEmit32.Ldrsb, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110011001xxxxxxxxxxxxxxxxxxxx", InstName.Ldrsb, InstEmit32.Ldrsb, OpCodeT32MemImm12.Create);
|
||||
SetT32("111110010011xxxx<<<<10x1xxxxxxxx", InstName.Ldrsh, InstEmit32.Ldrsh, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110010011xxxx<<<<1100xxxxxxxx", InstName.Ldrsh, InstEmit32.Ldrsh, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110010011xxxx<<<<11x1xxxxxxxx", InstName.Ldrsh, InstEmit32.Ldrsh, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110010001xxxx<<<<000000xxxxxx", InstName.Ldrsb, InstEmit32.Ldrsb, OpCodeT32MemRsImm.Create);
|
||||
SetT32("111110010011xxxxxxxx10x1xxxxxxxx", InstName.Ldrsh, InstEmit32.Ldrsh, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110010011xxxxxxxx1100xxxxxxxx", InstName.Ldrsh, InstEmit32.Ldrsh, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110010011xxxxxxxx11x1xxxxxxxx", InstName.Ldrsh, InstEmit32.Ldrsh, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110011011xxxxxxxxxxxxxxxxxxxx", InstName.Ldrsh, InstEmit32.Ldrsh, OpCodeT32MemImm12.Create);
|
||||
SetT32("111110010011xxxx<<<<000000xxxxxx", InstName.Ldrsh, InstEmit32.Ldrsh, OpCodeT32MemRsImm.Create);
|
||||
SetT32("111110110000xxxx<<<<xxxx0000xxxx", InstName.Mla, InstEmit32.Mla, OpCodeT32AluMla.Create);
|
||||
SetT32("111110110000xxxxxxxxxxxx0001xxxx", InstName.Mls, InstEmit32.Mls, OpCodeT32AluMla.Create);
|
||||
SetT32("11101010010x11110xxxxxxxxxxxxxxx", InstName.Mov, InstEmit32.Mov, OpCodeT32AluRsImm.Create);
|
||||
SetT32("111110100xxxxxxx1111xxxx0000xxxx", InstName.Mov, InstEmit32.Mov, OpCodeT32ShiftReg.Create);
|
||||
SetT32("11110x00010x11110xxxxxxxxxxxxxxx", InstName.Mov, InstEmit32.Mov, OpCodeT32AluImm.Create);
|
||||
SetT32("11110x100100xxxx0xxxxxxxxxxxxxxx", InstName.Mov, InstEmit32.Mov, OpCodeT32MovImm16.Create);
|
||||
SetT32("11110x101100xxxx0xxxxxxxxxxxxxxx", InstName.Movt, InstEmit32.Movt, OpCodeT32MovImm16.Create);
|
||||
SetT32("111110110000xxxx1111xxxx0000xxxx", InstName.Mul, InstEmit32.Mul, OpCodeT32AluMla.Create);
|
||||
SetT32("11101010011x11110xxxxxxxxxxxxxxx", InstName.Mvn, InstEmit32.Mvn, OpCodeT32AluRsImm.Create);
|
||||
SetT32("11110x00011x11110xxxxxxxxxxxxxxx", InstName.Mvn, InstEmit32.Mvn, OpCodeT32AluImm.Create);
|
||||
SetT32("11110011101011111000000000000000", InstName.Nop, InstEmit32.Nop, OpCodeT32.Create);
|
||||
SetT32("11101010011x<<<<0xxxxxxxxxxxxxxx", InstName.Orn, InstEmit32.Orn, OpCodeT32AluRsImm.Create);
|
||||
SetT32("11110x00011x<<<<0xxxxxxxxxxxxxxx", InstName.Orn, InstEmit32.Orn, OpCodeT32AluImm.Create);
|
||||
SetT32("11101010010x<<<<0xxxxxxxxxxxxxxx", InstName.Orr, InstEmit32.Orr, OpCodeT32AluRsImm.Create);
|
||||
@@ -1107,7 +1168,24 @@ namespace ARMeilleure.Decoders
|
||||
SetT32("11110x01110xxxxx0xxxxxxxxxxxxxxx", InstName.Rsb, InstEmit32.Rsb, OpCodeT32AluImm.Create);
|
||||
SetT32("11101011011xxxxx0xxxxxxxxxxxxxxx", InstName.Sbc, InstEmit32.Sbc, OpCodeT32AluRsImm.Create);
|
||||
SetT32("11110x01011xxxxx0xxxxxxxxxxxxxxx", InstName.Sbc, InstEmit32.Sbc, OpCodeT32AluImm.Create);
|
||||
SetT32("111100110100xxxx0xxxxxxxxx0xxxxx", InstName.Sbfx, InstEmit32.Sbfx, OpCodeT32AluBf.Create);
|
||||
SetT32("111110111001xxxx1111xxxx1111xxxx", InstName.Sdiv, InstEmit32.Sdiv, OpCodeT32AluMla.Create);
|
||||
SetT32("111110110001xxxx<<<<xxxx00xxxxxx", InstName.Smla__, InstEmit32.Smla__, OpCodeT32AluMla.Create);
|
||||
SetT32("111110111100xxxxxxxxxxxx0000xxxx", InstName.Smlal, InstEmit32.Smlal, OpCodeT32AluUmull.Create);
|
||||
SetT32("111110111100xxxxxxxxxxxx10xxxxxx", InstName.Smlal__, InstEmit32.Smlal__, OpCodeT32AluUmull.Create);
|
||||
SetT32("111110110011xxxx<<<<xxxx000xxxxx", InstName.Smlaw_, InstEmit32.Smlaw_, OpCodeT32AluMla.Create);
|
||||
SetT32("111110110101xxxx<<<<xxxx000xxxxx", InstName.Smmla, InstEmit32.Smmla, OpCodeT32AluMla.Create);
|
||||
SetT32("111110110110xxxxxxxxxxxx000xxxxx", InstName.Smmls, InstEmit32.Smmls, OpCodeT32AluMla.Create);
|
||||
SetT32("111110110001xxxx1111xxxx00xxxxxx", InstName.Smul__, InstEmit32.Smul__, OpCodeT32AluMla.Create);
|
||||
SetT32("111110111000xxxxxxxxxxxx0000xxxx", InstName.Smull, InstEmit32.Smull, OpCodeT32AluUmull.Create);
|
||||
SetT32("111110110011xxxx1111xxxx000xxxxx", InstName.Smulw_, InstEmit32.Smulw_, OpCodeT32AluMla.Create);
|
||||
SetT32("111010001100xxxxxxxx111110101111", InstName.Stl, InstEmit32.Stl, OpCodeT32MemStEx.Create);
|
||||
SetT32("111010001100xxxxxxxx111110001111", InstName.Stlb, InstEmit32.Stlb, OpCodeT32MemStEx.Create);
|
||||
SetT32("111010001100xxxxxxxx11111110xxxx", InstName.Stlex, InstEmit32.Stlex, OpCodeT32MemStEx.Create);
|
||||
SetT32("111010001100xxxxxxxx11111100xxxx", InstName.Stlexb, InstEmit32.Stlexb, OpCodeT32MemStEx.Create);
|
||||
SetT32("111010001100xxxxxxxxxxxx1111xxxx", InstName.Stlexd, InstEmit32.Stlexd, OpCodeT32MemStEx.Create);
|
||||
SetT32("111010001100xxxxxxxx11111101xxxx", InstName.Stlexh, InstEmit32.Stlexh, OpCodeT32MemStEx.Create);
|
||||
SetT32("111010001100xxxxxxxx111110011111", InstName.Stlh, InstEmit32.Stlh, OpCodeT32MemStEx.Create);
|
||||
SetT32("1110100010x0xxxx0xxxxxxxxxxxxxxx", InstName.Stm, InstEmit32.Stm, OpCodeT32MemMult.Create);
|
||||
SetT32("1110100100x0xxxx0xxxxxxxxxxxxxxx", InstName.Stm, InstEmit32.Stm, OpCodeT32MemMult.Create);
|
||||
SetT32("111110000100xxxxxxxx1<<>xxxxxxxx", InstName.Str, InstEmit32.Str, OpCodeT32MemImm8.Create);
|
||||
@@ -1115,15 +1193,31 @@ namespace ARMeilleure.Decoders
|
||||
SetT32("111110000100<<<<xxxx000000xxxxxx", InstName.Str, InstEmit32.Str, OpCodeT32MemRsImm.Create);
|
||||
SetT32("111110000000xxxxxxxx1<<>xxxxxxxx", InstName.Strb, InstEmit32.Strb, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110001000xxxxxxxxxxxxxxxxxxxx", InstName.Strb, InstEmit32.Strb, OpCodeT32MemImm12.Create);
|
||||
SetT32("1110100>x1>0<<<<xxxxxxxxxxxxxxxx", InstName.Strd, InstEmit32.Strd, OpCodeT32MemImm8D.Create);
|
||||
SetT32("111110000000<<<<xxxx000000xxxxxx", InstName.Strb, InstEmit32.Strb, OpCodeT32MemRsImm.Create);
|
||||
SetT32("11101000x110<<<<xxxxxxxxxxxxxxxx", InstName.Strd, InstEmit32.Strd, OpCodeT32MemImm8D.Create);
|
||||
SetT32("11101001x1x0<<<<xxxxxxxxxxxxxxxx", InstName.Strd, InstEmit32.Strd, OpCodeT32MemImm8D.Create);
|
||||
SetT32("111110000010xxxxxxxx1<<>xxxxxxxx", InstName.Strh, InstEmit32.Strh, OpCodeT32MemImm8.Create);
|
||||
SetT32("111110001010xxxxxxxxxxxxxxxxxxxx", InstName.Strh, InstEmit32.Strh, OpCodeT32MemImm12.Create);
|
||||
SetT32("111110000010<<<<xxxx000000xxxxxx", InstName.Strh, InstEmit32.Strh, OpCodeT32MemRsImm.Create);
|
||||
SetT32("11101011101<xxxx0xxx<<<<xxxxxxxx", InstName.Sub, InstEmit32.Sub, OpCodeT32AluRsImm.Create);
|
||||
SetT32("11110x01101<xxxx0xxx<<<<xxxxxxxx", InstName.Sub, InstEmit32.Sub, OpCodeT32AluImm.Create);
|
||||
SetT32("111110100100xxxx1111xxxx10xxxxxx", InstName.Sxtb, InstEmit32.Sxtb, OpCodeT32AluUx.Create);
|
||||
SetT32("111110100010xxxx1111xxxx10xxxxxx", InstName.Sxtb16, InstEmit32.Sxtb16, OpCodeT32AluUx.Create);
|
||||
SetT32("111110100000xxxx1111xxxx10xxxxxx", InstName.Sxth, InstEmit32.Sxth, OpCodeT32AluUx.Create);
|
||||
SetT32("111010001101xxxx111100000000xxxx", InstName.Tbb, InstEmit32.Tbb, OpCodeT32Tb.Create);
|
||||
SetT32("111010001101xxxx111100000001xxxx", InstName.Tbh, InstEmit32.Tbh, OpCodeT32Tb.Create);
|
||||
SetT32("111010101001xxxx0xxx1111xxxxxxxx", InstName.Teq, InstEmit32.Teq, OpCodeT32AluRsImm.Create);
|
||||
SetT32("11110x001001xxxx0xxx1111xxxxxxxx", InstName.Teq, InstEmit32.Teq, OpCodeT32AluImm.Create);
|
||||
SetT32("111010100001xxxx0xxx1111xxxxxxxx", InstName.Tst, InstEmit32.Tst, OpCodeT32AluRsImm.Create);
|
||||
SetT32("11110x000001xxxx0xxx1111xxxxxxxx", InstName.Tst, InstEmit32.Tst, OpCodeT32AluImm.Create);
|
||||
SetT32("111100111100xxxx0xxxxxxxxx0xxxxx", InstName.Ubfx, InstEmit32.Ubfx, OpCodeT32AluBf.Create);
|
||||
SetT32("111110111011xxxx1111xxxx1111xxxx", InstName.Udiv, InstEmit32.Udiv, OpCodeT32AluMla.Create);
|
||||
SetT32("111110111110xxxxxxxxxxxx0110xxxx", InstName.Umaal, InstEmit32.Umaal, OpCodeT32AluUmull.Create);
|
||||
SetT32("111110111110xxxxxxxxxxxx0000xxxx", InstName.Umlal, InstEmit32.Umlal, OpCodeT32AluUmull.Create);
|
||||
SetT32("111110111010xxxxxxxxxxxx0000xxxx", InstName.Umull, InstEmit32.Umull, OpCodeT32AluUmull.Create);
|
||||
SetT32("111110100101xxxx1111xxxx10xxxxxx", InstName.Uxtb, InstEmit32.Uxtb, OpCodeT32AluUx.Create);
|
||||
SetT32("111110100011xxxx1111xxxx10xxxxxx", InstName.Uxtb16, InstEmit32.Uxtb16, OpCodeT32AluUx.Create);
|
||||
SetT32("111110100001xxxx1111xxxx10xxxxxx", InstName.Uxth, InstEmit32.Uxth, OpCodeT32AluUx.Create);
|
||||
#endregion
|
||||
|
||||
FillFastLookupTable(InstA32FastLookup, AllInstA32, ToFastLookupIndexA);
|
||||
@@ -1180,6 +1274,18 @@ namespace ARMeilleure.Decoders
|
||||
Set(reversedEncoding, AllInstT32, new InstDescriptor(name, emitter), reversedMakeOp);
|
||||
}
|
||||
|
||||
private static void SetVfp(string encoding, InstName name, InstEmitter emitter, MakeOp makeOpA32, MakeOp makeOpT32)
|
||||
{
|
||||
SetA32(encoding, name, emitter, makeOpA32);
|
||||
|
||||
string thumbEncoding = encoding;
|
||||
if (thumbEncoding.StartsWith("<<<<"))
|
||||
{
|
||||
thumbEncoding = "1110" + thumbEncoding.Substring(4);
|
||||
}
|
||||
SetT32(thumbEncoding, name, emitter, makeOpT32);
|
||||
}
|
||||
|
||||
private static void SetA64(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp)
|
||||
{
|
||||
Set(encoding, AllInstA64, new InstDescriptor(name, emitter), makeOp);
|
||||
|
||||
@@ -1,51 +0,0 @@
|
||||
using System.Diagnostics.Tracing;
|
||||
|
||||
namespace ARMeilleure.Diagnostics.EventSources
|
||||
{
|
||||
[EventSource(Name = "ARMeilleure")]
|
||||
class AddressTableEventSource : EventSource
|
||||
{
|
||||
public static readonly AddressTableEventSource Log = new();
|
||||
|
||||
private ulong _size;
|
||||
private ulong _leafSize;
|
||||
private PollingCounter _sizeCounter;
|
||||
private PollingCounter _leafSizeCounter;
|
||||
|
||||
public AddressTableEventSource()
|
||||
{
|
||||
_sizeCounter = new PollingCounter("addr-tab-alloc", this, () => _size / 1024d / 1024d)
|
||||
{
|
||||
DisplayName = "AddressTable Total Bytes Allocated",
|
||||
DisplayUnits = "MB"
|
||||
};
|
||||
|
||||
_leafSizeCounter = new PollingCounter("addr-tab-leaf-alloc", this, () => _leafSize / 1024d / 1024d)
|
||||
{
|
||||
DisplayName = "AddressTable Total Leaf Bytes Allocated",
|
||||
DisplayUnits = "MB"
|
||||
};
|
||||
}
|
||||
|
||||
public void Allocated(int bytes, bool leaf)
|
||||
{
|
||||
_size += (uint)bytes;
|
||||
|
||||
if (leaf)
|
||||
{
|
||||
_leafSize += (uint)bytes;
|
||||
}
|
||||
}
|
||||
|
||||
protected override void Dispose(bool disposing)
|
||||
{
|
||||
_leafSizeCounter.Dispose();
|
||||
_leafSizeCounter = null;
|
||||
|
||||
_sizeCounter.Dispose();
|
||||
_sizeCounter = null;
|
||||
|
||||
base.Dispose(disposing);
|
||||
}
|
||||
}
|
||||
}
|
||||
67
ARMeilleure/Diagnostics/TranslatorEventSource.cs
Normal file
67
ARMeilleure/Diagnostics/TranslatorEventSource.cs
Normal file
@@ -0,0 +1,67 @@
|
||||
using System.Diagnostics.Tracing;
|
||||
using System.Threading;
|
||||
|
||||
namespace ARMeilleure.Diagnostics
|
||||
{
|
||||
[EventSource(Name = "ARMeilleure")]
|
||||
class TranslatorEventSource : EventSource
|
||||
{
|
||||
public static readonly TranslatorEventSource Log = new();
|
||||
|
||||
private int _rejitQueue;
|
||||
private ulong _funcTabSize;
|
||||
private ulong _funcTabLeafSize;
|
||||
private PollingCounter _rejitQueueCounter;
|
||||
private PollingCounter _funcTabSizeCounter;
|
||||
private PollingCounter _funcTabLeafSizeCounter;
|
||||
|
||||
public TranslatorEventSource()
|
||||
{
|
||||
_rejitQueueCounter = new PollingCounter("rejit-queue-length", this, () => _rejitQueue)
|
||||
{
|
||||
DisplayName = "Rejit Queue Length"
|
||||
};
|
||||
|
||||
_funcTabSizeCounter = new PollingCounter("addr-tab-alloc", this, () => _funcTabSize / 1024d / 1024d)
|
||||
{
|
||||
DisplayName = "AddressTable Total Bytes Allocated",
|
||||
DisplayUnits = "MB"
|
||||
};
|
||||
|
||||
_funcTabLeafSizeCounter = new PollingCounter("addr-tab-leaf-alloc", this, () => _funcTabLeafSize / 1024d / 1024d)
|
||||
{
|
||||
DisplayName = "AddressTable Total Leaf Bytes Allocated",
|
||||
DisplayUnits = "MB"
|
||||
};
|
||||
}
|
||||
|
||||
public void RejitQueueAdd(int count)
|
||||
{
|
||||
Interlocked.Add(ref _rejitQueue, count);
|
||||
}
|
||||
|
||||
public void AddressTableAllocated(int bytes, bool leaf)
|
||||
{
|
||||
_funcTabSize += (uint)bytes;
|
||||
|
||||
if (leaf)
|
||||
{
|
||||
_funcTabLeafSize += (uint)bytes;
|
||||
}
|
||||
}
|
||||
|
||||
protected override void Dispose(bool disposing)
|
||||
{
|
||||
_rejitQueueCounter.Dispose();
|
||||
_rejitQueueCounter = null;
|
||||
|
||||
_funcTabLeafSizeCounter.Dispose();
|
||||
_funcTabLeafSizeCounter = null;
|
||||
|
||||
_funcTabSizeCounter.Dispose();
|
||||
_funcTabSizeCounter = null;
|
||||
|
||||
base.Dispose(disposing);
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -74,7 +74,7 @@ namespace ARMeilleure.Instructions
|
||||
|
||||
public static void Bfc(ArmEmitterContext context)
|
||||
{
|
||||
OpCode32AluBf op = (OpCode32AluBf)context.CurrOp;
|
||||
IOpCode32AluBf op = (IOpCode32AluBf)context.CurrOp;
|
||||
|
||||
Operand d = GetIntA32(context, op.Rd);
|
||||
Operand res = context.BitwiseAnd(d, Const(~op.DestMask));
|
||||
@@ -84,7 +84,7 @@ namespace ARMeilleure.Instructions
|
||||
|
||||
public static void Bfi(ArmEmitterContext context)
|
||||
{
|
||||
OpCode32AluBf op = (OpCode32AluBf)context.CurrOp;
|
||||
IOpCode32AluBf op = (IOpCode32AluBf)context.CurrOp;
|
||||
|
||||
Operand n = GetIntA32(context, op.Rn);
|
||||
Operand d = GetIntA32(context, op.Rd);
|
||||
@@ -185,7 +185,7 @@ namespace ARMeilleure.Instructions
|
||||
|
||||
public static void Movt(ArmEmitterContext context)
|
||||
{
|
||||
OpCode32AluImm16 op = (OpCode32AluImm16)context.CurrOp;
|
||||
IOpCode32AluImm16 op = (IOpCode32AluImm16)context.CurrOp;
|
||||
|
||||
Operand d = GetIntA32(context, op.Rd);
|
||||
Operand imm = Const(op.Immediate << 16); // Immeditate value as top halfword.
|
||||
@@ -389,7 +389,7 @@ namespace ARMeilleure.Instructions
|
||||
|
||||
public static void Sbfx(ArmEmitterContext context)
|
||||
{
|
||||
OpCode32AluBf op = (OpCode32AluBf)context.CurrOp;
|
||||
IOpCode32AluBf op = (IOpCode32AluBf)context.CurrOp;
|
||||
|
||||
var msb = op.Lsb + op.Msb; // For this instruction, the msb is actually a width.
|
||||
|
||||
@@ -484,7 +484,7 @@ namespace ARMeilleure.Instructions
|
||||
|
||||
public static void Ubfx(ArmEmitterContext context)
|
||||
{
|
||||
OpCode32AluBf op = (OpCode32AluBf)context.CurrOp;
|
||||
IOpCode32AluBf op = (IOpCode32AluBf)context.CurrOp;
|
||||
|
||||
var msb = op.Lsb + op.Msb; // For this instruction, the msb is actually a width.
|
||||
|
||||
|
||||
@@ -128,7 +128,7 @@ namespace ARMeilleure.Instructions
|
||||
{
|
||||
Debug.Assert(value.Type == OperandType.I32);
|
||||
|
||||
if (((OpCode32)context.CurrOp).IsThumb())
|
||||
if (((OpCode32)context.CurrOp).IsThumb)
|
||||
{
|
||||
bool isReturn = IsA32Return(context);
|
||||
if (!isReturn)
|
||||
@@ -205,7 +205,7 @@ namespace ARMeilleure.Instructions
|
||||
return Const(op.Immediate);
|
||||
}
|
||||
|
||||
case OpCode32AluImm16 op: return Const(op.Immediate);
|
||||
case IOpCode32AluImm16 op: return Const(op.Immediate);
|
||||
|
||||
case IOpCode32AluRsImm op: return GetMShiftedByImmediate(context, op, setCarry);
|
||||
case IOpCode32AluRsReg op: return GetMShiftedByReg(context, op, setCarry);
|
||||
|
||||
@@ -34,7 +34,7 @@ namespace ARMeilleure.Instructions
|
||||
|
||||
uint pc = op.GetPc();
|
||||
|
||||
bool isThumb = ((OpCode32)context.CurrOp).IsThumb();
|
||||
bool isThumb = ((OpCode32)context.CurrOp).IsThumb;
|
||||
|
||||
uint currentPc = isThumb
|
||||
? pc | 1
|
||||
@@ -61,7 +61,7 @@ namespace ARMeilleure.Instructions
|
||||
Operand addr = context.Copy(GetIntA32(context, op.Rm));
|
||||
Operand bitOne = context.BitwiseAnd(addr, Const(1));
|
||||
|
||||
bool isThumb = ((OpCode32)context.CurrOp).IsThumb();
|
||||
bool isThumb = ((OpCode32)context.CurrOp).IsThumb;
|
||||
|
||||
uint currentPc = isThumb
|
||||
? (pc - 2) | 1
|
||||
@@ -107,5 +107,30 @@ namespace ARMeilleure.Instructions
|
||||
|
||||
context.SetIfThenBlockState(op.IfThenBlockConds);
|
||||
}
|
||||
|
||||
public static void Tbb(ArmEmitterContext context) => EmitTb(context, halfword: false);
|
||||
public static void Tbh(ArmEmitterContext context) => EmitTb(context, halfword: true);
|
||||
|
||||
private static void EmitTb(ArmEmitterContext context, bool halfword)
|
||||
{
|
||||
OpCodeT32Tb op = (OpCodeT32Tb)context.CurrOp;
|
||||
|
||||
Operand halfwords;
|
||||
|
||||
if (halfword)
|
||||
{
|
||||
Operand address = context.Add(GetIntA32(context, op.Rn), context.ShiftLeft(GetIntA32(context, op.Rm), Const(1)));
|
||||
halfwords = InstEmitMemoryHelper.EmitReadInt(context, address, 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
Operand address = context.Add(GetIntA32(context, op.Rn), GetIntA32(context, op.Rm));
|
||||
halfwords = InstEmitMemoryHelper.EmitReadIntAligned(context, address, 0);
|
||||
}
|
||||
|
||||
Operand targetAddress = context.Add(Const((int)op.GetPc()), context.ShiftLeft(halfwords, Const(1)));
|
||||
|
||||
EmitVirtualJump(context, targetAddress, isReturn: false);
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -204,15 +204,15 @@ namespace ARMeilleure.Instructions
|
||||
|
||||
context.BranchIfTrue(lblBigEndian, GetFlag(PState.EFlag));
|
||||
|
||||
Load(op.Rt, 0, WordSizeLog2);
|
||||
Load(op.Rt | 1, 4, WordSizeLog2);
|
||||
Load(op.Rt, 0, WordSizeLog2);
|
||||
Load(op.Rt2, 4, WordSizeLog2);
|
||||
|
||||
context.Branch(lblEnd);
|
||||
|
||||
context.MarkLabel(lblBigEndian);
|
||||
|
||||
Load(op.Rt | 1, 0, WordSizeLog2);
|
||||
Load(op.Rt, 4, WordSizeLog2);
|
||||
Load(op.Rt2, 0, WordSizeLog2);
|
||||
Load(op.Rt, 4, WordSizeLog2);
|
||||
|
||||
context.MarkLabel(lblEnd);
|
||||
}
|
||||
@@ -237,15 +237,15 @@ namespace ARMeilleure.Instructions
|
||||
|
||||
context.BranchIfTrue(lblBigEndian, GetFlag(PState.EFlag));
|
||||
|
||||
Store(op.Rt, 0, WordSizeLog2);
|
||||
Store(op.Rt | 1, 4, WordSizeLog2);
|
||||
Store(op.Rt, 0, WordSizeLog2);
|
||||
Store(op.Rt2, 4, WordSizeLog2);
|
||||
|
||||
context.Branch(lblEnd);
|
||||
|
||||
context.MarkLabel(lblBigEndian);
|
||||
|
||||
Store(op.Rt | 1, 0, WordSizeLog2);
|
||||
Store(op.Rt, 4, WordSizeLog2);
|
||||
Store(op.Rt2, 0, WordSizeLog2);
|
||||
Store(op.Rt, 4, WordSizeLog2);
|
||||
|
||||
context.MarkLabel(lblEnd);
|
||||
}
|
||||
|
||||
@@ -172,13 +172,13 @@ namespace ARMeilleure.Instructions
|
||||
context.BranchIfTrue(lblBigEndian, GetFlag(PState.EFlag));
|
||||
|
||||
SetIntA32(context, op.Rt, valueLow);
|
||||
SetIntA32(context, op.Rt | 1, valueHigh);
|
||||
SetIntA32(context, op.Rt2, valueHigh);
|
||||
|
||||
context.Branch(lblEnd);
|
||||
|
||||
context.MarkLabel(lblBigEndian);
|
||||
|
||||
SetIntA32(context, op.Rt | 1, valueLow);
|
||||
SetIntA32(context, op.Rt2, valueLow);
|
||||
SetIntA32(context, op.Rt, valueHigh);
|
||||
|
||||
context.MarkLabel(lblEnd);
|
||||
@@ -195,7 +195,7 @@ namespace ARMeilleure.Instructions
|
||||
// Split the result into 2 words (based on endianness)
|
||||
|
||||
Operand lo = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rt));
|
||||
Operand hi = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rt | 1));
|
||||
Operand hi = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rt2));
|
||||
|
||||
Operand lblBigEndian = Label();
|
||||
Operand lblEnd = Label();
|
||||
|
||||
@@ -123,6 +123,41 @@ namespace ARMeilleure.Instructions
|
||||
context.CurrOp is OpCodeSimdMemSs);
|
||||
}
|
||||
|
||||
public static Operand EmitReadInt(ArmEmitterContext context, Operand address, int size)
|
||||
{
|
||||
Operand temp = context.AllocateLocal(size == 3 ? OperandType.I64 : OperandType.I32);
|
||||
|
||||
Operand lblSlowPath = Label();
|
||||
Operand lblEnd = Label();
|
||||
|
||||
Operand physAddr = EmitPtPointerLoad(context, address, lblSlowPath, write: false, size);
|
||||
|
||||
Operand value = default;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0: value = context.Load8 (physAddr); break;
|
||||
case 1: value = context.Load16(physAddr); break;
|
||||
case 2: value = context.Load (OperandType.I32, physAddr); break;
|
||||
case 3: value = context.Load (OperandType.I64, physAddr); break;
|
||||
}
|
||||
|
||||
context.Copy(temp, value);
|
||||
|
||||
if (!context.Memory.Type.IsHostMapped())
|
||||
{
|
||||
context.Branch(lblEnd);
|
||||
|
||||
context.MarkLabel(lblSlowPath, BasicBlockFrequency.Cold);
|
||||
|
||||
context.Copy(temp, EmitReadIntFallback(context, address, size));
|
||||
|
||||
context.MarkLabel(lblEnd);
|
||||
}
|
||||
|
||||
return temp;
|
||||
}
|
||||
|
||||
private static void EmitReadInt(ArmEmitterContext context, Operand address, int rt, int size)
|
||||
{
|
||||
Operand lblSlowPath = Label();
|
||||
@@ -419,6 +454,11 @@ namespace ARMeilleure.Instructions
|
||||
}
|
||||
|
||||
private static void EmitReadIntFallback(ArmEmitterContext context, Operand address, int rt, int size)
|
||||
{
|
||||
SetInt(context, rt, EmitReadIntFallback(context, address, size));
|
||||
}
|
||||
|
||||
private static Operand EmitReadIntFallback(ArmEmitterContext context, Operand address, int size)
|
||||
{
|
||||
MethodInfo info = null;
|
||||
|
||||
@@ -430,7 +470,7 @@ namespace ARMeilleure.Instructions
|
||||
case 3: info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.ReadUInt64)); break;
|
||||
}
|
||||
|
||||
SetInt(context, rt, context.Call(info, address));
|
||||
return context.Call(info, address);
|
||||
}
|
||||
|
||||
private static void EmitReadVectorFallback(
|
||||
|
||||
@@ -25,7 +25,7 @@ namespace ARMeilleure.Instructions
|
||||
|
||||
public static void Mla(ArmEmitterContext context)
|
||||
{
|
||||
OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
|
||||
IOpCode32AluMla op = (IOpCode32AluMla)context.CurrOp;
|
||||
|
||||
Operand n = GetAluN(context);
|
||||
Operand m = GetAluM(context);
|
||||
@@ -43,7 +43,7 @@ namespace ARMeilleure.Instructions
|
||||
|
||||
public static void Mls(ArmEmitterContext context)
|
||||
{
|
||||
OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
|
||||
IOpCode32AluMla op = (IOpCode32AluMla)context.CurrOp;
|
||||
|
||||
Operand n = GetAluN(context);
|
||||
Operand m = GetAluM(context);
|
||||
@@ -71,7 +71,7 @@ namespace ARMeilleure.Instructions
|
||||
|
||||
private static void EmitSmmul(ArmEmitterContext context, MullFlags flags)
|
||||
{
|
||||
OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
|
||||
IOpCode32AluMla op = (IOpCode32AluMla)context.CurrOp;
|
||||
|
||||
Operand n = context.SignExtend32(OperandType.I64, GetIntA32(context, op.Rn));
|
||||
Operand m = context.SignExtend32(OperandType.I64, GetIntA32(context, op.Rm));
|
||||
@@ -99,7 +99,7 @@ namespace ARMeilleure.Instructions
|
||||
|
||||
public static void Smla__(ArmEmitterContext context)
|
||||
{
|
||||
OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
|
||||
IOpCode32AluMla op = (IOpCode32AluMla)context.CurrOp;
|
||||
|
||||
Operand n = GetIntA32(context, op.Rn);
|
||||
Operand m = GetIntA32(context, op.Rm);
|
||||
@@ -142,7 +142,7 @@ namespace ARMeilleure.Instructions
|
||||
|
||||
public static void Smlal__(ArmEmitterContext context)
|
||||
{
|
||||
OpCode32AluUmull op = (OpCode32AluUmull)context.CurrOp;
|
||||
IOpCode32AluUmull op = (IOpCode32AluUmull)context.CurrOp;
|
||||
|
||||
Operand n = GetIntA32(context, op.Rn);
|
||||
Operand m = GetIntA32(context, op.Rm);
|
||||
@@ -180,7 +180,7 @@ namespace ARMeilleure.Instructions
|
||||
|
||||
public static void Smlaw_(ArmEmitterContext context)
|
||||
{
|
||||
OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
|
||||
IOpCode32AluMla op = (IOpCode32AluMla)context.CurrOp;
|
||||
|
||||
Operand n = GetIntA32(context, op.Rn);
|
||||
Operand m = GetIntA32(context, op.Rm);
|
||||
@@ -210,7 +210,7 @@ namespace ARMeilleure.Instructions
|
||||
|
||||
public static void Smul__(ArmEmitterContext context)
|
||||
{
|
||||
OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
|
||||
IOpCode32AluMla op = (IOpCode32AluMla)context.CurrOp;
|
||||
|
||||
Operand n = GetIntA32(context, op.Rn);
|
||||
Operand m = GetIntA32(context, op.Rm);
|
||||
@@ -240,7 +240,7 @@ namespace ARMeilleure.Instructions
|
||||
|
||||
public static void Smull(ArmEmitterContext context)
|
||||
{
|
||||
OpCode32AluUmull op = (OpCode32AluUmull)context.CurrOp;
|
||||
IOpCode32AluUmull op = (IOpCode32AluUmull)context.CurrOp;
|
||||
|
||||
Operand n = context.SignExtend32(OperandType.I64, GetIntA32(context, op.Rn));
|
||||
Operand m = context.SignExtend32(OperandType.I64, GetIntA32(context, op.Rm));
|
||||
@@ -261,7 +261,7 @@ namespace ARMeilleure.Instructions
|
||||
|
||||
public static void Smulw_(ArmEmitterContext context)
|
||||
{
|
||||
OpCode32AluMla op = (OpCode32AluMla)context.CurrOp;
|
||||
IOpCode32AluMla op = (IOpCode32AluMla)context.CurrOp;
|
||||
|
||||
Operand n = GetIntA32(context, op.Rn);
|
||||
Operand m = GetIntA32(context, op.Rm);
|
||||
@@ -285,7 +285,7 @@ namespace ARMeilleure.Instructions
|
||||
|
||||
public static void Umaal(ArmEmitterContext context)
|
||||
{
|
||||
OpCode32AluUmull op = (OpCode32AluUmull)context.CurrOp;
|
||||
IOpCode32AluUmull op = (IOpCode32AluUmull)context.CurrOp;
|
||||
|
||||
Operand n = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rn));
|
||||
Operand m = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rm));
|
||||
@@ -310,7 +310,7 @@ namespace ARMeilleure.Instructions
|
||||
|
||||
public static void Umull(ArmEmitterContext context)
|
||||
{
|
||||
OpCode32AluUmull op = (OpCode32AluUmull)context.CurrOp;
|
||||
IOpCode32AluUmull op = (IOpCode32AluUmull)context.CurrOp;
|
||||
|
||||
Operand n = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rn));
|
||||
Operand m = context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rm));
|
||||
@@ -331,7 +331,7 @@ namespace ARMeilleure.Instructions
|
||||
|
||||
private static void EmitMlal(ArmEmitterContext context, bool signed)
|
||||
{
|
||||
OpCode32AluUmull op = (OpCode32AluUmull)context.CurrOp;
|
||||
IOpCode32AluUmull op = (IOpCode32AluUmull)context.CurrOp;
|
||||
|
||||
Operand n = GetIntA32(context, op.Rn);
|
||||
Operand m = GetIntA32(context, op.Rm);
|
||||
|
||||
@@ -777,6 +777,13 @@ namespace ARMeilleure.Instructions
|
||||
}
|
||||
}
|
||||
|
||||
public static void Vmlal_I(ArmEmitterContext context)
|
||||
{
|
||||
OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
|
||||
|
||||
EmitVectorTernaryLongOpI32(context, (d, n, m) => context.Add(d, context.Multiply(n, m)), !op.U);
|
||||
}
|
||||
|
||||
public static void Vmls_S(ArmEmitterContext context)
|
||||
{
|
||||
if (Optimizations.FastFP && Optimizations.UseSse2)
|
||||
@@ -992,6 +999,13 @@ namespace ARMeilleure.Instructions
|
||||
}
|
||||
}
|
||||
|
||||
public static void Vpaddl(ArmEmitterContext context)
|
||||
{
|
||||
OpCode32Simd op = (OpCode32Simd)context.CurrOp;
|
||||
|
||||
EmitVectorPairwiseLongOpI32(context, (op1, op2) => context.Add(op1, op2), (op.Opc & 1) == 0);
|
||||
}
|
||||
|
||||
public static void Vpmax_V(ArmEmitterContext context)
|
||||
{
|
||||
if (Optimizations.FastFP && Optimizations.UseSse2)
|
||||
@@ -1014,7 +1028,7 @@ namespace ARMeilleure.Instructions
|
||||
}
|
||||
else
|
||||
{
|
||||
EmitVectorPairwiseOpI32(context, (op1, op2) =>
|
||||
EmitVectorPairwiseOpI32(context, (op1, op2) =>
|
||||
{
|
||||
Operand greater = op.U ? context.ICompareGreaterUI(op1, op2) : context.ICompareGreater(op1, op2);
|
||||
return context.ConditionalSelect(greater, op1, op2);
|
||||
@@ -1052,6 +1066,62 @@ namespace ARMeilleure.Instructions
|
||||
}
|
||||
}
|
||||
|
||||
public static void Vqadd(ArmEmitterContext context)
|
||||
{
|
||||
OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
|
||||
|
||||
EmitSaturatingAddSubBinaryOp(context, add: true, !op.U);
|
||||
}
|
||||
|
||||
public static void Vqdmulh(ArmEmitterContext context)
|
||||
{
|
||||
OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
|
||||
int eSize = 8 << op.Size;
|
||||
|
||||
EmitVectorBinaryOpI32(context, (op1, op2) =>
|
||||
{
|
||||
if (op.Size == 2)
|
||||
{
|
||||
op1 = context.SignExtend32(OperandType.I64, op1);
|
||||
op2 = context.SignExtend32(OperandType.I64, op2);
|
||||
}
|
||||
|
||||
Operand res = context.Multiply(op1, op2);
|
||||
res = context.ShiftRightSI(res, Const(eSize - 1));
|
||||
res = EmitSatQ(context, res, eSize, signedSrc: true, signedDst: true);
|
||||
|
||||
if (op.Size == 2)
|
||||
{
|
||||
res = context.ConvertI64ToI32(res);
|
||||
}
|
||||
|
||||
return res;
|
||||
}, signed: true);
|
||||
}
|
||||
|
||||
public static void Vqmovn(ArmEmitterContext context)
|
||||
{
|
||||
OpCode32SimdMovn op = (OpCode32SimdMovn)context.CurrOp;
|
||||
|
||||
bool signed = !op.Q;
|
||||
|
||||
EmitVectorUnaryNarrowOp32(context, (op1) => EmitSatQ(context, op1, 8 << op.Size, signed, signed), signed);
|
||||
}
|
||||
|
||||
public static void Vqmovun(ArmEmitterContext context)
|
||||
{
|
||||
OpCode32SimdMovn op = (OpCode32SimdMovn)context.CurrOp;
|
||||
|
||||
EmitVectorUnaryNarrowOp32(context, (op1) => EmitSatQ(context, op1, 8 << op.Size, signedSrc: true, signedDst: false), signed: true);
|
||||
}
|
||||
|
||||
public static void Vqsub(ArmEmitterContext context)
|
||||
{
|
||||
OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
|
||||
|
||||
EmitSaturatingAddSubBinaryOp(context, add: false, !op.U);
|
||||
}
|
||||
|
||||
public static void Vrev(ArmEmitterContext context)
|
||||
{
|
||||
OpCode32SimdRev op = (OpCode32SimdRev)context.CurrOp;
|
||||
@@ -1202,6 +1272,30 @@ namespace ARMeilleure.Instructions
|
||||
}
|
||||
}
|
||||
|
||||
public static void Vrhadd(ArmEmitterContext context)
|
||||
{
|
||||
OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
|
||||
|
||||
EmitVectorBinaryOpI32(context, (op1, op2) =>
|
||||
{
|
||||
if (op.Size == 2)
|
||||
{
|
||||
op1 = context.ZeroExtend32(OperandType.I64, op1);
|
||||
op2 = context.ZeroExtend32(OperandType.I64, op2);
|
||||
}
|
||||
|
||||
Operand res = context.Add(context.Add(op1, op2), Const(op1.Type, 1L));
|
||||
res = context.ShiftRightUI(res, Const(1));
|
||||
|
||||
if (op.Size == 2)
|
||||
{
|
||||
res = context.ConvertI64ToI32(res);
|
||||
}
|
||||
|
||||
return res;
|
||||
}, !op.U);
|
||||
}
|
||||
|
||||
public static void Vrsqrte(ArmEmitterContext context)
|
||||
{
|
||||
OpCode32SimdSqrte op = (OpCode32SimdSqrte)context.CurrOp;
|
||||
@@ -1349,6 +1443,13 @@ namespace ARMeilleure.Instructions
|
||||
}
|
||||
}
|
||||
|
||||
public static void Vsubl_I(ArmEmitterContext context)
|
||||
{
|
||||
OpCode32SimdRegLong op = (OpCode32SimdRegLong)context.CurrOp;
|
||||
|
||||
EmitVectorBinaryLongOpI32(context, (op1, op2) => context.Subtract(op1, op2), !op.U);
|
||||
}
|
||||
|
||||
public static void Vsubw_I(ArmEmitterContext context)
|
||||
{
|
||||
OpCode32SimdRegWide op = (OpCode32SimdRegWide)context.CurrOp;
|
||||
@@ -1356,6 +1457,46 @@ namespace ARMeilleure.Instructions
|
||||
EmitVectorBinaryWideOpI32(context, (op1, op2) => context.Subtract(op1, op2), !op.U);
|
||||
}
|
||||
|
||||
private static void EmitSaturatingAddSubBinaryOp(ArmEmitterContext context, bool add, bool signed)
|
||||
{
|
||||
OpCode32Simd op = (OpCode32Simd)context.CurrOp;
|
||||
|
||||
EmitVectorBinaryOpI32(context, (ne, me) =>
|
||||
{
|
||||
if (op.Size <= 2)
|
||||
{
|
||||
if (op.Size == 2)
|
||||
{
|
||||
ne = signed ? context.SignExtend32(OperandType.I64, ne) : context.ZeroExtend32(OperandType.I64, ne);
|
||||
me = signed ? context.SignExtend32(OperandType.I64, me) : context.ZeroExtend32(OperandType.I64, me);
|
||||
}
|
||||
|
||||
Operand res = add ? context.Add(ne, me) : context.Subtract(ne, me);
|
||||
|
||||
res = EmitSatQ(context, res, 8 << op.Size, signedSrc: true, signed);
|
||||
|
||||
if (op.Size == 2)
|
||||
{
|
||||
res = context.ConvertI64ToI32(res);
|
||||
}
|
||||
|
||||
return res;
|
||||
}
|
||||
else if (add) /* if (op.Size == 3) */
|
||||
{
|
||||
return signed
|
||||
? EmitBinarySignedSatQAdd(context, ne, me)
|
||||
: EmitBinaryUnsignedSatQAdd(context, ne, me);
|
||||
}
|
||||
else /* if (sub) */
|
||||
{
|
||||
return signed
|
||||
? EmitBinarySignedSatQSub(context, ne, me)
|
||||
: EmitBinaryUnsignedSatQSub(context, ne, me);
|
||||
}
|
||||
}, signed);
|
||||
}
|
||||
|
||||
private static void EmitSse41MaxMinNumOpF32(ArmEmitterContext context, bool isMaxNum, bool scalar)
|
||||
{
|
||||
IOpCode32Simd op = (IOpCode32Simd)context.CurrOp;
|
||||
|
||||
@@ -323,6 +323,60 @@ namespace ARMeilleure.Instructions
|
||||
}
|
||||
}
|
||||
|
||||
// VRINTA (vector).
|
||||
public static void Vrinta_V(ArmEmitterContext context)
|
||||
{
|
||||
EmitVectorUnaryOpF32(context, (m) => EmitRoundMathCall(context, MidpointRounding.AwayFromZero, m));
|
||||
}
|
||||
|
||||
// VRINTM (vector).
|
||||
public static void Vrintm_V(ArmEmitterContext context)
|
||||
{
|
||||
if (Optimizations.UseSse2)
|
||||
{
|
||||
EmitVectorUnaryOpSimd32(context, (m) =>
|
||||
{
|
||||
return context.AddIntrinsic(Intrinsic.X86Roundps, m, Const(X86GetRoundControl(FPRoundingMode.TowardsMinusInfinity)));
|
||||
});
|
||||
}
|
||||
else
|
||||
{
|
||||
EmitVectorUnaryOpF32(context, (m) => EmitUnaryMathCall(context, nameof(Math.Floor), m));
|
||||
}
|
||||
}
|
||||
|
||||
// VRINTN (vector).
|
||||
public static void Vrintn_V(ArmEmitterContext context)
|
||||
{
|
||||
if (Optimizations.UseSse2)
|
||||
{
|
||||
EmitVectorUnaryOpSimd32(context, (m) =>
|
||||
{
|
||||
return context.AddIntrinsic(Intrinsic.X86Roundps, m, Const(X86GetRoundControl(FPRoundingMode.ToNearest)));
|
||||
});
|
||||
}
|
||||
else
|
||||
{
|
||||
EmitVectorUnaryOpF32(context, (m) => EmitRoundMathCall(context, MidpointRounding.ToEven, m));
|
||||
}
|
||||
}
|
||||
|
||||
// VRINTP (vector).
|
||||
public static void Vrintp_V(ArmEmitterContext context)
|
||||
{
|
||||
if (Optimizations.UseSse2)
|
||||
{
|
||||
EmitVectorUnaryOpSimd32(context, (m) =>
|
||||
{
|
||||
return context.AddIntrinsic(Intrinsic.X86Roundps, m, Const(X86GetRoundControl(FPRoundingMode.TowardsPlusInfinity)));
|
||||
});
|
||||
}
|
||||
else
|
||||
{
|
||||
EmitVectorUnaryOpF32(context, (m) => EmitUnaryMathCall(context, nameof(Math.Ceiling), m));
|
||||
}
|
||||
}
|
||||
|
||||
// VRINTZ (floating-point).
|
||||
public static void Vrint_Z(ArmEmitterContext context)
|
||||
{
|
||||
|
||||
@@ -1281,7 +1281,7 @@ namespace ARMeilleure.Instructions
|
||||
|
||||
public static void EmitSseOrAvxExitFtzAndDazModesOpF(ArmEmitterContext context, Operand isTrue = default)
|
||||
{
|
||||
isTrue = isTrue == default
|
||||
isTrue = isTrue == default
|
||||
? context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetFpcrFz)))
|
||||
: isTrue;
|
||||
|
||||
@@ -1352,7 +1352,7 @@ namespace ARMeilleure.Instructions
|
||||
|
||||
if (op.Size <= 2)
|
||||
{
|
||||
de = EmitSatQ(context, emit(ne), op.Size, signedSrc: true, signedDst: true);
|
||||
de = EmitSignedSrcSatQ(context, emit(ne), op.Size, signedDst: true);
|
||||
}
|
||||
else /* if (op.Size == 3) */
|
||||
{
|
||||
@@ -1419,15 +1419,18 @@ namespace ARMeilleure.Instructions
|
||||
{
|
||||
Operand temp = add ? context.Add(ne, me) : context.Subtract(ne, me);
|
||||
|
||||
de = EmitSatQ(context, temp, op.Size, signedSrc: true, signedDst: signed);
|
||||
de = EmitSignedSrcSatQ(context, temp, op.Size, signedDst: signed);
|
||||
}
|
||||
else if (add) /* if (op.Size == 3) */
|
||||
else /* if (op.Size == 3) */
|
||||
{
|
||||
de = EmitBinarySatQAdd(context, ne, me, signed);
|
||||
}
|
||||
else /* if (sub) */
|
||||
{
|
||||
de = EmitBinarySatQSub(context, ne, me, signed);
|
||||
if (add)
|
||||
{
|
||||
de = signed ? EmitBinarySignedSatQAdd(context, ne, me) : EmitBinaryUnsignedSatQAdd(context, ne, me);
|
||||
}
|
||||
else /* if (sub) */
|
||||
{
|
||||
de = signed ? EmitBinarySignedSatQSub(context, ne, me) : EmitBinaryUnsignedSatQSub(context, ne, me);
|
||||
}
|
||||
}
|
||||
|
||||
res = EmitVectorInsert(context, res, de, index, op.Size);
|
||||
@@ -1445,11 +1448,11 @@ namespace ARMeilleure.Instructions
|
||||
{
|
||||
Operand temp = context.Add(ne, me);
|
||||
|
||||
de = EmitSatQ(context, temp, op.Size, signedSrc: true, signedDst: signed);
|
||||
de = EmitSignedSrcSatQ(context, temp, op.Size, signedDst: signed);
|
||||
}
|
||||
else /* if (op.Size == 3) */
|
||||
{
|
||||
de = EmitBinarySatQAccumulate(context, ne, me, signed);
|
||||
de = signed ? EmitBinarySignedSatQAcc(context, ne, me) : EmitBinaryUnsignedSatQAcc(context, ne, me);
|
||||
}
|
||||
|
||||
res = EmitVectorInsert(context, res, de, index, op.Size);
|
||||
@@ -1475,7 +1478,7 @@ namespace ARMeilleure.Instructions
|
||||
me = EmitVectorExtract(context, ((OpCodeSimdReg)op).Rm, index, op.Size, signed);
|
||||
}
|
||||
|
||||
Operand de = EmitSatQ(context, emit(ne, me), op.Size, true, signed);
|
||||
Operand de = EmitSignedSrcSatQ(context, emit(ne, me), op.Size, signedDst: signed);
|
||||
|
||||
res = EmitVectorInsert(context, res, de, index, op.Size);
|
||||
}
|
||||
@@ -1520,7 +1523,9 @@ namespace ARMeilleure.Instructions
|
||||
{
|
||||
Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size + 1, signedSrc);
|
||||
|
||||
Operand temp = EmitSatQ(context, ne, op.Size, signedSrc, signedDst);
|
||||
Operand temp = signedSrc
|
||||
? EmitSignedSrcSatQ(context, ne, op.Size, signedDst)
|
||||
: EmitUnsignedSrcSatQ(context, ne, op.Size, signedDst);
|
||||
|
||||
res = EmitVectorInsert(context, res, temp, part + index, op.Size);
|
||||
}
|
||||
@@ -1528,74 +1533,248 @@ namespace ARMeilleure.Instructions
|
||||
context.Copy(d, res);
|
||||
}
|
||||
|
||||
// TSrc (16bit, 32bit, 64bit; signed, unsigned) > TDst (8bit, 16bit, 32bit; signed, unsigned).
|
||||
public static Operand EmitSatQ(ArmEmitterContext context, Operand op, int sizeDst, bool signedSrc, bool signedDst)
|
||||
// TSrc (16bit, 32bit, 64bit; signed) > TDst (8bit, 16bit, 32bit; signed, unsigned).
|
||||
// long SignedSrcSignedDstSatQ(long op, int size); ulong SignedSrcUnsignedDstSatQ(long op, int size);
|
||||
public static Operand EmitSignedSrcSatQ(ArmEmitterContext context, Operand op, int sizeDst, bool signedDst)
|
||||
{
|
||||
if ((uint)sizeDst > 2u)
|
||||
{
|
||||
throw new ArgumentOutOfRangeException(nameof(sizeDst));
|
||||
}
|
||||
Debug.Assert(op.Type == OperandType.I64 && (uint)sizeDst <= 2u);
|
||||
|
||||
MethodInfo info;
|
||||
Operand lbl1 = Label();
|
||||
Operand lblEnd = Label();
|
||||
|
||||
if (signedSrc)
|
||||
{
|
||||
info = signedDst
|
||||
? typeof(SoftFallback).GetMethod(nameof(SoftFallback.SignedSrcSignedDstSatQ))
|
||||
: typeof(SoftFallback).GetMethod(nameof(SoftFallback.SignedSrcUnsignedDstSatQ));
|
||||
}
|
||||
else
|
||||
{
|
||||
info = signedDst
|
||||
? typeof(SoftFallback).GetMethod(nameof(SoftFallback.UnsignedSrcSignedDstSatQ))
|
||||
: typeof(SoftFallback).GetMethod(nameof(SoftFallback.UnsignedSrcUnsignedDstSatQ));
|
||||
}
|
||||
int eSize = 8 << sizeDst;
|
||||
|
||||
return context.Call(info, op, Const(sizeDst));
|
||||
Operand maxT = signedDst ? Const((1L << (eSize - 1)) - 1L) : Const((1UL << eSize) - 1UL);
|
||||
Operand minT = signedDst ? Const(-(1L << (eSize - 1))) : Const(0UL);
|
||||
|
||||
Operand res = context.Copy(context.AllocateLocal(OperandType.I64), op);
|
||||
|
||||
context.BranchIf(lbl1, res, maxT, Comparison.LessOrEqual);
|
||||
context.Copy(res, maxT);
|
||||
context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
|
||||
context.Branch(lblEnd);
|
||||
|
||||
context.MarkLabel(lbl1);
|
||||
context.BranchIf(lblEnd, res, minT, Comparison.GreaterOrEqual);
|
||||
context.Copy(res, minT);
|
||||
context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
|
||||
context.Branch(lblEnd);
|
||||
|
||||
context.MarkLabel(lblEnd);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
// TSrc (64bit) == TDst (64bit); signed.
|
||||
public static Operand EmitUnarySignedSatQAbsOrNeg(ArmEmitterContext context, Operand op)
|
||||
// TSrc (16bit, 32bit, 64bit; unsigned) > TDst (8bit, 16bit, 32bit; signed, unsigned).
|
||||
// long UnsignedSrcSignedDstSatQ(ulong op, int size); ulong UnsignedSrcUnsignedDstSatQ(ulong op, int size);
|
||||
public static Operand EmitUnsignedSrcSatQ(ArmEmitterContext context, Operand op, int sizeDst, bool signedDst)
|
||||
{
|
||||
Debug.Assert(((OpCodeSimd)context.CurrOp).Size == 3, "Invalid element size.");
|
||||
Debug.Assert(op.Type == OperandType.I64 && (uint)sizeDst <= 2u);
|
||||
|
||||
return context.Call(typeof(SoftFallback).GetMethod(nameof(SoftFallback.UnarySignedSatQAbsOrNeg)), op);
|
||||
Operand lblEnd = Label();
|
||||
|
||||
int eSize = 8 << sizeDst;
|
||||
|
||||
Operand maxL = signedDst ? Const((1L << (eSize - 1)) - 1L) : Const((1UL << eSize) - 1UL);
|
||||
|
||||
Operand res = context.Copy(context.AllocateLocal(OperandType.I64), op);
|
||||
|
||||
context.BranchIf(lblEnd, res, maxL, Comparison.LessOrEqualUI);
|
||||
context.Copy(res, maxL);
|
||||
context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
|
||||
context.Branch(lblEnd);
|
||||
|
||||
context.MarkLabel(lblEnd);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
// TSrcs (64bit) == TDst (64bit); signed, unsigned.
|
||||
public static Operand EmitBinarySatQAdd(ArmEmitterContext context, Operand op1, Operand op2, bool signed)
|
||||
// long UnarySignedSatQAbsOrNeg(long op);
|
||||
private static Operand EmitUnarySignedSatQAbsOrNeg(ArmEmitterContext context, Operand op)
|
||||
{
|
||||
Debug.Assert(((OpCodeSimd)context.CurrOp).Size == 3, "Invalid element size.");
|
||||
Debug.Assert(op.Type == OperandType.I64);
|
||||
|
||||
MethodInfo info = signed
|
||||
? typeof(SoftFallback).GetMethod(nameof(SoftFallback.BinarySignedSatQAdd))
|
||||
: typeof(SoftFallback).GetMethod(nameof(SoftFallback.BinaryUnsignedSatQAdd));
|
||||
Operand lblEnd = Label();
|
||||
|
||||
return context.Call(info, op1, op2);
|
||||
Operand minL = Const(long.MinValue);
|
||||
Operand maxL = Const(long.MaxValue);
|
||||
|
||||
Operand res = context.Copy(context.AllocateLocal(OperandType.I64), op);
|
||||
|
||||
context.BranchIf(lblEnd, res, minL, Comparison.NotEqual);
|
||||
context.Copy(res, maxL);
|
||||
context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
|
||||
context.Branch(lblEnd);
|
||||
|
||||
context.MarkLabel(lblEnd);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
// TSrcs (64bit) == TDst (64bit); signed, unsigned.
|
||||
public static Operand EmitBinarySatQSub(ArmEmitterContext context, Operand op1, Operand op2, bool signed)
|
||||
// long BinarySignedSatQAdd(long op1, long op2);
|
||||
public static Operand EmitBinarySignedSatQAdd(ArmEmitterContext context, Operand op1, Operand op2)
|
||||
{
|
||||
Debug.Assert(((OpCodeSimd)context.CurrOp).Size == 3, "Invalid element size.");
|
||||
Debug.Assert(op1.Type == OperandType.I64 && op2.Type == OperandType.I64);
|
||||
|
||||
MethodInfo info = signed
|
||||
? typeof(SoftFallback).GetMethod(nameof(SoftFallback.BinarySignedSatQSub))
|
||||
: typeof(SoftFallback).GetMethod(nameof(SoftFallback.BinaryUnsignedSatQSub));
|
||||
Operand lblEnd = Label();
|
||||
|
||||
return context.Call(info, op1, op2);
|
||||
Operand minL = Const(long.MinValue);
|
||||
Operand maxL = Const(long.MaxValue);
|
||||
Operand zero = Const(0L);
|
||||
|
||||
Operand res = context.Copy(context.AllocateLocal(OperandType.I64), context.Add(op1, op2));
|
||||
|
||||
Operand left = context.BitwiseNot(context.BitwiseExclusiveOr(op1, op2));
|
||||
Operand right = context.BitwiseExclusiveOr(op1, res);
|
||||
context.BranchIf(lblEnd, context.BitwiseAnd(left, right), zero, Comparison.GreaterOrEqual);
|
||||
|
||||
Operand isPositive = context.ICompareGreaterOrEqual(op1, zero);
|
||||
context.Copy(res, context.ConditionalSelect(isPositive, maxL, minL));
|
||||
context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
|
||||
context.Branch(lblEnd);
|
||||
|
||||
context.MarkLabel(lblEnd);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
// TSrcs (64bit) == TDst (64bit); signed, unsigned.
|
||||
public static Operand EmitBinarySatQAccumulate(ArmEmitterContext context, Operand op1, Operand op2, bool signed)
|
||||
// ulong BinaryUnsignedSatQAdd(ulong op1, ulong op2);
|
||||
public static Operand EmitBinaryUnsignedSatQAdd(ArmEmitterContext context, Operand op1, Operand op2)
|
||||
{
|
||||
Debug.Assert(((OpCodeSimd)context.CurrOp).Size == 3, "Invalid element size.");
|
||||
Debug.Assert(op1.Type == OperandType.I64 && op2.Type == OperandType.I64);
|
||||
|
||||
MethodInfo info = signed
|
||||
? typeof(SoftFallback).GetMethod(nameof(SoftFallback.BinarySignedSatQAcc))
|
||||
: typeof(SoftFallback).GetMethod(nameof(SoftFallback.BinaryUnsignedSatQAcc));
|
||||
Operand lblEnd = Label();
|
||||
|
||||
return context.Call(info, op1, op2);
|
||||
Operand maxUL = Const(ulong.MaxValue);
|
||||
|
||||
Operand res = context.Copy(context.AllocateLocal(OperandType.I64), context.Add(op1, op2));
|
||||
|
||||
context.BranchIf(lblEnd, res, op1, Comparison.GreaterOrEqualUI);
|
||||
context.Copy(res, maxUL);
|
||||
context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
|
||||
context.Branch(lblEnd);
|
||||
|
||||
context.MarkLabel(lblEnd);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
// long BinarySignedSatQSub(long op1, long op2);
|
||||
public static Operand EmitBinarySignedSatQSub(ArmEmitterContext context, Operand op1, Operand op2)
|
||||
{
|
||||
Debug.Assert(op1.Type == OperandType.I64 && op2.Type == OperandType.I64);
|
||||
|
||||
Operand lblEnd = Label();
|
||||
|
||||
Operand minL = Const(long.MinValue);
|
||||
Operand maxL = Const(long.MaxValue);
|
||||
Operand zero = Const(0L);
|
||||
|
||||
Operand res = context.Copy(context.AllocateLocal(OperandType.I64), context.Subtract(op1, op2));
|
||||
|
||||
Operand left = context.BitwiseExclusiveOr(op1, op2);
|
||||
Operand right = context.BitwiseExclusiveOr(op1, res);
|
||||
context.BranchIf(lblEnd, context.BitwiseAnd(left, right), zero, Comparison.GreaterOrEqual);
|
||||
|
||||
Operand isPositive = context.ICompareGreaterOrEqual(op1, zero);
|
||||
context.Copy(res, context.ConditionalSelect(isPositive, maxL, minL));
|
||||
context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
|
||||
context.Branch(lblEnd);
|
||||
|
||||
context.MarkLabel(lblEnd);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
// ulong BinaryUnsignedSatQSub(ulong op1, ulong op2);
|
||||
public static Operand EmitBinaryUnsignedSatQSub(ArmEmitterContext context, Operand op1, Operand op2)
|
||||
{
|
||||
Debug.Assert(op1.Type == OperandType.I64 && op2.Type == OperandType.I64);
|
||||
|
||||
Operand lblEnd = Label();
|
||||
|
||||
Operand zero = Const(0L);
|
||||
|
||||
Operand res = context.Copy(context.AllocateLocal(OperandType.I64), context.Subtract(op1, op2));
|
||||
|
||||
context.BranchIf(lblEnd, op1, op2, Comparison.GreaterOrEqualUI);
|
||||
context.Copy(res, zero);
|
||||
context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
|
||||
context.Branch(lblEnd);
|
||||
|
||||
context.MarkLabel(lblEnd);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
// long BinarySignedSatQAcc(ulong op1, long op2);
|
||||
private static Operand EmitBinarySignedSatQAcc(ArmEmitterContext context, Operand op1, Operand op2)
|
||||
{
|
||||
Debug.Assert(op1.Type == OperandType.I64 && op2.Type == OperandType.I64);
|
||||
|
||||
Operand lbl1 = Label();
|
||||
Operand lbl2 = Label();
|
||||
Operand lblEnd = Label();
|
||||
|
||||
Operand maxL = Const(long.MaxValue);
|
||||
Operand zero = Const(0L);
|
||||
|
||||
Operand res = context.Copy(context.AllocateLocal(OperandType.I64), context.Add(op1, op2));
|
||||
|
||||
context.BranchIf(lbl1, op1, maxL, Comparison.GreaterUI);
|
||||
Operand notOp2AndRes = context.BitwiseAnd(context.BitwiseNot(op2), res);
|
||||
context.BranchIf(lblEnd, notOp2AndRes, zero, Comparison.GreaterOrEqual);
|
||||
context.Copy(res, maxL);
|
||||
context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
|
||||
context.Branch(lblEnd);
|
||||
|
||||
context.MarkLabel(lbl1);
|
||||
context.BranchIf(lbl2, op2, zero, Comparison.Less);
|
||||
context.Copy(res, maxL);
|
||||
context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
|
||||
context.Branch(lblEnd);
|
||||
|
||||
context.MarkLabel(lbl2);
|
||||
context.BranchIf(lblEnd, res, maxL, Comparison.LessOrEqualUI);
|
||||
context.Copy(res, maxL);
|
||||
context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
|
||||
context.Branch(lblEnd);
|
||||
|
||||
context.MarkLabel(lblEnd);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
// ulong BinaryUnsignedSatQAcc(long op1, ulong op2);
|
||||
private static Operand EmitBinaryUnsignedSatQAcc(ArmEmitterContext context, Operand op1, Operand op2)
|
||||
{
|
||||
Debug.Assert(op1.Type == OperandType.I64 && op2.Type == OperandType.I64);
|
||||
|
||||
Operand lbl1 = Label();
|
||||
Operand lblEnd = Label();
|
||||
|
||||
Operand maxUL = Const(ulong.MaxValue);
|
||||
Operand maxL = Const(long.MaxValue);
|
||||
Operand zero = Const(0L);
|
||||
|
||||
Operand res = context.Copy(context.AllocateLocal(OperandType.I64), context.Add(op1, op2));
|
||||
|
||||
context.BranchIf(lbl1, op1, zero, Comparison.Less);
|
||||
context.BranchIf(lblEnd, res, op1, Comparison.GreaterOrEqualUI);
|
||||
context.Copy(res, maxUL);
|
||||
context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
|
||||
context.Branch(lblEnd);
|
||||
|
||||
context.MarkLabel(lbl1);
|
||||
context.BranchIf(lblEnd, op2, maxL, Comparison.GreaterUI);
|
||||
context.BranchIf(lblEnd, res, zero, Comparison.GreaterOrEqual);
|
||||
context.Copy(res, zero);
|
||||
context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
|
||||
context.Branch(lblEnd);
|
||||
|
||||
context.MarkLabel(lblEnd);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
public static Operand EmitFloatAbs(ArmEmitterContext context, Operand value, bool single, bool vector)
|
||||
|
||||
@@ -219,6 +219,25 @@ namespace ARMeilleure.Instructions
|
||||
|
||||
// Integer
|
||||
|
||||
public static void EmitVectorUnaryAccumulateOpI32(ArmEmitterContext context, Func1I emit, bool signed)
|
||||
{
|
||||
OpCode32Simd op = (OpCode32Simd)context.CurrOp;
|
||||
|
||||
Operand res = GetVecA32(op.Qd);
|
||||
|
||||
int elems = op.GetBytesCount() >> op.Size;
|
||||
|
||||
for (int index = 0; index < elems; index++)
|
||||
{
|
||||
Operand de = EmitVectorExtract32(context, op.Qd, op.Id + index, op.Size, signed);
|
||||
Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, signed);
|
||||
|
||||
res = EmitVectorInsert(context, res, context.Add(de, emit(me)), op.Id + index, op.Size);
|
||||
}
|
||||
|
||||
context.Copy(GetVecA32(op.Qd), res);
|
||||
}
|
||||
|
||||
public static void EmitVectorUnaryOpI32(ArmEmitterContext context, Func1I emit, bool signed)
|
||||
{
|
||||
OpCode32Simd op = (OpCode32Simd)context.CurrOp;
|
||||
@@ -385,6 +404,18 @@ namespace ARMeilleure.Instructions
|
||||
EmitVectorUnaryOpI32(context, emit, true);
|
||||
}
|
||||
|
||||
public static void EmitVectorUnaryOpSx32(ArmEmitterContext context, Func1I emit, bool accumulate)
|
||||
{
|
||||
if (accumulate)
|
||||
{
|
||||
EmitVectorUnaryAccumulateOpI32(context, emit, true);
|
||||
}
|
||||
else
|
||||
{
|
||||
EmitVectorUnaryOpI32(context, emit, true);
|
||||
}
|
||||
}
|
||||
|
||||
public static void EmitVectorBinaryOpSx32(ArmEmitterContext context, Func2I emit)
|
||||
{
|
||||
EmitVectorBinaryOpI32(context, emit, true);
|
||||
@@ -400,6 +431,18 @@ namespace ARMeilleure.Instructions
|
||||
EmitVectorUnaryOpI32(context, emit, false);
|
||||
}
|
||||
|
||||
public static void EmitVectorUnaryOpZx32(ArmEmitterContext context, Func1I emit, bool accumulate)
|
||||
{
|
||||
if (accumulate)
|
||||
{
|
||||
EmitVectorUnaryAccumulateOpI32(context, emit, false);
|
||||
}
|
||||
else
|
||||
{
|
||||
EmitVectorUnaryOpI32(context, emit, false);
|
||||
}
|
||||
}
|
||||
|
||||
public static void EmitVectorBinaryOpZx32(ArmEmitterContext context, Func2I emit)
|
||||
{
|
||||
EmitVectorBinaryOpI32(context, emit, false);
|
||||
@@ -592,6 +635,34 @@ namespace ARMeilleure.Instructions
|
||||
context.Copy(GetVecA32(op.Qd), res);
|
||||
}
|
||||
|
||||
public static void EmitVectorPairwiseLongOpI32(ArmEmitterContext context, Func2I emit, bool signed)
|
||||
{
|
||||
OpCode32Simd op = (OpCode32Simd)context.CurrOp;
|
||||
|
||||
int elems = (op.Q ? 16 : 8) >> op.Size;
|
||||
int pairs = elems >> 1;
|
||||
int id = (op.Vd & 1) * pairs;
|
||||
|
||||
Operand res = GetVecA32(op.Qd);
|
||||
|
||||
for (int index = 0; index < pairs; index++)
|
||||
{
|
||||
int pairIndex = index << 1;
|
||||
Operand m1 = EmitVectorExtract32(context, op.Qm, op.Im + pairIndex, op.Size, signed);
|
||||
Operand m2 = EmitVectorExtract32(context, op.Qm, op.Im + pairIndex + 1, op.Size, signed);
|
||||
|
||||
if (op.Size == 2)
|
||||
{
|
||||
m1 = signed ? context.SignExtend32(OperandType.I64, m1) : context.ZeroExtend32(OperandType.I64, m1);
|
||||
m2 = signed ? context.SignExtend32(OperandType.I64, m2) : context.ZeroExtend32(OperandType.I64, m2);
|
||||
}
|
||||
|
||||
res = EmitVectorInsert(context, res, emit(m1, m2), id + index, op.Size + 1);
|
||||
}
|
||||
|
||||
context.Copy(GetVecA32(op.Qd), res);
|
||||
}
|
||||
|
||||
// Narrow
|
||||
|
||||
public static void EmitVectorUnaryNarrowOp32(ArmEmitterContext context, Func1I emit, bool signed = false)
|
||||
|
||||
@@ -67,7 +67,7 @@ namespace ARMeilleure.Instructions
|
||||
|
||||
for (int i = 0; i < count; i++)
|
||||
{
|
||||
// Write an element from a double simd register.
|
||||
// Accesses an element from a double simd register.
|
||||
Operand address = context.Add(n, Const(offset));
|
||||
if (eBytes == 8)
|
||||
{
|
||||
@@ -131,6 +131,7 @@ namespace ARMeilleure.Instructions
|
||||
{
|
||||
OpCode32SimdMemPair op = (OpCode32SimdMemPair)context.CurrOp;
|
||||
|
||||
int increment = count > 1 ? op.Increment : 1;
|
||||
int eBytes = 1 << op.Size;
|
||||
|
||||
Operand n = context.Copy(GetIntA32(context, op.Rn));
|
||||
@@ -144,7 +145,7 @@ namespace ARMeilleure.Instructions
|
||||
int elemD = d + reg;
|
||||
for (int i = 0; i < count; i++)
|
||||
{
|
||||
// Write an element from a double simd register
|
||||
// Accesses an element from a double simd register,
|
||||
// add ebytes for each element.
|
||||
Operand address = context.Add(n, Const(offset));
|
||||
int index = ((elemD & 1) << (3 - op.Size)) + elem;
|
||||
@@ -161,7 +162,6 @@ namespace ARMeilleure.Instructions
|
||||
}
|
||||
else
|
||||
{
|
||||
|
||||
if (load)
|
||||
{
|
||||
EmitLoadSimd(context, address, GetVecA32(elemD >> 1), elemD >> 1, index, op.Size);
|
||||
@@ -173,7 +173,7 @@ namespace ARMeilleure.Instructions
|
||||
}
|
||||
|
||||
offset += eBytes;
|
||||
elemD += op.Increment;
|
||||
elemD += increment;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1004,7 +1004,7 @@ namespace ARMeilleure.Instructions
|
||||
e = EmitShrImm64(context, e, signedSrc, roundConst, shift); // shift <= 32
|
||||
}
|
||||
|
||||
e = EmitSatQ(context, e, op.Size, signedSrc, signedDst);
|
||||
e = signedSrc ? EmitSignedSrcSatQ(context, e, op.Size, signedDst) : EmitUnsignedSrcSatQ(context, e, op.Size, signedDst);
|
||||
|
||||
res = EmitVectorInsert(context, res, e, part + index, op.Size);
|
||||
}
|
||||
|
||||
@@ -33,64 +33,24 @@ namespace ARMeilleure.Instructions
|
||||
EmitShrImmSaturatingNarrowOp(context, op.U ? ShrImmSaturatingNarrowFlags.VectorZxZx : ShrImmSaturatingNarrowFlags.VectorSxSx);
|
||||
}
|
||||
|
||||
public static void Vqshrun(ArmEmitterContext context)
|
||||
{
|
||||
EmitShrImmSaturatingNarrowOp(context, ShrImmSaturatingNarrowFlags.VectorSxZx);
|
||||
}
|
||||
|
||||
public static void Vrshr(ArmEmitterContext context)
|
||||
{
|
||||
OpCode32SimdShImm op = (OpCode32SimdShImm)context.CurrOp;
|
||||
int shift = GetImmShr(op);
|
||||
long roundConst = 1L << (shift - 1);
|
||||
EmitRoundShrImmOp(context, accumulate: false);
|
||||
}
|
||||
|
||||
if (op.U)
|
||||
{
|
||||
if (op.Size < 2)
|
||||
{
|
||||
EmitVectorUnaryOpZx32(context, (op1) =>
|
||||
{
|
||||
op1 = context.Add(op1, Const(op1.Type, roundConst));
|
||||
public static void Vrshrn(ArmEmitterContext context)
|
||||
{
|
||||
EmitRoundShrImmNarrowOp(context, signed: false);
|
||||
}
|
||||
|
||||
return context.ShiftRightUI(op1, Const(shift));
|
||||
});
|
||||
}
|
||||
else if (op.Size == 2)
|
||||
{
|
||||
EmitVectorUnaryOpZx32(context, (op1) =>
|
||||
{
|
||||
op1 = context.ZeroExtend32(OperandType.I64, op1);
|
||||
op1 = context.Add(op1, Const(op1.Type, roundConst));
|
||||
|
||||
return context.ConvertI64ToI32(context.ShiftRightUI(op1, Const(shift)));
|
||||
});
|
||||
}
|
||||
else /* if (op.Size == 3) */
|
||||
{
|
||||
EmitVectorUnaryOpZx32(context, (op1) => EmitShrImm64(context, op1, signed: false, roundConst, shift));
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (op.Size < 2)
|
||||
{
|
||||
EmitVectorUnaryOpSx32(context, (op1) =>
|
||||
{
|
||||
op1 = context.Add(op1, Const(op1.Type, roundConst));
|
||||
|
||||
return context.ShiftRightSI(op1, Const(shift));
|
||||
});
|
||||
}
|
||||
else if (op.Size == 2)
|
||||
{
|
||||
EmitVectorUnaryOpSx32(context, (op1) =>
|
||||
{
|
||||
op1 = context.SignExtend32(OperandType.I64, op1);
|
||||
op1 = context.Add(op1, Const(op1.Type, roundConst));
|
||||
|
||||
return context.ConvertI64ToI32(context.ShiftRightSI(op1, Const(shift)));
|
||||
});
|
||||
}
|
||||
else /* if (op.Size == 3) */
|
||||
{
|
||||
EmitVectorUnaryOpZx32(context, (op1) => EmitShrImm64(context, op1, signed: true, roundConst, shift));
|
||||
}
|
||||
}
|
||||
public static void Vrsra(ArmEmitterContext context)
|
||||
{
|
||||
EmitRoundShrImmOp(context, accumulate: true);
|
||||
}
|
||||
|
||||
public static void Vshl(ArmEmitterContext context)
|
||||
@@ -191,6 +151,89 @@ namespace ARMeilleure.Instructions
|
||||
}
|
||||
}
|
||||
|
||||
public static void EmitRoundShrImmOp(ArmEmitterContext context, bool accumulate)
|
||||
{
|
||||
OpCode32SimdShImm op = (OpCode32SimdShImm)context.CurrOp;
|
||||
int shift = GetImmShr(op);
|
||||
long roundConst = 1L << (shift - 1);
|
||||
|
||||
if (op.U)
|
||||
{
|
||||
if (op.Size < 2)
|
||||
{
|
||||
EmitVectorUnaryOpZx32(context, (op1) =>
|
||||
{
|
||||
op1 = context.Add(op1, Const(op1.Type, roundConst));
|
||||
|
||||
return context.ShiftRightUI(op1, Const(shift));
|
||||
}, accumulate);
|
||||
}
|
||||
else if (op.Size == 2)
|
||||
{
|
||||
EmitVectorUnaryOpZx32(context, (op1) =>
|
||||
{
|
||||
op1 = context.ZeroExtend32(OperandType.I64, op1);
|
||||
op1 = context.Add(op1, Const(op1.Type, roundConst));
|
||||
|
||||
return context.ConvertI64ToI32(context.ShiftRightUI(op1, Const(shift)));
|
||||
}, accumulate);
|
||||
}
|
||||
else /* if (op.Size == 3) */
|
||||
{
|
||||
EmitVectorUnaryOpZx32(context, (op1) => EmitShrImm64(context, op1, signed: false, roundConst, shift), accumulate);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (op.Size < 2)
|
||||
{
|
||||
EmitVectorUnaryOpSx32(context, (op1) =>
|
||||
{
|
||||
op1 = context.Add(op1, Const(op1.Type, roundConst));
|
||||
|
||||
return context.ShiftRightSI(op1, Const(shift));
|
||||
}, accumulate);
|
||||
}
|
||||
else if (op.Size == 2)
|
||||
{
|
||||
EmitVectorUnaryOpSx32(context, (op1) =>
|
||||
{
|
||||
op1 = context.SignExtend32(OperandType.I64, op1);
|
||||
op1 = context.Add(op1, Const(op1.Type, roundConst));
|
||||
|
||||
return context.ConvertI64ToI32(context.ShiftRightSI(op1, Const(shift)));
|
||||
}, accumulate);
|
||||
}
|
||||
else /* if (op.Size == 3) */
|
||||
{
|
||||
EmitVectorUnaryOpZx32(context, (op1) => EmitShrImm64(context, op1, signed: true, roundConst, shift), accumulate);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
private static void EmitRoundShrImmNarrowOp(ArmEmitterContext context, bool signed)
|
||||
{
|
||||
OpCode32SimdShImm op = (OpCode32SimdShImm)context.CurrOp;
|
||||
|
||||
int shift = GetImmShr(op);
|
||||
long roundConst = 1L << (shift - 1);
|
||||
|
||||
EmitVectorUnaryNarrowOp32(context, (op1) =>
|
||||
{
|
||||
if (op.Size <= 1)
|
||||
{
|
||||
op1 = context.Add(op1, Const(op1.Type, roundConst));
|
||||
op1 = signed ? context.ShiftRightSI(op1, Const(shift)) : context.ShiftRightUI(op1, Const(shift));
|
||||
}
|
||||
else /* if (op.Size == 2 && round) */
|
||||
{
|
||||
op1 = EmitShrImm64(context, op1, signed, roundConst, shift); // shift <= 32
|
||||
}
|
||||
|
||||
return op1;
|
||||
}, signed);
|
||||
}
|
||||
|
||||
private static Operand EmitShlRegOp(ArmEmitterContext context, Operand op, Operand shiftLsB, int size, bool unsigned)
|
||||
{
|
||||
if (shiftLsB.Type == OperandType.I64)
|
||||
@@ -289,7 +332,7 @@ namespace ARMeilleure.Instructions
|
||||
op1 = EmitShrImm64(context, op1, signedSrc, roundConst, shift); // shift <= 32
|
||||
}
|
||||
|
||||
return EmitSatQ(context, op1, 8 << op.Size, signedDst);
|
||||
return EmitSatQ(context, op1, 8 << op.Size, signedSrc, signedDst);
|
||||
}, signedSrc);
|
||||
}
|
||||
|
||||
@@ -313,15 +356,20 @@ namespace ARMeilleure.Instructions
|
||||
return context.Call(info, value, Const(roundConst), Const(shift));
|
||||
}
|
||||
|
||||
private static Operand EmitSatQ(ArmEmitterContext context, Operand value, int eSize, bool signed)
|
||||
private static Operand EmitSatQ(ArmEmitterContext context, Operand value, int eSize, bool signedSrc, bool signedDst)
|
||||
{
|
||||
Debug.Assert(eSize <= 32);
|
||||
|
||||
long intMin = signed ? -(1L << (eSize - 1)) : 0;
|
||||
long intMax = signed ? (1L << (eSize - 1)) - 1 : (1L << eSize) - 1;
|
||||
long intMin = signedDst ? -(1L << (eSize - 1)) : 0;
|
||||
long intMax = signedDst ? (1L << (eSize - 1)) - 1 : (1L << eSize) - 1;
|
||||
|
||||
Operand gt = context.ICompareGreater(value, Const(value.Type, intMax));
|
||||
Operand lt = context.ICompareLess(value, Const(value.Type, intMin));
|
||||
Operand gt = signedSrc
|
||||
? context.ICompareGreater(value, Const(value.Type, intMax))
|
||||
: context.ICompareGreaterUI(value, Const(value.Type, intMax));
|
||||
|
||||
Operand lt = signedSrc
|
||||
? context.ICompareLess(value, Const(value.Type, intMin))
|
||||
: context.ICompareLessUI(value, Const(value.Type, intMin));
|
||||
|
||||
value = context.ConditionalSelect(gt, Const(value.Type, intMax), value);
|
||||
value = context.ConditionalSelect(lt, Const(value.Type, intMin), value);
|
||||
|
||||
@@ -16,18 +16,13 @@ namespace ARMeilleure.Instructions
|
||||
{
|
||||
OpCode32System op = (OpCode32System)context.CurrOp;
|
||||
|
||||
if (op.Coproc != 15)
|
||||
if (op.Coproc != 15 || op.Opc1 != 0)
|
||||
{
|
||||
InstEmit.Und(context);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
if (op.Opc1 != 0)
|
||||
{
|
||||
throw new NotImplementedException($"Unknown MRC Opc1 0x{op.Opc1:X16} at 0x{op.Address:X16}.");
|
||||
}
|
||||
|
||||
MethodInfo info;
|
||||
|
||||
switch (op.CRn)
|
||||
@@ -35,7 +30,7 @@ namespace ARMeilleure.Instructions
|
||||
case 13: // Process and Thread Info.
|
||||
if (op.CRm != 0)
|
||||
{
|
||||
throw new NotImplementedException($"Unknown MRC CRm 0x{op.CRm:X16} at 0x{op.Address:X16}.");
|
||||
throw new NotImplementedException($"Unknown MRC CRm 0x{op.CRm:X} at 0x{op.Address:X} (0x{op.RawOpCode:X}).");
|
||||
}
|
||||
|
||||
switch (op.Opc2)
|
||||
@@ -44,7 +39,7 @@ namespace ARMeilleure.Instructions
|
||||
info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetTpidrEl032)); break;
|
||||
|
||||
default:
|
||||
throw new NotImplementedException($"Unknown MRC Opc2 0x{op.Opc2:X16} at 0x{op.Address:X16}.");
|
||||
throw new NotImplementedException($"Unknown MRC Opc2 0x{op.Opc2:X} at 0x{op.Address:X} (0x{op.RawOpCode:X}).");
|
||||
}
|
||||
|
||||
break;
|
||||
@@ -59,11 +54,11 @@ namespace ARMeilleure.Instructions
|
||||
return; // No-op.
|
||||
|
||||
default:
|
||||
throw new NotImplementedException($"Unknown MRC Opc2 0x{op.Opc2:X16} at 0x{op.Address:X16}.");
|
||||
throw new NotImplementedException($"Unknown MRC Opc2 0x{op.Opc2:X16} at 0x{op.Address:X16} (0x{op.RawOpCode:X}).");
|
||||
}
|
||||
|
||||
default:
|
||||
throw new NotImplementedException($"Unknown MRC CRm 0x{op.CRm:X16} at 0x{op.Address:X16}.");
|
||||
throw new NotImplementedException($"Unknown MRC CRm 0x{op.CRm:X16} at 0x{op.Address:X16} (0x{op.RawOpCode:X}).");
|
||||
}
|
||||
|
||||
default:
|
||||
@@ -77,18 +72,13 @@ namespace ARMeilleure.Instructions
|
||||
{
|
||||
OpCode32System op = (OpCode32System)context.CurrOp;
|
||||
|
||||
if (op.Coproc != 15)
|
||||
if (op.Coproc != 15 || op.Opc1 != 0)
|
||||
{
|
||||
InstEmit.Und(context);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
if (op.Opc1 != 0)
|
||||
{
|
||||
throw new NotImplementedException($"Unknown MRC Opc1 0x{op.Opc1:X16} at 0x{op.Address:X16}.");
|
||||
}
|
||||
|
||||
MethodInfo info;
|
||||
|
||||
switch (op.CRn)
|
||||
@@ -96,7 +86,7 @@ namespace ARMeilleure.Instructions
|
||||
case 13: // Process and Thread Info.
|
||||
if (op.CRm != 0)
|
||||
{
|
||||
throw new NotImplementedException($"Unknown MRC CRm 0x{op.CRm:X16} at 0x{op.Address:X16}.");
|
||||
throw new NotImplementedException($"Unknown MRC CRm 0x{op.CRm:X} at 0x{op.Address:X} (0x{op.RawOpCode:X}).");
|
||||
}
|
||||
|
||||
switch (op.Opc2)
|
||||
@@ -108,13 +98,13 @@ namespace ARMeilleure.Instructions
|
||||
info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetTpidr32)); break;
|
||||
|
||||
default:
|
||||
throw new NotImplementedException($"Unknown MRC Opc2 0x{op.Opc2:X16} at 0x{op.Address:X16}.");
|
||||
throw new NotImplementedException($"Unknown MRC Opc2 0x{op.Opc2:X} at 0x{op.Address:X} (0x{op.RawOpCode:X}).");
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
default:
|
||||
throw new NotImplementedException($"Unknown MRC 0x{op.RawOpCode:X8} at 0x{op.Address:X16}.");
|
||||
throw new NotImplementedException($"Unknown MRC 0x{op.RawOpCode:X} at 0x{op.Address:X}.");
|
||||
}
|
||||
|
||||
if (op.Rt == RegisterAlias.Aarch32Pc)
|
||||
@@ -154,13 +144,13 @@ namespace ARMeilleure.Instructions
|
||||
info = typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetCntpctEl0)); break;
|
||||
|
||||
default:
|
||||
throw new NotImplementedException($"Unknown MRRC Opc1 0x{opc:X16} at 0x{op.Address:X16}.");
|
||||
throw new NotImplementedException($"Unknown MRRC Opc1 0x{opc:X} at 0x{op.Address:X} (0x{op.RawOpCode:X}).");
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
default:
|
||||
throw new NotImplementedException($"Unknown MRRC 0x{op.RawOpCode:X8} at 0x{op.Address:X16}.");
|
||||
throw new NotImplementedException($"Unknown MRRC 0x{op.RawOpCode:X} at 0x{op.Address:X}.");
|
||||
}
|
||||
|
||||
Operand result = context.Call(info);
|
||||
@@ -265,7 +255,7 @@ namespace ARMeilleure.Instructions
|
||||
case 0b1000: // FPEXC
|
||||
throw new NotImplementedException("Supervisor Only");
|
||||
default:
|
||||
throw new NotImplementedException($"Unknown VMRS 0x{op.RawOpCode:X8} at 0x{op.Address:X16}.");
|
||||
throw new NotImplementedException($"Unknown VMRS 0x{op.RawOpCode:X} at 0x{op.Address:X}.");
|
||||
}
|
||||
}
|
||||
|
||||
@@ -288,7 +278,7 @@ namespace ARMeilleure.Instructions
|
||||
case 0b1000: // FPEXC
|
||||
throw new NotImplementedException("Supervisor Only");
|
||||
default:
|
||||
throw new NotImplementedException($"Unknown VMSR 0x{op.RawOpCode:X8} at 0x{op.Address:X16}.");
|
||||
throw new NotImplementedException($"Unknown VMSR 0x{op.RawOpCode:X} at 0x{op.Address:X}.");
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -545,6 +545,8 @@ namespace ARMeilleure.Instructions
|
||||
Strexh,
|
||||
Strh,
|
||||
Sxtb16,
|
||||
Tbb,
|
||||
Tbh,
|
||||
Teq,
|
||||
Trap,
|
||||
Tst,
|
||||
@@ -601,6 +603,7 @@ namespace ARMeilleure.Instructions
|
||||
Vmin,
|
||||
Vminnm,
|
||||
Vmla,
|
||||
Vmlal,
|
||||
Vmls,
|
||||
Vmlsl,
|
||||
Vmov,
|
||||
@@ -618,15 +621,28 @@ namespace ARMeilleure.Instructions
|
||||
Vorn,
|
||||
Vorr,
|
||||
Vpadd,
|
||||
Vpaddl,
|
||||
Vpmax,
|
||||
Vpmin,
|
||||
Vqadd,
|
||||
Vqdmulh,
|
||||
Vqmovn,
|
||||
Vqmovun,
|
||||
Vqrshrn,
|
||||
Vqrshrun,
|
||||
Vqshrn,
|
||||
Vqshrun,
|
||||
Vqsub,
|
||||
Vrev,
|
||||
Vrhadd,
|
||||
Vrint,
|
||||
Vrinta,
|
||||
Vrintm,
|
||||
Vrintn,
|
||||
Vrintp,
|
||||
Vrintx,
|
||||
Vrshr,
|
||||
Vrshrn,
|
||||
Vsel,
|
||||
Vshl,
|
||||
Vshll,
|
||||
@@ -643,8 +659,10 @@ namespace ARMeilleure.Instructions
|
||||
Vrecps,
|
||||
Vrsqrte,
|
||||
Vrsqrts,
|
||||
Vrsra,
|
||||
Vsra,
|
||||
Vsub,
|
||||
Vsubl,
|
||||
Vsubw,
|
||||
Vtbl,
|
||||
Vtrn,
|
||||
|
||||
@@ -91,7 +91,7 @@ namespace ARMeilleure.Instructions
|
||||
}
|
||||
else /* if (eSize != 64) */
|
||||
{
|
||||
return SignedSrcSignedDstSatQ(value << shiftLsB, size);
|
||||
return SignedSrcSignedDstSatQ(value << shiftLsB, size); // InstEmitSimdHelper.EmitSignedSrcSatQ(signedDst: true).
|
||||
}
|
||||
}
|
||||
else /* if (shiftLsB == 0) */
|
||||
@@ -135,7 +135,7 @@ namespace ARMeilleure.Instructions
|
||||
}
|
||||
else /* if (eSize != 64) */
|
||||
{
|
||||
return UnsignedSrcUnsignedDstSatQ(value << shiftLsB, size);
|
||||
return UnsignedSrcUnsignedDstSatQ(value << shiftLsB, size); // InstEmitSimdHelper.EmitUnsignedSrcSatQ(signedDst: false).
|
||||
}
|
||||
}
|
||||
else /* if (shiftLsB == 0) */
|
||||
@@ -509,7 +509,7 @@ namespace ARMeilleure.Instructions
|
||||
#endregion
|
||||
|
||||
#region "Saturating"
|
||||
public static long SignedSrcSignedDstSatQ(long op, int size)
|
||||
private static long SignedSrcSignedDstSatQ(long op, int size)
|
||||
{
|
||||
ExecutionContext context = NativeInterface.GetContext();
|
||||
|
||||
@@ -536,54 +536,7 @@ namespace ARMeilleure.Instructions
|
||||
}
|
||||
}
|
||||
|
||||
public static ulong SignedSrcUnsignedDstSatQ(long op, int size)
|
||||
{
|
||||
ExecutionContext context = NativeInterface.GetContext();
|
||||
|
||||
int eSize = 8 << size;
|
||||
|
||||
ulong tMaxValue = (1UL << eSize) - 1UL;
|
||||
ulong tMinValue = 0UL;
|
||||
|
||||
if (op > (long)tMaxValue)
|
||||
{
|
||||
context.Fpsr |= FPSR.Qc;
|
||||
|
||||
return tMaxValue;
|
||||
}
|
||||
else if (op < (long)tMinValue)
|
||||
{
|
||||
context.Fpsr |= FPSR.Qc;
|
||||
|
||||
return tMinValue;
|
||||
}
|
||||
else
|
||||
{
|
||||
return (ulong)op;
|
||||
}
|
||||
}
|
||||
|
||||
public static long UnsignedSrcSignedDstSatQ(ulong op, int size)
|
||||
{
|
||||
ExecutionContext context = NativeInterface.GetContext();
|
||||
|
||||
int eSize = 8 << size;
|
||||
|
||||
long tMaxValue = (1L << (eSize - 1)) - 1L;
|
||||
|
||||
if (op > (ulong)tMaxValue)
|
||||
{
|
||||
context.Fpsr |= FPSR.Qc;
|
||||
|
||||
return tMaxValue;
|
||||
}
|
||||
else
|
||||
{
|
||||
return (long)op;
|
||||
}
|
||||
}
|
||||
|
||||
public static ulong UnsignedSrcUnsignedDstSatQ(ulong op, int size)
|
||||
private static ulong UnsignedSrcUnsignedDstSatQ(ulong op, int size)
|
||||
{
|
||||
ExecutionContext context = NativeInterface.GetContext();
|
||||
|
||||
@@ -602,208 +555,6 @@ namespace ARMeilleure.Instructions
|
||||
return op;
|
||||
}
|
||||
}
|
||||
|
||||
public static long UnarySignedSatQAbsOrNeg(long op)
|
||||
{
|
||||
ExecutionContext context = NativeInterface.GetContext();
|
||||
|
||||
if (op == long.MinValue)
|
||||
{
|
||||
context.Fpsr |= FPSR.Qc;
|
||||
|
||||
return long.MaxValue;
|
||||
}
|
||||
else
|
||||
{
|
||||
return op;
|
||||
}
|
||||
}
|
||||
|
||||
public static long BinarySignedSatQAdd(long op1, long op2)
|
||||
{
|
||||
ExecutionContext context = NativeInterface.GetContext();
|
||||
|
||||
long add = op1 + op2;
|
||||
|
||||
if ((~(op1 ^ op2) & (op1 ^ add)) < 0L)
|
||||
{
|
||||
context.Fpsr |= FPSR.Qc;
|
||||
|
||||
if (op1 < 0L)
|
||||
{
|
||||
return long.MinValue;
|
||||
}
|
||||
else
|
||||
{
|
||||
return long.MaxValue;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
return add;
|
||||
}
|
||||
}
|
||||
|
||||
public static ulong BinaryUnsignedSatQAdd(ulong op1, ulong op2)
|
||||
{
|
||||
ExecutionContext context = NativeInterface.GetContext();
|
||||
|
||||
ulong add = op1 + op2;
|
||||
|
||||
if ((add < op1) && (add < op2))
|
||||
{
|
||||
context.Fpsr |= FPSR.Qc;
|
||||
|
||||
return ulong.MaxValue;
|
||||
}
|
||||
else
|
||||
{
|
||||
return add;
|
||||
}
|
||||
}
|
||||
|
||||
public static long BinarySignedSatQSub(long op1, long op2)
|
||||
{
|
||||
ExecutionContext context = NativeInterface.GetContext();
|
||||
|
||||
long sub = op1 - op2;
|
||||
|
||||
if (((op1 ^ op2) & (op1 ^ sub)) < 0L)
|
||||
{
|
||||
context.Fpsr |= FPSR.Qc;
|
||||
|
||||
if (op1 < 0L)
|
||||
{
|
||||
return long.MinValue;
|
||||
}
|
||||
else
|
||||
{
|
||||
return long.MaxValue;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
return sub;
|
||||
}
|
||||
}
|
||||
|
||||
public static ulong BinaryUnsignedSatQSub(ulong op1, ulong op2)
|
||||
{
|
||||
ExecutionContext context = NativeInterface.GetContext();
|
||||
|
||||
ulong sub = op1 - op2;
|
||||
|
||||
if (op1 < op2)
|
||||
{
|
||||
context.Fpsr |= FPSR.Qc;
|
||||
|
||||
return ulong.MinValue;
|
||||
}
|
||||
else
|
||||
{
|
||||
return sub;
|
||||
}
|
||||
}
|
||||
|
||||
public static long BinarySignedSatQAcc(ulong op1, long op2)
|
||||
{
|
||||
ExecutionContext context = NativeInterface.GetContext();
|
||||
|
||||
if (op1 <= (ulong)long.MaxValue)
|
||||
{
|
||||
// op1 from ulong.MinValue to (ulong)long.MaxValue
|
||||
// op2 from long.MinValue to long.MaxValue
|
||||
|
||||
long add = (long)op1 + op2;
|
||||
|
||||
if ((~op2 & add) < 0L)
|
||||
{
|
||||
context.Fpsr |= FPSR.Qc;
|
||||
|
||||
return long.MaxValue;
|
||||
}
|
||||
else
|
||||
{
|
||||
return add;
|
||||
}
|
||||
}
|
||||
else if (op2 >= 0L)
|
||||
{
|
||||
// op1 from (ulong)long.MaxValue + 1UL to ulong.MaxValue
|
||||
// op2 from (long)ulong.MinValue to long.MaxValue
|
||||
|
||||
context.Fpsr |= FPSR.Qc;
|
||||
|
||||
return long.MaxValue;
|
||||
}
|
||||
else
|
||||
{
|
||||
// op1 from (ulong)long.MaxValue + 1UL to ulong.MaxValue
|
||||
// op2 from long.MinValue to (long)ulong.MinValue - 1L
|
||||
|
||||
ulong add = op1 + (ulong)op2;
|
||||
|
||||
if (add > (ulong)long.MaxValue)
|
||||
{
|
||||
context.Fpsr |= FPSR.Qc;
|
||||
|
||||
return long.MaxValue;
|
||||
}
|
||||
else
|
||||
{
|
||||
return (long)add;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
public static ulong BinaryUnsignedSatQAcc(long op1, ulong op2)
|
||||
{
|
||||
ExecutionContext context = NativeInterface.GetContext();
|
||||
|
||||
if (op1 >= 0L)
|
||||
{
|
||||
// op1 from (long)ulong.MinValue to long.MaxValue
|
||||
// op2 from ulong.MinValue to ulong.MaxValue
|
||||
|
||||
ulong add = (ulong)op1 + op2;
|
||||
|
||||
if ((add < (ulong)op1) && (add < op2))
|
||||
{
|
||||
context.Fpsr |= FPSR.Qc;
|
||||
|
||||
return ulong.MaxValue;
|
||||
}
|
||||
else
|
||||
{
|
||||
return add;
|
||||
}
|
||||
}
|
||||
else if (op2 > (ulong)long.MaxValue)
|
||||
{
|
||||
// op1 from long.MinValue to (long)ulong.MinValue - 1L
|
||||
// op2 from (ulong)long.MaxValue + 1UL to ulong.MaxValue
|
||||
|
||||
return (ulong)op1 + op2;
|
||||
}
|
||||
else
|
||||
{
|
||||
// op1 from long.MinValue to (long)ulong.MinValue - 1L
|
||||
// op2 from ulong.MinValue to (ulong)long.MaxValue
|
||||
|
||||
long add = op1 + (long)op2;
|
||||
|
||||
if (add < (long)ulong.MinValue)
|
||||
{
|
||||
context.Fpsr |= FPSR.Qc;
|
||||
|
||||
return ulong.MinValue;
|
||||
}
|
||||
else
|
||||
{
|
||||
return (ulong)add;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endregion
|
||||
|
||||
#region "Count"
|
||||
|
||||
@@ -127,7 +127,7 @@ namespace ARMeilleure.Translation
|
||||
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpcr)));
|
||||
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpscr))); // A32 only.
|
||||
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsr)));
|
||||
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc))); // A32 only.
|
||||
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetFpsrQc)));
|
||||
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetTpidrEl0)));
|
||||
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SetTpidrEl032))); // A32 only.
|
||||
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.SignalMemoryTracking)));
|
||||
@@ -140,12 +140,6 @@ namespace ARMeilleure.Translation
|
||||
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteUInt64)));
|
||||
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.WriteVector128)));
|
||||
|
||||
SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.BinarySignedSatQAcc)));
|
||||
SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.BinarySignedSatQAdd)));
|
||||
SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.BinarySignedSatQSub)));
|
||||
SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.BinaryUnsignedSatQAcc)));
|
||||
SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.BinaryUnsignedSatQAdd)));
|
||||
SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.BinaryUnsignedSatQSub)));
|
||||
SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.CountLeadingSigns)));
|
||||
SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.CountLeadingZeros)));
|
||||
SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Crc32b)));
|
||||
@@ -188,8 +182,6 @@ namespace ARMeilleure.Translation
|
||||
SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.SignedShlReg)));
|
||||
SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.SignedShlRegSatQ)));
|
||||
SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.SignedShrImm64)));
|
||||
SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.SignedSrcSignedDstSatQ)));
|
||||
SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.SignedSrcUnsignedDstSatQ)));
|
||||
SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl1)));
|
||||
SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl2)));
|
||||
SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbl3)));
|
||||
@@ -198,12 +190,9 @@ namespace ARMeilleure.Translation
|
||||
SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx2)));
|
||||
SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx3)));
|
||||
SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.Tbx4)));
|
||||
SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.UnarySignedSatQAbsOrNeg)));
|
||||
SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.UnsignedShlReg)));
|
||||
SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.UnsignedShlRegSatQ)));
|
||||
SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.UnsignedShrImm64)));
|
||||
SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.UnsignedSrcSignedDstSatQ)));
|
||||
SetDelegateInfo(typeof(SoftFallback).GetMethod(nameof(SoftFallback.UnsignedSrcUnsignedDstSatQ)));
|
||||
|
||||
SetDelegateInfo(typeof(SoftFloat16_32).GetMethod(nameof(SoftFloat16_32.FPConvert)));
|
||||
SetDelegateInfo(typeof(SoftFloat16_64).GetMethod(nameof(SoftFloat16_64.FPConvert)));
|
||||
|
||||
@@ -27,7 +27,7 @@ namespace ARMeilleure.Translation.PTC
|
||||
private const string OuterHeaderMagicString = "PTCohd\0\0";
|
||||
private const string InnerHeaderMagicString = "PTCihd\0\0";
|
||||
|
||||
private const uint InternalVersion = 3585; //! To be incremented manually for each change to the ARMeilleure project.
|
||||
private const uint InternalVersion = 3695; //! To be incremented manually for each change to the ARMeilleure project.
|
||||
|
||||
private const string ActualDir = "0";
|
||||
private const string BackupDir = "1";
|
||||
|
||||
@@ -44,15 +44,11 @@ namespace ARMeilleure.Translation
|
||||
private readonly IJitMemoryAllocator _allocator;
|
||||
private readonly ConcurrentQueue<KeyValuePair<ulong, TranslatedFunction>> _oldFuncs;
|
||||
|
||||
private readonly ConcurrentDictionary<ulong, object> _backgroundSet;
|
||||
private readonly ConcurrentStack<RejitRequest> _backgroundStack;
|
||||
private readonly AutoResetEvent _backgroundTranslatorEvent;
|
||||
private readonly ReaderWriterLock _backgroundTranslatorLock;
|
||||
|
||||
internal TranslatorCache<TranslatedFunction> Functions { get; }
|
||||
internal AddressTable<ulong> FunctionTable { get; }
|
||||
internal EntryTable<uint> CountTable { get; }
|
||||
internal TranslatorStubs Stubs { get; }
|
||||
internal TranslatorQueue Queue { get; }
|
||||
internal IMemoryManager Memory { get; }
|
||||
|
||||
private volatile int _threadCount;
|
||||
@@ -67,10 +63,7 @@ namespace ARMeilleure.Translation
|
||||
|
||||
_oldFuncs = new ConcurrentQueue<KeyValuePair<ulong, TranslatedFunction>>();
|
||||
|
||||
_backgroundSet = new ConcurrentDictionary<ulong, object>();
|
||||
_backgroundStack = new ConcurrentStack<RejitRequest>();
|
||||
_backgroundTranslatorEvent = new AutoResetEvent(false);
|
||||
_backgroundTranslatorLock = new ReaderWriterLock();
|
||||
Queue = new TranslatorQueue();
|
||||
|
||||
JitCache.Initialize(allocator);
|
||||
|
||||
@@ -87,43 +80,6 @@ namespace ARMeilleure.Translation
|
||||
}
|
||||
}
|
||||
|
||||
private void TranslateStackedSubs()
|
||||
{
|
||||
while (_threadCount != 0)
|
||||
{
|
||||
_backgroundTranslatorLock.AcquireReaderLock(Timeout.Infinite);
|
||||
|
||||
if (_backgroundStack.TryPop(out RejitRequest request) &&
|
||||
_backgroundSet.TryRemove(request.Address, out _))
|
||||
{
|
||||
TranslatedFunction func = Translate(request.Address, request.Mode, highCq: true);
|
||||
|
||||
Functions.AddOrUpdate(request.Address, func.GuestSize, func, (key, oldFunc) =>
|
||||
{
|
||||
EnqueueForDeletion(key, oldFunc);
|
||||
return func;
|
||||
});
|
||||
|
||||
if (PtcProfiler.Enabled)
|
||||
{
|
||||
PtcProfiler.UpdateEntry(request.Address, request.Mode, highCq: true);
|
||||
}
|
||||
|
||||
RegisterFunction(request.Address, func);
|
||||
|
||||
_backgroundTranslatorLock.ReleaseReaderLock();
|
||||
}
|
||||
else
|
||||
{
|
||||
_backgroundTranslatorLock.ReleaseReaderLock();
|
||||
_backgroundTranslatorEvent.WaitOne();
|
||||
}
|
||||
}
|
||||
|
||||
// Wake up any other background translator threads, to encourage them to exit.
|
||||
_backgroundTranslatorEvent.Set();
|
||||
}
|
||||
|
||||
public void Execute(State.ExecutionContext context, ulong address)
|
||||
{
|
||||
if (Interlocked.Increment(ref _threadCount) == 1)
|
||||
@@ -155,7 +111,7 @@ namespace ARMeilleure.Translation
|
||||
{
|
||||
bool last = i != 0 && i == unboundedThreadCount - 1;
|
||||
|
||||
Thread backgroundTranslatorThread = new Thread(TranslateStackedSubs)
|
||||
Thread backgroundTranslatorThread = new Thread(BackgroundTranslate)
|
||||
{
|
||||
Name = "CPU.BackgroundTranslatorThread." + i,
|
||||
Priority = last ? ThreadPriority.Lowest : ThreadPriority.Normal
|
||||
@@ -186,10 +142,9 @@ namespace ARMeilleure.Translation
|
||||
|
||||
if (Interlocked.Decrement(ref _threadCount) == 0)
|
||||
{
|
||||
_backgroundTranslatorEvent.Set();
|
||||
|
||||
ClearJitCache();
|
||||
|
||||
Queue.Dispose();
|
||||
Stubs.Dispose();
|
||||
FunctionTable.Dispose();
|
||||
CountTable.Dispose();
|
||||
@@ -317,6 +272,27 @@ namespace ARMeilleure.Translation
|
||||
return new TranslatedFunction(func, counter, funcSize, highCq);
|
||||
}
|
||||
|
||||
private void BackgroundTranslate()
|
||||
{
|
||||
while (_threadCount != 0 && Queue.TryDequeue(out RejitRequest request))
|
||||
{
|
||||
TranslatedFunction func = Translate(request.Address, request.Mode, highCq: true);
|
||||
|
||||
Functions.AddOrUpdate(request.Address, func.GuestSize, func, (key, oldFunc) =>
|
||||
{
|
||||
EnqueueForDeletion(key, oldFunc);
|
||||
return func;
|
||||
});
|
||||
|
||||
if (PtcProfiler.Enabled)
|
||||
{
|
||||
PtcProfiler.UpdateEntry(request.Address, request.Mode, highCq: true);
|
||||
}
|
||||
|
||||
RegisterFunction(request.Address, func);
|
||||
}
|
||||
}
|
||||
|
||||
private struct Range
|
||||
{
|
||||
public ulong Start { get; }
|
||||
@@ -504,11 +480,7 @@ namespace ARMeilleure.Translation
|
||||
|
||||
internal void EnqueueForRejit(ulong guestAddress, ExecutionMode mode)
|
||||
{
|
||||
if (_backgroundSet.TryAdd(guestAddress, null))
|
||||
{
|
||||
_backgroundStack.Push(new RejitRequest(guestAddress, mode));
|
||||
_backgroundTranslatorEvent.Set();
|
||||
}
|
||||
Queue.Enqueue(guestAddress, mode);
|
||||
}
|
||||
|
||||
private void EnqueueForDeletion(ulong guestAddress, TranslatedFunction func)
|
||||
@@ -542,26 +514,23 @@ namespace ARMeilleure.Translation
|
||||
|
||||
private void ClearRejitQueue(bool allowRequeue)
|
||||
{
|
||||
_backgroundTranslatorLock.AcquireWriterLock(Timeout.Infinite);
|
||||
|
||||
if (allowRequeue)
|
||||
if (!allowRequeue)
|
||||
{
|
||||
while (_backgroundStack.TryPop(out var request))
|
||||
Queue.Clear();
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
lock (Queue.Sync)
|
||||
{
|
||||
while (Queue.Count > 0 && Queue.TryDequeue(out RejitRequest request))
|
||||
{
|
||||
if (Functions.TryGetValue(request.Address, out var func) && func.CallCounter != null)
|
||||
{
|
||||
Volatile.Write(ref func.CallCounter.Value, 0);
|
||||
}
|
||||
|
||||
_backgroundSet.TryRemove(request.Address, out _);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
_backgroundStack.Clear();
|
||||
}
|
||||
|
||||
_backgroundTranslatorLock.ReleaseWriterLock();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
121
ARMeilleure/Translation/TranslatorQueue.cs
Normal file
121
ARMeilleure/Translation/TranslatorQueue.cs
Normal file
@@ -0,0 +1,121 @@
|
||||
using ARMeilleure.Diagnostics;
|
||||
using ARMeilleure.State;
|
||||
using System;
|
||||
using System.Collections.Generic;
|
||||
using System.Threading;
|
||||
|
||||
namespace ARMeilleure.Translation
|
||||
{
|
||||
/// <summary>
|
||||
/// Represents a queue of <see cref="RejitRequest"/>.
|
||||
/// </summary>
|
||||
/// <remarks>
|
||||
/// This does not necessarily behave like a queue, i.e: a FIFO collection.
|
||||
/// </remarks>
|
||||
sealed class TranslatorQueue : IDisposable
|
||||
{
|
||||
private bool _disposed;
|
||||
private readonly Stack<RejitRequest> _requests;
|
||||
private readonly HashSet<ulong> _requestAddresses;
|
||||
|
||||
/// <summary>
|
||||
/// Gets the object used to synchronize access to the <see cref="TranslatorQueue"/>.
|
||||
/// </summary>
|
||||
public object Sync { get; }
|
||||
|
||||
/// <summary>
|
||||
/// Gets the number of requests in the <see cref="TranslatorQueue"/>.
|
||||
/// </summary>
|
||||
public int Count => _requests.Count;
|
||||
|
||||
/// <summary>
|
||||
/// Initializes a new instance of the <see cref="TranslatorQueue"/> class.
|
||||
/// </summary>
|
||||
public TranslatorQueue()
|
||||
{
|
||||
Sync = new object();
|
||||
|
||||
_requests = new Stack<RejitRequest>();
|
||||
_requestAddresses = new HashSet<ulong>();
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// Enqueues a request with the specified <paramref name="address"/> and <paramref name="mode"/>.
|
||||
/// </summary>
|
||||
/// <param name="address">Address of request</param>
|
||||
/// <param name="mode"><see cref="ExecutionMode"/> of request</param>
|
||||
public void Enqueue(ulong address, ExecutionMode mode)
|
||||
{
|
||||
lock (Sync)
|
||||
{
|
||||
if (_requestAddresses.Add(address))
|
||||
{
|
||||
_requests.Push(new RejitRequest(address, mode));
|
||||
|
||||
TranslatorEventSource.Log.RejitQueueAdd(1);
|
||||
|
||||
Monitor.Pulse(Sync);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// Tries to dequeue a <see cref="RejitRequest"/>. This will block the thread until a <see cref="RejitRequest"/>
|
||||
/// is enqueued or the <see cref="TranslatorQueue"/> is disposed.
|
||||
/// </summary>
|
||||
/// <param name="result"><see cref="RejitRequest"/> dequeued</param>
|
||||
/// <returns><see langword="true"/> on success; otherwise <see langword="false"/></returns>
|
||||
public bool TryDequeue(out RejitRequest result)
|
||||
{
|
||||
while (!_disposed)
|
||||
{
|
||||
lock (Sync)
|
||||
{
|
||||
if (_requests.TryPop(out result))
|
||||
{
|
||||
_requestAddresses.Remove(result.Address);
|
||||
|
||||
TranslatorEventSource.Log.RejitQueueAdd(-1);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
Monitor.Wait(Sync);
|
||||
}
|
||||
}
|
||||
|
||||
result = default;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// Clears the <see cref="TranslatorQueue"/>.
|
||||
/// </summary>
|
||||
public void Clear()
|
||||
{
|
||||
lock (Sync)
|
||||
{
|
||||
TranslatorEventSource.Log.RejitQueueAdd(-_requests.Count);
|
||||
|
||||
_requests.Clear();
|
||||
_requestAddresses.Clear();
|
||||
|
||||
Monitor.PulseAll(Sync);
|
||||
}
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// Releases all resources used by the <see cref="TranslatorQueue"/> instance.
|
||||
/// </summary>
|
||||
public void Dispose()
|
||||
{
|
||||
if (!_disposed)
|
||||
{
|
||||
_disposed = true;
|
||||
|
||||
Clear();
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
10
README.md
10
README.md
@@ -36,8 +36,8 @@
|
||||
|
||||
## Compatibility
|
||||
|
||||
As of January 2022, Ryujinx has been tested on approximately 3,500 titles; over 3,200 boot past menus and into gameplay, with roughly 2,500 of those being considered playable.
|
||||
You can check out the compatibility list [here](https://github.com/Ryujinx/Ryujinx-Games-List/issues). Anyone is free to submit an updated test on an existing game entry; simply follow the new issue template and testing guidelines, or post as a reply to the applicable game issue. Use the search function to see if a game has been tested already!
|
||||
As of September 2022, Ryujinx has been tested on approximately 3,600 titles; over 3,400 boot past menus and into gameplay, with roughly 2,700 of those being considered playable. You can check out the compatibility list [here](https://github.com/Ryujinx/Ryujinx-Games-List/issues).
|
||||
Anyone is free to submit a new game test or update an existing game test entry; simply follow the new issue template and testing guidelines, or post as a reply to the applicable game issue. Use the search function to see if a game has been tested already!
|
||||
|
||||
## Usage
|
||||
|
||||
@@ -118,11 +118,11 @@ If you'd like to support the project financially, Ryujinx has an active Patreon
|
||||
<img src="https://images.squarespace-cdn.com/content/v1/560c1d39e4b0b4fae0c9cf2a/1567548955044-WVD994WZP76EWF15T0L3/Patreon+Button.png?format=500w" width="150">
|
||||
</a>
|
||||
|
||||
All the developers working on the project do so on their free time, but the project has several expenses:
|
||||
All developers working on the project do so in their free time, but the project has several expenses:
|
||||
* Hackable Nintendo Switch consoles to reverse-engineer the hardware
|
||||
* Additional computer hardware for testing purposes (e.g. GPUs to diagnose graphical bugs, etc.)
|
||||
* Licenses for various software development tools (e.g. Jetbrains, LDN servers, IDA)
|
||||
* Web hosting and infrastructure maintenance
|
||||
* Licenses for various software development tools (e.g. Jetbrains, IDA)
|
||||
* Web hosting and infrastructure maintenance (e.g. LDN servers)
|
||||
|
||||
All funds received through Patreon are considered a donation to support the project. Patrons receive early access to progress reports and exclusive access to developer interviews.
|
||||
|
||||
|
||||
@@ -55,7 +55,6 @@ namespace Ryujinx.Audio.Renderer.Server
|
||||
private uint _processHandle;
|
||||
private ulong _appletResourceId;
|
||||
|
||||
private WritableRegion _workBufferRegion;
|
||||
private MemoryHandle _workBufferMemoryPin;
|
||||
|
||||
private Memory<float> _mixBuffer;
|
||||
@@ -98,7 +97,15 @@ namespace Ryujinx.Audio.Renderer.Server
|
||||
_sessionId = 0;
|
||||
}
|
||||
|
||||
public ResultCode Initialize(ref AudioRendererConfiguration parameter, uint processHandle, CpuAddress workBuffer, ulong workBufferSize, int sessionId, ulong appletResourceId, IVirtualMemoryManager memoryManager)
|
||||
public ResultCode Initialize(
|
||||
ref AudioRendererConfiguration parameter,
|
||||
uint processHandle,
|
||||
Memory<byte> workBufferMemory,
|
||||
CpuAddress workBuffer,
|
||||
ulong workBufferSize,
|
||||
int sessionId,
|
||||
ulong appletResourceId,
|
||||
IVirtualMemoryManager memoryManager)
|
||||
{
|
||||
if (!BehaviourContext.CheckValidRevision(parameter.Revision))
|
||||
{
|
||||
@@ -134,11 +141,10 @@ namespace Ryujinx.Audio.Renderer.Server
|
||||
|
||||
WorkBufferAllocator workBufferAllocator;
|
||||
|
||||
_workBufferRegion = MemoryManager.GetWritableRegion(workBuffer, (int)workBufferSize);
|
||||
_workBufferRegion.Memory.Span.Fill(0);
|
||||
_workBufferMemoryPin = _workBufferRegion.Memory.Pin();
|
||||
workBufferMemory.Span.Fill(0);
|
||||
_workBufferMemoryPin = workBufferMemory.Pin();
|
||||
|
||||
workBufferAllocator = new WorkBufferAllocator(_workBufferRegion.Memory);
|
||||
workBufferAllocator = new WorkBufferAllocator(workBufferMemory);
|
||||
|
||||
PoolMapper poolMapper = new PoolMapper(processHandle, false);
|
||||
poolMapper.InitializeSystemPool(ref _dspMemoryPoolState, workBuffer, workBufferSize);
|
||||
@@ -841,7 +847,6 @@ namespace Ryujinx.Audio.Renderer.Server
|
||||
_manager.Unregister(this);
|
||||
_terminationEvent.Dispose();
|
||||
_workBufferMemoryPin.Dispose();
|
||||
_workBufferRegion.Dispose();
|
||||
|
||||
if (MemoryManager is IRefCounted rc)
|
||||
{
|
||||
|
||||
@@ -305,13 +305,34 @@ namespace Ryujinx.Audio.Renderer.Server
|
||||
/// <param name="workBufferSize">The guest work buffer size.</param>
|
||||
/// <param name="processHandle">The process handle of the application.</param>
|
||||
/// <returns>A <see cref="ResultCode"/> reporting an error or a success.</returns>
|
||||
public ResultCode OpenAudioRenderer(out AudioRenderSystem renderer, IVirtualMemoryManager memoryManager, ref AudioRendererConfiguration parameter, ulong appletResourceUserId, ulong workBufferAddress, ulong workBufferSize, uint processHandle, float volume)
|
||||
public ResultCode OpenAudioRenderer(
|
||||
out AudioRenderSystem renderer,
|
||||
IVirtualMemoryManager memoryManager,
|
||||
ref AudioRendererConfiguration parameter,
|
||||
ulong appletResourceUserId,
|
||||
ulong workBufferAddress,
|
||||
ulong workBufferSize,
|
||||
uint processHandle,
|
||||
float volume)
|
||||
{
|
||||
int sessionId = AcquireSessionId();
|
||||
|
||||
AudioRenderSystem audioRenderer = new AudioRenderSystem(this, _sessionsSystemEvent[sessionId]);
|
||||
|
||||
ResultCode result = audioRenderer.Initialize(ref parameter, processHandle, workBufferAddress, workBufferSize, sessionId, appletResourceUserId, memoryManager);
|
||||
// TODO: Eventually, we should try to use the guest supplied work buffer instead of allocating
|
||||
// our own. However, it was causing problems on some applications that would unmap the memory
|
||||
// before the audio renderer was fully disposed.
|
||||
Memory<byte> workBufferMemory = GC.AllocateArray<byte>((int)workBufferSize, pinned: true);
|
||||
|
||||
ResultCode result = audioRenderer.Initialize(
|
||||
ref parameter,
|
||||
processHandle,
|
||||
workBufferMemory,
|
||||
workBufferAddress,
|
||||
workBufferSize,
|
||||
sessionId,
|
||||
appletResourceUserId,
|
||||
memoryManager);
|
||||
|
||||
if (result == ResultCode.Success)
|
||||
{
|
||||
|
||||
@@ -52,8 +52,8 @@
|
||||
"GameListContextMenuOpenModsDirectory": "Modディレクトリを開く",
|
||||
"GameListContextMenuOpenModsDirectoryToolTip": "アプリケーションの Mod データを格納するディレクトリを開きます",
|
||||
"GameListContextMenuCacheManagement": "キャッシュ管理",
|
||||
"GameListContextMenuCacheManagementPurgePptc": "PPTC キャッシュを破棄",
|
||||
"GameListContextMenuCacheManagementPurgePptcToolTip": "アプリケーションの PPTC キャッシュを破棄します",
|
||||
"GameListContextMenuCacheManagementPurgePptc": "PPTC を再構築",
|
||||
"GameListContextMenuCacheManagementPurgePptcToolTip": "次回のゲーム起動時に PPTC を再構築します",
|
||||
"GameListContextMenuCacheManagementPurgeShaderCache": "シェーダキャッシュを破棄",
|
||||
"GameListContextMenuCacheManagementPurgeShaderCacheToolTip": "アプリケーションのシェーダキャッシュを破棄します",
|
||||
"GameListContextMenuCacheManagementOpenPptcDirectory": "PPTC ディレクトリを開く",
|
||||
@@ -121,9 +121,9 @@
|
||||
"SettingsTabSystemHacksNote": " (挙動が不安定になる可能性があります)",
|
||||
"SettingsTabSystemExpandDramSize": "DRAMサイズを6GBに拡大",
|
||||
"SettingsTabSystemIgnoreMissingServices": "未実装サービスを無視",
|
||||
"SettingsTabGraphics": "グラフィクス",
|
||||
"SettingsTabGraphicsEnhancements": "拡張",
|
||||
"SettingsTabGraphicsEnableShaderCache": "シェーダキャッシュ",
|
||||
"SettingsTabGraphics": "グラフィックス",
|
||||
"SettingsTabGraphicsAPI": "グラフィックスAPI",
|
||||
"SettingsTabGraphicsEnableShaderCache": "シェーダキャッシュを有効",
|
||||
"SettingsTabGraphicsAnisotropicFiltering": "異方性フィルタリング:",
|
||||
"SettingsTabGraphicsAnisotropicFilteringAuto": "自動",
|
||||
"SettingsTabGraphicsAnisotropicFiltering2x": "2x",
|
||||
@@ -144,7 +144,7 @@
|
||||
"SettingsTabGraphicsAspectRatio32x9": "32:9",
|
||||
"SettingsTabGraphicsAspectRatioStretch": "ウインドウサイズに合わせる",
|
||||
"SettingsTabGraphicsDeveloperOptions": "開発者向けオプション",
|
||||
"SettingsTabGraphicsShaderDumpPath": "グラフィクス シェーダダンプパス:",
|
||||
"SettingsTabGraphicsShaderDumpPath": "グラフィックス シェーダダンプパス:",
|
||||
"SettingsTabLogging": "ロギング",
|
||||
"SettingsTabLoggingLogging": "ロギング",
|
||||
"SettingsTabLoggingEnableLoggingToFile": "ファイルへのロギングを有効",
|
||||
@@ -350,7 +350,7 @@
|
||||
"DialogProfileDeleteProfileTitle": "プロファイルを削除中",
|
||||
"DialogProfileDeleteProfileMessage": "このアクションは元に戻せません. 本当に続けてよろしいですか?",
|
||||
"DialogWarning": "警告",
|
||||
"DialogPPTCDeletionMessage": "PPTC キャッシュを破棄しようとしています:\n\n{0}\n\n実行してよろしいですか?",
|
||||
"DialogPPTCDeletionMessage": "次回起動時に PPTC を再構築します:\n\n{0}\n\n実行してよろしいですか?",
|
||||
"DialogPPTCDeletionErrorMessage": "PPTC キャッシュ破棄エラー {0}: {1}",
|
||||
"DialogShaderDeletionMessage": "シェーダキャッシュを破棄しようとしています:\n\n{0}\n\n実行してよろしいですか?",
|
||||
"DialogShaderDeletionErrorMessage": "シェーダキャッシュ破棄エラー {0}: {1}",
|
||||
@@ -379,7 +379,7 @@
|
||||
"DialogSettingsBackendThreadingWarningTitle": "警告 - バックエンドスレッディング",
|
||||
"DialogSettingsBackendThreadingWarningMessage": "このオプションの変更を完全に適用するには Ryujinx の再起動が必要です. プラットフォームによっては, Ryujinx のものを使用する前に手動でドライバ自身のマルチスレッディングを無効にする必要があるかもしれません.",
|
||||
"SettingsTabGraphicsFeaturesOptions": "機能",
|
||||
"SettingsTabGraphicsBackendMultithreading": "グラフィクスバックエンドのマルチスレッド実行:",
|
||||
"SettingsTabGraphicsBackendMultithreading": "グラフィックスバックエンドのマルチスレッド実行:",
|
||||
"CommonAuto": "自動",
|
||||
"CommonOff": "オフ",
|
||||
"CommonOn": "オン",
|
||||
@@ -425,7 +425,7 @@
|
||||
"CustomThemeCheckTooltip": "エミュレータのメニュー外観を変更するためカスタム Avalonia テーマを使用します",
|
||||
"CustomThemePathTooltip": "カスタム GUI テーマのパスです",
|
||||
"CustomThemeBrowseTooltip": "カスタム GUI テーマを参照します",
|
||||
"DockModeToggleTooltip": "有効にすると,ドッキングされた Nintendo Switch をエミュレートします.多くのゲームではグラフィクス品質が向上します.\n無効にすると,携帯モードの Nintendo Switch をエミュレートします.グラフィクスの品質は低下します.\n\nドッキングモード有効ならプレイヤー1の,無効なら携帯の入力を設定してください.\n\nよくわからない場合はオンのままにしてください.",
|
||||
"DockModeToggleTooltip": "有効にすると,ドッキングされた Nintendo Switch をエミュレートします.多くのゲームではグラフィックス品質が向上します.\n無効にすると,携帯モードの Nintendo Switch をエミュレートします.グラフィックスの品質は低下します.\n\nドッキングモード有効ならプレイヤー1の,無効なら携帯の入力を設定してください.\n\nよくわからない場合はオンのままにしてください.",
|
||||
"DirectKeyboardTooltip": "キーボード直接アクセス (HID) に対応します. キーボードをテキスト入力デバイスとして使用できます.",
|
||||
"DirectMouseTooltip": "マウス直接アクセス (HID) に対応します. マウスをポインティングデバイスとして使用できます.",
|
||||
"RegionTooltip": "システムの地域を変更します",
|
||||
@@ -442,14 +442,14 @@
|
||||
"MemoryManagerUnsafeTooltip": "メモリを直接マップしますが, アクセス前にゲストのアドレス空間内のアドレスをマスクしません. より高速になりますが, 安全性が犠牲になります. ゲストアプリケーションは Ryujinx のどこからでもメモリにアクセスできるので,このモードでは信頼できるプログラムだけを実行するようにしてください.",
|
||||
"DRamTooltip": "エミュレートされたシステムのメモリ容量を 4GB から 6GB に増加します.\n\n高解像度のテクスチャパックや 4K解像度の mod を使用する場合に有用です. パフォーマンスを改善するものではありません.\n\nよくわからない場合はオフのままにしてください.",
|
||||
"IgnoreMissingServicesTooltip": "未実装の Horizon OS サービスを無視します. 特定のゲームにおいて起動時のクラッシュを回避できる場合があります.\n\nよくわからない場合はオフのままにしてください.",
|
||||
"GraphicsBackendThreadingTooltip": "グラフィクスバックエンドのコマンドを別スレッドで実行します.\n\nシェーダのコンパイルを高速化し, 遅延を軽減し, マルチスレッド非対応の GPU ドライバにおいてパフォーマンスを改善します. マルチスレッド対応のドライバでも若干パフォーマンス改善が見られます.\n\nよくわからない場合は自動に設定してください.",
|
||||
"GalThreadingTooltip": "グラフィクスバックエンドのコマンドを別スレッドで実行します.\n\nシェーダのコンパイルを高速化し, 遅延を軽減し, マルチスレッド非対応の GPU ドライバにおいてパフォーマンスを改善します. マルチスレッド対応のドライバでも若干パフォーマンス改善が見られます.\n\nよくわからない場合は自動に設定してください.",
|
||||
"GraphicsBackendThreadingTooltip": "グラフィックスバックエンドのコマンドを別スレッドで実行します.\n\nシェーダのコンパイルを高速化し, 遅延を軽減し, マルチスレッド非対応の GPU ドライバにおいてパフォーマンスを改善します. マルチスレッド対応のドライバでも若干パフォーマンス改善が見られます.\n\nよくわからない場合は自動に設定してください.",
|
||||
"GalThreadingTooltip": "グラフィックスバックエンドのコマンドを別スレッドで実行します.\n\nシェーダのコンパイルを高速化し, 遅延を軽減し, マルチスレッド非対応の GPU ドライバにおいてパフォーマンスを改善します. マルチスレッド対応のドライバでも若干パフォーマンス改善が見られます.\n\nよくわからない場合は自動に設定してください.",
|
||||
"ShaderCacheToggleTooltip": "ディスクシェーダキャッシュをセーブし,次回以降の実行時遅延を軽減します.\n\nよくわからない場合はオンのままにしてください.",
|
||||
"ResolutionScaleTooltip": "レンダリングに適用される解像度の倍率です",
|
||||
"ResolutionScaleEntryTooltip": "1.5 のような整数でない倍率を指定すると,問題が発生したりクラッシュしたりする場合があります.",
|
||||
"AnisotropyTooltip": "異方性フィルタリングのレベルです (ゲームが要求する値を使用する場合は｢自動｣を設定してください)",
|
||||
"AspectRatioTooltip": "レンダリングに適用されるアスペクト比です.",
|
||||
"ShaderDumpPathTooltip": "グラフィクス シェーダダンプのパスです",
|
||||
"ShaderDumpPathTooltip": "グラフィックス シェーダダンプのパスです",
|
||||
"FileLogTooltip": "コンソール出力されるログをディスク上のログファイルにセーブします. パフォーマンスには影響を与えません.",
|
||||
"StubLogTooltip": "stub ログメッセージをコンソールに出力します. パフォーマンスには影響を与えません.",
|
||||
"InfoLogTooltip": "info ログメッセージをコンソールに出力します. パフォーマンスには影響を与えません.",
|
||||
@@ -539,7 +539,7 @@
|
||||
"LoadingHeading": "ロード中: {0}",
|
||||
"CompilingPPTC": "PTC をコンパイル中",
|
||||
"CompilingShaders": "シェーダをコンパイル中",
|
||||
"AllKeyboards": "すべてキーボード",
|
||||
"AllKeyboards": "すべてのキーボード",
|
||||
"OpenFileDialogTitle": "開くファイルを選択",
|
||||
"OpenFolderDialogTitle": "展開されたゲームフォルダを選択",
|
||||
"AllSupportedFormats": "すべての対応フォーマット",
|
||||
@@ -573,9 +573,20 @@
|
||||
"Save": "セーブ",
|
||||
"Discard": "破棄",
|
||||
"UserProfilesSetProfileImage": "プロファイル画像を設定",
|
||||
"UserProfileEmptyNameError": "名前が必要です",
|
||||
"UserProfileEmptyNameError": "名称が必要です",
|
||||
"UserProfileNoImageError": "プロファイル画像が必要です",
|
||||
"GameUpdateWindowHeading": "利用可能なアップデート {0} [{1}]",
|
||||
"SettingsTabHotkeysResScaleUpHotkey": "解像度を上げる:",
|
||||
"SettingsTabHotkeysResScaleDownHotkey": "解像度を下げる:"
|
||||
"SettingsTabHotkeysResScaleDownHotkey": "解像度を下げる:",
|
||||
"UserProfilesName": "名称:",
|
||||
"UserProfilesUserId" : "ユーザID:",
|
||||
"SettingsTabGraphicsBackend": "グラフィックスバックエンド",
|
||||
"SettingsTabGraphicsBackendTooltip": "使用するグラフィックスバックエンドです",
|
||||
"SettingsEnableTextureRecompression": "テクスチャの再圧縮を有効",
|
||||
"SettingsEnableTextureRecompressionTooltip": "VRAMの使用量を削減するためテクスチャを圧縮します.\n\nGPUのVRAMが4GB未満の場合は使用を推奨します.\n\nよくわからない場合はオフのままにしてください.",
|
||||
"SettingsTabGraphicsPreferredGpu": "優先使用するGPU",
|
||||
"SettingsTabGraphicsPreferredGpuTooltip": "Vulkanグラフィックスバックエンドで使用されるグラフィックスカードを選択します.\n\nOpenGLが使用するGPUには影響しません.\n\n不明な場合は, \"dGPU\" としてフラグが立っているGPUに設定します. ない場合はそのままにします.",
|
||||
"SettingsAppRequiredRestartMessage": "Ryujinx の再起動が必要です",
|
||||
"SettingsGpuBackendRestartMessage": "グラフィックスバックエンドまたはGPUの設定が変更されました. 変更を適用するには再起動する必要があります",
|
||||
"SettingsGpuBackendRestartSubMessage": "今すぐ再起動しますか?"
|
||||
}
|
||||
|
||||
@@ -5,10 +5,10 @@ namespace Ryujinx.Common.Collections
|
||||
/// </summary>
|
||||
public class IntrusiveRedBlackTreeNode<T> where T : IntrusiveRedBlackTreeNode<T>
|
||||
{
|
||||
public bool Color = true;
|
||||
public T Left;
|
||||
public T Right;
|
||||
public T Parent;
|
||||
internal bool Color = true;
|
||||
internal T Left;
|
||||
internal T Right;
|
||||
internal T Parent;
|
||||
|
||||
public T Predecessor => IntrusiveRedBlackTreeImpl<T>.PredecessorOf((T)this);
|
||||
public T Successor => IntrusiveRedBlackTreeImpl<T>.SuccessorOf((T)this);
|
||||
|
||||
@@ -274,7 +274,8 @@ namespace Ryujinx.Cpu.Jit
|
||||
/// <inheritdoc/>
|
||||
public void Write(ulong va, ReadOnlySpan<byte> data)
|
||||
{
|
||||
try {
|
||||
try
|
||||
{
|
||||
SignalMemoryTracking(va, (ulong)data.Length, write: true);
|
||||
|
||||
_addressSpaceMirror.Write(va, data);
|
||||
|
||||
@@ -26,6 +26,7 @@ namespace Ryujinx.Graphics.GAL
|
||||
public readonly bool SupportsNonConstantTextureOffset;
|
||||
public readonly bool SupportsShaderBallot;
|
||||
public readonly bool SupportsTextureShadowLod;
|
||||
public readonly bool SupportsViewportIndex;
|
||||
public readonly bool SupportsViewportSwizzle;
|
||||
public readonly bool SupportsIndirectParameters;
|
||||
|
||||
@@ -59,6 +60,7 @@ namespace Ryujinx.Graphics.GAL
|
||||
bool supportsNonConstantTextureOffset,
|
||||
bool supportsShaderBallot,
|
||||
bool supportsTextureShadowLod,
|
||||
bool supportsViewportIndex,
|
||||
bool supportsViewportSwizzle,
|
||||
bool supportsIndirectParameters,
|
||||
uint maximumUniformBuffersPerStage,
|
||||
@@ -89,6 +91,7 @@ namespace Ryujinx.Graphics.GAL
|
||||
SupportsNonConstantTextureOffset = supportsNonConstantTextureOffset;
|
||||
SupportsShaderBallot = supportsShaderBallot;
|
||||
SupportsTextureShadowLod = supportsTextureShadowLod;
|
||||
SupportsViewportIndex = supportsViewportIndex;
|
||||
SupportsViewportSwizzle = supportsViewportSwizzle;
|
||||
SupportsIndirectParameters = supportsIndirectParameters;
|
||||
MaximumUniformBuffersPerStage = maximumUniformBuffersPerStage;
|
||||
|
||||
@@ -151,6 +151,190 @@ namespace Ryujinx.Graphics.GAL
|
||||
|
||||
public static class FormatExtensions
|
||||
{
|
||||
/// <summary>
|
||||
/// The largest scalar size for a buffer format.
|
||||
/// </summary>
|
||||
public const int MaxBufferFormatScalarSize = 4;
|
||||
|
||||
/// <summary>
|
||||
/// Gets the byte size for a single component of this format, or its packed size.
|
||||
/// </summary>
|
||||
/// <param name="format">Texture format</param>
|
||||
/// <returns>Byte size for a single component, or packed size</returns>
|
||||
public static int GetScalarSize(this Format format)
|
||||
{
|
||||
switch (format)
|
||||
{
|
||||
case Format.R8Unorm:
|
||||
case Format.R8Snorm:
|
||||
case Format.R8Uint:
|
||||
case Format.R8Sint:
|
||||
case Format.R8G8Unorm:
|
||||
case Format.R8G8Snorm:
|
||||
case Format.R8G8Uint:
|
||||
case Format.R8G8Sint:
|
||||
case Format.R8G8B8Unorm:
|
||||
case Format.R8G8B8Snorm:
|
||||
case Format.R8G8B8Uint:
|
||||
case Format.R8G8B8Sint:
|
||||
case Format.R8G8B8A8Unorm:
|
||||
case Format.R8G8B8A8Snorm:
|
||||
case Format.R8G8B8A8Uint:
|
||||
case Format.R8G8B8A8Sint:
|
||||
case Format.R8G8B8A8Srgb:
|
||||
case Format.R4G4Unorm:
|
||||
case Format.R8Uscaled:
|
||||
case Format.R8Sscaled:
|
||||
case Format.R8G8Uscaled:
|
||||
case Format.R8G8Sscaled:
|
||||
case Format.R8G8B8Uscaled:
|
||||
case Format.R8G8B8Sscaled:
|
||||
case Format.R8G8B8A8Uscaled:
|
||||
case Format.R8G8B8A8Sscaled:
|
||||
case Format.B8G8R8A8Unorm:
|
||||
case Format.B8G8R8A8Srgb:
|
||||
return 1;
|
||||
|
||||
case Format.R16Float:
|
||||
case Format.R16Unorm:
|
||||
case Format.R16Snorm:
|
||||
case Format.R16Uint:
|
||||
case Format.R16Sint:
|
||||
case Format.R16G16Float:
|
||||
case Format.R16G16Unorm:
|
||||
case Format.R16G16Snorm:
|
||||
case Format.R16G16Uint:
|
||||
case Format.R16G16Sint:
|
||||
case Format.R16G16B16Float:
|
||||
case Format.R16G16B16Unorm:
|
||||
case Format.R16G16B16Snorm:
|
||||
case Format.R16G16B16Uint:
|
||||
case Format.R16G16B16Sint:
|
||||
case Format.R16G16B16A16Float:
|
||||
case Format.R16G16B16A16Unorm:
|
||||
case Format.R16G16B16A16Snorm:
|
||||
case Format.R16G16B16A16Uint:
|
||||
case Format.R16G16B16A16Sint:
|
||||
case Format.R4G4B4A4Unorm:
|
||||
case Format.R5G5B5X1Unorm:
|
||||
case Format.R5G5B5A1Unorm:
|
||||
case Format.R5G6B5Unorm:
|
||||
case Format.R16Uscaled:
|
||||
case Format.R16Sscaled:
|
||||
case Format.R16G16Uscaled:
|
||||
case Format.R16G16Sscaled:
|
||||
case Format.R16G16B16Uscaled:
|
||||
case Format.R16G16B16Sscaled:
|
||||
case Format.R16G16B16A16Uscaled:
|
||||
case Format.R16G16B16A16Sscaled:
|
||||
case Format.B5G6R5Unorm:
|
||||
case Format.B5G5R5A1Unorm:
|
||||
case Format.A1B5G5R5Unorm:
|
||||
return 2;
|
||||
|
||||
case Format.R32Float:
|
||||
case Format.R32Uint:
|
||||
case Format.R32Sint:
|
||||
case Format.R32G32Float:
|
||||
case Format.R32G32Uint:
|
||||
case Format.R32G32Sint:
|
||||
case Format.R32G32B32Float:
|
||||
case Format.R32G32B32Uint:
|
||||
case Format.R32G32B32Sint:
|
||||
case Format.R32G32B32A32Float:
|
||||
case Format.R32G32B32A32Uint:
|
||||
case Format.R32G32B32A32Sint:
|
||||
case Format.R10G10B10A2Unorm:
|
||||
case Format.R10G10B10A2Uint:
|
||||
case Format.R11G11B10Float:
|
||||
case Format.R9G9B9E5Float:
|
||||
case Format.R32Uscaled:
|
||||
case Format.R32Sscaled:
|
||||
case Format.R32G32Uscaled:
|
||||
case Format.R32G32Sscaled:
|
||||
case Format.R32G32B32Uscaled:
|
||||
case Format.R32G32B32Sscaled:
|
||||
case Format.R32G32B32A32Uscaled:
|
||||
case Format.R32G32B32A32Sscaled:
|
||||
case Format.R10G10B10A2Snorm:
|
||||
case Format.R10G10B10A2Sint:
|
||||
case Format.R10G10B10A2Uscaled:
|
||||
case Format.R10G10B10A2Sscaled:
|
||||
return 4;
|
||||
|
||||
case Format.S8Uint:
|
||||
return 1;
|
||||
case Format.D16Unorm:
|
||||
return 2;
|
||||
case Format.S8UintD24Unorm:
|
||||
case Format.D32Float:
|
||||
case Format.D24UnormS8Uint:
|
||||
return 4;
|
||||
case Format.D32FloatS8Uint:
|
||||
return 8;
|
||||
|
||||
case Format.Bc1RgbaUnorm:
|
||||
case Format.Bc1RgbaSrgb:
|
||||
return 8;
|
||||
|
||||
case Format.Bc2Unorm:
|
||||
case Format.Bc3Unorm:
|
||||
case Format.Bc2Srgb:
|
||||
case Format.Bc3Srgb:
|
||||
case Format.Bc4Unorm:
|
||||
case Format.Bc4Snorm:
|
||||
case Format.Bc5Unorm:
|
||||
case Format.Bc5Snorm:
|
||||
case Format.Bc7Unorm:
|
||||
case Format.Bc7Srgb:
|
||||
case Format.Bc6HSfloat:
|
||||
case Format.Bc6HUfloat:
|
||||
return 16;
|
||||
|
||||
case Format.Etc2RgbUnorm:
|
||||
case Format.Etc2RgbPtaUnorm:
|
||||
case Format.Etc2RgbSrgb:
|
||||
case Format.Etc2RgbPtaSrgb:
|
||||
return 8;
|
||||
|
||||
case Format.Etc2RgbaUnorm:
|
||||
case Format.Etc2RgbaSrgb:
|
||||
return 16;
|
||||
|
||||
case Format.Astc4x4Unorm:
|
||||
case Format.Astc5x4Unorm:
|
||||
case Format.Astc5x5Unorm:
|
||||
case Format.Astc6x5Unorm:
|
||||
case Format.Astc6x6Unorm:
|
||||
case Format.Astc8x5Unorm:
|
||||
case Format.Astc8x6Unorm:
|
||||
case Format.Astc8x8Unorm:
|
||||
case Format.Astc10x5Unorm:
|
||||
case Format.Astc10x6Unorm:
|
||||
case Format.Astc10x8Unorm:
|
||||
case Format.Astc10x10Unorm:
|
||||
case Format.Astc12x10Unorm:
|
||||
case Format.Astc12x12Unorm:
|
||||
case Format.Astc4x4Srgb:
|
||||
case Format.Astc5x4Srgb:
|
||||
case Format.Astc5x5Srgb:
|
||||
case Format.Astc6x5Srgb:
|
||||
case Format.Astc6x6Srgb:
|
||||
case Format.Astc8x5Srgb:
|
||||
case Format.Astc8x6Srgb:
|
||||
case Format.Astc8x8Srgb:
|
||||
case Format.Astc10x5Srgb:
|
||||
case Format.Astc10x6Srgb:
|
||||
case Format.Astc10x8Srgb:
|
||||
case Format.Astc10x10Srgb:
|
||||
case Format.Astc12x10Srgb:
|
||||
case Format.Astc12x12Srgb:
|
||||
return 16;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// Checks if the texture format is valid to use as image format.
|
||||
/// </summary>
|
||||
|
||||
@@ -1,4 +1,5 @@
|
||||
using Ryujinx.Graphics.GAL;
|
||||
using System;
|
||||
|
||||
namespace Ryujinx.Graphics.Gpu.Engine.Threed
|
||||
{
|
||||
@@ -151,10 +152,21 @@ namespace Ryujinx.Graphics.Gpu.Engine.Threed
|
||||
|
||||
ulong ticks = _context.GetTimestamp();
|
||||
|
||||
float divisor = type switch
|
||||
{
|
||||
ReportCounterType.SamplesPassed => _channel.TextureManager.RenderTargetScale * _channel.TextureManager.RenderTargetScale,
|
||||
_ => 1f
|
||||
};
|
||||
|
||||
ICounterEvent counter = null;
|
||||
|
||||
void resultHandler(object evt, ulong result)
|
||||
{
|
||||
if (divisor != 1f)
|
||||
{
|
||||
result = (ulong)MathF.Ceiling(result / divisor);
|
||||
}
|
||||
|
||||
CounterData counterData = new CounterData
|
||||
{
|
||||
Counter = result,
|
||||
|
||||
@@ -8,195 +8,542 @@ namespace Ryujinx.Graphics.Gpu.Image
|
||||
/// </summary>
|
||||
static class FormatTable
|
||||
{
|
||||
private static Dictionary<uint, FormatInfo> _textureFormats = new Dictionary<uint, FormatInfo>()
|
||||
private enum TextureFormat : uint
|
||||
{
|
||||
{ 0x2491d, new FormatInfo(Format.R8Unorm, 1, 1, 1, 1) },
|
||||
{ 0x1249d, new FormatInfo(Format.R8Snorm, 1, 1, 1, 1) },
|
||||
{ 0x4921d, new FormatInfo(Format.R8Uint, 1, 1, 1, 1) },
|
||||
{ 0x36d9d, new FormatInfo(Format.R8Sint, 1, 1, 1, 1) },
|
||||
{ 0x7ff9b, new FormatInfo(Format.R16Float, 1, 1, 2, 1) },
|
||||
{ 0x2491b, new FormatInfo(Format.R16Unorm, 1, 1, 2, 1) },
|
||||
{ 0x1249b, new FormatInfo(Format.R16Snorm, 1, 1, 2, 1) },
|
||||
{ 0x4921b, new FormatInfo(Format.R16Uint, 1, 1, 2, 1) },
|
||||
{ 0x36d9b, new FormatInfo(Format.R16Sint, 1, 1, 2, 1) },
|
||||
{ 0x7ff8f, new FormatInfo(Format.R32Float, 1, 1, 4, 1) },
|
||||
{ 0x4920f, new FormatInfo(Format.R32Uint, 1, 1, 4, 1) },
|
||||
{ 0x36d8f, new FormatInfo(Format.R32Sint, 1, 1, 4, 1) },
|
||||
{ 0x24918, new FormatInfo(Format.R8G8Unorm, 1, 1, 2, 2) },
|
||||
{ 0x12498, new FormatInfo(Format.R8G8Snorm, 1, 1, 2, 2) },
|
||||
{ 0x49218, new FormatInfo(Format.R8G8Uint, 1, 1, 2, 2) },
|
||||
{ 0x36d98, new FormatInfo(Format.R8G8Sint, 1, 1, 2, 2) },
|
||||
{ 0x7ff8c, new FormatInfo(Format.R16G16Float, 1, 1, 4, 2) },
|
||||
{ 0x2490c, new FormatInfo(Format.R16G16Unorm, 1, 1, 4, 2) },
|
||||
{ 0x1248c, new FormatInfo(Format.R16G16Snorm, 1, 1, 4, 2) },
|
||||
{ 0x4920c, new FormatInfo(Format.R16G16Uint, 1, 1, 4, 2) },
|
||||
{ 0x36d8c, new FormatInfo(Format.R16G16Sint, 1, 1, 4, 2) },
|
||||
{ 0x7ff84, new FormatInfo(Format.R32G32Float, 1, 1, 8, 2) },
|
||||
{ 0x49204, new FormatInfo(Format.R32G32Uint, 1, 1, 8, 2) },
|
||||
{ 0x36d84, new FormatInfo(Format.R32G32Sint, 1, 1, 8, 2) },
|
||||
{ 0x7ff82, new FormatInfo(Format.R32G32B32Float, 1, 1, 12, 3) },
|
||||
{ 0x49202, new FormatInfo(Format.R32G32B32Uint, 1, 1, 12, 3) },
|
||||
{ 0x36d82, new FormatInfo(Format.R32G32B32Sint, 1, 1, 12, 3) },
|
||||
{ 0x24908, new FormatInfo(Format.R8G8B8A8Unorm, 1, 1, 4, 4) },
|
||||
{ 0x12488, new FormatInfo(Format.R8G8B8A8Snorm, 1, 1, 4, 4) },
|
||||
{ 0x49208, new FormatInfo(Format.R8G8B8A8Uint, 1, 1, 4, 4) },
|
||||
{ 0x36d88, new FormatInfo(Format.R8G8B8A8Sint, 1, 1, 4, 4) },
|
||||
{ 0x7ff83, new FormatInfo(Format.R16G16B16A16Float, 1, 1, 8, 4) },
|
||||
{ 0x24903, new FormatInfo(Format.R16G16B16A16Unorm, 1, 1, 8, 4) },
|
||||
{ 0x12483, new FormatInfo(Format.R16G16B16A16Snorm, 1, 1, 8, 4) },
|
||||
{ 0x49203, new FormatInfo(Format.R16G16B16A16Uint, 1, 1, 8, 4) },
|
||||
{ 0x36d83, new FormatInfo(Format.R16G16B16A16Sint, 1, 1, 8, 4) },
|
||||
{ 0x7ff81, new FormatInfo(Format.R32G32B32A32Float, 1, 1, 16, 4) },
|
||||
{ 0x49201, new FormatInfo(Format.R32G32B32A32Uint, 1, 1, 16, 4) },
|
||||
{ 0x36d81, new FormatInfo(Format.R32G32B32A32Sint, 1, 1, 16, 4) },
|
||||
{ 0x2493a, new FormatInfo(Format.D16Unorm, 1, 1, 2, 1) },
|
||||
{ 0x493af, new FormatInfo(Format.D32Float, 1, 1, 4, 1) },
|
||||
{ 0x7ffaf, new FormatInfo(Format.D32Float, 1, 1, 4, 1) },
|
||||
{ 0x24a0e, new FormatInfo(Format.D24UnormS8Uint, 1, 1, 4, 2) },
|
||||
{ 0x24a29, new FormatInfo(Format.D24UnormS8Uint, 1, 1, 4, 2) },
|
||||
{ 0x48a29, new FormatInfo(Format.D24UnormS8Uint, 1, 1, 4, 2) },
|
||||
{ 0x4912b, new FormatInfo(Format.S8UintD24Unorm, 1, 1, 4, 2) },
|
||||
{ 0x25385, new FormatInfo(Format.D32FloatS8Uint, 1, 1, 8, 2) },
|
||||
{ 0x253b0, new FormatInfo(Format.D32FloatS8Uint, 1, 1, 8, 2) },
|
||||
{ 0xa4908, new FormatInfo(Format.R8G8B8A8Srgb, 1, 1, 4, 4) },
|
||||
{ 0x2491e, new FormatInfo(Format.R4G4Unorm, 1, 1, 1, 2) },
|
||||
{ 0x24912, new FormatInfo(Format.R4G4B4A4Unorm, 1, 1, 2, 4) },
|
||||
{ 0x24914, new FormatInfo(Format.R5G5B5A1Unorm, 1, 1, 2, 4) },
|
||||
{ 0x24915, new FormatInfo(Format.R5G6B5Unorm, 1, 1, 2, 3) },
|
||||
{ 0x24909, new FormatInfo(Format.R10G10B10A2Unorm, 1, 1, 4, 4) },
|
||||
{ 0x49209, new FormatInfo(Format.R10G10B10A2Uint, 1, 1, 4, 4) },
|
||||
{ 0x7ffa1, new FormatInfo(Format.R11G11B10Float, 1, 1, 4, 3) },
|
||||
{ 0x7ffa0, new FormatInfo(Format.R9G9B9E5Float, 1, 1, 4, 4) },
|
||||
{ 0x24924, new FormatInfo(Format.Bc1RgbaUnorm, 4, 4, 8, 4) },
|
||||
{ 0x24925, new FormatInfo(Format.Bc2Unorm, 4, 4, 16, 4) },
|
||||
{ 0x24926, new FormatInfo(Format.Bc3Unorm, 4, 4, 16, 4) },
|
||||
{ 0xa4924, new FormatInfo(Format.Bc1RgbaSrgb, 4, 4, 8, 4) },
|
||||
{ 0xa4925, new FormatInfo(Format.Bc2Srgb, 4, 4, 16, 4) },
|
||||
{ 0xa4926, new FormatInfo(Format.Bc3Srgb, 4, 4, 16, 4) },
|
||||
{ 0x24927, new FormatInfo(Format.Bc4Unorm, 4, 4, 8, 1) },
|
||||
{ 0x124a7, new FormatInfo(Format.Bc4Snorm, 4, 4, 8, 1) },
|
||||
{ 0x24928, new FormatInfo(Format.Bc5Unorm, 4, 4, 16, 2) },
|
||||
{ 0x124a8, new FormatInfo(Format.Bc5Snorm, 4, 4, 16, 2) },
|
||||
{ 0x24917, new FormatInfo(Format.Bc7Unorm, 4, 4, 16, 4) },
|
||||
{ 0xa4917, new FormatInfo(Format.Bc7Srgb, 4, 4, 16, 4) },
|
||||
{ 0x7ff90, new FormatInfo(Format.Bc6HSfloat, 4, 4, 16, 4) },
|
||||
{ 0x7ff91, new FormatInfo(Format.Bc6HUfloat, 4, 4, 16, 4) },
|
||||
{ 0x24906, new FormatInfo(Format.Etc2RgbUnorm, 4, 4, 8, 3) },
|
||||
{ 0x2490b, new FormatInfo(Format.Etc2RgbaUnorm, 4, 4, 16, 4) },
|
||||
{ 0xa4906, new FormatInfo(Format.Etc2RgbSrgb, 4, 4, 8, 3) },
|
||||
{ 0xa490b, new FormatInfo(Format.Etc2RgbaSrgb, 4, 4, 16, 4) },
|
||||
{ 0x24940, new FormatInfo(Format.Astc4x4Unorm, 4, 4, 16, 4) },
|
||||
{ 0x24950, new FormatInfo(Format.Astc5x4Unorm, 5, 4, 16, 4) },
|
||||
{ 0x24941, new FormatInfo(Format.Astc5x5Unorm, 5, 5, 16, 4) },
|
||||
{ 0x24951, new FormatInfo(Format.Astc6x5Unorm, 6, 5, 16, 4) },
|
||||
{ 0x24942, new FormatInfo(Format.Astc6x6Unorm, 6, 6, 16, 4) },
|
||||
{ 0x24955, new FormatInfo(Format.Astc8x5Unorm, 8, 5, 16, 4) },
|
||||
{ 0x24952, new FormatInfo(Format.Astc8x6Unorm, 8, 6, 16, 4) },
|
||||
{ 0x24944, new FormatInfo(Format.Astc8x8Unorm, 8, 8, 16, 4) },
|
||||
{ 0x24956, new FormatInfo(Format.Astc10x5Unorm, 10, 5, 16, 4) },
|
||||
{ 0x24957, new FormatInfo(Format.Astc10x6Unorm, 10, 6, 16, 4) },
|
||||
{ 0x24953, new FormatInfo(Format.Astc10x8Unorm, 10, 8, 16, 4) },
|
||||
{ 0x24945, new FormatInfo(Format.Astc10x10Unorm, 10, 10, 16, 4) },
|
||||
{ 0x24954, new FormatInfo(Format.Astc12x10Unorm, 12, 10, 16, 4) },
|
||||
{ 0x24946, new FormatInfo(Format.Astc12x12Unorm, 12, 12, 16, 4) },
|
||||
{ 0xa4940, new FormatInfo(Format.Astc4x4Srgb, 4, 4, 16, 4) },
|
||||
{ 0xa4950, new FormatInfo(Format.Astc5x4Srgb, 5, 4, 16, 4) },
|
||||
{ 0xa4941, new FormatInfo(Format.Astc5x5Srgb, 5, 5, 16, 4) },
|
||||
{ 0xa4951, new FormatInfo(Format.Astc6x5Srgb, 6, 5, 16, 4) },
|
||||
{ 0xa4942, new FormatInfo(Format.Astc6x6Srgb, 6, 6, 16, 4) },
|
||||
{ 0xa4955, new FormatInfo(Format.Astc8x5Srgb, 8, 5, 16, 4) },
|
||||
{ 0xa4952, new FormatInfo(Format.Astc8x6Srgb, 8, 6, 16, 4) },
|
||||
{ 0xa4944, new FormatInfo(Format.Astc8x8Srgb, 8, 8, 16, 4) },
|
||||
{ 0xa4956, new FormatInfo(Format.Astc10x5Srgb, 10, 5, 16, 4) },
|
||||
{ 0xa4957, new FormatInfo(Format.Astc10x6Srgb, 10, 6, 16, 4) },
|
||||
{ 0xa4953, new FormatInfo(Format.Astc10x8Srgb, 10, 8, 16, 4) },
|
||||
{ 0xa4945, new FormatInfo(Format.Astc10x10Srgb, 10, 10, 16, 4) },
|
||||
{ 0xa4954, new FormatInfo(Format.Astc12x10Srgb, 12, 10, 16, 4) },
|
||||
{ 0xa4946, new FormatInfo(Format.Astc12x12Srgb, 12, 12, 16, 4) },
|
||||
{ 0x24913, new FormatInfo(Format.A1B5G5R5Unorm, 1, 1, 2, 4) }
|
||||
// Formats
|
||||
R32G32B32A32 = 0x01,
|
||||
R32G32B32 = 0x02,
|
||||
R16G16B16A16 = 0x03,
|
||||
R32G32 = 0x04,
|
||||
R32B24G8 = 0x05,
|
||||
X8B8G8R8 = 0x07,
|
||||
A8B8G8R8 = 0x08,
|
||||
A2B10G10R10 = 0x09,
|
||||
R16G16 = 0x0c,
|
||||
G8R24 = 0x0d,
|
||||
G24R8 = 0x0e,
|
||||
R32 = 0x0f,
|
||||
A4B4G4R4 = 0x12,
|
||||
A5B5G5R1 = 0x13,
|
||||
A1B5G5R5 = 0x14,
|
||||
B5G6R5 = 0x15,
|
||||
B6G5R5 = 0x16,
|
||||
G8R8 = 0x18,
|
||||
R16 = 0x1b,
|
||||
Y8Video = 0x1c,
|
||||
R8 = 0x1d,
|
||||
G4R4 = 0x1e,
|
||||
R1 = 0x1f,
|
||||
E5B9G9R9SharedExp = 0x20,
|
||||
Bf10Gf11Rf11 = 0x21,
|
||||
G8B8G8R8 = 0x22,
|
||||
B8G8R8G8 = 0x23,
|
||||
Bc1 = 0x24,
|
||||
Bc2 = 0x25,
|
||||
Bc3 = 0x26,
|
||||
Bc4 = 0x27,
|
||||
Bc5 = 0x28,
|
||||
Bc6HSf16 = 0x10,
|
||||
Bc6HUf16 = 0x11,
|
||||
Bc7U = 0x17,
|
||||
Etc2Rgb = 0x06,
|
||||
Etc2RgbPta = 0x0a,
|
||||
Etc2Rgba = 0x0b,
|
||||
Eac = 0x19,
|
||||
Eacx2 = 0x1a,
|
||||
Z24S8 = 0x29,
|
||||
X8Z24 = 0x2a,
|
||||
S8Z24 = 0x2b,
|
||||
X4V4Z24Cov4R4V = 0x2c,
|
||||
X4V4Z24Cov8R8V = 0x2d,
|
||||
V8Z24Cov4R12V = 0x2e,
|
||||
Zf32 = 0x2f,
|
||||
Zf32X24S8 = 0x30,
|
||||
X8Z24X20V4S8Cov4R4V = 0x31,
|
||||
X8Z24X20V4S8Cov8R8V = 0x32,
|
||||
Zf32X20V4X8Cov4R4V = 0x33,
|
||||
Zf32X20V4X8Cov8R8V = 0x34,
|
||||
Zf32X20V4S8Cov4R4V = 0x35,
|
||||
Zf32X20V4S8Cov8R8V = 0x36,
|
||||
X8Z24X16V8S8Cov4R12V = 0x37,
|
||||
Zf32X16V8X8Cov4R12V = 0x38,
|
||||
Zf32X16V8S8Cov4R12V = 0x39,
|
||||
Z16 = 0x3a,
|
||||
V8Z24Cov8R24V = 0x3b,
|
||||
X8Z24X16V8S8Cov8R24V = 0x3c,
|
||||
Zf32X16V8X8Cov8R24V = 0x3d,
|
||||
Zf32X16V8S8Cov8R24V = 0x3e,
|
||||
Astc2D4x4 = 0x40,
|
||||
Astc2D5x4 = 0x50,
|
||||
Astc2D5x5 = 0x41,
|
||||
Astc2D6x5 = 0x51,
|
||||
Astc2D6x6 = 0x42,
|
||||
Astc2D8x5 = 0x55,
|
||||
Astc2D8x6 = 0x52,
|
||||
Astc2D8x8 = 0x44,
|
||||
Astc2D10x5 = 0x56,
|
||||
Astc2D10x6 = 0x57,
|
||||
Astc2D10x8 = 0x53,
|
||||
Astc2D10x10 = 0x45,
|
||||
Astc2D12x10 = 0x54,
|
||||
Astc2D12x12 = 0x46,
|
||||
|
||||
// Types
|
||||
Snorm = 0x1,
|
||||
Unorm = 0x2,
|
||||
Sint = 0x3,
|
||||
Uint = 0x4,
|
||||
SnormForceFp16 = 0x5,
|
||||
UnormForceFp16 = 0x6,
|
||||
Float = 0x7,
|
||||
|
||||
// Component Types
|
||||
RSnorm = Snorm << 7,
|
||||
GSnorm = Snorm << 10,
|
||||
BSnorm = Snorm << 13,
|
||||
ASnorm = Snorm << 16,
|
||||
|
||||
RUnorm = Unorm << 7,
|
||||
GUnorm = Unorm << 10,
|
||||
BUnorm = Unorm << 13,
|
||||
AUnorm = Unorm << 16,
|
||||
|
||||
RSint = Sint << 7,
|
||||
GSint = Sint << 10,
|
||||
BSint = Sint << 13,
|
||||
ASint = Sint << 16,
|
||||
|
||||
RUint = Uint << 7,
|
||||
GUint = Uint << 10,
|
||||
BUint = Uint << 13,
|
||||
AUint = Uint << 16,
|
||||
|
||||
RSnormForceFp16 = SnormForceFp16 << 7,
|
||||
GSnormForceFp16 = SnormForceFp16 << 10,
|
||||
BSnormForceFp16 = SnormForceFp16 << 13,
|
||||
ASnormForceFp16 = SnormForceFp16 << 16,
|
||||
|
||||
RUnormForceFp16 = UnormForceFp16 << 7,
|
||||
GUnormForceFp16 = UnormForceFp16 << 10,
|
||||
BUnormForceFp16 = UnormForceFp16 << 13,
|
||||
AUnormForceFp16 = UnormForceFp16 << 16,
|
||||
|
||||
RFloat = Float << 7,
|
||||
GFloat = Float << 10,
|
||||
BFloat = Float << 13,
|
||||
AFloat = Float << 16,
|
||||
|
||||
Srgb = 0x1 << 19, // Custom encoding
|
||||
|
||||
// Combinations
|
||||
R8Unorm = R8 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x2491d
|
||||
R8Snorm = R8 | RSnorm | GSnorm | BSnorm | ASnorm, // 0x1249d
|
||||
R8Uint = R8 | RUint | GUint | BUint | AUint, // 0x4921d
|
||||
R8Sint = R8 | RSint | GSint | BSint | ASint, // 0x36d9d
|
||||
R16Float = R16 | RFloat | GFloat | BFloat | AFloat, // 0x7ff9b
|
||||
R16Unorm = R16 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x2491b
|
||||
R16Snorm = R16 | RSnorm | GSnorm | BSnorm | ASnorm, // 0x1249b
|
||||
R16Uint = R16 | RUint | GUint | BUint | AUint, // 0x4921b
|
||||
R16Sint = R16 | RSint | GSint | BSint | ASint, // 0x36d9b
|
||||
R32Float = R32 | RFloat | GFloat | BFloat | AFloat, // 0x7ff8f
|
||||
R32Uint = R32 | RUint | GUint | BUint | AUint, // 0x4920f
|
||||
R32Sint = R32 | RSint | GSint | BSint | ASint, // 0x36d8f
|
||||
G8R8Unorm = G8R8 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24918
|
||||
G8R8Snorm = G8R8 | RSnorm | GSnorm | BSnorm | ASnorm, // 0x12498
|
||||
G8R8Uint = G8R8 | RUint | GUint | BUint | AUint, // 0x49218
|
||||
G8R8Sint = G8R8 | RSint | GSint | BSint | ASint, // 0x36d98
|
||||
R16G16Float = R16G16 | RFloat | GFloat | BFloat | AFloat, // 0x7ff8c
|
||||
R16G16Unorm = R16G16 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x2490c
|
||||
R16G16Snorm = R16G16 | RSnorm | GSnorm | BSnorm | ASnorm, // 0x1248c
|
||||
R16G16Uint = R16G16 | RUint | GUint | BUint | AUint, // 0x4920c
|
||||
R16G16Sint = R16G16 | RSint | GSint | BSint | ASint, // 0x36d8c
|
||||
R32G32Float = R32G32 | RFloat | GFloat | BFloat | AFloat, // 0x7ff84
|
||||
R32G32Uint = R32G32 | RUint | GUint | BUint | AUint, // 0x49204
|
||||
R32G32Sint = R32G32 | RSint | GSint | BSint | ASint, // 0x36d84
|
||||
R32G32B32Float = R32G32B32 | RFloat | GFloat | BFloat | AFloat, // 0x7ff82
|
||||
R32G32B32Uint = R32G32B32 | RUint | GUint | BUint | AUint, // 0x49202
|
||||
R32G32B32Sint = R32G32B32 | RSint | GSint | BSint | ASint, // 0x36d82
|
||||
A8B8G8R8Unorm = A8B8G8R8 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24908
|
||||
A8B8G8R8Snorm = A8B8G8R8 | RSnorm | GSnorm | BSnorm | ASnorm, // 0x12488
|
||||
A8B8G8R8Uint = A8B8G8R8 | RUint | GUint | BUint | AUint, // 0x49208
|
||||
A8B8G8R8Sint = A8B8G8R8 | RSint | GSint | BSint | ASint, // 0x36d88
|
||||
R16G16B16A16Float = R16G16B16A16 | RFloat | GFloat | BFloat | AFloat, // 0x7ff83
|
||||
R16G16B16A16Unorm = R16G16B16A16 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24903
|
||||
R16G16B16A16Snorm = R16G16B16A16 | RSnorm | GSnorm | BSnorm | ASnorm, // 0x12483
|
||||
R16G16B16A16Uint = R16G16B16A16 | RUint | GUint | BUint | AUint, // 0x49203
|
||||
R16G16B16A16Sint = R16G16B16A16 | RSint | GSint | BSint | ASint, // 0x36d83
|
||||
R32G32B32A32Float = R32G32B32A32 | RFloat | GFloat | BFloat | AFloat, // 0x7ff81
|
||||
R32G32B32A32Uint = R32G32B32A32 | RUint | GUint | BUint | AUint, // 0x49201
|
||||
R32G32B32A32Sint = R32G32B32A32 | RSint | GSint | BSint | ASint, // 0x36d81
|
||||
Z16Unorm = Z16 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x2493a
|
||||
Zf32RFloatGUintBUintAUint = Zf32 | RFloat | GUint | BUint | AUint, // 0x493af
|
||||
Zf32Float = Zf32 | RFloat | GFloat | BFloat | AFloat, // 0x7ffaf
|
||||
G24R8RUintGUnormBUnormAUnorm = G24R8 | RUint | GUnorm | BUnorm | AUnorm, // 0x24a0e
|
||||
Z24S8RUintGUnormBUnormAUnorm = Z24S8 | RUint | GUnorm | BUnorm | AUnorm, // 0x24a29
|
||||
Z24S8RUintGUnormBUintAUint = Z24S8 | RUint | GUnorm | BUint | AUint, // 0x48a29
|
||||
S8Z24RUnormGUintBUintAUint = S8Z24 | RUnorm | GUint | BUint | AUint, // 0x4912b
|
||||
R32B24G8RFloatGUintBUnormAUnorm = R32B24G8 | RFloat | GUint | BUnorm | AUnorm, // 0x25385
|
||||
Zf32X24S8RFloatGUintBUnormAUnorm = Zf32X24S8 | RFloat | GUint | BUnorm | AUnorm, // 0x253b0
|
||||
A8B8G8R8UnormSrgb = A8B8G8R8 | RUnorm | GUnorm | BUnorm | AUnorm | Srgb, // 0xa4908
|
||||
G4R4Unorm = G4R4 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x2491e
|
||||
A4B4G4R4Unorm = A4B4G4R4 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24912
|
||||
A1B5G5R5Unorm = A1B5G5R5 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24914
|
||||
B5G6R5Unorm = B5G6R5 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24915
|
||||
A2B10G10R10Unorm = A2B10G10R10 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24909
|
||||
A2B10G10R10Uint = A2B10G10R10 | RUint | GUint | BUint | AUint, // 0x49209
|
||||
Bf10Gf11Rf11Float = Bf10Gf11Rf11 | RFloat | GFloat | BFloat | AFloat, // 0x7ffa1
|
||||
E5B9G9R9SharedExpFloat = E5B9G9R9SharedExp | RFloat | GFloat | BFloat | AFloat, // 0x7ffa0
|
||||
Bc1Unorm = Bc1 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24924
|
||||
Bc2Unorm = Bc2 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24925
|
||||
Bc3Unorm = Bc3 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24926
|
||||
Bc1UnormSrgb = Bc1 | RUnorm | GUnorm | BUnorm | AUnorm | Srgb, // 0xa4924
|
||||
Bc2UnormSrgb = Bc2 | RUnorm | GUnorm | BUnorm | AUnorm | Srgb, // 0xa4925
|
||||
Bc3UnormSrgb = Bc3 | RUnorm | GUnorm | BUnorm | AUnorm | Srgb, // 0xa4926
|
||||
Bc4Unorm = Bc4 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24927
|
||||
Bc4Snorm = Bc4 | RSnorm | GSnorm | BSnorm | ASnorm, // 0x124a7
|
||||
Bc5Unorm = Bc5 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24928
|
||||
Bc5Snorm = Bc5 | RSnorm | GSnorm | BSnorm | ASnorm, // 0x124a8
|
||||
Bc7UUnorm = Bc7U | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24917
|
||||
Bc7UUnormSrgb = Bc7U | RUnorm | GUnorm | BUnorm | AUnorm | Srgb, // 0xa4917
|
||||
Bc6HSf16Float = Bc6HSf16 | RFloat | GFloat | BFloat | AFloat, // 0x7ff90
|
||||
Bc6HUf16Float = Bc6HUf16 | RFloat | GFloat | BFloat | AFloat, // 0x7ff91
|
||||
Etc2RgbUnorm = Etc2Rgb | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24906
|
||||
Etc2RgbaUnorm = Etc2Rgba | RUnorm | GUnorm | BUnorm | AUnorm, // 0x2490b
|
||||
Etc2RgbUnormSrgb = Etc2Rgb | RUnorm | GUnorm | BUnorm | AUnorm | Srgb, // 0xa4906
|
||||
Etc2RgbaUnormSrgb = Etc2Rgba | RUnorm | GUnorm | BUnorm | AUnorm | Srgb, // 0xa490b
|
||||
Astc2D4x4Unorm = Astc2D4x4 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24940
|
||||
Astc2D5x4Unorm = Astc2D5x4 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24950
|
||||
Astc2D5x5Unorm = Astc2D5x5 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24941
|
||||
Astc2D6x5Unorm = Astc2D6x5 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24951
|
||||
Astc2D6x6Unorm = Astc2D6x6 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24942
|
||||
Astc2D8x5Unorm = Astc2D8x5 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24955
|
||||
Astc2D8x6Unorm = Astc2D8x6 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24952
|
||||
Astc2D8x8Unorm = Astc2D8x8 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24944
|
||||
Astc2D10x5Unorm = Astc2D10x5 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24956
|
||||
Astc2D10x6Unorm = Astc2D10x6 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24957
|
||||
Astc2D10x8Unorm = Astc2D10x8 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24953
|
||||
Astc2D10x10Unorm = Astc2D10x10 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24945
|
||||
Astc2D12x10Unorm = Astc2D12x10 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24954
|
||||
Astc2D12x12Unorm = Astc2D12x12 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24946
|
||||
Astc2D4x4UnormSrgb = Astc2D4x4 | RUnorm | GUnorm | BUnorm | AUnorm | Srgb, // 0xa4940
|
||||
Astc2D5x4UnormSrgb = Astc2D5x4 | RUnorm | GUnorm | BUnorm | AUnorm | Srgb, // 0xa4950
|
||||
Astc2D5x5UnormSrgb = Astc2D5x5 | RUnorm | GUnorm | BUnorm | AUnorm | Srgb, // 0xa4941
|
||||
Astc2D6x5UnormSrgb = Astc2D6x5 | RUnorm | GUnorm | BUnorm | AUnorm | Srgb, // 0xa4951
|
||||
Astc2D6x6UnormSrgb = Astc2D6x6 | RUnorm | GUnorm | BUnorm | AUnorm | Srgb, // 0xa4942
|
||||
Astc2D8x5UnormSrgb = Astc2D8x5 | RUnorm | GUnorm | BUnorm | AUnorm | Srgb, // 0xa4955
|
||||
Astc2D8x6UnormSrgb = Astc2D8x6 | RUnorm | GUnorm | BUnorm | AUnorm | Srgb, // 0xa4952
|
||||
Astc2D8x8UnormSrgb = Astc2D8x8 | RUnorm | GUnorm | BUnorm | AUnorm | Srgb, // 0xa4944
|
||||
Astc2D10x5UnormSrgb = Astc2D10x5 | RUnorm | GUnorm | BUnorm | AUnorm | Srgb, // 0xa4956
|
||||
Astc2D10x6UnormSrgb = Astc2D10x6 | RUnorm | GUnorm | BUnorm | AUnorm | Srgb, // 0xa4957
|
||||
Astc2D10x8UnormSrgb = Astc2D10x8 | RUnorm | GUnorm | BUnorm | AUnorm | Srgb, // 0xa4953
|
||||
Astc2D10x10UnormSrgb = Astc2D10x10 | RUnorm | GUnorm | BUnorm | AUnorm | Srgb, // 0xa4945
|
||||
Astc2D12x10UnormSrgb = Astc2D12x10 | RUnorm | GUnorm | BUnorm | AUnorm | Srgb, // 0xa4954
|
||||
Astc2D12x12UnormSrgb = Astc2D12x12 | RUnorm | GUnorm | BUnorm | AUnorm | Srgb, // 0xa4946
|
||||
A5B5G5R1Unorm = A5B5G5R1 | RUnorm | GUnorm | BUnorm | AUnorm, // 0x24913
|
||||
}
|
||||
|
||||
private enum VertexAttributeFormat : uint
|
||||
{
|
||||
// Width
|
||||
R32G32B32A32 = 0x01,
|
||||
R32G32B32 = 0x02,
|
||||
R16G16B16A16 = 0x03,
|
||||
R32G32 = 0x04,
|
||||
R16G16B16 = 0x05,
|
||||
A8B8G8R8 = 0x2f,
|
||||
R8G8B8A8 = 0x0a,
|
||||
X8B8G8R8 = 0x33,
|
||||
A2B10G10R10 = 0x30,
|
||||
B10G11R11 = 0x31,
|
||||
R16G16 = 0x0f,
|
||||
R32 = 0x12,
|
||||
R8G8B8 = 0x13,
|
||||
G8R8 = 0x32,
|
||||
R8G8 = 0x18,
|
||||
R16 = 0x1b,
|
||||
R8 = 0x1d,
|
||||
A8 = 0x34,
|
||||
|
||||
// Type
|
||||
Snorm = 0x01,
|
||||
Unorm = 0x02,
|
||||
Sint = 0x03,
|
||||
Uint = 0x04,
|
||||
Uscaled = 0x05,
|
||||
Sscaled = 0x06,
|
||||
Float = 0x07,
|
||||
|
||||
// Combinations
|
||||
R8Unorm = (R8 << 21) | (Unorm << 27), // 0x13a00000
|
||||
R8Snorm = (R8 << 21) | (Snorm << 27), // 0x0ba00000
|
||||
R8Uint = (R8 << 21) | (Uint << 27), // 0x23a00000
|
||||
R8Sint = (R8 << 21) | (Sint << 27), // 0x1ba00000
|
||||
R16Float = (R16 << 21) | (Float << 27), // 0x3b600000
|
||||
R16Unorm = (R16 << 21) | (Unorm << 27), // 0x13600000
|
||||
R16Snorm = (R16 << 21) | (Snorm << 27), // 0x0b600000
|
||||
R16Uint = (R16 << 21) | (Uint << 27), // 0x23600000
|
||||
R16Sint = (R16 << 21) | (Sint << 27), // 0x1b600000
|
||||
R32Float = (R32 << 21) | (Float << 27), // 0x3a400000
|
||||
R32Uint = (R32 << 21) | (Uint << 27), // 0x22400000
|
||||
R32Sint = (R32 << 21) | (Sint << 27), // 0x1a400000
|
||||
R8G8Unorm = (R8G8 << 21) | (Unorm << 27), // 0x13000000
|
||||
R8G8Snorm = (R8G8 << 21) | (Snorm << 27), // 0x0b000000
|
||||
R8G8Uint = (R8G8 << 21) | (Uint << 27), // 0x23000000
|
||||
R8G8Sint = (R8G8 << 21) | (Sint << 27), // 0x1b000000
|
||||
R16G16Float = (R16G16 << 21) | (Float << 27), // 0x39e00000
|
||||
R16G16Unorm = (R16G16 << 21) | (Unorm << 27), // 0x11e00000
|
||||
R16G16Snorm = (R16G16 << 21) | (Snorm << 27), // 0x09e00000
|
||||
R16G16Uint = (R16G16 << 21) | (Uint << 27), // 0x21e00000
|
||||
R16G16Sint = (R16G16 << 21) | (Sint << 27), // 0x19e00000
|
||||
R32G32Float = (R32G32 << 21) | (Float << 27), // 0x38800000
|
||||
R32G32Uint = (R32G32 << 21) | (Uint << 27), // 0x20800000
|
||||
R32G32Sint = (R32G32 << 21) | (Sint << 27), // 0x18800000
|
||||
R8G8B8Unorm = (R8G8B8 << 21) | (Unorm << 27), // 0x12600000
|
||||
R8G8B8Snorm = (R8G8B8 << 21) | (Snorm << 27), // 0x0a600000
|
||||
R8G8B8Uint = (R8G8B8 << 21) | (Uint << 27), // 0x22600000
|
||||
R8G8B8Sint = (R8G8B8 << 21) | (Sint << 27), // 0x1a600000
|
||||
R16G16B16Float = (R16G16B16 << 21) | (Float << 27), // 0x38a00000
|
||||
R16G16B16Unorm = (R16G16B16 << 21) | (Unorm << 27), // 0x10a00000
|
||||
R16G16B16Snorm = (R16G16B16 << 21) | (Snorm << 27), // 0x08a00000
|
||||
R16G16B16Uint = (R16G16B16 << 21) | (Uint << 27), // 0x20a00000
|
||||
R16G16B16Sint = (R16G16B16 << 21) | (Sint << 27), // 0x18a00000
|
||||
R32G32B32Float = (R32G32B32 << 21) | (Float << 27), // 0x38400000
|
||||
R32G32B32Uint = (R32G32B32 << 21) | (Uint << 27), // 0x20400000
|
||||
R32G32B32Sint = (R32G32B32 << 21) | (Sint << 27), // 0x18400000
|
||||
R8G8B8A8Unorm = (R8G8B8A8 << 21) | (Unorm << 27), // 0x11400000
|
||||
R8G8B8A8Snorm = (R8G8B8A8 << 21) | (Snorm << 27), // 0x09400000
|
||||
R8G8B8A8Uint = (R8G8B8A8 << 21) | (Uint << 27), // 0x21400000
|
||||
R8G8B8A8Sint = (R8G8B8A8 << 21) | (Sint << 27), // 0x19400000
|
||||
R16G16B16A16Float = (R16G16B16A16 << 21) | (Float << 27), // 0x38600000
|
||||
R16G16B16A16Unorm = (R16G16B16A16 << 21) | (Unorm << 27), // 0x10600000
|
||||
R16G16B16A16Snorm = (R16G16B16A16 << 21) | (Snorm << 27), // 0x08600000
|
||||
R16G16B16A16Uint = (R16G16B16A16 << 21) | (Uint << 27), // 0x20600000
|
||||
R16G16B16A16Sint = (R16G16B16A16 << 21) | (Sint << 27), // 0x18600000
|
||||
R32G32B32A32Float = (R32G32B32A32 << 21) | (Float << 27), // 0x38200000
|
||||
R32G32B32A32Uint = (R32G32B32A32 << 21) | (Uint << 27), // 0x20200000
|
||||
R32G32B32A32Sint = (R32G32B32A32 << 21) | (Sint << 27), // 0x18200000
|
||||
A2B10G10R10Unorm = (A2B10G10R10 << 21) | (Unorm << 27), // 0x16000000
|
||||
A2B10G10R10Uint = (A2B10G10R10 << 21) | (Uint << 27), // 0x26000000
|
||||
B10G11R11Float = (B10G11R11 << 21) | (Float << 27), // 0x3e200000
|
||||
R8Uscaled = (R8 << 21) | (Uscaled << 27), // 0x2ba00000
|
||||
R8Sscaled = (R8 << 21) | (Sscaled << 27), // 0x33a00000
|
||||
R16Uscaled = (R16 << 21) | (Uscaled << 27), // 0x2b600000
|
||||
R16Sscaled = (R16 << 21) | (Sscaled << 27), // 0x33600000
|
||||
R32Uscaled = (R32 << 21) | (Uscaled << 27), // 0x2a400000
|
||||
R32Sscaled = (R32 << 21) | (Sscaled << 27), // 0x32400000
|
||||
R8G8Uscaled = (R8G8 << 21) | (Uscaled << 27), // 0x2b000000
|
||||
R8G8Sscaled = (R8G8 << 21) | (Sscaled << 27), // 0x33000000
|
||||
R16G16Uscaled = (R16G16 << 21) | (Uscaled << 27), // 0x29e00000
|
||||
R16G16Sscaled = (R16G16 << 21) | (Sscaled << 27), // 0x31e00000
|
||||
R32G32Uscaled = (R32G32 << 21) | (Uscaled << 27), // 0x28800000
|
||||
R32G32Sscaled = (R32G32 << 21) | (Sscaled << 27), // 0x30800000
|
||||
R8G8B8Uscaled = (R8G8B8 << 21) | (Uscaled << 27), // 0x2a600000
|
||||
R8G8B8Sscaled = (R8G8B8 << 21) | (Sscaled << 27), // 0x32600000
|
||||
R16G16B16Uscaled = (R16G16B16 << 21) | (Uscaled << 27), // 0x28a00000
|
||||
R16G16B16Sscaled = (R16G16B16 << 21) | (Sscaled << 27), // 0x30a00000
|
||||
R32G32B32Uscaled = (R32G32B32 << 21) | (Uscaled << 27), // 0x28400000
|
||||
R32G32B32Sscaled = (R32G32B32 << 21) | (Sscaled << 27), // 0x30400000
|
||||
R8G8B8A8Uscaled = (R8G8B8A8 << 21) | (Uscaled << 27), // 0x29400000
|
||||
R8G8B8A8Sscaled = (R8G8B8A8 << 21) | (Sscaled << 27), // 0x31400000
|
||||
R16G16B16A16Uscaled = (R16G16B16A16 << 21) | (Uscaled << 27), // 0x28600000
|
||||
R16G16B16A16Sscaled = (R16G16B16A16 << 21) | (Sscaled << 27), // 0x30600000
|
||||
R32G32B32A32Uscaled = (R32G32B32A32 << 21) | (Uscaled << 27), // 0x28200000
|
||||
R32G32B32A32Sscaled = (R32G32B32A32 << 21) | (Sscaled << 27), // 0x30200000
|
||||
A2B10G10R10Snorm = (A2B10G10R10 << 21) | (Snorm << 27), // 0x0e000000
|
||||
A2B10G10R10Sint = (A2B10G10R10 << 21) | (Sint << 27), // 0x1e000000
|
||||
A2B10G10R10Uscaled = (A2B10G10R10 << 21) | (Uscaled << 27), // 0x2e000000
|
||||
A2B10G10R10Sscaled = (A2B10G10R10 << 21) | (Sscaled << 27), // 0x36000000
|
||||
}
|
||||
|
||||
private static readonly Dictionary<TextureFormat, FormatInfo> _textureFormats = new Dictionary<TextureFormat, FormatInfo>()
|
||||
{
|
||||
{ TextureFormat.R8Unorm, new FormatInfo(Format.R8Unorm, 1, 1, 1, 1) },
|
||||
{ TextureFormat.R8Snorm, new FormatInfo(Format.R8Snorm, 1, 1, 1, 1) },
|
||||
{ TextureFormat.R8Uint, new FormatInfo(Format.R8Uint, 1, 1, 1, 1) },
|
||||
{ TextureFormat.R8Sint, new FormatInfo(Format.R8Sint, 1, 1, 1, 1) },
|
||||
{ TextureFormat.R16Float, new FormatInfo(Format.R16Float, 1, 1, 2, 1) },
|
||||
{ TextureFormat.R16Unorm, new FormatInfo(Format.R16Unorm, 1, 1, 2, 1) },
|
||||
{ TextureFormat.R16Snorm, new FormatInfo(Format.R16Snorm, 1, 1, 2, 1) },
|
||||
{ TextureFormat.R16Uint, new FormatInfo(Format.R16Uint, 1, 1, 2, 1) },
|
||||
{ TextureFormat.R16Sint, new FormatInfo(Format.R16Sint, 1, 1, 2, 1) },
|
||||
{ TextureFormat.R32Float, new FormatInfo(Format.R32Float, 1, 1, 4, 1) },
|
||||
{ TextureFormat.R32Uint, new FormatInfo(Format.R32Uint, 1, 1, 4, 1) },
|
||||
{ TextureFormat.R32Sint, new FormatInfo(Format.R32Sint, 1, 1, 4, 1) },
|
||||
{ TextureFormat.G8R8Unorm, new FormatInfo(Format.R8G8Unorm, 1, 1, 2, 2) },
|
||||
{ TextureFormat.G8R8Snorm, new FormatInfo(Format.R8G8Snorm, 1, 1, 2, 2) },
|
||||
{ TextureFormat.G8R8Uint, new FormatInfo(Format.R8G8Uint, 1, 1, 2, 2) },
|
||||
{ TextureFormat.G8R8Sint, new FormatInfo(Format.R8G8Sint, 1, 1, 2, 2) },
|
||||
{ TextureFormat.R16G16Float, new FormatInfo(Format.R16G16Float, 1, 1, 4, 2) },
|
||||
{ TextureFormat.R16G16Unorm, new FormatInfo(Format.R16G16Unorm, 1, 1, 4, 2) },
|
||||
{ TextureFormat.R16G16Snorm, new FormatInfo(Format.R16G16Snorm, 1, 1, 4, 2) },
|
||||
{ TextureFormat.R16G16Uint, new FormatInfo(Format.R16G16Uint, 1, 1, 4, 2) },
|
||||
{ TextureFormat.R16G16Sint, new FormatInfo(Format.R16G16Sint, 1, 1, 4, 2) },
|
||||
{ TextureFormat.R32G32Float, new FormatInfo(Format.R32G32Float, 1, 1, 8, 2) },
|
||||
{ TextureFormat.R32G32Uint, new FormatInfo(Format.R32G32Uint, 1, 1, 8, 2) },
|
||||
{ TextureFormat.R32G32Sint, new FormatInfo(Format.R32G32Sint, 1, 1, 8, 2) },
|
||||
{ TextureFormat.R32G32B32Float, new FormatInfo(Format.R32G32B32Float, 1, 1, 12, 3) },
|
||||
{ TextureFormat.R32G32B32Uint, new FormatInfo(Format.R32G32B32Uint, 1, 1, 12, 3) },
|
||||
{ TextureFormat.R32G32B32Sint, new FormatInfo(Format.R32G32B32Sint, 1, 1, 12, 3) },
|
||||
{ TextureFormat.A8B8G8R8Unorm, new FormatInfo(Format.R8G8B8A8Unorm, 1, 1, 4, 4) },
|
||||
{ TextureFormat.A8B8G8R8Snorm, new FormatInfo(Format.R8G8B8A8Snorm, 1, 1, 4, 4) },
|
||||
{ TextureFormat.A8B8G8R8Uint, new FormatInfo(Format.R8G8B8A8Uint, 1, 1, 4, 4) },
|
||||
{ TextureFormat.A8B8G8R8Sint, new FormatInfo(Format.R8G8B8A8Sint, 1, 1, 4, 4) },
|
||||
{ TextureFormat.R16G16B16A16Float, new FormatInfo(Format.R16G16B16A16Float, 1, 1, 8, 4) },
|
||||
{ TextureFormat.R16G16B16A16Unorm, new FormatInfo(Format.R16G16B16A16Unorm, 1, 1, 8, 4) },
|
||||
{ TextureFormat.R16G16B16A16Snorm, new FormatInfo(Format.R16G16B16A16Snorm, 1, 1, 8, 4) },
|
||||
{ TextureFormat.R16G16B16A16Uint, new FormatInfo(Format.R16G16B16A16Uint, 1, 1, 8, 4) },
|
||||
{ TextureFormat.R16G16B16A16Sint, new FormatInfo(Format.R16G16B16A16Sint, 1, 1, 8, 4) },
|
||||
{ TextureFormat.R32G32B32A32Float, new FormatInfo(Format.R32G32B32A32Float, 1, 1, 16, 4) },
|
||||
{ TextureFormat.R32G32B32A32Uint, new FormatInfo(Format.R32G32B32A32Uint, 1, 1, 16, 4) },
|
||||
{ TextureFormat.R32G32B32A32Sint, new FormatInfo(Format.R32G32B32A32Sint, 1, 1, 16, 4) },
|
||||
{ TextureFormat.Z16Unorm, new FormatInfo(Format.D16Unorm, 1, 1, 2, 1) },
|
||||
{ TextureFormat.Zf32RFloatGUintBUintAUint, new FormatInfo(Format.D32Float, 1, 1, 4, 1) },
|
||||
{ TextureFormat.Zf32Float, new FormatInfo(Format.D32Float, 1, 1, 4, 1) },
|
||||
{ TextureFormat.G24R8RUintGUnormBUnormAUnorm, new FormatInfo(Format.D24UnormS8Uint, 1, 1, 4, 2) },
|
||||
{ TextureFormat.Z24S8RUintGUnormBUnormAUnorm, new FormatInfo(Format.D24UnormS8Uint, 1, 1, 4, 2) },
|
||||
{ TextureFormat.Z24S8RUintGUnormBUintAUint, new FormatInfo(Format.D24UnormS8Uint, 1, 1, 4, 2) },
|
||||
{ TextureFormat.S8Z24RUnormGUintBUintAUint, new FormatInfo(Format.S8UintD24Unorm, 1, 1, 4, 2) },
|
||||
{ TextureFormat.R32B24G8RFloatGUintBUnormAUnorm, new FormatInfo(Format.D32FloatS8Uint, 1, 1, 8, 2) },
|
||||
{ TextureFormat.Zf32X24S8RFloatGUintBUnormAUnorm, new FormatInfo(Format.D32FloatS8Uint, 1, 1, 8, 2) },
|
||||
{ TextureFormat.A8B8G8R8UnormSrgb, new FormatInfo(Format.R8G8B8A8Srgb, 1, 1, 4, 4) },
|
||||
{ TextureFormat.G4R4Unorm, new FormatInfo(Format.R4G4Unorm, 1, 1, 1, 2) },
|
||||
{ TextureFormat.A4B4G4R4Unorm, new FormatInfo(Format.R4G4B4A4Unorm, 1, 1, 2, 4) },
|
||||
{ TextureFormat.A1B5G5R5Unorm, new FormatInfo(Format.R5G5B5A1Unorm, 1, 1, 2, 4) },
|
||||
{ TextureFormat.B5G6R5Unorm, new FormatInfo(Format.R5G6B5Unorm, 1, 1, 2, 3) },
|
||||
{ TextureFormat.A2B10G10R10Unorm, new FormatInfo(Format.R10G10B10A2Unorm, 1, 1, 4, 4) },
|
||||
{ TextureFormat.A2B10G10R10Uint, new FormatInfo(Format.R10G10B10A2Uint, 1, 1, 4, 4) },
|
||||
{ TextureFormat.Bf10Gf11Rf11Float, new FormatInfo(Format.R11G11B10Float, 1, 1, 4, 3) },
|
||||
{ TextureFormat.E5B9G9R9SharedExpFloat, new FormatInfo(Format.R9G9B9E5Float, 1, 1, 4, 4) },
|
||||
{ TextureFormat.Bc1Unorm, new FormatInfo(Format.Bc1RgbaUnorm, 4, 4, 8, 4) },
|
||||
{ TextureFormat.Bc2Unorm, new FormatInfo(Format.Bc2Unorm, 4, 4, 16, 4) },
|
||||
{ TextureFormat.Bc3Unorm, new FormatInfo(Format.Bc3Unorm, 4, 4, 16, 4) },
|
||||
{ TextureFormat.Bc1UnormSrgb, new FormatInfo(Format.Bc1RgbaSrgb, 4, 4, 8, 4) },
|
||||
{ TextureFormat.Bc2UnormSrgb, new FormatInfo(Format.Bc2Srgb, 4, 4, 16, 4) },
|
||||
{ TextureFormat.Bc3UnormSrgb, new FormatInfo(Format.Bc3Srgb, 4, 4, 16, 4) },
|
||||
{ TextureFormat.Bc4Unorm, new FormatInfo(Format.Bc4Unorm, 4, 4, 8, 1) },
|
||||
{ TextureFormat.Bc4Snorm, new FormatInfo(Format.Bc4Snorm, 4, 4, 8, 1) },
|
||||
{ TextureFormat.Bc5Unorm, new FormatInfo(Format.Bc5Unorm, 4, 4, 16, 2) },
|
||||
{ TextureFormat.Bc5Snorm, new FormatInfo(Format.Bc5Snorm, 4, 4, 16, 2) },
|
||||
{ TextureFormat.Bc7UUnorm, new FormatInfo(Format.Bc7Unorm, 4, 4, 16, 4) },
|
||||
{ TextureFormat.Bc7UUnormSrgb, new FormatInfo(Format.Bc7Srgb, 4, 4, 16, 4) },
|
||||
{ TextureFormat.Bc6HSf16Float, new FormatInfo(Format.Bc6HSfloat, 4, 4, 16, 4) },
|
||||
{ TextureFormat.Bc6HUf16Float, new FormatInfo(Format.Bc6HUfloat, 4, 4, 16, 4) },
|
||||
{ TextureFormat.Etc2RgbUnorm, new FormatInfo(Format.Etc2RgbUnorm, 4, 4, 8, 3) },
|
||||
{ TextureFormat.Etc2RgbaUnorm, new FormatInfo(Format.Etc2RgbaUnorm, 4, 4, 16, 4) },
|
||||
{ TextureFormat.Etc2RgbUnormSrgb, new FormatInfo(Format.Etc2RgbSrgb, 4, 4, 8, 3) },
|
||||
{ TextureFormat.Etc2RgbaUnormSrgb, new FormatInfo(Format.Etc2RgbaSrgb, 4, 4, 16, 4) },
|
||||
{ TextureFormat.Astc2D4x4Unorm, new FormatInfo(Format.Astc4x4Unorm, 4, 4, 16, 4) },
|
||||
{ TextureFormat.Astc2D5x4Unorm, new FormatInfo(Format.Astc5x4Unorm, 5, 4, 16, 4) },
|
||||
{ TextureFormat.Astc2D5x5Unorm, new FormatInfo(Format.Astc5x5Unorm, 5, 5, 16, 4) },
|
||||
{ TextureFormat.Astc2D6x5Unorm, new FormatInfo(Format.Astc6x5Unorm, 6, 5, 16, 4) },
|
||||
{ TextureFormat.Astc2D6x6Unorm, new FormatInfo(Format.Astc6x6Unorm, 6, 6, 16, 4) },
|
||||
{ TextureFormat.Astc2D8x5Unorm, new FormatInfo(Format.Astc8x5Unorm, 8, 5, 16, 4) },
|
||||
{ TextureFormat.Astc2D8x6Unorm, new FormatInfo(Format.Astc8x6Unorm, 8, 6, 16, 4) },
|
||||
{ TextureFormat.Astc2D8x8Unorm, new FormatInfo(Format.Astc8x8Unorm, 8, 8, 16, 4) },
|
||||
{ TextureFormat.Astc2D10x5Unorm, new FormatInfo(Format.Astc10x5Unorm, 10, 5, 16, 4) },
|
||||
{ TextureFormat.Astc2D10x6Unorm, new FormatInfo(Format.Astc10x6Unorm, 10, 6, 16, 4) },
|
||||
{ TextureFormat.Astc2D10x8Unorm, new FormatInfo(Format.Astc10x8Unorm, 10, 8, 16, 4) },
|
||||
{ TextureFormat.Astc2D10x10Unorm, new FormatInfo(Format.Astc10x10Unorm, 10, 10, 16, 4) },
|
||||
{ TextureFormat.Astc2D12x10Unorm, new FormatInfo(Format.Astc12x10Unorm, 12, 10, 16, 4) },
|
||||
{ TextureFormat.Astc2D12x12Unorm, new FormatInfo(Format.Astc12x12Unorm, 12, 12, 16, 4) },
|
||||
{ TextureFormat.Astc2D4x4UnormSrgb, new FormatInfo(Format.Astc4x4Srgb, 4, 4, 16, 4) },
|
||||
{ TextureFormat.Astc2D5x4UnormSrgb, new FormatInfo(Format.Astc5x4Srgb, 5, 4, 16, 4) },
|
||||
{ TextureFormat.Astc2D5x5UnormSrgb, new FormatInfo(Format.Astc5x5Srgb, 5, 5, 16, 4) },
|
||||
{ TextureFormat.Astc2D6x5UnormSrgb, new FormatInfo(Format.Astc6x5Srgb, 6, 5, 16, 4) },
|
||||
{ TextureFormat.Astc2D6x6UnormSrgb, new FormatInfo(Format.Astc6x6Srgb, 6, 6, 16, 4) },
|
||||
{ TextureFormat.Astc2D8x5UnormSrgb, new FormatInfo(Format.Astc8x5Srgb, 8, 5, 16, 4) },
|
||||
{ TextureFormat.Astc2D8x6UnormSrgb, new FormatInfo(Format.Astc8x6Srgb, 8, 6, 16, 4) },
|
||||
{ TextureFormat.Astc2D8x8UnormSrgb, new FormatInfo(Format.Astc8x8Srgb, 8, 8, 16, 4) },
|
||||
{ TextureFormat.Astc2D10x5UnormSrgb, new FormatInfo(Format.Astc10x5Srgb, 10, 5, 16, 4) },
|
||||
{ TextureFormat.Astc2D10x6UnormSrgb, new FormatInfo(Format.Astc10x6Srgb, 10, 6, 16, 4) },
|
||||
{ TextureFormat.Astc2D10x8UnormSrgb, new FormatInfo(Format.Astc10x8Srgb, 10, 8, 16, 4) },
|
||||
{ TextureFormat.Astc2D10x10UnormSrgb, new FormatInfo(Format.Astc10x10Srgb, 10, 10, 16, 4) },
|
||||
{ TextureFormat.Astc2D12x10UnormSrgb, new FormatInfo(Format.Astc12x10Srgb, 12, 10, 16, 4) },
|
||||
{ TextureFormat.Astc2D12x12UnormSrgb, new FormatInfo(Format.Astc12x12Srgb, 12, 12, 16, 4) },
|
||||
{ TextureFormat.A5B5G5R1Unorm, new FormatInfo(Format.A1B5G5R5Unorm, 1, 1, 2, 4) }
|
||||
};
|
||||
|
||||
private static Dictionary<ulong, Format> _attribFormats = new Dictionary<ulong, Format>()
|
||||
private static readonly Dictionary<VertexAttributeFormat, Format> _attribFormats = new Dictionary<VertexAttributeFormat, Format>()
|
||||
{
|
||||
{ 0x13a00000, Format.R8Unorm },
|
||||
{ 0x0ba00000, Format.R8Snorm },
|
||||
{ 0x23a00000, Format.R8Uint },
|
||||
{ 0x1ba00000, Format.R8Sint },
|
||||
{ 0x3b600000, Format.R16Float },
|
||||
{ 0x13600000, Format.R16Unorm },
|
||||
{ 0x0b600000, Format.R16Snorm },
|
||||
{ 0x23600000, Format.R16Uint },
|
||||
{ 0x1b600000, Format.R16Sint },
|
||||
{ 0x3a400000, Format.R32Float },
|
||||
{ 0x22400000, Format.R32Uint },
|
||||
{ 0x1a400000, Format.R32Sint },
|
||||
{ 0x13000000, Format.R8G8Unorm },
|
||||
{ 0x0b000000, Format.R8G8Snorm },
|
||||
{ 0x23000000, Format.R8G8Uint },
|
||||
{ 0x1b000000, Format.R8G8Sint },
|
||||
{ 0x39e00000, Format.R16G16Float },
|
||||
{ 0x11e00000, Format.R16G16Unorm },
|
||||
{ 0x09e00000, Format.R16G16Snorm },
|
||||
{ 0x21e00000, Format.R16G16Uint },
|
||||
{ 0x19e00000, Format.R16G16Sint },
|
||||
{ 0x38800000, Format.R32G32Float },
|
||||
{ 0x20800000, Format.R32G32Uint },
|
||||
{ 0x18800000, Format.R32G32Sint },
|
||||
{ 0x12600000, Format.R8G8B8Unorm },
|
||||
{ 0x0a600000, Format.R8G8B8Snorm },
|
||||
{ 0x22600000, Format.R8G8B8Uint },
|
||||
{ 0x1a600000, Format.R8G8B8Sint },
|
||||
{ 0x38a00000, Format.R16G16B16Float },
|
||||
{ 0x10a00000, Format.R16G16B16Unorm },
|
||||
{ 0x08a00000, Format.R16G16B16Snorm },
|
||||
{ 0x20a00000, Format.R16G16B16Uint },
|
||||
{ 0x18a00000, Format.R16G16B16Sint },
|
||||
{ 0x38400000, Format.R32G32B32Float },
|
||||
{ 0x20400000, Format.R32G32B32Uint },
|
||||
{ 0x18400000, Format.R32G32B32Sint },
|
||||
{ 0x11400000, Format.R8G8B8A8Unorm },
|
||||
{ 0x09400000, Format.R8G8B8A8Snorm },
|
||||
{ 0x21400000, Format.R8G8B8A8Uint },
|
||||
{ 0x19400000, Format.R8G8B8A8Sint },
|
||||
{ 0x38600000, Format.R16G16B16A16Float },
|
||||
{ 0x10600000, Format.R16G16B16A16Unorm },
|
||||
{ 0x08600000, Format.R16G16B16A16Snorm },
|
||||
{ 0x20600000, Format.R16G16B16A16Uint },
|
||||
{ 0x18600000, Format.R16G16B16A16Sint },
|
||||
{ 0x38200000, Format.R32G32B32A32Float },
|
||||
{ 0x20200000, Format.R32G32B32A32Uint },
|
||||
{ 0x18200000, Format.R32G32B32A32Sint },
|
||||
{ 0x16000000, Format.R10G10B10A2Unorm },
|
||||
{ 0x26000000, Format.R10G10B10A2Uint },
|
||||
{ 0x3e200000, Format.R11G11B10Float },
|
||||
{ 0x2ba00000, Format.R8Uscaled },
|
||||
{ 0x33a00000, Format.R8Sscaled },
|
||||
{ 0x2b600000, Format.R16Uscaled },
|
||||
{ 0x33600000, Format.R16Sscaled },
|
||||
{ 0x2a400000, Format.R32Uscaled },
|
||||
{ 0x32400000, Format.R32Sscaled },
|
||||
{ 0x2b000000, Format.R8G8Uscaled },
|
||||
{ 0x33000000, Format.R8G8Sscaled },
|
||||
{ 0x29e00000, Format.R16G16Uscaled },
|
||||
{ 0x31e00000, Format.R16G16Sscaled },
|
||||
{ 0x28800000, Format.R32G32Uscaled },
|
||||
{ 0x30800000, Format.R32G32Sscaled },
|
||||
{ 0x2a600000, Format.R8G8B8Uscaled },
|
||||
{ 0x32600000, Format.R8G8B8Sscaled },
|
||||
{ 0x28a00000, Format.R16G16B16Uscaled },
|
||||
{ 0x30a00000, Format.R16G16B16Sscaled },
|
||||
{ 0x28400000, Format.R32G32B32Uscaled },
|
||||
{ 0x30400000, Format.R32G32B32Sscaled },
|
||||
{ 0x29400000, Format.R8G8B8A8Uscaled },
|
||||
{ 0x31400000, Format.R8G8B8A8Sscaled },
|
||||
{ 0x28600000, Format.R16G16B16A16Uscaled },
|
||||
{ 0x30600000, Format.R16G16B16A16Sscaled },
|
||||
{ 0x28200000, Format.R32G32B32A32Uscaled },
|
||||
{ 0x30200000, Format.R32G32B32A32Sscaled },
|
||||
{ 0x0e000000, Format.R10G10B10A2Snorm },
|
||||
{ 0x1e000000, Format.R10G10B10A2Sint },
|
||||
{ 0x2e000000, Format.R10G10B10A2Uscaled },
|
||||
{ 0x36000000, Format.R10G10B10A2Sscaled }
|
||||
{ VertexAttributeFormat.R8Unorm, Format.R8Unorm },
|
||||
{ VertexAttributeFormat.R8Snorm, Format.R8Snorm },
|
||||
{ VertexAttributeFormat.R8Uint, Format.R8Uint },
|
||||
{ VertexAttributeFormat.R8Sint, Format.R8Sint },
|
||||
{ VertexAttributeFormat.R16Float, Format.R16Float },
|
||||
{ VertexAttributeFormat.R16Unorm, Format.R16Unorm },
|
||||
{ VertexAttributeFormat.R16Snorm, Format.R16Snorm },
|
||||
{ VertexAttributeFormat.R16Uint, Format.R16Uint },
|
||||
{ VertexAttributeFormat.R16Sint, Format.R16Sint },
|
||||
{ VertexAttributeFormat.R32Float, Format.R32Float },
|
||||
{ VertexAttributeFormat.R32Uint, Format.R32Uint },
|
||||
{ VertexAttributeFormat.R32Sint, Format.R32Sint },
|
||||
{ VertexAttributeFormat.R8G8Unorm, Format.R8G8Unorm },
|
||||
{ VertexAttributeFormat.R8G8Snorm, Format.R8G8Snorm },
|
||||
{ VertexAttributeFormat.R8G8Uint, Format.R8G8Uint },
|
||||
{ VertexAttributeFormat.R8G8Sint, Format.R8G8Sint },
|
||||
{ VertexAttributeFormat.R16G16Float, Format.R16G16Float },
|
||||
{ VertexAttributeFormat.R16G16Unorm, Format.R16G16Unorm },
|
||||
{ VertexAttributeFormat.R16G16Snorm, Format.R16G16Snorm },
|
||||
{ VertexAttributeFormat.R16G16Uint, Format.R16G16Uint },
|
||||
{ VertexAttributeFormat.R16G16Sint, Format.R16G16Sint },
|
||||
{ VertexAttributeFormat.R32G32Float, Format.R32G32Float },
|
||||
{ VertexAttributeFormat.R32G32Uint, Format.R32G32Uint },
|
||||
{ VertexAttributeFormat.R32G32Sint, Format.R32G32Sint },
|
||||
{ VertexAttributeFormat.R8G8B8Unorm, Format.R8G8B8Unorm },
|
||||
{ VertexAttributeFormat.R8G8B8Snorm, Format.R8G8B8Snorm },
|
||||
{ VertexAttributeFormat.R8G8B8Uint, Format.R8G8B8Uint },
|
||||
{ VertexAttributeFormat.R8G8B8Sint, Format.R8G8B8Sint },
|
||||
{ VertexAttributeFormat.R16G16B16Float, Format.R16G16B16Float },
|
||||
{ VertexAttributeFormat.R16G16B16Unorm, Format.R16G16B16Unorm },
|
||||
{ VertexAttributeFormat.R16G16B16Snorm, Format.R16G16B16Snorm },
|
||||
{ VertexAttributeFormat.R16G16B16Uint, Format.R16G16B16Uint },
|
||||
{ VertexAttributeFormat.R16G16B16Sint, Format.R16G16B16Sint },
|
||||
{ VertexAttributeFormat.R32G32B32Float, Format.R32G32B32Float },
|
||||
{ VertexAttributeFormat.R32G32B32Uint, Format.R32G32B32Uint },
|
||||
{ VertexAttributeFormat.R32G32B32Sint, Format.R32G32B32Sint },
|
||||
{ VertexAttributeFormat.R8G8B8A8Unorm, Format.R8G8B8A8Unorm },
|
||||
{ VertexAttributeFormat.R8G8B8A8Snorm, Format.R8G8B8A8Snorm },
|
||||
{ VertexAttributeFormat.R8G8B8A8Uint, Format.R8G8B8A8Uint },
|
||||
{ VertexAttributeFormat.R8G8B8A8Sint, Format.R8G8B8A8Sint },
|
||||
{ VertexAttributeFormat.R16G16B16A16Float, Format.R16G16B16A16Float },
|
||||
{ VertexAttributeFormat.R16G16B16A16Unorm, Format.R16G16B16A16Unorm },
|
||||
{ VertexAttributeFormat.R16G16B16A16Snorm, Format.R16G16B16A16Snorm },
|
||||
{ VertexAttributeFormat.R16G16B16A16Uint, Format.R16G16B16A16Uint },
|
||||
{ VertexAttributeFormat.R16G16B16A16Sint, Format.R16G16B16A16Sint },
|
||||
{ VertexAttributeFormat.R32G32B32A32Float, Format.R32G32B32A32Float },
|
||||
{ VertexAttributeFormat.R32G32B32A32Uint, Format.R32G32B32A32Uint },
|
||||
{ VertexAttributeFormat.R32G32B32A32Sint, Format.R32G32B32A32Sint },
|
||||
{ VertexAttributeFormat.A2B10G10R10Unorm, Format.R10G10B10A2Unorm },
|
||||
{ VertexAttributeFormat.A2B10G10R10Uint, Format.R10G10B10A2Uint },
|
||||
{ VertexAttributeFormat.B10G11R11Float, Format.R11G11B10Float },
|
||||
{ VertexAttributeFormat.R8Uscaled, Format.R8Uscaled },
|
||||
{ VertexAttributeFormat.R8Sscaled, Format.R8Sscaled },
|
||||
{ VertexAttributeFormat.R16Uscaled, Format.R16Uscaled },
|
||||
{ VertexAttributeFormat.R16Sscaled, Format.R16Sscaled },
|
||||
{ VertexAttributeFormat.R32Uscaled, Format.R32Uscaled },
|
||||
{ VertexAttributeFormat.R32Sscaled, Format.R32Sscaled },
|
||||
{ VertexAttributeFormat.R8G8Uscaled, Format.R8G8Uscaled },
|
||||
{ VertexAttributeFormat.R8G8Sscaled, Format.R8G8Sscaled },
|
||||
{ VertexAttributeFormat.R16G16Uscaled, Format.R16G16Uscaled },
|
||||
{ VertexAttributeFormat.R16G16Sscaled, Format.R16G16Sscaled },
|
||||
{ VertexAttributeFormat.R32G32Uscaled, Format.R32G32Uscaled },
|
||||
{ VertexAttributeFormat.R32G32Sscaled, Format.R32G32Sscaled },
|
||||
{ VertexAttributeFormat.R8G8B8Uscaled, Format.R8G8B8Uscaled },
|
||||
{ VertexAttributeFormat.R8G8B8Sscaled, Format.R8G8B8Sscaled },
|
||||
{ VertexAttributeFormat.R16G16B16Uscaled, Format.R16G16B16Uscaled },
|
||||
{ VertexAttributeFormat.R16G16B16Sscaled, Format.R16G16B16Sscaled },
|
||||
{ VertexAttributeFormat.R32G32B32Uscaled, Format.R32G32B32Uscaled },
|
||||
{ VertexAttributeFormat.R32G32B32Sscaled, Format.R32G32B32Sscaled },
|
||||
{ VertexAttributeFormat.R8G8B8A8Uscaled, Format.R8G8B8A8Uscaled },
|
||||
{ VertexAttributeFormat.R8G8B8A8Sscaled, Format.R8G8B8A8Sscaled },
|
||||
{ VertexAttributeFormat.R16G16B16A16Uscaled, Format.R16G16B16A16Uscaled },
|
||||
{ VertexAttributeFormat.R16G16B16A16Sscaled, Format.R16G16B16A16Sscaled },
|
||||
{ VertexAttributeFormat.R32G32B32A32Uscaled, Format.R32G32B32A32Uscaled },
|
||||
{ VertexAttributeFormat.R32G32B32A32Sscaled, Format.R32G32B32A32Sscaled },
|
||||
{ VertexAttributeFormat.A2B10G10R10Snorm, Format.R10G10B10A2Snorm },
|
||||
{ VertexAttributeFormat.A2B10G10R10Sint, Format.R10G10B10A2Sint },
|
||||
{ VertexAttributeFormat.A2B10G10R10Uscaled, Format.R10G10B10A2Uscaled },
|
||||
{ VertexAttributeFormat.A2B10G10R10Sscaled, Format.R10G10B10A2Sscaled }
|
||||
};
|
||||
|
||||
/// <summary>
|
||||
@@ -210,7 +557,7 @@ namespace Ryujinx.Graphics.Gpu.Image
|
||||
{
|
||||
encoded |= (isSrgb ? 1u << 19 : 0u);
|
||||
|
||||
return _textureFormats.TryGetValue(encoded, out format);
|
||||
return _textureFormats.TryGetValue((TextureFormat)encoded, out format);
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
@@ -221,7 +568,7 @@ namespace Ryujinx.Graphics.Gpu.Image
|
||||
/// <returns>True if the format is valid, false otherwise</returns>
|
||||
public static bool TryGetAttribFormat(uint encoded, out Format format)
|
||||
{
|
||||
return _attribFormats.TryGetValue(encoded, out format);
|
||||
return _attribFormats.TryGetValue((VertexAttributeFormat)encoded, out format);
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -47,6 +47,7 @@ namespace Ryujinx.Graphics.Gpu.Image
|
||||
|
||||
public int TextureHandle;
|
||||
public int SamplerHandle;
|
||||
public Format ImageFormat;
|
||||
public int InvalidatedSequence;
|
||||
public Texture CachedTexture;
|
||||
public Sampler CachedSampler;
|
||||
@@ -564,6 +565,9 @@ namespace Ryujinx.Graphics.Gpu.Image
|
||||
// Buffers are frequently re-created to accomodate larger data, so we need to re-bind
|
||||
// to ensure we're not using a old buffer that was already deleted.
|
||||
_channel.BufferManager.SetBufferTextureStorage(stage, hostTexture, texture.Range.GetSubRange(0).Address, texture.Size, bindingInfo, bindingInfo.Format, false);
|
||||
|
||||
// Cache is not used for buffer texture, it must always rebind.
|
||||
state.CachedTexture = null;
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -659,14 +663,16 @@ namespace Ryujinx.Graphics.Gpu.Image
|
||||
cachedTexture?.SignalModified();
|
||||
}
|
||||
|
||||
if ((usageFlags & TextureUsageFlags.NeedsScaleValue) != 0 &&
|
||||
UpdateScale(state.CachedTexture, usageFlags, scaleIndex, stage))
|
||||
Format format = bindingInfo.Format == 0 ? cachedTexture.Format : bindingInfo.Format;
|
||||
|
||||
if (state.ImageFormat != format ||
|
||||
((usageFlags & TextureUsageFlags.NeedsScaleValue) != 0 &&
|
||||
UpdateScale(state.CachedTexture, usageFlags, scaleIndex, stage)))
|
||||
{
|
||||
ITexture hostTextureRebind = state.CachedTexture.GetTargetTexture(bindingInfo.Target);
|
||||
|
||||
Format format = bindingInfo.Format == 0 ? cachedTexture.Format : bindingInfo.Format;
|
||||
|
||||
state.Texture = hostTextureRebind;
|
||||
state.ImageFormat = format;
|
||||
|
||||
_context.Renderer.Pipeline.SetImage(bindingInfo.Binding, hostTextureRebind, format);
|
||||
}
|
||||
@@ -696,6 +702,9 @@ namespace Ryujinx.Graphics.Gpu.Image
|
||||
}
|
||||
|
||||
_channel.BufferManager.SetBufferTextureStorage(stage, hostTexture, texture.Range.GetSubRange(0).Address, texture.Size, bindingInfo, format, true);
|
||||
|
||||
// Cache is not used for buffer texture, it must always rebind.
|
||||
state.CachedTexture = null;
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -721,6 +730,8 @@ namespace Ryujinx.Graphics.Gpu.Image
|
||||
format = texture.Format;
|
||||
}
|
||||
|
||||
state.ImageFormat = format;
|
||||
|
||||
_context.Renderer.Pipeline.SetImage(bindingInfo.Binding, hostTexture, format);
|
||||
}
|
||||
|
||||
|
||||
@@ -22,7 +22,7 @@ namespace Ryujinx.Graphics.Gpu.Shader.DiskCache
|
||||
private const ushort FileFormatVersionMajor = 1;
|
||||
private const ushort FileFormatVersionMinor = 2;
|
||||
private const uint FileFormatVersionPacked = ((uint)FileFormatVersionMajor << 16) | FileFormatVersionMinor;
|
||||
private const uint CodeGenVersion = 3525;
|
||||
private const uint CodeGenVersion = 3697;
|
||||
|
||||
private const string SharedTocFileName = "shared.toc";
|
||||
private const string SharedDataFileName = "shared.data";
|
||||
@@ -827,4 +827,4 @@ namespace Ryujinx.Graphics.Gpu.Shader.DiskCache
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -134,6 +134,8 @@ namespace Ryujinx.Graphics.Gpu.Shader
|
||||
|
||||
public bool QueryHostSupportsTextureShadowLod() => _context.Capabilities.SupportsTextureShadowLod;
|
||||
|
||||
public bool QueryHostSupportsViewportIndex() => _context.Capabilities.SupportsViewportIndex;
|
||||
|
||||
/// <summary>
|
||||
/// Converts a packed Maxwell texture format to the shader translator texture format.
|
||||
/// </summary>
|
||||
|
||||
@@ -120,6 +120,7 @@ namespace Ryujinx.Graphics.OpenGL
|
||||
supportsNonConstantTextureOffset: HwCapabilities.SupportsNonConstantTextureOffset,
|
||||
supportsShaderBallot: HwCapabilities.SupportsShaderBallot,
|
||||
supportsTextureShadowLod: HwCapabilities.SupportsTextureShadowLod,
|
||||
supportsViewportIndex: true,
|
||||
supportsViewportSwizzle: HwCapabilities.SupportsViewportSwizzle,
|
||||
supportsIndirectParameters: HwCapabilities.SupportsIndirectParameters,
|
||||
maximumUniformBuffersPerStage: 13, // TODO: Avoid hardcoding those limits here and get from driver?
|
||||
|
||||
@@ -267,6 +267,15 @@ namespace Ryujinx.Graphics.Shader
|
||||
return true;
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// Queries host GPU shader viewport index output support.
|
||||
/// </summary>
|
||||
/// <returns>True if the GPU and driver supports shader viewport index output, false otherwise</returns>
|
||||
bool QueryHostSupportsViewportIndex()
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// Queries the point size from the GPU state, used when it is not explicitly set on the shader.
|
||||
/// </summary>
|
||||
|
||||
@@ -16,7 +16,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
||||
{ 0b0111, 0b1011, 0b1101, 0b1110, 0b1111, 0b0000, 0b0000, 0b0000 }
|
||||
};
|
||||
|
||||
private const bool Sample1DAs2D = true;
|
||||
public const bool Sample1DAs2D = true;
|
||||
|
||||
private enum TexsType
|
||||
{
|
||||
|
||||
@@ -180,6 +180,18 @@ namespace Ryujinx.Graphics.Shader.IntermediateRepresentation
|
||||
_sources[index] = source;
|
||||
}
|
||||
|
||||
public void InsertSource(int index, Operand source)
|
||||
{
|
||||
Operand[] newSources = new Operand[_sources.Length + 1];
|
||||
|
||||
Array.Copy(_sources, 0, newSources, 0, index);
|
||||
Array.Copy(_sources, index, newSources, index + 1, _sources.Length - index);
|
||||
|
||||
newSources[index] = source;
|
||||
|
||||
_sources = newSources;
|
||||
}
|
||||
|
||||
protected void RemoveSource(int index)
|
||||
{
|
||||
SetSource(index, null);
|
||||
|
||||
@@ -60,5 +60,10 @@ namespace Ryujinx.Graphics.Shader.IntermediateRepresentation
|
||||
CbufSlot = cbufSlot;
|
||||
Handle = handle;
|
||||
}
|
||||
|
||||
public void SetLodLevelFlag()
|
||||
{
|
||||
Flags |= TextureFlags.LodLevel;
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -78,6 +78,11 @@ namespace Ryujinx.Graphics.Shader.Translation
|
||||
|
||||
public static bool Validate(ShaderConfig config, int value, bool isOutAttr)
|
||||
{
|
||||
if (value == AttributeConsts.ViewportIndex && !config.GpuAccessor.QueryHostSupportsViewportIndex())
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
return From(config, value, isOutAttr).IsValid;
|
||||
}
|
||||
|
||||
|
||||
@@ -1,4 +1,5 @@
|
||||
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
|
||||
using Ryujinx.Graphics.Shader.Instructions;
|
||||
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
|
||||
using System.Collections.Generic;
|
||||
|
||||
namespace Ryujinx.Graphics.Shader.Translation.Optimizations
|
||||
@@ -30,11 +31,19 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations
|
||||
texOp.Inst == Instruction.TextureSize)
|
||||
{
|
||||
Operand bindlessHandle = Utils.FindLastOperation(texOp.GetSource(0), block);
|
||||
bool rewriteSamplerType = texOp.Inst == Instruction.TextureSize;
|
||||
|
||||
// Some instructions do not encode an accurate sampler type:
|
||||
// - Most instructions uses the same type for 1D and Buffer.
|
||||
// - Query instructions may not have any type.
|
||||
// For those cases, we need to try getting the type from current GPU state,
|
||||
// as long bindless elimination is successful and we know where the texture descriptor is located.
|
||||
bool rewriteSamplerType =
|
||||
texOp.Type == SamplerType.TextureBuffer ||
|
||||
texOp.Inst == Instruction.TextureSize;
|
||||
|
||||
if (bindlessHandle.Type == OperandType.ConstantBuffer)
|
||||
{
|
||||
SetHandle(config, texOp, bindlessHandle.GetCbufOffset(), bindlessHandle.GetCbufSlot(), rewriteSamplerType);
|
||||
SetHandle(config, texOp, bindlessHandle.GetCbufOffset(), bindlessHandle.GetCbufSlot(), rewriteSamplerType, isImage: false);
|
||||
continue;
|
||||
}
|
||||
|
||||
@@ -137,7 +146,8 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations
|
||||
texOp,
|
||||
TextureHandle.PackOffsets(src0.GetCbufOffset(), ((src1.Value >> 20) & 0xfff), handleType),
|
||||
TextureHandle.PackSlots(src0.GetCbufSlot(), 0),
|
||||
rewriteSamplerType);
|
||||
rewriteSamplerType,
|
||||
isImage: false);
|
||||
}
|
||||
else if (src1.Type == OperandType.ConstantBuffer)
|
||||
{
|
||||
@@ -146,7 +156,8 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations
|
||||
texOp,
|
||||
TextureHandle.PackOffsets(src0.GetCbufOffset(), src1.GetCbufOffset(), handleType),
|
||||
TextureHandle.PackSlots(src0.GetCbufSlot(), src1.GetCbufSlot()),
|
||||
rewriteSamplerType);
|
||||
rewriteSamplerType,
|
||||
isImage: false);
|
||||
}
|
||||
}
|
||||
else if (texOp.Inst == Instruction.ImageLoad ||
|
||||
@@ -172,7 +183,9 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations
|
||||
}
|
||||
}
|
||||
|
||||
SetHandle(config, texOp, cbufOffset, cbufSlot, false);
|
||||
bool rewriteSamplerType = texOp.Type == SamplerType.TextureBuffer;
|
||||
|
||||
SetHandle(config, texOp, cbufOffset, cbufSlot, rewriteSamplerType, isImage: true);
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -209,13 +222,39 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations
|
||||
return null;
|
||||
}
|
||||
|
||||
private static void SetHandle(ShaderConfig config, TextureOperation texOp, int cbufOffset, int cbufSlot, bool rewriteSamplerType)
|
||||
private static void SetHandle(ShaderConfig config, TextureOperation texOp, int cbufOffset, int cbufSlot, bool rewriteSamplerType, bool isImage)
|
||||
{
|
||||
texOp.SetHandle(cbufOffset, cbufSlot);
|
||||
|
||||
if (rewriteSamplerType)
|
||||
{
|
||||
texOp.Type = config.GpuAccessor.QuerySamplerType(cbufOffset, cbufSlot);
|
||||
SamplerType newType = config.GpuAccessor.QuerySamplerType(cbufOffset, cbufSlot);
|
||||
|
||||
if (texOp.Inst.IsTextureQuery())
|
||||
{
|
||||
texOp.Type = newType;
|
||||
}
|
||||
else if (texOp.Type == SamplerType.TextureBuffer && newType == SamplerType.Texture1D)
|
||||
{
|
||||
int coordsCount = 1;
|
||||
|
||||
if (InstEmit.Sample1DAs2D)
|
||||
{
|
||||
newType = SamplerType.Texture2D;
|
||||
texOp.InsertSource(coordsCount++, OperandHelper.Const(0));
|
||||
}
|
||||
|
||||
if (!isImage &&
|
||||
(texOp.Flags & TextureFlags.IntCoords) != 0 &&
|
||||
(texOp.Flags & TextureFlags.LodLevel) == 0)
|
||||
{
|
||||
// IntCoords textures must always have explicit LOD.
|
||||
texOp.SetLodLevelFlag();
|
||||
texOp.InsertSource(coordsCount, OperandHelper.Const(0));
|
||||
}
|
||||
|
||||
texOp.Type = newType;
|
||||
}
|
||||
}
|
||||
|
||||
config.SetUsedTexture(texOp.Inst, texOp.Type, texOp.Format, texOp.Flags, cbufSlot, cbufOffset);
|
||||
|
||||
@@ -153,6 +153,10 @@ namespace Ryujinx.Graphics.Shader.Translation.Optimizations
|
||||
EvaluateFPUnary(operation, (x) => float.IsNaN(x));
|
||||
break;
|
||||
|
||||
case Instruction.LoadConstant:
|
||||
operation.TurnIntoCopy(Cbuf(operation.GetSource(0).Value, operation.GetSource(1).Value));
|
||||
break;
|
||||
|
||||
case Instruction.Maximum:
|
||||
EvaluateBinary(operation, (x, y) => Math.Max(x, y));
|
||||
break;
|
||||
|
||||
@@ -27,7 +27,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
private readonly Auto<MemoryAllocation> _allocationAuto;
|
||||
private readonly ulong _bufferHandle;
|
||||
|
||||
private CacheByRange<BufferHolder> _cachedConvertedIndexBuffers;
|
||||
private CacheByRange<BufferHolder> _cachedConvertedBuffers;
|
||||
|
||||
public int Size { get; }
|
||||
|
||||
@@ -109,7 +109,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
{
|
||||
if (isWrite)
|
||||
{
|
||||
_cachedConvertedIndexBuffers.Clear();
|
||||
_cachedConvertedBuffers.Clear();
|
||||
}
|
||||
|
||||
return _buffer;
|
||||
@@ -364,13 +364,35 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
|
||||
public Auto<DisposableBuffer> GetBufferI8ToI16(CommandBufferScoped cbs, int offset, int size)
|
||||
{
|
||||
if (!_cachedConvertedIndexBuffers.TryGetValue(offset, size, out var holder))
|
||||
var key = new I8ToI16CacheKey();
|
||||
|
||||
if (!_cachedConvertedBuffers.TryGetValue(offset, size, key, out var holder))
|
||||
{
|
||||
holder = _gd.BufferManager.Create(_gd, (size * 2 + 3) & ~3);
|
||||
|
||||
_gd.HelperShader.ConvertI8ToI16(_gd, cbs, this, holder, offset, size);
|
||||
|
||||
_cachedConvertedIndexBuffers.Add(offset, size, holder);
|
||||
_cachedConvertedBuffers.Add(offset, size, key, holder);
|
||||
}
|
||||
|
||||
return holder.GetBuffer();
|
||||
}
|
||||
|
||||
public Auto<DisposableBuffer> GetAlignedVertexBuffer(CommandBufferScoped cbs, int offset, int size, int stride, int alignment)
|
||||
{
|
||||
var key = new AlignedVertexBufferCacheKey(_gd, stride, alignment);
|
||||
|
||||
if (!_cachedConvertedBuffers.TryGetValue(offset, size, key, out var holder))
|
||||
{
|
||||
int alignedStride = (stride + (alignment - 1)) & -alignment;
|
||||
|
||||
holder = _gd.BufferManager.Create(_gd, (size / stride) * alignedStride);
|
||||
|
||||
_gd.HelperShader.ChangeStride(_gd, cbs, this, holder, offset, size, stride, alignedStride);
|
||||
|
||||
key.SetBuffer(holder.GetBuffer());
|
||||
|
||||
_cachedConvertedBuffers.Add(offset, size, key, holder);
|
||||
}
|
||||
|
||||
return holder.GetBuffer();
|
||||
@@ -382,7 +404,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
|
||||
_buffer.Dispose();
|
||||
_allocationAuto.Dispose();
|
||||
_cachedConvertedIndexBuffers.Dispose();
|
||||
_cachedConvertedBuffers.Dispose();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -130,6 +130,16 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
return null;
|
||||
}
|
||||
|
||||
public Auto<DisposableBuffer> GetAlignedVertexBuffer(CommandBufferScoped cbs, BufferHandle handle, int offset, int size, int stride, int alignment)
|
||||
{
|
||||
if (TryGetBuffer(handle, out var holder))
|
||||
{
|
||||
return holder.GetAlignedVertexBuffer(cbs, offset, size, stride, alignment);
|
||||
}
|
||||
|
||||
return null;
|
||||
}
|
||||
|
||||
public Auto<DisposableBuffer> GetBuffer(CommandBuffer commandBuffer, BufferHandle handle, bool isWrite, out int size)
|
||||
{
|
||||
if (TryGetBuffer(handle, out var holder))
|
||||
|
||||
@@ -7,28 +7,28 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
{
|
||||
public static BufferState Null => new BufferState(null, 0, 0);
|
||||
|
||||
private readonly Auto<DisposableBuffer> _buffer;
|
||||
private readonly int _offset;
|
||||
private readonly int _size;
|
||||
private readonly ulong _stride;
|
||||
private readonly IndexType _type;
|
||||
|
||||
private readonly Auto<DisposableBuffer> _buffer;
|
||||
|
||||
public BufferState(Auto<DisposableBuffer> buffer, int offset, int size, IndexType type)
|
||||
{
|
||||
_buffer = buffer;
|
||||
|
||||
_offset = offset;
|
||||
_size = size;
|
||||
_stride = 0;
|
||||
_type = type;
|
||||
buffer?.IncrementReferenceCount();
|
||||
}
|
||||
|
||||
public BufferState(Auto<DisposableBuffer> buffer, int offset, int size, ulong stride = 0UL)
|
||||
public BufferState(Auto<DisposableBuffer> buffer, int offset, int size)
|
||||
{
|
||||
_buffer = buffer;
|
||||
|
||||
_offset = offset;
|
||||
_size = size;
|
||||
_stride = stride;
|
||||
_type = IndexType.Uint16;
|
||||
buffer?.IncrementReferenceCount();
|
||||
}
|
||||
@@ -51,30 +51,6 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
}
|
||||
}
|
||||
|
||||
public void BindVertexBuffer(VulkanRenderer gd, CommandBufferScoped cbs, uint binding)
|
||||
{
|
||||
if (_buffer != null)
|
||||
{
|
||||
var buffer = _buffer.Get(cbs, _offset, _size).Value;
|
||||
|
||||
if (gd.Capabilities.SupportsExtendedDynamicState)
|
||||
{
|
||||
gd.ExtendedDynamicStateApi.CmdBindVertexBuffers2(
|
||||
cbs.CommandBuffer,
|
||||
binding,
|
||||
1,
|
||||
buffer,
|
||||
(ulong)_offset,
|
||||
(ulong)_size,
|
||||
_stride);
|
||||
}
|
||||
else
|
||||
{
|
||||
gd.Api.CmdBindVertexBuffers(cbs.CommandBuffer, binding, 1, buffer, (ulong)_offset);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
public void Dispose()
|
||||
{
|
||||
_buffer?.DecrementReferenceCount();
|
||||
|
||||
@@ -3,29 +3,110 @@ using System.Collections.Generic;
|
||||
|
||||
namespace Ryujinx.Graphics.Vulkan
|
||||
{
|
||||
struct CacheByRange<T> where T : IDisposable
|
||||
interface ICacheKey : IDisposable
|
||||
{
|
||||
private Dictionary<ulong, T> _ranges;
|
||||
bool KeyEqual(ICacheKey other);
|
||||
}
|
||||
|
||||
public void Add(int offset, int size, T value)
|
||||
struct I8ToI16CacheKey : ICacheKey
|
||||
{
|
||||
public I8ToI16CacheKey() { }
|
||||
|
||||
public bool KeyEqual(ICacheKey other)
|
||||
{
|
||||
EnsureInitialized();
|
||||
_ranges.Add(PackRange(offset, size), value);
|
||||
return other is I8ToI16CacheKey;
|
||||
}
|
||||
|
||||
public bool TryGetValue(int offset, int size, out T value)
|
||||
public void Dispose() { }
|
||||
}
|
||||
|
||||
struct AlignedVertexBufferCacheKey : ICacheKey
|
||||
{
|
||||
private readonly int _stride;
|
||||
private readonly int _alignment;
|
||||
|
||||
// Used to notify the pipeline that bindings have invalidated on dispose.
|
||||
private readonly VulkanRenderer _gd;
|
||||
private Auto<DisposableBuffer> _buffer;
|
||||
|
||||
public AlignedVertexBufferCacheKey(VulkanRenderer gd, int stride, int alignment)
|
||||
{
|
||||
EnsureInitialized();
|
||||
return _ranges.TryGetValue(PackRange(offset, size), out value);
|
||||
_gd = gd;
|
||||
_stride = stride;
|
||||
_alignment = alignment;
|
||||
_buffer = null;
|
||||
}
|
||||
|
||||
public bool KeyEqual(ICacheKey other)
|
||||
{
|
||||
return other is AlignedVertexBufferCacheKey entry &&
|
||||
entry._stride == _stride &&
|
||||
entry._alignment == _alignment;
|
||||
}
|
||||
|
||||
public void SetBuffer(Auto<DisposableBuffer> buffer)
|
||||
{
|
||||
_buffer = buffer;
|
||||
}
|
||||
|
||||
public void Dispose()
|
||||
{
|
||||
_gd.PipelineInternal.DirtyVertexBuffer(_buffer);
|
||||
}
|
||||
}
|
||||
|
||||
struct CacheByRange<T> where T : IDisposable
|
||||
{
|
||||
private struct Entry
|
||||
{
|
||||
public ICacheKey Key;
|
||||
public T Value;
|
||||
|
||||
public Entry(ICacheKey key, T value)
|
||||
{
|
||||
Key = key;
|
||||
Value = value;
|
||||
}
|
||||
}
|
||||
|
||||
private Dictionary<ulong, List<Entry>> _ranges;
|
||||
|
||||
public void Add(int offset, int size, ICacheKey key, T value)
|
||||
{
|
||||
List<Entry> entries = GetEntries(offset, size);
|
||||
|
||||
entries.Add(new Entry(key, value));
|
||||
}
|
||||
|
||||
public bool TryGetValue(int offset, int size, ICacheKey key, out T value)
|
||||
{
|
||||
List<Entry> entries = GetEntries(offset, size);
|
||||
|
||||
foreach (Entry entry in entries)
|
||||
{
|
||||
if (entry.Key.KeyEqual(key))
|
||||
{
|
||||
value = entry.Value;
|
||||
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
value = default;
|
||||
return false;
|
||||
}
|
||||
|
||||
public void Clear()
|
||||
{
|
||||
if (_ranges != null)
|
||||
{
|
||||
foreach (T value in _ranges.Values)
|
||||
foreach (List<Entry> entries in _ranges.Values)
|
||||
{
|
||||
value.Dispose();
|
||||
foreach (Entry entry in entries)
|
||||
{
|
||||
entry.Key.Dispose();
|
||||
entry.Value.Dispose();
|
||||
}
|
||||
}
|
||||
|
||||
_ranges.Clear();
|
||||
@@ -33,12 +114,23 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
}
|
||||
}
|
||||
|
||||
private void EnsureInitialized()
|
||||
private List<Entry> GetEntries(int offset, int size)
|
||||
{
|
||||
if (_ranges == null)
|
||||
{
|
||||
_ranges = new Dictionary<ulong, T>();
|
||||
_ranges = new Dictionary<ulong, List<Entry>>();
|
||||
}
|
||||
|
||||
ulong key = PackRange(offset, size);
|
||||
|
||||
List<Entry> value;
|
||||
if (!_ranges.TryGetValue(key, out value))
|
||||
{
|
||||
value = new List<Entry>();
|
||||
_ranges.Add(key, value);
|
||||
}
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
private static ulong PackRange(int offset, int size)
|
||||
|
||||
@@ -185,6 +185,34 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
SignalDirty(DirtyFlags.Storage);
|
||||
}
|
||||
|
||||
public void SetStorageBuffers(CommandBuffer commandBuffer, int first, ReadOnlySpan<Auto<DisposableBuffer>> buffers)
|
||||
{
|
||||
for (int i = 0; i < buffers.Length; i++)
|
||||
{
|
||||
var vkBuffer = buffers[i];
|
||||
int index = first + i;
|
||||
|
||||
ref Auto<DisposableBuffer> currentVkBuffer = ref _storageBufferRefs[index];
|
||||
|
||||
DescriptorBufferInfo info = new DescriptorBufferInfo()
|
||||
{
|
||||
Offset = 0,
|
||||
Range = Vk.WholeSize
|
||||
};
|
||||
ref DescriptorBufferInfo currentInfo = ref _storageBuffers[index];
|
||||
|
||||
if (vkBuffer != currentVkBuffer || currentInfo.Offset != info.Offset || currentInfo.Range != info.Range)
|
||||
{
|
||||
_storageSet[index] = false;
|
||||
|
||||
currentInfo = info;
|
||||
currentVkBuffer = vkBuffer;
|
||||
}
|
||||
}
|
||||
|
||||
SignalDirty(DirtyFlags.Storage);
|
||||
}
|
||||
|
||||
public void SetTextureAndSampler(CommandBufferScoped cbs, ShaderStage stage, int binding, ITexture texture, ISampler sampler)
|
||||
{
|
||||
if (texture == null)
|
||||
@@ -388,7 +416,14 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
}
|
||||
|
||||
ReadOnlySpan<DescriptorBufferInfo> storageBuffers = _storageBuffers;
|
||||
dsc.UpdateStorageBuffers(0, binding, storageBuffers.Slice(binding, count));
|
||||
if (program.HasMinimalLayout)
|
||||
{
|
||||
dsc.UpdateBuffers(0, binding, storageBuffers.Slice(binding, count), DescriptorType.StorageBuffer);
|
||||
}
|
||||
else
|
||||
{
|
||||
dsc.UpdateStorageBuffers(0, binding, storageBuffers.Slice(binding, count));
|
||||
}
|
||||
}
|
||||
else if (setIndex == PipelineBase.TextureSetIndex)
|
||||
{
|
||||
|
||||
@@ -108,6 +108,10 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
{
|
||||
format = VkFormat.D32SfloatS8Uint;
|
||||
}
|
||||
else if (srcFormat == GAL.Format.R4G4B4A4Unorm)
|
||||
{
|
||||
format = VkFormat.R4G4B4A4UnormPack16;
|
||||
}
|
||||
else
|
||||
{
|
||||
Logger.Error?.Print(LogClass.Gpu, $"Format {srcFormat} is not supported by the host.");
|
||||
|
||||
@@ -6,11 +6,11 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
{
|
||||
static class FormatTable
|
||||
{
|
||||
private static readonly VkFormat[] Table;
|
||||
private static readonly VkFormat[] _table;
|
||||
|
||||
static FormatTable()
|
||||
{
|
||||
Table = new VkFormat[Enum.GetNames(typeof(Format)).Length];
|
||||
_table = new VkFormat[Enum.GetNames(typeof(Format)).Length];
|
||||
|
||||
Add(Format.R8Unorm, VkFormat.R8Unorm);
|
||||
Add(Format.R8Snorm, VkFormat.R8SNorm);
|
||||
@@ -68,7 +68,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
Add(Format.D32FloatS8Uint, VkFormat.D32SfloatS8Uint);
|
||||
Add(Format.R8G8B8A8Srgb, VkFormat.R8G8B8A8Srgb);
|
||||
Add(Format.R4G4Unorm, VkFormat.R4G4UnormPack8);
|
||||
Add(Format.R4G4B4A4Unorm, VkFormat.R4G4B4A4UnormPack16);
|
||||
Add(Format.R4G4B4A4Unorm, VkFormat.A4B4G4R4UnormPack16Ext);
|
||||
Add(Format.R5G5B5X1Unorm, VkFormat.A1R5G5B5UnormPack16);
|
||||
Add(Format.R5G5B5A1Unorm, VkFormat.A1R5G5B5UnormPack16);
|
||||
Add(Format.R5G6B5Unorm, VkFormat.R5G6B5UnormPack16);
|
||||
@@ -161,12 +161,12 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
|
||||
private static void Add(Format format, VkFormat vkFormat)
|
||||
{
|
||||
Table[(int)format] = vkFormat;
|
||||
_table[(int)format] = vkFormat;
|
||||
}
|
||||
|
||||
public static VkFormat GetFormat(Format format)
|
||||
{
|
||||
return Table[(int)format];
|
||||
return _table[(int)format];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -10,6 +10,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
public readonly bool SupportsFragmentShaderInterlock;
|
||||
public readonly bool SupportsGeometryShaderPassthrough;
|
||||
public readonly bool SupportsSubgroupSizeControl;
|
||||
public readonly bool SupportsShaderInt8;
|
||||
public readonly bool SupportsConditionalRendering;
|
||||
public readonly bool SupportsExtendedDynamicState;
|
||||
public readonly bool SupportsMultiView;
|
||||
@@ -29,6 +30,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
bool supportsFragmentShaderInterlock,
|
||||
bool supportsGeometryShaderPassthrough,
|
||||
bool supportsSubgroupSizeControl,
|
||||
bool supportsShaderInt8,
|
||||
bool supportsConditionalRendering,
|
||||
bool supportsExtendedDynamicState,
|
||||
bool supportsMultiView,
|
||||
@@ -47,6 +49,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
SupportsFragmentShaderInterlock = supportsFragmentShaderInterlock;
|
||||
SupportsGeometryShaderPassthrough = supportsGeometryShaderPassthrough;
|
||||
SupportsSubgroupSizeControl = supportsSubgroupSizeControl;
|
||||
SupportsShaderInt8 = supportsShaderInt8;
|
||||
SupportsConditionalRendering = supportsConditionalRendering;
|
||||
SupportsExtendedDynamicState = supportsExtendedDynamicState;
|
||||
SupportsMultiView = supportsMultiView;
|
||||
|
||||
@@ -16,6 +16,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
private readonly IProgram _programColorBlit;
|
||||
private readonly IProgram _programColorBlitClearAlpha;
|
||||
private readonly IProgram _programColorClear;
|
||||
private readonly IProgram _programStrideChange;
|
||||
|
||||
public HelperShader(VulkanRenderer gd, Device device)
|
||||
{
|
||||
@@ -39,14 +40,14 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
|
||||
_programColorBlit = gd.CreateProgramWithMinimalLayout(new[]
|
||||
{
|
||||
new ShaderSource(ShaderBinaries.ColorBlitVertexShaderSource, vertexBindings, ShaderStage.Vertex, TargetLanguage.Glsl),
|
||||
new ShaderSource(ShaderBinaries.ColorBlitFragmentShaderSource, fragmentBindings, ShaderStage.Fragment, TargetLanguage.Glsl),
|
||||
new ShaderSource(ShaderBinaries.ColorBlitVertexShaderSource, vertexBindings, ShaderStage.Vertex, TargetLanguage.Spirv),
|
||||
new ShaderSource(ShaderBinaries.ColorBlitFragmentShaderSource, fragmentBindings, ShaderStage.Fragment, TargetLanguage.Spirv),
|
||||
});
|
||||
|
||||
_programColorBlitClearAlpha = gd.CreateProgramWithMinimalLayout(new[]
|
||||
{
|
||||
new ShaderSource(ShaderBinaries.ColorBlitVertexShaderSource, vertexBindings, ShaderStage.Vertex, TargetLanguage.Glsl),
|
||||
new ShaderSource(ShaderBinaries.ColorBlitClearAlphaFragmentShaderSource, fragmentBindings, ShaderStage.Fragment, TargetLanguage.Glsl),
|
||||
new ShaderSource(ShaderBinaries.ColorBlitVertexShaderSource, vertexBindings, ShaderStage.Vertex, TargetLanguage.Spirv),
|
||||
new ShaderSource(ShaderBinaries.ColorBlitClearAlphaFragmentShaderSource, fragmentBindings, ShaderStage.Fragment, TargetLanguage.Spirv),
|
||||
});
|
||||
|
||||
var fragmentBindings2 = new ShaderBindings(
|
||||
@@ -57,8 +58,19 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
|
||||
_programColorClear = gd.CreateProgramWithMinimalLayout(new[]
|
||||
{
|
||||
new ShaderSource(ShaderBinaries.ColorClearVertexShaderSource, vertexBindings, ShaderStage.Vertex, TargetLanguage.Glsl),
|
||||
new ShaderSource(ShaderBinaries.ColorClearFragmentShaderSource, fragmentBindings2, ShaderStage.Fragment, TargetLanguage.Glsl),
|
||||
new ShaderSource(ShaderBinaries.ColorClearVertexShaderSource, vertexBindings, ShaderStage.Vertex, TargetLanguage.Spirv),
|
||||
new ShaderSource(ShaderBinaries.ColorClearFragmentShaderSource, fragmentBindings2, ShaderStage.Fragment, TargetLanguage.Spirv),
|
||||
});
|
||||
|
||||
var strideChangeBindings = new ShaderBindings(
|
||||
new[] { 0 },
|
||||
new[] { 1, 2 },
|
||||
Array.Empty<int>(),
|
||||
Array.Empty<int>());
|
||||
|
||||
_programStrideChange = gd.CreateProgramWithMinimalLayout(new[]
|
||||
{
|
||||
new ShaderSource(ShaderBinaries.ChangeBufferStrideShaderSource, strideChangeBindings, ShaderStage.Compute, TargetLanguage.Spirv),
|
||||
});
|
||||
}
|
||||
|
||||
@@ -163,7 +175,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
_pipeline.SetViewports(viewports, false);
|
||||
_pipeline.SetPrimitiveTopology(GAL.PrimitiveTopology.TriangleStrip);
|
||||
_pipeline.Draw(4, 1, 0, 0);
|
||||
_pipeline.Finish();
|
||||
_pipeline.Finish(gd, cbs);
|
||||
|
||||
gd.BufferManager.Delete(bufferHandle);
|
||||
}
|
||||
@@ -291,45 +303,100 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
|
||||
public unsafe void ConvertI8ToI16(VulkanRenderer gd, CommandBufferScoped cbs, BufferHolder src, BufferHolder dst, int srcOffset, int size)
|
||||
{
|
||||
// TODO: Do this with a compute shader?
|
||||
var srcBuffer = src.GetBuffer().Get(cbs, srcOffset, size).Value;
|
||||
var dstBuffer = dst.GetBuffer().Get(cbs, 0, size * 2).Value;
|
||||
ChangeStride(gd, cbs, src, dst, srcOffset, size, 1, 2);
|
||||
}
|
||||
|
||||
gd.Api.CmdFillBuffer(cbs.CommandBuffer, dstBuffer, 0, Vk.WholeSize, 0);
|
||||
public unsafe void ChangeStride(VulkanRenderer gd, CommandBufferScoped cbs, BufferHolder src, BufferHolder dst, int srcOffset, int size, int stride, int newStride)
|
||||
{
|
||||
bool supportsUint8 = gd.Capabilities.SupportsShaderInt8;
|
||||
|
||||
var bufferCopy = new BufferCopy[size];
|
||||
int elems = size / stride;
|
||||
int newSize = elems * newStride;
|
||||
|
||||
for (ulong i = 0; i < (ulong)size; i++)
|
||||
{
|
||||
bufferCopy[i] = new BufferCopy((ulong)srcOffset + i, i * 2, 1);
|
||||
}
|
||||
var srcBufferAuto = src.GetBuffer();
|
||||
var dstBufferAuto = dst.GetBuffer();
|
||||
|
||||
var srcBuffer = srcBufferAuto.Get(cbs, srcOffset, size).Value;
|
||||
var dstBuffer = dstBufferAuto.Get(cbs, 0, newSize).Value;
|
||||
|
||||
var access = supportsUint8 ? AccessFlags.AccessShaderWriteBit : AccessFlags.AccessTransferWriteBit;
|
||||
var stage = supportsUint8 ? PipelineStageFlags.PipelineStageComputeShaderBit : PipelineStageFlags.PipelineStageTransferBit;
|
||||
|
||||
BufferHolder.InsertBufferBarrier(
|
||||
gd,
|
||||
cbs.CommandBuffer,
|
||||
dstBuffer,
|
||||
BufferHolder.DefaultAccessFlags,
|
||||
AccessFlags.AccessTransferWriteBit,
|
||||
access,
|
||||
PipelineStageFlags.PipelineStageAllCommandsBit,
|
||||
PipelineStageFlags.PipelineStageTransferBit,
|
||||
stage,
|
||||
0,
|
||||
size * 2);
|
||||
newSize);
|
||||
|
||||
fixed (BufferCopy* pBufferCopy = bufferCopy)
|
||||
if (supportsUint8)
|
||||
{
|
||||
gd.Api.CmdCopyBuffer(cbs.CommandBuffer, srcBuffer, dstBuffer, (uint)size, pBufferCopy);
|
||||
const int ParamsBufferSize = 16;
|
||||
|
||||
Span<int> shaderParams = stackalloc int[ParamsBufferSize / sizeof(int)];
|
||||
|
||||
shaderParams[0] = stride;
|
||||
shaderParams[1] = newStride;
|
||||
shaderParams[2] = size;
|
||||
shaderParams[3] = srcOffset;
|
||||
|
||||
var bufferHandle = gd.BufferManager.CreateWithHandle(gd, ParamsBufferSize, false);
|
||||
|
||||
gd.BufferManager.SetData<int>(bufferHandle, 0, shaderParams);
|
||||
|
||||
_pipeline.SetCommandBuffer(cbs);
|
||||
|
||||
Span<BufferRange> cbRanges = stackalloc BufferRange[1];
|
||||
|
||||
cbRanges[0] = new BufferRange(bufferHandle, 0, ParamsBufferSize);
|
||||
|
||||
_pipeline.SetUniformBuffers(0, cbRanges);
|
||||
|
||||
Span<Auto<DisposableBuffer>> sbRanges = new Auto<DisposableBuffer>[2];
|
||||
|
||||
sbRanges[0] = srcBufferAuto;
|
||||
sbRanges[1] = dstBufferAuto;
|
||||
|
||||
_pipeline.SetStorageBuffers(1, sbRanges);
|
||||
|
||||
_pipeline.SetProgram(_programStrideChange);
|
||||
_pipeline.DispatchCompute(1, 1, 1);
|
||||
|
||||
gd.BufferManager.Delete(bufferHandle);
|
||||
|
||||
_pipeline.Finish(gd, cbs);
|
||||
}
|
||||
else
|
||||
{
|
||||
gd.Api.CmdFillBuffer(cbs.CommandBuffer, dstBuffer, 0, Vk.WholeSize, 0);
|
||||
|
||||
var bufferCopy = new BufferCopy[elems];
|
||||
|
||||
for (ulong i = 0; i < (ulong)elems; i++)
|
||||
{
|
||||
bufferCopy[i] = new BufferCopy((ulong)srcOffset + i * (ulong)stride, i * (ulong)newStride, (ulong)stride);
|
||||
}
|
||||
|
||||
fixed (BufferCopy* pBufferCopy = bufferCopy)
|
||||
{
|
||||
gd.Api.CmdCopyBuffer(cbs.CommandBuffer, srcBuffer, dstBuffer, (uint)elems, pBufferCopy);
|
||||
}
|
||||
}
|
||||
|
||||
BufferHolder.InsertBufferBarrier(
|
||||
gd,
|
||||
cbs.CommandBuffer,
|
||||
dstBuffer,
|
||||
AccessFlags.AccessTransferWriteBit,
|
||||
access,
|
||||
BufferHolder.DefaultAccessFlags,
|
||||
PipelineStageFlags.PipelineStageTransferBit,
|
||||
stage,
|
||||
PipelineStageFlags.PipelineStageAllCommandsBit,
|
||||
0,
|
||||
size * 2);
|
||||
newSize);
|
||||
}
|
||||
|
||||
protected virtual void Dispose(bool disposing)
|
||||
|
||||
@@ -2,6 +2,7 @@
|
||||
using Ryujinx.Graphics.Shader;
|
||||
using Silk.NET.Vulkan;
|
||||
using System;
|
||||
using System.Numerics;
|
||||
|
||||
namespace Ryujinx.Graphics.Vulkan
|
||||
{
|
||||
@@ -50,14 +51,14 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
|
||||
private BufferState _indexBuffer;
|
||||
private readonly BufferState[] _transformFeedbackBuffers;
|
||||
private readonly BufferState[] _vertexBuffers;
|
||||
private readonly VertexBufferState[] _vertexBuffers;
|
||||
private ulong _vertexBuffersDirty;
|
||||
protected Rectangle<int> ClearScissor;
|
||||
|
||||
public SupportBufferUpdater SupportBufferUpdater;
|
||||
|
||||
private bool _needsIndexBufferRebind;
|
||||
private bool _needsTransformFeedbackBuffersRebind;
|
||||
private bool _needsVertexBuffersRebind;
|
||||
|
||||
private bool _tfEnabled;
|
||||
private bool _tfActive;
|
||||
@@ -79,14 +80,14 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
_descriptorSetUpdater = new DescriptorSetUpdater(gd, this);
|
||||
|
||||
_transformFeedbackBuffers = new BufferState[Constants.MaxTransformFeedbackBuffers];
|
||||
_vertexBuffers = new BufferState[Constants.MaxVertexBuffers + 1];
|
||||
_vertexBuffers = new VertexBufferState[Constants.MaxVertexBuffers + 1];
|
||||
|
||||
const int EmptyVbSize = 16;
|
||||
|
||||
using var emptyVb = gd.BufferManager.Create(gd, EmptyVbSize);
|
||||
emptyVb.SetData(0, new byte[EmptyVbSize]);
|
||||
_vertexBuffers[0] = new BufferState(emptyVb.GetBuffer(), 0, EmptyVbSize, 0UL);
|
||||
_needsVertexBuffersRebind = true;
|
||||
_vertexBuffers[0] = new VertexBufferState(emptyVb.GetBuffer(), 0, EmptyVbSize, 0);
|
||||
_vertexBuffersDirty = ulong.MaxValue >> (64 - _vertexBuffers.Length);
|
||||
|
||||
ClearScissor = new Rectangle<int>(0, 0, 0xffff, 0xffff);
|
||||
|
||||
@@ -229,6 +230,17 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
BufferHolder.Copy(Gd, Cbs, src, dst, srcOffset, dstOffset, size);
|
||||
}
|
||||
|
||||
public void DirtyVertexBuffer(Auto<DisposableBuffer> buffer)
|
||||
{
|
||||
for (int i = 0; i < _vertexBuffers.Length; i++)
|
||||
{
|
||||
if (_vertexBuffers[i].BoundEquals(buffer))
|
||||
{
|
||||
_vertexBuffersDirty |= 1UL << i;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
public void DispatchCompute(int groupsX, int groupsY, int groupsZ)
|
||||
{
|
||||
if (!_program.IsLinked)
|
||||
@@ -345,6 +357,11 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
_tfEnabled = false;
|
||||
}
|
||||
|
||||
public bool IsCommandBufferActive(CommandBuffer cb)
|
||||
{
|
||||
return CommandBuffer.Handle == cb.Handle;
|
||||
}
|
||||
|
||||
public void MultiDrawIndirectCount(BufferRange indirectBuffer, BufferRange parameterBuffer, int maxDrawCount, int stride)
|
||||
{
|
||||
if (!Gd.Capabilities.SupportsIndirectParameters)
|
||||
@@ -689,6 +706,11 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
_descriptorSetUpdater.SetStorageBuffers(CommandBuffer, first, buffers);
|
||||
}
|
||||
|
||||
public void SetStorageBuffers(int first, ReadOnlySpan<Auto<DisposableBuffer>> buffers)
|
||||
{
|
||||
_descriptorSetUpdater.SetStorageBuffers(CommandBuffer, first, buffers);
|
||||
}
|
||||
|
||||
public void SetTextureAndSampler(ShaderStage stage, int binding, ITexture texture, ISampler sampler)
|
||||
{
|
||||
_descriptorSetUpdater.SetTextureAndSampler(Cbs, stage, binding, texture, sampler);
|
||||
@@ -732,12 +754,22 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
{
|
||||
var formatCapabilities = Gd.FormatCapabilities;
|
||||
|
||||
Span<int> newVbScalarSizes = stackalloc int[Constants.MaxVertexBuffers];
|
||||
|
||||
int count = Math.Min(Constants.MaxVertexAttributes, vertexAttribs.Length);
|
||||
uint dirtyVbSizes = 0;
|
||||
|
||||
for (int i = 0; i < count; i++)
|
||||
{
|
||||
var attribute = vertexAttribs[i];
|
||||
var bufferIndex = attribute.IsZero ? 0 : attribute.BufferIndex + 1;
|
||||
var rawIndex = attribute.BufferIndex;
|
||||
var bufferIndex = attribute.IsZero ? 0 : rawIndex + 1;
|
||||
|
||||
if (!attribute.IsZero)
|
||||
{
|
||||
newVbScalarSizes[rawIndex] = Math.Max(newVbScalarSizes[rawIndex], attribute.Format.GetScalarSize());
|
||||
dirtyVbSizes |= 1u << rawIndex;
|
||||
}
|
||||
|
||||
_newState.Internal.VertexAttributeDescriptions[i] = new VertexInputAttributeDescription(
|
||||
(uint)i,
|
||||
@@ -746,6 +778,21 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
(uint)attribute.Offset);
|
||||
}
|
||||
|
||||
while (dirtyVbSizes != 0)
|
||||
{
|
||||
int dirtyBit = BitOperations.TrailingZeroCount(dirtyVbSizes);
|
||||
|
||||
ref var buffer = ref _vertexBuffers[dirtyBit + 1];
|
||||
|
||||
if (buffer.AttributeScalarAlignment != newVbScalarSizes[dirtyBit])
|
||||
{
|
||||
_vertexBuffersDirty |= 1UL << (dirtyBit + 1);
|
||||
buffer.AttributeScalarAlignment = newVbScalarSizes[dirtyBit];
|
||||
}
|
||||
|
||||
dirtyVbSizes &= ~(1u << dirtyBit);
|
||||
}
|
||||
|
||||
_newState.VertexAttributeDescriptionsCount = (uint)count;
|
||||
SignalStateChange();
|
||||
}
|
||||
@@ -792,14 +839,37 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
}
|
||||
}
|
||||
|
||||
_vertexBuffers[binding].Dispose();
|
||||
_vertexBuffers[binding] = new BufferState(
|
||||
vb,
|
||||
vertexBuffer.Buffer.Offset,
|
||||
vbSize,
|
||||
(ulong)vertexBuffer.Stride);
|
||||
ref var buffer = ref _vertexBuffers[binding];
|
||||
int oldScalarAlign = buffer.AttributeScalarAlignment;
|
||||
|
||||
_vertexBuffers[binding].BindVertexBuffer(Gd, Cbs, (uint)binding);
|
||||
buffer.Dispose();
|
||||
|
||||
if ((vertexBuffer.Stride % FormatExtensions.MaxBufferFormatScalarSize) == 0)
|
||||
{
|
||||
buffer = new VertexBufferState(
|
||||
vb,
|
||||
descriptorIndex,
|
||||
vertexBuffer.Buffer.Offset,
|
||||
vbSize,
|
||||
vertexBuffer.Stride);
|
||||
|
||||
buffer.BindVertexBuffer(Gd, Cbs, (uint)binding, ref _newState);
|
||||
}
|
||||
else
|
||||
{
|
||||
// May need to be rewritten. Bind this buffer before draw.
|
||||
|
||||
buffer = new VertexBufferState(
|
||||
vertexBuffer.Buffer.Handle,
|
||||
descriptorIndex,
|
||||
vertexBuffer.Buffer.Offset,
|
||||
vbSize,
|
||||
vertexBuffer.Stride);
|
||||
|
||||
_vertexBuffersDirty |= 1UL << binding;
|
||||
}
|
||||
|
||||
buffer.AttributeScalarAlignment = oldScalarAlign;
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -907,7 +977,7 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
{
|
||||
_needsIndexBufferRebind = true;
|
||||
_needsTransformFeedbackBuffersRebind = true;
|
||||
_needsVertexBuffersRebind = true;
|
||||
_vertexBuffersDirty = ulong.MaxValue >> (64 - _vertexBuffers.Length);
|
||||
|
||||
_descriptorSetUpdater.SignalCommandBufferChange();
|
||||
_dynamicState.ForceAllDirty();
|
||||
@@ -1053,13 +1123,6 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
// Commit changes to the support buffer before drawing.
|
||||
SupportBufferUpdater.Commit();
|
||||
|
||||
if (_stateDirty || Pbp != pbp)
|
||||
{
|
||||
CreatePipeline(pbp);
|
||||
_stateDirty = false;
|
||||
Pbp = pbp;
|
||||
}
|
||||
|
||||
if (_needsIndexBufferRebind)
|
||||
{
|
||||
_indexBuffer.BindIndexBuffer(Gd.Api, Cbs);
|
||||
@@ -1078,14 +1141,23 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
_needsTransformFeedbackBuffersRebind = false;
|
||||
}
|
||||
|
||||
if (_needsVertexBuffersRebind)
|
||||
if (_vertexBuffersDirty != 0)
|
||||
{
|
||||
for (int i = 0; i < Constants.MaxVertexBuffers + 1; i++)
|
||||
while (_vertexBuffersDirty != 0)
|
||||
{
|
||||
_vertexBuffers[i].BindVertexBuffer(Gd, Cbs, (uint)i);
|
||||
}
|
||||
int i = BitOperations.TrailingZeroCount(_vertexBuffersDirty);
|
||||
|
||||
_needsVertexBuffersRebind = false;
|
||||
_vertexBuffers[i].BindVertexBuffer(Gd, Cbs, (uint)i, ref _newState);
|
||||
|
||||
_vertexBuffersDirty &= ~(1u << i);
|
||||
}
|
||||
}
|
||||
|
||||
if (_stateDirty || Pbp != pbp)
|
||||
{
|
||||
CreatePipeline(pbp);
|
||||
_stateDirty = false;
|
||||
Pbp = pbp;
|
||||
}
|
||||
|
||||
_descriptorSetUpdater.UpdateAndBindDescriptorSets(Cbs, pbp);
|
||||
|
||||
@@ -202,6 +202,9 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
pipeline.Topology = state.Topology.Convert();
|
||||
|
||||
int vaCount = Math.Min(Constants.MaxVertexAttributes, state.VertexAttribCount);
|
||||
int vbCount = Math.Min(Constants.MaxVertexBuffers, state.VertexBufferCount);
|
||||
|
||||
Span<int> vbScalarSizes = stackalloc int[vbCount];
|
||||
|
||||
for (int i = 0; i < vaCount; i++)
|
||||
{
|
||||
@@ -213,13 +216,16 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
(uint)bufferIndex,
|
||||
gd.FormatCapabilities.ConvertToVertexVkFormat(attribute.Format),
|
||||
(uint)attribute.Offset);
|
||||
|
||||
if (!attribute.IsZero && bufferIndex < vbCount)
|
||||
{
|
||||
vbScalarSizes[bufferIndex - 1] = Math.Max(attribute.Format.GetScalarSize(), vbScalarSizes[bufferIndex - 1]);
|
||||
}
|
||||
}
|
||||
|
||||
int descriptorIndex = 1;
|
||||
pipeline.Internal.VertexBindingDescriptions[0] = new VertexInputBindingDescription(0, 0, VertexInputRate.Vertex);
|
||||
|
||||
int vbCount = Math.Min(Constants.MaxVertexBuffers, state.VertexBufferCount);
|
||||
|
||||
for (int i = 0; i < vbCount; i++)
|
||||
{
|
||||
var vertexBuffer = state.VertexBuffers[i];
|
||||
@@ -228,10 +234,17 @@ namespace Ryujinx.Graphics.Vulkan
|
||||
{
|
||||
var inputRate = vertexBuffer.Divisor != 0 ? VertexInputRate.Instance : VertexInputRate.Vertex;
|
||||
|
||||
int alignedStride = vertexBuffer.Stride;
|
||||
|
||||
if (gd.NeedsVertexBufferAlignment(vbScalarSizes[i], out int alignment))
|
||||
{
|
||||
alignedStride = (vertexBuffer.Stride + (alignment - 1)) & -alignment;
|
||||
}
|
||||
|
||||
// TODO: Support divisor > 1
|
||||
pipeline.Internal.VertexBindingDescriptions[descriptorIndex++] = new VertexInputBindingDescription(
|
||||
(uint)i + 1,
|
||||
(uint)vertexBuffer.Stride,
|
||||
(uint)alignedStride,
|
||||
inputRate);
|
||||
}
|
||||
}
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user