InstEmitMemory32: Literal loads always have word-aligned PC (#3104)

* Fix missing geometry shader passthrough inputs

* Shader cache version bump

ARMeilleure/CodeGen/X86/X86Optimizer.cs

@@ -9,13 +9,17 @@ namespace ARMeilleure.CodeGen.X86
 {
     static class X86Optimizer
     {
+        private const int MaxConstantUses = 10000;
+
         public static void RunPass(ControlFlowGraph cfg)
         {
             var constants = new Dictionary<ulong, Operand>();
 
             Operand GetConstantCopy(BasicBlock block, Operation operation, Operand source)
             {
-                if (!constants.TryGetValue(source.Value, out var constant))
+                // If the constant has many uses, we also force a new constant mov to be added, in order
+                // to avoid overflow of the counts field (that is limited to 16 bits).
+                if (!constants.TryGetValue(source.Value, out var constant) || constant.UsesCount > MaxConstantUses)
                 {
                     constant = Local(source.Type);
 
@@ -23,7 +27,7 @@ namespace ARMeilleure.CodeGen.X86
 
                     block.Operations.AddBefore(operation, copyOp);
 
-                    constants.Add(source.Value, constant);
+                    constants[source.Value] = constant;
                 }
 
                 return constant;

ARMeilleure/Instructions/InstEmitHelper.cs

@@ -47,6 +47,20 @@ namespace ARMeilleure.Instructions
             }
         }
 
+        public static Operand GetIntA32AlignedPC(ArmEmitterContext context, int regIndex)
+        {
+            if (regIndex == RegisterAlias.Aarch32Pc)
+            {
+                OpCode32 op = (OpCode32)context.CurrOp;
+
+                return Const((int)(op.GetPc() & 0xfffffffc));
+            }
+            else
+            {
+                return Register(GetRegisterAlias(context.Mode, regIndex), RegisterType.Integer, OperandType.I32);
+            }
+        }
+
         public static Operand GetVecA32(int regIndex)
         {
             return Register(regIndex, RegisterType.Vector, OperandType.V128);

ARMeilleure/Instructions/InstEmitMemory32.cs

@@ -153,7 +153,7 @@ namespace ARMeilleure.Instructions
         {
             OpCode32Mem op = (OpCode32Mem)context.CurrOp;
 
-            Operand n = context.Copy(GetIntA32(context, op.Rn));
+            Operand n = context.Copy(GetIntA32AlignedPC(context, op.Rn));
             Operand m = GetMemM(context, setCarry: false);
 
             Operand temp = default;

Ryujinx.Audio.Backends.SoundIo/Ryujinx.Audio.Backends.SoundIo.csproj

@@ -3,6 +3,7 @@
   <PropertyGroup>
     <TargetFramework>net6.0</TargetFramework>
     <AllowUnsafeBlocks>true</AllowUnsafeBlocks>
+    <RuntimeIdentifiers>win-x64;linux-x64;osx-x64</RuntimeIdentifiers>
   </PropertyGroup>
 
   <ItemGroup>

Ryujinx.Graphics.Gpu/Shader/ShaderCache.cs

@@ -40,7 +40,7 @@ namespace Ryujinx.Graphics.Gpu.Shader
         /// <summary>
         /// Version of the codegen (to be changed when codegen or guest format change).
         /// </summary>
-        private const ulong ShaderCodeGenVersion = 3012;
+        private const ulong ShaderCodeGenVersion = 3106;
 
         // Progress reporting helpers
         private volatile int _shaderCount;

Ryujinx.Graphics.Shader/CodeGen/Glsl/Declarations.cs

@@ -490,7 +490,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
             }
             else
             {
-                int usedAttributes = context.Config.UsedInputAttributes;
+                int usedAttributes = context.Config.UsedInputAttributes | context.Config.PassthroughAttributes;
                 while (usedAttributes != 0)
                 {
                     int index = BitOperations.TrailingZeroCount(usedAttributes);