86de288142
* Integral numbers should not be shifted by zero or more than their number of bits-1 * more
42 lines
1.2 KiB
C#
42 lines
1.2 KiB
C#
// This file was auto-generated from NVIDIA official Maxwell definitions.
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namespace Ryujinx.Graphics.Gpu.Engine.GPFifo
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{
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enum TertOp
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{
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Grp0IncMethod = 0,
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Grp0SetSubDevMask = 1,
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Grp0StoreSubDevMask = 2,
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Grp0UseSubDevMask = 3,
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Grp2NonIncMethod = 0
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}
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enum SecOp
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{
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Grp0UseTert = 0,
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IncMethod = 1,
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Grp2UseTert = 2,
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NonIncMethod = 3,
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ImmdDataMethod = 4,
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OneInc = 5,
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Reserved6 = 6,
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EndPbSegment = 7
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}
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struct CompressedMethod
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{
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#pragma warning disable CS0649
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public uint Method;
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#pragma warning restore CS0649
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public int MethodAddressOld => (int)((Method >> 2) & 0x7FF);
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public int MethodAddress => (int)(Method & 0xFFF);
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public int SubdeviceMask => (int)((Method >> 4) & 0xFFF);
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public int MethodSubchannel => (int)((Method >> 13) & 0x7);
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public TertOp TertOp => (TertOp)((Method >> 16) & 0x3);
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public int MethodCountOld => (int)((Method >> 18) & 0x7FF);
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public int MethodCount => (int)((Method >> 16) & 0x1FFF);
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public int ImmdData => (int)((Method >> 16) & 0x1FFF);
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public SecOp SecOp => (SecOp)((Method >> 29) & 0x7);
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}
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}
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