Compare commits
39 Commits
Author | SHA1 | Date | |
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79becc4b78 | |||
223172ac0b | |||
8c9633d72f | |||
1f93fd52d9 | |||
aac7bbd378 | |||
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69b05f9918 | |||
fb7c80e928 | |||
bb2f9df0a1 | |||
54bfaa125d | |||
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ee174be57c | |||
0bcbe32367 | |||
b97ff4da5e | |||
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497199bb50 | |||
bd9ac0fdaa | |||
ac21abbb9d | |||
a3dd04deef | |||
3705c20668 | |||
7b35ebc64a | |||
0a24aa6af2 | |||
c9c65af59e | |||
dc063eac83 | |||
ccf23fc629 | |||
f1460d5494 | |||
644b497df1 | |||
fb935fd201 | |||
f2087ca29e | |||
92d166ecb7 | |||
72e543e946 | |||
98c838b24c | |||
63c9c64196 | |||
a113ed0811 | |||
747876dc67 | |||
95cc18a7b4 | |||
c017c77365 | |||
98e05ee4b7 | |||
868919e101 |
@ -18,7 +18,7 @@ namespace ARMeilleure.Decoders
|
|||||||
// For lower code quality translation, we set a lower limit since we're blocking execution.
|
// For lower code quality translation, we set a lower limit since we're blocking execution.
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||||||
private const int MaxInstsPerFunctionLowCq = 500;
|
private const int MaxInstsPerFunctionLowCq = 500;
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||||||
|
|
||||||
public static Block[] Decode(IMemoryManager memory, ulong address, ExecutionMode mode, bool highCq, bool singleBlock)
|
public static Block[] Decode(IMemoryManager memory, ulong address, ExecutionMode mode, bool highCq, DecoderMode dMode)
|
||||||
{
|
{
|
||||||
List<Block> blocks = new List<Block>();
|
List<Block> blocks = new List<Block>();
|
||||||
|
|
||||||
@ -38,7 +38,7 @@ namespace ARMeilleure.Decoders
|
|||||||
{
|
{
|
||||||
block = new Block(blkAddress);
|
block = new Block(blkAddress);
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||||||
|
|
||||||
if ((singleBlock && visited.Count >= 1) || opsCount > instructionLimit || !memory.IsMapped(blkAddress))
|
if ((dMode != DecoderMode.MultipleBlocks && visited.Count >= 1) || opsCount > instructionLimit || !memory.IsMapped(blkAddress))
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||||||
{
|
{
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||||||
block.Exit = true;
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block.Exit = true;
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block.EndAddress = blkAddress;
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block.EndAddress = blkAddress;
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@ -96,6 +96,12 @@ namespace ARMeilleure.Decoders
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|||||||
}
|
}
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}
|
}
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||||||
|
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||||||
|
if (dMode == DecoderMode.SingleInstruction)
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||||||
|
{
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|
// Only read at most one instruction
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|
limitAddress = currBlock.Address + 1;
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|
}
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|
|
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FillBlock(memory, mode, currBlock, limitAddress);
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FillBlock(memory, mode, currBlock, limitAddress);
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|
|
||||||
opsCount += currBlock.OpCodes.Count;
|
opsCount += currBlock.OpCodes.Count;
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@ -115,7 +121,7 @@ namespace ARMeilleure.Decoders
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|||||||
currBlock.Branch = GetBlock((ulong)op.Immediate);
|
currBlock.Branch = GetBlock((ulong)op.Immediate);
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}
|
}
|
||||||
|
|
||||||
if (!IsUnconditionalBranch(lastOp) || isCall)
|
if (isCall || !(IsUnconditionalBranch(lastOp) || IsTrap(lastOp)))
|
||||||
{
|
{
|
||||||
currBlock.Next = GetBlock(currBlock.EndAddress);
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currBlock.Next = GetBlock(currBlock.EndAddress);
|
||||||
}
|
}
|
||||||
@ -143,7 +149,7 @@ namespace ARMeilleure.Decoders
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|||||||
throw new InvalidOperationException($"Decoded a single empty exit block. Entry point = 0x{address:X}.");
|
throw new InvalidOperationException($"Decoded a single empty exit block. Entry point = 0x{address:X}.");
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||||||
}
|
}
|
||||||
|
|
||||||
if (!singleBlock)
|
if (dMode == DecoderMode.MultipleBlocks)
|
||||||
{
|
{
|
||||||
return TailCallRemover.RunPass(address, blocks);
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return TailCallRemover.RunPass(address, blocks);
|
||||||
}
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}
|
||||||
@ -195,12 +201,13 @@ namespace ARMeilleure.Decoders
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|||||||
ulong limitAddress)
|
ulong limitAddress)
|
||||||
{
|
{
|
||||||
ulong address = block.Address;
|
ulong address = block.Address;
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||||||
|
int itBlockSize = 0;
|
||||||
|
|
||||||
OpCode opCode;
|
OpCode opCode;
|
||||||
|
|
||||||
do
|
do
|
||||||
{
|
{
|
||||||
if (address >= limitAddress)
|
if (address >= limitAddress && itBlockSize == 0)
|
||||||
{
|
{
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
@ -210,6 +217,15 @@ namespace ARMeilleure.Decoders
|
|||||||
block.OpCodes.Add(opCode);
|
block.OpCodes.Add(opCode);
|
||||||
|
|
||||||
address += (ulong)opCode.OpCodeSizeInBytes;
|
address += (ulong)opCode.OpCodeSizeInBytes;
|
||||||
|
|
||||||
|
if (opCode is OpCodeT16IfThen it)
|
||||||
|
{
|
||||||
|
itBlockSize = it.IfThenBlockSize;
|
||||||
|
}
|
||||||
|
else if (itBlockSize > 0)
|
||||||
|
{
|
||||||
|
itBlockSize--;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
while (!(IsBranch(opCode) || IsException(opCode)));
|
while (!(IsBranch(opCode) || IsException(opCode)));
|
||||||
|
|
||||||
@ -247,6 +263,11 @@ namespace ARMeilleure.Decoders
|
|||||||
// so we must consider such operations as a branch in potential aswell.
|
// so we must consider such operations as a branch in potential aswell.
|
||||||
if (opCode is IOpCode32Alu opAlu && opAlu.Rd == RegisterAlias.Aarch32Pc)
|
if (opCode is IOpCode32Alu opAlu && opAlu.Rd == RegisterAlias.Aarch32Pc)
|
||||||
{
|
{
|
||||||
|
if (opCode is OpCodeT32)
|
||||||
|
{
|
||||||
|
return opCode.Instruction.Name != InstName.Tst && opCode.Instruction.Name != InstName.Teq &&
|
||||||
|
opCode.Instruction.Name != InstName.Cmp && opCode.Instruction.Name != InstName.Cmn;
|
||||||
|
}
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -308,9 +329,13 @@ namespace ARMeilleure.Decoders
|
|||||||
}
|
}
|
||||||
|
|
||||||
private static bool IsException(OpCode opCode)
|
private static bool IsException(OpCode opCode)
|
||||||
|
{
|
||||||
|
return IsTrap(opCode) || opCode.Instruction.Name == InstName.Svc;
|
||||||
|
}
|
||||||
|
|
||||||
|
private static bool IsTrap(OpCode opCode)
|
||||||
{
|
{
|
||||||
return opCode.Instruction.Name == InstName.Brk ||
|
return opCode.Instruction.Name == InstName.Brk ||
|
||||||
opCode.Instruction.Name == InstName.Svc ||
|
|
||||||
opCode.Instruction.Name == InstName.Trap ||
|
opCode.Instruction.Name == InstName.Trap ||
|
||||||
opCode.Instruction.Name == InstName.Und;
|
opCode.Instruction.Name == InstName.Und;
|
||||||
}
|
}
|
||||||
@ -345,7 +370,14 @@ namespace ARMeilleure.Decoders
|
|||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
return new OpCode(inst, address, opCode);
|
if (mode == ExecutionMode.Aarch32Thumb)
|
||||||
|
{
|
||||||
|
return new OpCodeT16(inst, address, opCode);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return new OpCode(inst, address, opCode);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
9
ARMeilleure/Decoders/DecoderMode.cs
Normal file
9
ARMeilleure/Decoders/DecoderMode.cs
Normal file
@ -0,0 +1,9 @@
|
|||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
enum DecoderMode
|
||||||
|
{
|
||||||
|
MultipleBlocks,
|
||||||
|
SingleBlock,
|
||||||
|
SingleInstruction,
|
||||||
|
}
|
||||||
|
}
|
9
ARMeilleure/Decoders/IOpCode32Adr.cs
Normal file
9
ARMeilleure/Decoders/IOpCode32Adr.cs
Normal file
@ -0,0 +1,9 @@
|
|||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
interface IOpCode32Adr
|
||||||
|
{
|
||||||
|
int Rd { get; }
|
||||||
|
|
||||||
|
int Immediate { get; }
|
||||||
|
}
|
||||||
|
}
|
@ -1,10 +1,8 @@
|
|||||||
namespace ARMeilleure.Decoders
|
namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
interface IOpCode32Alu : IOpCode32
|
interface IOpCode32Alu : IOpCode32, IOpCode32HasSetFlags
|
||||||
{
|
{
|
||||||
int Rd { get; }
|
int Rd { get; }
|
||||||
int Rn { get; }
|
int Rn { get; }
|
||||||
|
|
||||||
bool SetFlags { get; }
|
|
||||||
}
|
}
|
||||||
}
|
}
|
9
ARMeilleure/Decoders/IOpCode32AluImm.cs
Normal file
9
ARMeilleure/Decoders/IOpCode32AluImm.cs
Normal file
@ -0,0 +1,9 @@
|
|||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
interface IOpCode32AluImm : IOpCode32Alu
|
||||||
|
{
|
||||||
|
int Immediate { get; }
|
||||||
|
|
||||||
|
bool IsRotated { get; }
|
||||||
|
}
|
||||||
|
}
|
10
ARMeilleure/Decoders/IOpCode32AluRsImm.cs
Normal file
10
ARMeilleure/Decoders/IOpCode32AluRsImm.cs
Normal file
@ -0,0 +1,10 @@
|
|||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
interface IOpCode32AluRsImm : IOpCode32Alu
|
||||||
|
{
|
||||||
|
int Rm { get; }
|
||||||
|
int Immediate { get; }
|
||||||
|
|
||||||
|
ShiftType ShiftType { get; }
|
||||||
|
}
|
||||||
|
}
|
10
ARMeilleure/Decoders/IOpCode32AluRsReg.cs
Normal file
10
ARMeilleure/Decoders/IOpCode32AluRsReg.cs
Normal file
@ -0,0 +1,10 @@
|
|||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
interface IOpCode32AluRsReg : IOpCode32Alu
|
||||||
|
{
|
||||||
|
int Rm { get; }
|
||||||
|
int Rs { get; }
|
||||||
|
|
||||||
|
ShiftType ShiftType { get; }
|
||||||
|
}
|
||||||
|
}
|
6
ARMeilleure/Decoders/IOpCode32Exception.cs
Normal file
6
ARMeilleure/Decoders/IOpCode32Exception.cs
Normal file
@ -0,0 +1,6 @@
|
|||||||
|
namespace ARMeilleure.Decoders;
|
||||||
|
|
||||||
|
interface IOpCode32Exception
|
||||||
|
{
|
||||||
|
int Id { get; }
|
||||||
|
}
|
7
ARMeilleure/Decoders/IOpCode32HasSetFlags.cs
Normal file
7
ARMeilleure/Decoders/IOpCode32HasSetFlags.cs
Normal file
@ -0,0 +1,7 @@
|
|||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
interface IOpCode32HasSetFlags
|
||||||
|
{
|
||||||
|
bool? SetFlags { get; }
|
||||||
|
}
|
||||||
|
}
|
@ -7,5 +7,9 @@ namespace ARMeilleure.Decoders
|
|||||||
|
|
||||||
bool WBack { get; }
|
bool WBack { get; }
|
||||||
bool IsLoad { get; }
|
bool IsLoad { get; }
|
||||||
|
bool Index { get; }
|
||||||
|
bool Add { get; }
|
||||||
|
|
||||||
|
int Immediate { get; }
|
||||||
}
|
}
|
||||||
}
|
}
|
@ -9,5 +9,7 @@ namespace ARMeilleure.Decoders
|
|||||||
int PostOffset { get; }
|
int PostOffset { get; }
|
||||||
|
|
||||||
bool IsLoad { get; }
|
bool IsLoad { get; }
|
||||||
|
|
||||||
|
int Offset { get; }
|
||||||
}
|
}
|
||||||
}
|
}
|
7
ARMeilleure/Decoders/IOpCode32MemReg.cs
Normal file
7
ARMeilleure/Decoders/IOpCode32MemReg.cs
Normal file
@ -0,0 +1,7 @@
|
|||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
interface IOpCode32MemReg : IOpCode32Mem
|
||||||
|
{
|
||||||
|
int Rm { get; }
|
||||||
|
}
|
||||||
|
}
|
@ -18,10 +18,9 @@ namespace ARMeilleure.Decoders
|
|||||||
|
|
||||||
public OpCode(InstDescriptor inst, ulong address, int opCode)
|
public OpCode(InstDescriptor inst, ulong address, int opCode)
|
||||||
{
|
{
|
||||||
Address = address;
|
|
||||||
RawOpCode = opCode;
|
|
||||||
|
|
||||||
Instruction = inst;
|
Instruction = inst;
|
||||||
|
Address = address;
|
||||||
|
RawOpCode = opCode;
|
||||||
|
|
||||||
RegisterSize = RegisterSize.Int64;
|
RegisterSize = RegisterSize.Int64;
|
||||||
}
|
}
|
||||||
|
@ -13,11 +13,25 @@ namespace ARMeilleure.Decoders
|
|||||||
Cond = (Condition)((uint)opCode >> 28);
|
Cond = (Condition)((uint)opCode >> 28);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
public bool IsThumb()
|
||||||
|
{
|
||||||
|
return this is OpCodeT16 || this is OpCodeT32;
|
||||||
|
}
|
||||||
|
|
||||||
public uint GetPc()
|
public uint GetPc()
|
||||||
{
|
{
|
||||||
// Due to backwards compatibility and legacy behavior of ARMv4 CPUs pipeline,
|
// Due to backwards compatibility and legacy behavior of ARMv4 CPUs pipeline,
|
||||||
// the PC actually points 2 instructions ahead.
|
// the PC actually points 2 instructions ahead.
|
||||||
return (uint)Address + (uint)OpCodeSizeInBytes * 2;
|
if (IsThumb())
|
||||||
|
{
|
||||||
|
// PC is ahead by 4 in thumb mode whether or not the current instruction
|
||||||
|
// is 16 or 32 bit.
|
||||||
|
return (uint)Address + 4u;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return (uint)Address + 8u;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
@ -5,7 +5,7 @@ namespace ARMeilleure.Decoders
|
|||||||
public int Rd { get; }
|
public int Rd { get; }
|
||||||
public int Rn { get; }
|
public int Rn { get; }
|
||||||
|
|
||||||
public bool SetFlags { get; }
|
public bool? SetFlags { get; }
|
||||||
|
|
||||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Alu(inst, address, opCode);
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Alu(inst, address, opCode);
|
||||||
|
|
||||||
|
@ -2,7 +2,7 @@ using ARMeilleure.Common;
|
|||||||
|
|
||||||
namespace ARMeilleure.Decoders
|
namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCode32AluImm : OpCode32Alu
|
class OpCode32AluImm : OpCode32Alu, IOpCode32AluImm
|
||||||
{
|
{
|
||||||
public int Immediate { get; }
|
public int Immediate { get; }
|
||||||
|
|
||||||
|
@ -10,7 +10,7 @@
|
|||||||
public bool NHigh { get; }
|
public bool NHigh { get; }
|
||||||
public bool MHigh { get; }
|
public bool MHigh { get; }
|
||||||
public bool R { get; }
|
public bool R { get; }
|
||||||
public bool SetFlags { get; }
|
public bool? SetFlags { get; }
|
||||||
|
|
||||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluMla(inst, address, opCode);
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluMla(inst, address, opCode);
|
||||||
|
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
namespace ARMeilleure.Decoders
|
namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCode32AluRsImm : OpCode32Alu
|
class OpCode32AluRsImm : OpCode32Alu, IOpCode32AluRsImm
|
||||||
{
|
{
|
||||||
public int Rm { get; }
|
public int Rm { get; }
|
||||||
public int Immediate { get; }
|
public int Immediate { get; }
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
namespace ARMeilleure.Decoders
|
namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCode32AluRsReg : OpCode32Alu
|
class OpCode32AluRsReg : OpCode32Alu, IOpCode32AluRsReg
|
||||||
{
|
{
|
||||||
public int Rm { get; }
|
public int Rm { get; }
|
||||||
public int Rs { get; }
|
public int Rs { get; }
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
namespace ARMeilleure.Decoders
|
namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCode32AluUmull : OpCode32
|
class OpCode32AluUmull : OpCode32, IOpCode32HasSetFlags
|
||||||
{
|
{
|
||||||
public int RdLo { get; }
|
public int RdLo { get; }
|
||||||
public int RdHi { get; }
|
public int RdHi { get; }
|
||||||
@ -10,7 +10,7 @@
|
|||||||
public bool NHigh { get; }
|
public bool NHigh { get; }
|
||||||
public bool MHigh { get; }
|
public bool MHigh { get; }
|
||||||
|
|
||||||
public bool SetFlags { get; }
|
public bool? SetFlags { get; }
|
||||||
public DataOp DataOp { get; }
|
public DataOp DataOp { get; }
|
||||||
|
|
||||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluUmull(inst, address, opCode);
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32AluUmull(inst, address, opCode);
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
namespace ARMeilleure.Decoders
|
namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCode32Exception : OpCode32
|
class OpCode32Exception : OpCode32, IOpCode32Exception
|
||||||
{
|
{
|
||||||
public int Id { get; }
|
public int Id { get; }
|
||||||
|
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
namespace ARMeilleure.Decoders
|
namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCode32MemReg : OpCode32Mem
|
class OpCode32MemReg : OpCode32Mem, IOpCode32MemReg
|
||||||
{
|
{
|
||||||
public int Rm { get; }
|
public int Rm { get; }
|
||||||
|
|
||||||
|
24
ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs
Normal file
24
ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs
Normal file
@ -0,0 +1,24 @@
|
|||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT16AddSubImm3: OpCodeT16, IOpCode32AluImm
|
||||||
|
{
|
||||||
|
public int Rd { get; }
|
||||||
|
public int Rn { get; }
|
||||||
|
|
||||||
|
public bool? SetFlags => null;
|
||||||
|
|
||||||
|
public int Immediate { get; }
|
||||||
|
|
||||||
|
public bool IsRotated { get; }
|
||||||
|
|
||||||
|
public static new OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16AddSubImm3(inst, address, opCode);
|
||||||
|
|
||||||
|
public OpCodeT16AddSubImm3(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
|
{
|
||||||
|
Rd = (opCode >> 0) & 0x7;
|
||||||
|
Rn = (opCode >> 3) & 0x7;
|
||||||
|
Immediate = (opCode >> 6) & 0x7;
|
||||||
|
IsRotated = false;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
20
ARMeilleure/Decoders/OpCodeT16AddSubReg.cs
Normal file
20
ARMeilleure/Decoders/OpCodeT16AddSubReg.cs
Normal file
@ -0,0 +1,20 @@
|
|||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT16AddSubReg : OpCodeT16, IOpCode32AluReg
|
||||||
|
{
|
||||||
|
public int Rm { get; }
|
||||||
|
public int Rd { get; }
|
||||||
|
public int Rn { get; }
|
||||||
|
|
||||||
|
public bool? SetFlags => null;
|
||||||
|
|
||||||
|
public static new OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16AddSubReg(inst, address, opCode);
|
||||||
|
|
||||||
|
public OpCodeT16AddSubReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
|
{
|
||||||
|
Rd = (opCode >> 0) & 0x7;
|
||||||
|
Rn = (opCode >> 3) & 0x7;
|
||||||
|
Rm = (opCode >> 6) & 0x7;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
23
ARMeilleure/Decoders/OpCodeT16AddSubSp.cs
Normal file
23
ARMeilleure/Decoders/OpCodeT16AddSubSp.cs
Normal file
@ -0,0 +1,23 @@
|
|||||||
|
using ARMeilleure.State;
|
||||||
|
|
||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT16AddSubSp : OpCodeT16, IOpCode32AluImm
|
||||||
|
{
|
||||||
|
public int Rd => RegisterAlias.Aarch32Sp;
|
||||||
|
public int Rn => RegisterAlias.Aarch32Sp;
|
||||||
|
|
||||||
|
public bool? SetFlags => false;
|
||||||
|
|
||||||
|
public int Immediate { get; }
|
||||||
|
|
||||||
|
public bool IsRotated => false;
|
||||||
|
|
||||||
|
public static new OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16AddSubSp(inst, address, opCode);
|
||||||
|
|
||||||
|
public OpCodeT16AddSubSp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
|
{
|
||||||
|
Immediate = ((opCode >> 0) & 0x7f) << 2;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
20
ARMeilleure/Decoders/OpCodeT16Adr.cs
Normal file
20
ARMeilleure/Decoders/OpCodeT16Adr.cs
Normal file
@ -0,0 +1,20 @@
|
|||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT16Adr : OpCodeT16, IOpCode32Adr
|
||||||
|
{
|
||||||
|
public int Rd { get; }
|
||||||
|
|
||||||
|
public bool Add => true;
|
||||||
|
public int Immediate { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16Adr(inst, address, opCode);
|
||||||
|
|
||||||
|
public OpCodeT16Adr(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
|
{
|
||||||
|
Rd = (opCode >> 8) & 7;
|
||||||
|
|
||||||
|
int imm = (opCode & 0xff) << 2;
|
||||||
|
Immediate = (int)(GetPc() & 0xfffffffc) + imm;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
@ -1,22 +1,24 @@
|
|||||||
namespace ARMeilleure.Decoders
|
namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeT16AluImm8 : OpCodeT16, IOpCode32Alu
|
class OpCodeT16AluImm8 : OpCodeT16, IOpCode32AluImm
|
||||||
{
|
{
|
||||||
private int _rdn;
|
public int Rd { get; }
|
||||||
|
public int Rn { get; }
|
||||||
|
|
||||||
public int Rd => _rdn;
|
public bool? SetFlags => null;
|
||||||
public int Rn => _rdn;
|
|
||||||
|
|
||||||
public bool SetFlags => false;
|
|
||||||
|
|
||||||
public int Immediate { get; }
|
public int Immediate { get; }
|
||||||
|
|
||||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16AluImm8(inst, address, opCode);
|
public bool IsRotated { get; }
|
||||||
|
|
||||||
|
public static new OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16AluImm8(inst, address, opCode);
|
||||||
|
|
||||||
public OpCodeT16AluImm8(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
public OpCodeT16AluImm8(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
{
|
{
|
||||||
|
Rd = (opCode >> 8) & 0x7;
|
||||||
|
Rn = (opCode >> 8) & 0x7;
|
||||||
Immediate = (opCode >> 0) & 0xff;
|
Immediate = (opCode >> 0) & 0xff;
|
||||||
_rdn = (opCode >> 8) & 0x7;
|
IsRotated = false;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
24
ARMeilleure/Decoders/OpCodeT16AluImmZero.cs
Normal file
24
ARMeilleure/Decoders/OpCodeT16AluImmZero.cs
Normal file
@ -0,0 +1,24 @@
|
|||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT16AluImmZero : OpCodeT16, IOpCode32AluImm
|
||||||
|
{
|
||||||
|
public int Rd { get; }
|
||||||
|
public int Rn { get; }
|
||||||
|
|
||||||
|
public bool? SetFlags => null;
|
||||||
|
|
||||||
|
public int Immediate { get; }
|
||||||
|
|
||||||
|
public bool IsRotated { get; }
|
||||||
|
|
||||||
|
public static new OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16AluImmZero(inst, address, opCode);
|
||||||
|
|
||||||
|
public OpCodeT16AluImmZero(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
|
{
|
||||||
|
Rd = (opCode >> 0) & 0x7;
|
||||||
|
Rn = (opCode >> 3) & 0x7;
|
||||||
|
Immediate = 0;
|
||||||
|
IsRotated = false;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
20
ARMeilleure/Decoders/OpCodeT16AluRegHigh.cs
Normal file
20
ARMeilleure/Decoders/OpCodeT16AluRegHigh.cs
Normal file
@ -0,0 +1,20 @@
|
|||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT16AluRegHigh : OpCodeT16, IOpCode32AluReg
|
||||||
|
{
|
||||||
|
public int Rm { get; }
|
||||||
|
public int Rd { get; }
|
||||||
|
public int Rn { get; }
|
||||||
|
|
||||||
|
public bool? SetFlags => false;
|
||||||
|
|
||||||
|
public static new OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16AluRegHigh(inst, address, opCode);
|
||||||
|
|
||||||
|
public OpCodeT16AluRegHigh(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
|
{
|
||||||
|
Rd = ((opCode >> 0) & 0x7) | ((opCode >> 4) & 0x8);
|
||||||
|
Rn = ((opCode >> 0) & 0x7) | ((opCode >> 4) & 0x8);
|
||||||
|
Rm = (opCode >> 3) & 0xf;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
20
ARMeilleure/Decoders/OpCodeT16AluRegLow.cs
Normal file
20
ARMeilleure/Decoders/OpCodeT16AluRegLow.cs
Normal file
@ -0,0 +1,20 @@
|
|||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT16AluRegLow : OpCodeT16, IOpCode32AluReg
|
||||||
|
{
|
||||||
|
public int Rm { get; }
|
||||||
|
public int Rd { get; }
|
||||||
|
public int Rn { get; }
|
||||||
|
|
||||||
|
public bool? SetFlags => null;
|
||||||
|
|
||||||
|
public static new OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16AluRegLow(inst, address, opCode);
|
||||||
|
|
||||||
|
public OpCodeT16AluRegLow(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
|
{
|
||||||
|
Rd = (opCode >> 0) & 0x7;
|
||||||
|
Rn = (opCode >> 0) & 0x7;
|
||||||
|
Rm = (opCode >> 3) & 0x7;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
22
ARMeilleure/Decoders/OpCodeT16AluUx.cs
Normal file
22
ARMeilleure/Decoders/OpCodeT16AluUx.cs
Normal file
@ -0,0 +1,22 @@
|
|||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT16AluUx : OpCodeT16, IOpCode32AluUx
|
||||||
|
{
|
||||||
|
public int Rm { get; }
|
||||||
|
public int Rd { get; }
|
||||||
|
public int Rn { get; }
|
||||||
|
|
||||||
|
public bool? SetFlags => false;
|
||||||
|
|
||||||
|
public int RotateBits => 0;
|
||||||
|
public bool Add => false;
|
||||||
|
|
||||||
|
public static new OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16AluUx(inst, address, opCode);
|
||||||
|
|
||||||
|
public OpCodeT16AluUx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
|
{
|
||||||
|
Rd = (opCode >> 0) & 0x7;
|
||||||
|
Rm = (opCode >> 3) & 0x7;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
15
ARMeilleure/Decoders/OpCodeT16BImm11.cs
Normal file
15
ARMeilleure/Decoders/OpCodeT16BImm11.cs
Normal file
@ -0,0 +1,15 @@
|
|||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT16BImm11 : OpCodeT16, IOpCode32BImm
|
||||||
|
{
|
||||||
|
public long Immediate { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16BImm11(inst, address, opCode);
|
||||||
|
|
||||||
|
public OpCodeT16BImm11(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
|
{
|
||||||
|
int imm = (opCode << 21) >> 20;
|
||||||
|
Immediate = GetPc() + imm;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
17
ARMeilleure/Decoders/OpCodeT16BImm8.cs
Normal file
17
ARMeilleure/Decoders/OpCodeT16BImm8.cs
Normal file
@ -0,0 +1,17 @@
|
|||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT16BImm8 : OpCodeT16, IOpCode32BImm
|
||||||
|
{
|
||||||
|
public long Immediate { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16BImm8(inst, address, opCode);
|
||||||
|
|
||||||
|
public OpCodeT16BImm8(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
|
{
|
||||||
|
Cond = (Condition)((opCode >> 8) & 0xf);
|
||||||
|
|
||||||
|
int imm = (opCode << 24) >> 23;
|
||||||
|
Immediate = GetPc() + imm;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
19
ARMeilleure/Decoders/OpCodeT16BImmCmp.cs
Normal file
19
ARMeilleure/Decoders/OpCodeT16BImmCmp.cs
Normal file
@ -0,0 +1,19 @@
|
|||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT16BImmCmp : OpCodeT16
|
||||||
|
{
|
||||||
|
public int Rn { get; }
|
||||||
|
|
||||||
|
public int Immediate { get; }
|
||||||
|
|
||||||
|
public static new OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16BImmCmp(inst, address, opCode);
|
||||||
|
|
||||||
|
public OpCodeT16BImmCmp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
|
{
|
||||||
|
Rn = (opCode >> 0) & 0x7;
|
||||||
|
|
||||||
|
int imm = ((opCode >> 2) & 0x3e) | ((opCode >> 3) & 0x40);
|
||||||
|
Immediate = (int)GetPc() + imm;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
@ -1,4 +1,4 @@
|
|||||||
namespace ARMeilleure.Decoders
|
namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
class OpCodeT16BReg : OpCodeT16, IOpCode32BReg
|
class OpCodeT16BReg : OpCodeT16, IOpCode32BReg
|
||||||
{
|
{
|
||||||
@ -11,4 +11,4 @@ namespace ARMeilleure.Decoders
|
|||||||
Rm = (opCode >> 3) & 0xf;
|
Rm = (opCode >> 3) & 0xf;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
14
ARMeilleure/Decoders/OpCodeT16Exception.cs
Normal file
14
ARMeilleure/Decoders/OpCodeT16Exception.cs
Normal file
@ -0,0 +1,14 @@
|
|||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT16Exception : OpCodeT16, IOpCode32Exception
|
||||||
|
{
|
||||||
|
public int Id { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16Exception(inst, address, opCode);
|
||||||
|
|
||||||
|
public OpCodeT16Exception(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
|
{
|
||||||
|
Id = opCode & 0xFF;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
34
ARMeilleure/Decoders/OpCodeT16IfThen.cs
Normal file
34
ARMeilleure/Decoders/OpCodeT16IfThen.cs
Normal file
@ -0,0 +1,34 @@
|
|||||||
|
using System.Collections.Generic;
|
||||||
|
using System.Reflection.Emit;
|
||||||
|
|
||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT16IfThen : OpCodeT16
|
||||||
|
{
|
||||||
|
public Condition[] IfThenBlockConds { get; }
|
||||||
|
|
||||||
|
public int IfThenBlockSize { get { return IfThenBlockConds.Length; } }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16IfThen(inst, address, opCode);
|
||||||
|
|
||||||
|
public OpCodeT16IfThen(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
|
{
|
||||||
|
List<Condition> conds = new();
|
||||||
|
|
||||||
|
int cond = (opCode >> 4) & 0xf;
|
||||||
|
int mask = opCode & 0xf;
|
||||||
|
|
||||||
|
conds.Add((Condition)cond);
|
||||||
|
|
||||||
|
while ((mask & 7) != 0)
|
||||||
|
{
|
||||||
|
int newLsb = (mask >> 3) & 1;
|
||||||
|
cond = (cond & 0xe) | newLsb;
|
||||||
|
mask <<= 1;
|
||||||
|
conds.Add((Condition)cond);
|
||||||
|
}
|
||||||
|
|
||||||
|
IfThenBlockConds = conds.ToArray();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
58
ARMeilleure/Decoders/OpCodeT16MemImm5.cs
Normal file
58
ARMeilleure/Decoders/OpCodeT16MemImm5.cs
Normal file
@ -0,0 +1,58 @@
|
|||||||
|
using ARMeilleure.Instructions;
|
||||||
|
using System;
|
||||||
|
|
||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT16MemImm5 : OpCodeT16, IOpCode32Mem
|
||||||
|
{
|
||||||
|
public int Rt { get; }
|
||||||
|
public int Rn { get; }
|
||||||
|
|
||||||
|
public bool WBack => false;
|
||||||
|
public bool IsLoad { get; }
|
||||||
|
public bool Index => true;
|
||||||
|
public bool Add => true;
|
||||||
|
|
||||||
|
public int Immediate { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16MemImm5(inst, address, opCode);
|
||||||
|
|
||||||
|
public OpCodeT16MemImm5(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
|
{
|
||||||
|
Rt = (opCode >> 0) & 7;
|
||||||
|
Rn = (opCode >> 3) & 7;
|
||||||
|
|
||||||
|
switch (inst.Name)
|
||||||
|
{
|
||||||
|
case InstName.Ldr:
|
||||||
|
case InstName.Ldrb:
|
||||||
|
case InstName.Ldrh:
|
||||||
|
IsLoad = true;
|
||||||
|
break;
|
||||||
|
case InstName.Str:
|
||||||
|
case InstName.Strb:
|
||||||
|
case InstName.Strh:
|
||||||
|
IsLoad = false;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
switch (inst.Name)
|
||||||
|
{
|
||||||
|
case InstName.Str:
|
||||||
|
case InstName.Ldr:
|
||||||
|
Immediate = ((opCode >> 6) & 0x1f) << 2;
|
||||||
|
break;
|
||||||
|
case InstName.Strb:
|
||||||
|
case InstName.Ldrb:
|
||||||
|
Immediate = ((opCode >> 6) & 0x1f);
|
||||||
|
break;
|
||||||
|
case InstName.Strh:
|
||||||
|
case InstName.Ldrh:
|
||||||
|
Immediate = ((opCode >> 6) & 0x1f) << 1;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
throw new InvalidOperationException();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
26
ARMeilleure/Decoders/OpCodeT16MemLit.cs
Normal file
26
ARMeilleure/Decoders/OpCodeT16MemLit.cs
Normal file
@ -0,0 +1,26 @@
|
|||||||
|
using ARMeilleure.State;
|
||||||
|
|
||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT16MemLit : OpCodeT16, IOpCode32Mem
|
||||||
|
{
|
||||||
|
public int Rt { get; }
|
||||||
|
public int Rn => RegisterAlias.Aarch32Pc;
|
||||||
|
|
||||||
|
public bool WBack => false;
|
||||||
|
public bool IsLoad => true;
|
||||||
|
public bool Index => true;
|
||||||
|
public bool Add => true;
|
||||||
|
|
||||||
|
public int Immediate { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16MemLit(inst, address, opCode);
|
||||||
|
|
||||||
|
public OpCodeT16MemLit(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
|
{
|
||||||
|
Rt = (opCode >> 8) & 7;
|
||||||
|
|
||||||
|
Immediate = (opCode & 0xff) << 2;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
34
ARMeilleure/Decoders/OpCodeT16MemMult.cs
Normal file
34
ARMeilleure/Decoders/OpCodeT16MemMult.cs
Normal file
@ -0,0 +1,34 @@
|
|||||||
|
using ARMeilleure.Instructions;
|
||||||
|
using System;
|
||||||
|
using System.Numerics;
|
||||||
|
|
||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT16MemMult : OpCodeT16, IOpCode32MemMult
|
||||||
|
{
|
||||||
|
public int Rn { get; }
|
||||||
|
public int RegisterMask { get; }
|
||||||
|
public int PostOffset { get; }
|
||||||
|
public bool IsLoad { get; }
|
||||||
|
public int Offset { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16MemMult(inst, address, opCode);
|
||||||
|
|
||||||
|
public OpCodeT16MemMult(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
|
{
|
||||||
|
RegisterMask = opCode & 0xff;
|
||||||
|
Rn = (opCode >> 8) & 7;
|
||||||
|
|
||||||
|
int regCount = BitOperations.PopCount((uint)RegisterMask);
|
||||||
|
|
||||||
|
Offset = 0;
|
||||||
|
PostOffset = 4 * regCount;
|
||||||
|
IsLoad = inst.Name switch
|
||||||
|
{
|
||||||
|
InstName.Ldm => true,
|
||||||
|
InstName.Stm => false,
|
||||||
|
_ => throw new InvalidOperationException()
|
||||||
|
};
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
27
ARMeilleure/Decoders/OpCodeT16MemReg.cs
Normal file
27
ARMeilleure/Decoders/OpCodeT16MemReg.cs
Normal file
@ -0,0 +1,27 @@
|
|||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT16MemReg : OpCodeT16, IOpCode32MemReg
|
||||||
|
{
|
||||||
|
public int Rm { get; }
|
||||||
|
public int Rt { get; }
|
||||||
|
public int Rn { get; }
|
||||||
|
|
||||||
|
public bool WBack => false;
|
||||||
|
public bool IsLoad { get; }
|
||||||
|
public bool Index => true;
|
||||||
|
public bool Add => true;
|
||||||
|
|
||||||
|
public int Immediate => throw new System.InvalidOperationException();
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16MemReg(inst, address, opCode);
|
||||||
|
|
||||||
|
public OpCodeT16MemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
|
{
|
||||||
|
Rt = (opCode >> 0) & 7;
|
||||||
|
Rn = (opCode >> 3) & 7;
|
||||||
|
Rm = (opCode >> 6) & 7;
|
||||||
|
|
||||||
|
IsLoad = ((opCode >> 9) & 7) >= 3;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
28
ARMeilleure/Decoders/OpCodeT16MemSp.cs
Normal file
28
ARMeilleure/Decoders/OpCodeT16MemSp.cs
Normal file
@ -0,0 +1,28 @@
|
|||||||
|
using ARMeilleure.State;
|
||||||
|
|
||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT16MemSp : OpCodeT16, IOpCode32Mem
|
||||||
|
{
|
||||||
|
public int Rt { get; }
|
||||||
|
public int Rn => RegisterAlias.Aarch32Sp;
|
||||||
|
|
||||||
|
public bool WBack => false;
|
||||||
|
public bool IsLoad { get; }
|
||||||
|
public bool Index => true;
|
||||||
|
public bool Add => true;
|
||||||
|
|
||||||
|
public int Immediate { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16MemSp(inst, address, opCode);
|
||||||
|
|
||||||
|
public OpCodeT16MemSp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
|
{
|
||||||
|
Rt = (opCode >> 8) & 7;
|
||||||
|
|
||||||
|
IsLoad = ((opCode >> 11) & 1) != 0;
|
||||||
|
|
||||||
|
Immediate = ((opCode >> 0) & 0xff) << 2;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
42
ARMeilleure/Decoders/OpCodeT16MemStack.cs
Normal file
42
ARMeilleure/Decoders/OpCodeT16MemStack.cs
Normal file
@ -0,0 +1,42 @@
|
|||||||
|
using ARMeilleure.Instructions;
|
||||||
|
using ARMeilleure.State;
|
||||||
|
using System;
|
||||||
|
using System.Numerics;
|
||||||
|
|
||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT16MemStack : OpCodeT16, IOpCode32MemMult
|
||||||
|
{
|
||||||
|
public int Rn => RegisterAlias.Aarch32Sp;
|
||||||
|
public int RegisterMask { get; }
|
||||||
|
public int PostOffset { get; }
|
||||||
|
public bool IsLoad { get; }
|
||||||
|
public int Offset { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16MemStack(inst, address, opCode);
|
||||||
|
|
||||||
|
public OpCodeT16MemStack(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
|
{
|
||||||
|
int extra = (opCode >> 8) & 1;
|
||||||
|
int regCount = BitOperations.PopCount((uint)opCode & 0x1ff);
|
||||||
|
|
||||||
|
switch (inst.Name)
|
||||||
|
{
|
||||||
|
case InstName.Push:
|
||||||
|
RegisterMask = (opCode & 0xff) | (extra << 14);
|
||||||
|
IsLoad = false;
|
||||||
|
Offset = -4 * regCount;
|
||||||
|
PostOffset = -4 * regCount;
|
||||||
|
break;
|
||||||
|
case InstName.Pop:
|
||||||
|
RegisterMask = (opCode & 0xff) | (extra << 15);
|
||||||
|
IsLoad = true;
|
||||||
|
Offset = 0;
|
||||||
|
PostOffset = 4 * regCount;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
throw new InvalidOperationException();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
24
ARMeilleure/Decoders/OpCodeT16ShiftImm.cs
Normal file
24
ARMeilleure/Decoders/OpCodeT16ShiftImm.cs
Normal file
@ -0,0 +1,24 @@
|
|||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT16ShiftImm : OpCodeT16, IOpCode32AluRsImm
|
||||||
|
{
|
||||||
|
public int Rd { get; }
|
||||||
|
public int Rn { get; }
|
||||||
|
public int Rm { get; }
|
||||||
|
|
||||||
|
public int Immediate { get; }
|
||||||
|
public ShiftType ShiftType { get; }
|
||||||
|
|
||||||
|
public bool? SetFlags => null;
|
||||||
|
|
||||||
|
public static new OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16ShiftImm(inst, address, opCode);
|
||||||
|
|
||||||
|
public OpCodeT16ShiftImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
|
{
|
||||||
|
Rd = (opCode >> 0) & 0x7;
|
||||||
|
Rm = (opCode >> 3) & 0x7;
|
||||||
|
Immediate = (opCode >> 6) & 0x1F;
|
||||||
|
ShiftType = (ShiftType)((opCode >> 11) & 3);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
27
ARMeilleure/Decoders/OpCodeT16ShiftReg.cs
Normal file
27
ARMeilleure/Decoders/OpCodeT16ShiftReg.cs
Normal file
@ -0,0 +1,27 @@
|
|||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT16ShiftReg : OpCodeT16, IOpCode32AluRsReg
|
||||||
|
{
|
||||||
|
public int Rm { get; }
|
||||||
|
public int Rs { get; }
|
||||||
|
public int Rd { get; }
|
||||||
|
|
||||||
|
public int Rn { get; }
|
||||||
|
|
||||||
|
public ShiftType ShiftType { get; }
|
||||||
|
|
||||||
|
public bool? SetFlags => null;
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16ShiftReg(inst, address, opCode);
|
||||||
|
|
||||||
|
public OpCodeT16ShiftReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
|
{
|
||||||
|
Rd = (opCode >> 0) & 7;
|
||||||
|
Rm = (opCode >> 0) & 7;
|
||||||
|
Rn = (opCode >> 3) & 7;
|
||||||
|
Rs = (opCode >> 3) & 7;
|
||||||
|
|
||||||
|
ShiftType = (ShiftType)(((opCode >> 6) & 1) | ((opCode >> 7) & 2));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
24
ARMeilleure/Decoders/OpCodeT16SpRel.cs
Normal file
24
ARMeilleure/Decoders/OpCodeT16SpRel.cs
Normal file
@ -0,0 +1,24 @@
|
|||||||
|
using ARMeilleure.State;
|
||||||
|
|
||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT16SpRel : OpCodeT16, IOpCode32AluImm
|
||||||
|
{
|
||||||
|
public int Rd { get; }
|
||||||
|
public int Rn => RegisterAlias.Aarch32Sp;
|
||||||
|
|
||||||
|
public bool? SetFlags => false;
|
||||||
|
|
||||||
|
public int Immediate { get; }
|
||||||
|
|
||||||
|
public bool IsRotated => false;
|
||||||
|
|
||||||
|
public static new OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16SpRel(inst, address, opCode);
|
||||||
|
|
||||||
|
public OpCodeT16SpRel(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
|
{
|
||||||
|
Rd = (opCode >> 8) & 0x7;
|
||||||
|
Immediate = ((opCode >> 0) & 0xff) << 2;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
14
ARMeilleure/Decoders/OpCodeT32.cs
Normal file
14
ARMeilleure/Decoders/OpCodeT32.cs
Normal file
@ -0,0 +1,14 @@
|
|||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT32 : OpCode32
|
||||||
|
{
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32(inst, address, opCode);
|
||||||
|
|
||||||
|
public OpCodeT32(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
|
{
|
||||||
|
Cond = Condition.Al;
|
||||||
|
|
||||||
|
OpCodeSizeInBytes = 4;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
20
ARMeilleure/Decoders/OpCodeT32Alu.cs
Normal file
20
ARMeilleure/Decoders/OpCodeT32Alu.cs
Normal file
@ -0,0 +1,20 @@
|
|||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT32Alu : OpCodeT32, IOpCode32Alu
|
||||||
|
{
|
||||||
|
public int Rd { get; }
|
||||||
|
public int Rn { get; }
|
||||||
|
|
||||||
|
public bool? SetFlags { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32Alu(inst, address, opCode);
|
||||||
|
|
||||||
|
public OpCodeT32Alu(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
|
{
|
||||||
|
Rd = (opCode >> 8) & 0xf;
|
||||||
|
Rn = (opCode >> 16) & 0xf;
|
||||||
|
|
||||||
|
SetFlags = ((opCode >> 20) & 1) != 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
38
ARMeilleure/Decoders/OpCodeT32AluImm.cs
Normal file
38
ARMeilleure/Decoders/OpCodeT32AluImm.cs
Normal file
@ -0,0 +1,38 @@
|
|||||||
|
using ARMeilleure.Common;
|
||||||
|
using System.Runtime.Intrinsics;
|
||||||
|
|
||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT32AluImm : OpCodeT32Alu, IOpCode32AluImm
|
||||||
|
{
|
||||||
|
public int Immediate { get; }
|
||||||
|
|
||||||
|
public bool IsRotated { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32AluImm(inst, address, opCode);
|
||||||
|
|
||||||
|
private static readonly Vector128<int> _factor = Vector128.Create(1, 0x00010001, 0x01000100, 0x01010101);
|
||||||
|
|
||||||
|
public OpCodeT32AluImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
|
{
|
||||||
|
int imm8 = (opCode >> 0) & 0xff;
|
||||||
|
int imm3 = (opCode >> 12) & 7;
|
||||||
|
int imm1 = (opCode >> 26) & 1;
|
||||||
|
|
||||||
|
int imm12 = imm8 | (imm3 << 8) | (imm1 << 11);
|
||||||
|
|
||||||
|
if ((imm12 >> 10) == 0)
|
||||||
|
{
|
||||||
|
Immediate = imm8 * _factor.GetElement((imm12 >> 8) & 3);
|
||||||
|
IsRotated = false;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
int shift = imm12 >> 7;
|
||||||
|
|
||||||
|
Immediate = BitUtils.RotateRight(0x80 | (imm12 & 0x7f), shift, 32);
|
||||||
|
IsRotated = shift != 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
20
ARMeilleure/Decoders/OpCodeT32AluRsImm.cs
Normal file
20
ARMeilleure/Decoders/OpCodeT32AluRsImm.cs
Normal file
@ -0,0 +1,20 @@
|
|||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT32AluRsImm : OpCodeT32Alu, IOpCode32AluRsImm
|
||||||
|
{
|
||||||
|
public int Rm { get; }
|
||||||
|
public int Immediate { get; }
|
||||||
|
|
||||||
|
public ShiftType ShiftType { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32AluRsImm(inst, address, opCode);
|
||||||
|
|
||||||
|
public OpCodeT32AluRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
|
{
|
||||||
|
Rm = (opCode >> 0) & 0xf;
|
||||||
|
Immediate = ((opCode >> 6) & 3) | ((opCode >> 10) & 0x1c);
|
||||||
|
|
||||||
|
ShiftType = (ShiftType)((opCode >> 4) & 3);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
29
ARMeilleure/Decoders/OpCodeT32BImm20.cs
Normal file
29
ARMeilleure/Decoders/OpCodeT32BImm20.cs
Normal file
@ -0,0 +1,29 @@
|
|||||||
|
using ARMeilleure.Instructions;
|
||||||
|
|
||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT32BImm20 : OpCodeT32, IOpCode32BImm
|
||||||
|
{
|
||||||
|
public long Immediate { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32BImm20(inst, address, opCode);
|
||||||
|
|
||||||
|
public OpCodeT32BImm20(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
|
{
|
||||||
|
uint pc = GetPc();
|
||||||
|
|
||||||
|
int imm11 = (opCode >> 0) & 0x7ff;
|
||||||
|
int j2 = (opCode >> 11) & 1;
|
||||||
|
int j1 = (opCode >> 13) & 1;
|
||||||
|
int imm6 = (opCode >> 16) & 0x3f;
|
||||||
|
int s = (opCode >> 26) & 1;
|
||||||
|
|
||||||
|
int imm32 = imm11 | (imm6 << 11) | (j1 << 17) | (j2 << 18) | (s << 19);
|
||||||
|
imm32 = (imm32 << 13) >> 12;
|
||||||
|
|
||||||
|
Immediate = pc + imm32;
|
||||||
|
|
||||||
|
Cond = (Condition)((opCode >> 22) & 0xf);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
35
ARMeilleure/Decoders/OpCodeT32BImm24.cs
Normal file
35
ARMeilleure/Decoders/OpCodeT32BImm24.cs
Normal file
@ -0,0 +1,35 @@
|
|||||||
|
using ARMeilleure.Instructions;
|
||||||
|
|
||||||
|
namespace ARMeilleure.Decoders
|
||||||
|
{
|
||||||
|
class OpCodeT32BImm24 : OpCodeT32, IOpCode32BImm
|
||||||
|
{
|
||||||
|
public long Immediate { get; }
|
||||||
|
|
||||||
|
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32BImm24(inst, address, opCode);
|
||||||
|
|
||||||
|
public OpCodeT32BImm24(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||||
|
{
|
||||||
|
uint pc = GetPc();
|
||||||
|
|
||||||
|
if (inst.Name == InstName.Blx)
|
||||||
|
{
|
||||||
|
pc &= ~3u;
|
||||||
|
}
|
||||||
|
|
||||||
|
int imm11 = (opCode >> 0) & 0x7ff;
|
||||||
|
int j2 = (opCode >> 11) & 1;
|
||||||
|
int j1 = (opCode >> 13) & 1;
|
||||||
|
int imm10 = (opCode >> 16) & 0x3ff;
|
||||||
|
int s = (opCode >> 26) & 1;
|
||||||
|
|
||||||
|
int i1 = j1 ^ s ^ 1;
|
||||||
|
int i2 = j2 ^ s ^ 1;
|
||||||
|
|
||||||
|
int imm32 = imm11 | (imm10 << 11) | (i2 << 21) | (i1 << 22) | (s << 23);
|
||||||
|
imm32 = (imm32 << 9) >> 8;
|
||||||
|
|
||||||
|
Immediate = pc + imm32;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
@ -1,7 +1,7 @@
|
|||||||
using ARMeilleure.Instructions;
|
using ARMeilleure.Instructions;
|
||||||
using ARMeilleure.State;
|
|
||||||
using System;
|
using System;
|
||||||
using System.Collections.Generic;
|
using System.Collections.Generic;
|
||||||
|
using System.Numerics;
|
||||||
|
|
||||||
namespace ARMeilleure.Decoders
|
namespace ARMeilleure.Decoders
|
||||||
{
|
{
|
||||||
@ -29,9 +29,9 @@ namespace ARMeilleure.Decoders
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
private static List<InstInfo> AllInstA32 = new List<InstInfo>();
|
private static List<InstInfo> AllInstA32 = new();
|
||||||
private static List<InstInfo> AllInstT32 = new List<InstInfo>();
|
private static List<InstInfo> AllInstT32 = new();
|
||||||
private static List<InstInfo> AllInstA64 = new List<InstInfo>();
|
private static List<InstInfo> AllInstA64 = new();
|
||||||
|
|
||||||
private static InstInfo[][] InstA32FastLookup = new InstInfo[FastLookupSize][];
|
private static InstInfo[][] InstA32FastLookup = new InstInfo[FastLookupSize][];
|
||||||
private static InstInfo[][] InstT32FastLookup = new InstInfo[FastLookupSize][];
|
private static InstInfo[][] InstT32FastLookup = new InstInfo[FastLookupSize][];
|
||||||
@ -628,7 +628,7 @@ namespace ARMeilleure.Decoders
|
|||||||
SetA64("0>001110<<0xxxxx011110xxxxxxxxxx", InstName.Zip2_V, InstEmit.Zip2_V, OpCodeSimdReg.Create);
|
SetA64("0>001110<<0xxxxx011110xxxxxxxxxx", InstName.Zip2_V, InstEmit.Zip2_V, OpCodeSimdReg.Create);
|
||||||
#endregion
|
#endregion
|
||||||
|
|
||||||
#region "OpCode Table (AArch32)"
|
#region "OpCode Table (AArch32, A32)"
|
||||||
// Base
|
// Base
|
||||||
SetA32("<<<<0010101xxxxxxxxxxxxxxxxxxxxx", InstName.Adc, InstEmit32.Adc, OpCode32AluImm.Create);
|
SetA32("<<<<0010101xxxxxxxxxxxxxxxxxxxxx", InstName.Adc, InstEmit32.Adc, OpCode32AluImm.Create);
|
||||||
SetA32("<<<<0000101xxxxxxxxxxxxxxxx0xxxx", InstName.Adc, InstEmit32.Adc, OpCode32AluRsImm.Create);
|
SetA32("<<<<0000101xxxxxxxxxxxxxxxx0xxxx", InstName.Adc, InstEmit32.Adc, OpCode32AluRsImm.Create);
|
||||||
@ -649,7 +649,6 @@ namespace ARMeilleure.Decoders
|
|||||||
SetA32("1111101xxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Blx, InstEmit32.Blx, OpCode32BImm.Create);
|
SetA32("1111101xxxxxxxxxxxxxxxxxxxxxxxxx", InstName.Blx, InstEmit32.Blx, OpCode32BImm.Create);
|
||||||
SetA32("<<<<000100101111111111110011xxxx", InstName.Blx, InstEmit32.Blxr, OpCode32BReg.Create);
|
SetA32("<<<<000100101111111111110011xxxx", InstName.Blx, InstEmit32.Blxr, OpCode32BReg.Create);
|
||||||
SetA32("<<<<000100101111111111110001xxxx", InstName.Bx, InstEmit32.Bx, OpCode32BReg.Create);
|
SetA32("<<<<000100101111111111110001xxxx", InstName.Bx, InstEmit32.Bx, OpCode32BReg.Create);
|
||||||
SetT32("xxxxxxxxxxxxxxxx010001110xxxx000", InstName.Bx, InstEmit32.Bx, OpCodeT16BReg.Create);
|
|
||||||
SetA32("11110101011111111111000000011111", InstName.Clrex, InstEmit32.Clrex, OpCode32.Create);
|
SetA32("11110101011111111111000000011111", InstName.Clrex, InstEmit32.Clrex, OpCode32.Create);
|
||||||
SetA32("<<<<000101101111xxxx11110001xxxx", InstName.Clz, InstEmit32.Clz, OpCode32AluReg.Create);
|
SetA32("<<<<000101101111xxxx11110001xxxx", InstName.Clz, InstEmit32.Clz, OpCode32AluReg.Create);
|
||||||
SetA32("<<<<00110111xxxx0000xxxxxxxxxxxx", InstName.Cmn, InstEmit32.Cmn, OpCode32AluImm.Create);
|
SetA32("<<<<00110111xxxx0000xxxxxxxxxxxx", InstName.Cmn, InstEmit32.Cmn, OpCode32AluImm.Create);
|
||||||
@ -702,7 +701,6 @@ namespace ARMeilleure.Decoders
|
|||||||
SetA32("<<<<0001101x0000xxxxxxxxxxx0xxxx", InstName.Mov, InstEmit32.Mov, OpCode32AluRsImm.Create);
|
SetA32("<<<<0001101x0000xxxxxxxxxxx0xxxx", InstName.Mov, InstEmit32.Mov, OpCode32AluRsImm.Create);
|
||||||
SetA32("<<<<0001101x0000xxxxxxxx0xx1xxxx", InstName.Mov, InstEmit32.Mov, OpCode32AluRsReg.Create);
|
SetA32("<<<<0001101x0000xxxxxxxx0xx1xxxx", InstName.Mov, InstEmit32.Mov, OpCode32AluRsReg.Create);
|
||||||
SetA32("<<<<00110000xxxxxxxxxxxxxxxxxxxx", InstName.Mov, InstEmit32.Mov, OpCode32AluImm16.Create);
|
SetA32("<<<<00110000xxxxxxxxxxxxxxxxxxxx", InstName.Mov, InstEmit32.Mov, OpCode32AluImm16.Create);
|
||||||
SetT32("xxxxxxxxxxxxxxxx00100xxxxxxxxxxx", InstName.Mov, InstEmit32.Mov, OpCodeT16AluImm8.Create);
|
|
||||||
SetA32("<<<<00110100xxxxxxxxxxxxxxxxxxxx", InstName.Movt, InstEmit32.Movt, OpCode32AluImm16.Create);
|
SetA32("<<<<00110100xxxxxxxxxxxxxxxxxxxx", InstName.Movt, InstEmit32.Movt, OpCode32AluImm16.Create);
|
||||||
SetA32("<<<<1110xxx1xxxxxxxx111xxxx1xxxx", InstName.Mrc, InstEmit32.Mrc, OpCode32System.Create);
|
SetA32("<<<<1110xxx1xxxxxxxx111xxxx1xxxx", InstName.Mrc, InstEmit32.Mrc, OpCode32System.Create);
|
||||||
SetA32("<<<<11000101xxxxxxxx111xxxxxxxxx", InstName.Mrrc, InstEmit32.Mrrc, OpCode32System.Create);
|
SetA32("<<<<11000101xxxxxxxx111xxxxxxxxx", InstName.Mrrc, InstEmit32.Mrrc, OpCode32System.Create);
|
||||||
@ -975,12 +973,124 @@ namespace ARMeilleure.Decoders
|
|||||||
SetA32("111100111x11<<10xxxx00011xx0xxxx", InstName.Vzip, InstEmit32.Vzip, OpCode32SimdCmpZ.Create);
|
SetA32("111100111x11<<10xxxx00011xx0xxxx", InstName.Vzip, InstEmit32.Vzip, OpCode32SimdCmpZ.Create);
|
||||||
#endregion
|
#endregion
|
||||||
|
|
||||||
FillFastLookupTable(InstA32FastLookup, AllInstA32);
|
#region "OpCode Table (AArch32, T16)"
|
||||||
FillFastLookupTable(InstT32FastLookup, AllInstT32);
|
SetT16("000<<xxxxxxxxxxx", InstName.Mov, InstEmit32.Mov, OpCodeT16ShiftImm.Create);
|
||||||
FillFastLookupTable(InstA64FastLookup, AllInstA64);
|
SetT16("0001100xxxxxxxxx", InstName.Add, InstEmit32.Add, OpCodeT16AddSubReg.Create);
|
||||||
|
SetT16("0001101xxxxxxxxx", InstName.Sub, InstEmit32.Sub, OpCodeT16AddSubReg.Create);
|
||||||
|
SetT16("0001110xxxxxxxxx", InstName.Add, InstEmit32.Add, OpCodeT16AddSubImm3.Create);
|
||||||
|
SetT16("0001111xxxxxxxxx", InstName.Sub, InstEmit32.Sub, OpCodeT16AddSubImm3.Create);
|
||||||
|
SetT16("00100xxxxxxxxxxx", InstName.Mov, InstEmit32.Mov, OpCodeT16AluImm8.Create);
|
||||||
|
SetT16("00101xxxxxxxxxxx", InstName.Cmp, InstEmit32.Cmp, OpCodeT16AluImm8.Create);
|
||||||
|
SetT16("00110xxxxxxxxxxx", InstName.Add, InstEmit32.Add, OpCodeT16AluImm8.Create);
|
||||||
|
SetT16("00111xxxxxxxxxxx", InstName.Sub, InstEmit32.Sub, OpCodeT16AluImm8.Create);
|
||||||
|
SetT16("0100000000xxxxxx", InstName.And, InstEmit32.And, OpCodeT16AluRegLow.Create);
|
||||||
|
SetT16("0100000001xxxxxx", InstName.Eor, InstEmit32.Eor, OpCodeT16AluRegLow.Create);
|
||||||
|
SetT16("0100000010xxxxxx", InstName.Mov, InstEmit32.Mov, OpCodeT16ShiftReg.Create);
|
||||||
|
SetT16("0100000011xxxxxx", InstName.Mov, InstEmit32.Mov, OpCodeT16ShiftReg.Create);
|
||||||
|
SetT16("0100000100xxxxxx", InstName.Mov, InstEmit32.Mov, OpCodeT16ShiftReg.Create);
|
||||||
|
SetT16("0100000101xxxxxx", InstName.Adc, InstEmit32.Adc, OpCodeT16AluRegLow.Create);
|
||||||
|
SetT16("0100000110xxxxxx", InstName.Sbc, InstEmit32.Sbc, OpCodeT16AluRegLow.Create);
|
||||||
|
SetT16("0100000111xxxxxx", InstName.Mov, InstEmit32.Mov, OpCodeT16ShiftReg.Create);
|
||||||
|
SetT16("0100001000xxxxxx", InstName.Tst, InstEmit32.Tst, OpCodeT16AluRegLow.Create);
|
||||||
|
SetT16("0100001001xxxxxx", InstName.Rsb, InstEmit32.Rsb, OpCodeT16AluImmZero.Create);
|
||||||
|
SetT16("0100001010xxxxxx", InstName.Cmp, InstEmit32.Cmp, OpCodeT16AluRegLow.Create);
|
||||||
|
SetT16("0100001011xxxxxx", InstName.Cmn, InstEmit32.Cmn, OpCodeT16AluRegLow.Create);
|
||||||
|
SetT16("0100001100xxxxxx", InstName.Orr, InstEmit32.Orr, OpCodeT16AluRegLow.Create);
|
||||||
|
SetT16("0100001101xxxxxx", InstName.Mul, InstEmit32.Mul, OpCodeT16AluRegLow.Create);
|
||||||
|
SetT16("0100001110xxxxxx", InstName.Bic, InstEmit32.Bic, OpCodeT16AluRegLow.Create);
|
||||||
|
SetT16("0100001111xxxxxx", InstName.Mvn, InstEmit32.Mvn, OpCodeT16AluRegLow.Create);
|
||||||
|
SetT16("01000100xxxxxxxx", InstName.Add, InstEmit32.Add, OpCodeT16AluRegHigh.Create);
|
||||||
|
SetT16("01000101xxxxxxxx", InstName.Cmp, InstEmit32.Cmp, OpCodeT16AluRegHigh.Create);
|
||||||
|
SetT16("01000110xxxxxxxx", InstName.Mov, InstEmit32.Mov, OpCodeT16AluRegHigh.Create);
|
||||||
|
SetT16("010001110xxxx000", InstName.Bx, InstEmit32.Bx, OpCodeT16BReg.Create);
|
||||||
|
SetT16("010001111xxxx000", InstName.Blx, InstEmit32.Blx, OpCodeT16BReg.Create);
|
||||||
|
SetT16("01001xxxxxxxxxxx", InstName.Ldr, InstEmit32.Ldr, OpCodeT16MemLit.Create);
|
||||||
|
SetT16("0101000xxxxxxxxx", InstName.Str, InstEmit32.Str, OpCodeT16MemReg.Create);
|
||||||
|
SetT16("0101001xxxxxxxxx", InstName.Strh, InstEmit32.Strh, OpCodeT16MemReg.Create);
|
||||||
|
SetT16("0101010xxxxxxxxx", InstName.Strb, InstEmit32.Strb, OpCodeT16MemReg.Create);
|
||||||
|
SetT16("0101011xxxxxxxxx", InstName.Ldrsb, InstEmit32.Ldrsb, OpCodeT16MemReg.Create);
|
||||||
|
SetT16("0101100xxxxxxxxx", InstName.Ldr, InstEmit32.Ldr, OpCodeT16MemReg.Create);
|
||||||
|
SetT16("0101101xxxxxxxxx", InstName.Ldrh, InstEmit32.Ldrh, OpCodeT16MemReg.Create);
|
||||||
|
SetT16("0101110xxxxxxxxx", InstName.Ldrb, InstEmit32.Ldrb, OpCodeT16MemReg.Create);
|
||||||
|
SetT16("0101111xxxxxxxxx", InstName.Ldrsh, InstEmit32.Ldrsh, OpCodeT16MemReg.Create);
|
||||||
|
SetT16("01100xxxxxxxxxxx", InstName.Str, InstEmit32.Str, OpCodeT16MemImm5.Create);
|
||||||
|
SetT16("01101xxxxxxxxxxx", InstName.Ldr, InstEmit32.Ldr, OpCodeT16MemImm5.Create);
|
||||||
|
SetT16("01110xxxxxxxxxxx", InstName.Strb, InstEmit32.Strb, OpCodeT16MemImm5.Create);
|
||||||
|
SetT16("01111xxxxxxxxxxx", InstName.Ldrb, InstEmit32.Ldrb, OpCodeT16MemImm5.Create);
|
||||||
|
SetT16("10000xxxxxxxxxxx", InstName.Strh, InstEmit32.Strh, OpCodeT16MemImm5.Create);
|
||||||
|
SetT16("10001xxxxxxxxxxx", InstName.Ldrh, InstEmit32.Ldrh, OpCodeT16MemImm5.Create);
|
||||||
|
SetT16("10010xxxxxxxxxxx", InstName.Str, InstEmit32.Str, OpCodeT16MemSp.Create);
|
||||||
|
SetT16("10011xxxxxxxxxxx", InstName.Ldr, InstEmit32.Ldr, OpCodeT16MemSp.Create);
|
||||||
|
SetT16("10100xxxxxxxxxxx", InstName.Adr, InstEmit32.Adr, OpCodeT16Adr.Create);
|
||||||
|
SetT16("10101xxxxxxxxxxx", InstName.Add, InstEmit32.Add, OpCodeT16SpRel.Create);
|
||||||
|
SetT16("101100000xxxxxxx", InstName.Add, InstEmit32.Add, OpCodeT16AddSubSp.Create);
|
||||||
|
SetT16("101100001xxxxxxx", InstName.Sub, InstEmit32.Sub, OpCodeT16AddSubSp.Create);
|
||||||
|
SetT16("1011001000xxxxxx", InstName.Sxth, InstEmit32.Sxth, OpCodeT16AluUx.Create);
|
||||||
|
SetT16("1011001001xxxxxx", InstName.Sxtb, InstEmit32.Sxtb, OpCodeT16AluUx.Create);
|
||||||
|
SetT16("1011001010xxxxxx", InstName.Uxth, InstEmit32.Uxth, OpCodeT16AluUx.Create);
|
||||||
|
SetT16("1011001011xxxxxx", InstName.Uxtb, InstEmit32.Uxtb, OpCodeT16AluUx.Create);
|
||||||
|
SetT16("101100x1xxxxxxxx", InstName.Cbz, InstEmit32.Cbz, OpCodeT16BImmCmp.Create);
|
||||||
|
SetT16("1011010xxxxxxxxx", InstName.Push, InstEmit32.Stm, OpCodeT16MemStack.Create);
|
||||||
|
SetT16("1011101000xxxxxx", InstName.Rev, InstEmit32.Rev, OpCodeT16AluRegLow.Create);
|
||||||
|
SetT16("1011101001xxxxxx", InstName.Rev16, InstEmit32.Rev16, OpCodeT16AluRegLow.Create);
|
||||||
|
SetT16("1011101011xxxxxx", InstName.Revsh, InstEmit32.Revsh, OpCodeT16AluRegLow.Create);
|
||||||
|
SetT16("101110x1xxxxxxxx", InstName.Cbnz, InstEmit32.Cbnz, OpCodeT16BImmCmp.Create);
|
||||||
|
SetT16("1011110xxxxxxxxx", InstName.Pop, InstEmit32.Ldm, OpCodeT16MemStack.Create);
|
||||||
|
SetT16("10111111xxxx0000", InstName.Nop, InstEmit32.Nop, OpCodeT16.Create);
|
||||||
|
SetT16("10111111xxxx>>>>", InstName.It, InstEmit32.It, OpCodeT16IfThen.Create);
|
||||||
|
SetT16("11000xxxxxxxxxxx", InstName.Stm, InstEmit32.Stm, OpCodeT16MemMult.Create);
|
||||||
|
SetT16("11001xxxxxxxxxxx", InstName.Ldm, InstEmit32.Ldm, OpCodeT16MemMult.Create);
|
||||||
|
SetT16("1101<<<xxxxxxxxx", InstName.B, InstEmit32.B, OpCodeT16BImm8.Create);
|
||||||
|
SetT16("11011111xxxxxxxx", InstName.Svc, InstEmit32.Svc, OpCodeT16Exception.Create);
|
||||||
|
SetT16("11100xxxxxxxxxxx", InstName.B, InstEmit32.B, OpCodeT16BImm11.Create);
|
||||||
|
#endregion
|
||||||
|
|
||||||
|
#region "OpCode Table (AArch32, T32)"
|
||||||
|
// Base
|
||||||
|
SetT32("11101011010xxxxx0xxxxxxxxxxxxxxx", InstName.Adc, InstEmit32.Adc, OpCodeT32AluRsImm.Create);
|
||||||
|
SetT32("11110x01010xxxxx0xxxxxxxxxxxxxxx", InstName.Adc, InstEmit32.Adc, OpCodeT32AluImm.Create);
|
||||||
|
SetT32("11101011000<xxxx0xxx<<<<xxxxxxxx", InstName.Add, InstEmit32.Add, OpCodeT32AluRsImm.Create);
|
||||||
|
SetT32("11110x01000<xxxx0xxx<<<<xxxxxxxx", InstName.Add, InstEmit32.Add, OpCodeT32AluImm.Create);
|
||||||
|
SetT32("11101010000<xxxx0xxx<<<<xxxxxxxx", InstName.And, InstEmit32.And, OpCodeT32AluRsImm.Create);
|
||||||
|
SetT32("11110x00000<xxxx0xxx<<<<xxxxxxxx", InstName.And, InstEmit32.And, OpCodeT32AluImm.Create);
|
||||||
|
SetT32("11110x<<<xxxxxxx10x0xxxxxxxxxxxx", InstName.B, InstEmit32.B, OpCodeT32BImm20.Create);
|
||||||
|
SetT32("11110xxxxxxxxxxx10x1xxxxxxxxxxxx", InstName.B, InstEmit32.B, OpCodeT32BImm24.Create);
|
||||||
|
SetT32("11101010001xxxxx0xxxxxxxxxxxxxxx", InstName.Bic, InstEmit32.Bic, OpCodeT32AluRsImm.Create);
|
||||||
|
SetT32("11110x00001xxxxx0xxxxxxxxxxxxxxx", InstName.Bic, InstEmit32.Bic, OpCodeT32AluImm.Create);
|
||||||
|
SetT32("11110xxxxxxxxxxx11x1xxxxxxxxxxxx", InstName.Bl, InstEmit32.Bl, OpCodeT32BImm24.Create);
|
||||||
|
SetT32("11110xxxxxxxxxxx11x0xxxxxxxxxxx0", InstName.Blx, InstEmit32.Blx, OpCodeT32BImm24.Create);
|
||||||
|
SetT32("111010110001xxxx0xxx1111xxxxxxxx", InstName.Cmn, InstEmit32.Cmn, OpCodeT32AluRsImm.Create);
|
||||||
|
SetT32("11110x010001xxxx0xxx1111xxxxxxxx", InstName.Cmn, InstEmit32.Cmn, OpCodeT32AluImm.Create);
|
||||||
|
SetT32("111010111011xxxx0xxx1111xxxxxxxx", InstName.Cmp, InstEmit32.Cmp, OpCodeT32AluRsImm.Create);
|
||||||
|
SetT32("11110x011011xxxx0xxx1111xxxxxxxx", InstName.Cmp, InstEmit32.Cmp, OpCodeT32AluImm.Create);
|
||||||
|
SetT32("11101010100<xxxx0xxx<<<<xxxxxxxx", InstName.Eor, InstEmit32.Eor, OpCodeT32AluRsImm.Create);
|
||||||
|
SetT32("11110x00100<xxxx0xxx<<<<xxxxxxxx", InstName.Eor, InstEmit32.Eor, OpCodeT32AluImm.Create);
|
||||||
|
SetT32("11101010010x11110xxxxxxxxxxxxxxx", InstName.Mov, InstEmit32.Mov, OpCodeT32AluRsImm.Create);
|
||||||
|
SetT32("11110x00010x11110xxxxxxxxxxxxxxx", InstName.Mov, InstEmit32.Mov, OpCodeT32AluImm.Create);
|
||||||
|
SetT32("11101010011x11110xxxxxxxxxxxxxxx", InstName.Mvn, InstEmit32.Mvn, OpCodeT32AluRsImm.Create);
|
||||||
|
SetT32("11110x00011x11110xxxxxxxxxxxxxxx", InstName.Mvn, InstEmit32.Mvn, OpCodeT32AluImm.Create);
|
||||||
|
SetT32("11101010011x<<<<0xxxxxxxxxxxxxxx", InstName.Orn, InstEmit32.Orn, OpCodeT32AluRsImm.Create);
|
||||||
|
SetT32("11110x00011x<<<<0xxxxxxxxxxxxxxx", InstName.Orn, InstEmit32.Orn, OpCodeT32AluImm.Create);
|
||||||
|
SetT32("11101010010x<<<<0xxxxxxxxxxxxxxx", InstName.Orr, InstEmit32.Orr, OpCodeT32AluRsImm.Create);
|
||||||
|
SetT32("11110x00010x<<<<0xxxxxxxxxxxxxxx", InstName.Orr, InstEmit32.Orr, OpCodeT32AluImm.Create);
|
||||||
|
SetT32("11101011110xxxxx0xxxxxxxxxxxxxxx", InstName.Rsb, InstEmit32.Rsb, OpCodeT32AluRsImm.Create);
|
||||||
|
SetT32("11110x01110xxxxx0xxxxxxxxxxxxxxx", InstName.Rsb, InstEmit32.Rsb, OpCodeT32AluImm.Create);
|
||||||
|
SetT32("11101011011xxxxx0xxxxxxxxxxxxxxx", InstName.Sbc, InstEmit32.Sbc, OpCodeT32AluRsImm.Create);
|
||||||
|
SetT32("11110x01011xxxxx0xxxxxxxxxxxxxxx", InstName.Sbc, InstEmit32.Sbc, OpCodeT32AluImm.Create);
|
||||||
|
SetT32("11101011101<xxxx0xxx<<<<xxxxxxxx", InstName.Sub, InstEmit32.Sub, OpCodeT32AluRsImm.Create);
|
||||||
|
SetT32("11110x01101<xxxx0xxx<<<<xxxxxxxx", InstName.Sub, InstEmit32.Sub, OpCodeT32AluImm.Create);
|
||||||
|
SetT32("111010101001xxxx0xxx1111xxxxxxxx", InstName.Teq, InstEmit32.Teq, OpCodeT32AluRsImm.Create);
|
||||||
|
SetT32("11110x001001xxxx0xxx1111xxxxxxxx", InstName.Teq, InstEmit32.Teq, OpCodeT32AluImm.Create);
|
||||||
|
SetT32("111010100001xxxx0xxx1111xxxxxxxx", InstName.Tst, InstEmit32.Tst, OpCodeT32AluRsImm.Create);
|
||||||
|
SetT32("11110x000001xxxx0xxx1111xxxxxxxx", InstName.Tst, InstEmit32.Tst, OpCodeT32AluImm.Create);
|
||||||
|
#endregion
|
||||||
|
|
||||||
|
FillFastLookupTable(InstA32FastLookup, AllInstA32, ToFastLookupIndexA);
|
||||||
|
FillFastLookupTable(InstT32FastLookup, AllInstT32, ToFastLookupIndexT);
|
||||||
|
FillFastLookupTable(InstA64FastLookup, AllInstA64, ToFastLookupIndexA);
|
||||||
}
|
}
|
||||||
|
|
||||||
private static void FillFastLookupTable(InstInfo[][] table, List<InstInfo> allInsts)
|
private static void FillFastLookupTable(InstInfo[][] table, List<InstInfo> allInsts, Func<int, int> ToFastLookupIndex)
|
||||||
{
|
{
|
||||||
List<InstInfo>[] temp = new List<InstInfo>[FastLookupSize];
|
List<InstInfo>[] temp = new List<InstInfo>[FastLookupSize];
|
||||||
|
|
||||||
@ -1011,20 +1121,30 @@ namespace ARMeilleure.Decoders
|
|||||||
|
|
||||||
private static void SetA32(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp)
|
private static void SetA32(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp)
|
||||||
{
|
{
|
||||||
Set(encoding, ExecutionMode.Aarch32Arm, new InstDescriptor(name, emitter), makeOp);
|
Set(encoding, AllInstA32, new InstDescriptor(name, emitter), makeOp);
|
||||||
|
}
|
||||||
|
|
||||||
|
private static void SetT16(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp)
|
||||||
|
{
|
||||||
|
encoding = "xxxxxxxxxxxxxxxx" + encoding;
|
||||||
|
Set(encoding, AllInstT32, new InstDescriptor(name, emitter), makeOp);
|
||||||
}
|
}
|
||||||
|
|
||||||
private static void SetT32(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp)
|
private static void SetT32(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp)
|
||||||
{
|
{
|
||||||
Set(encoding, ExecutionMode.Aarch32Thumb, new InstDescriptor(name, emitter), makeOp);
|
string reversedEncoding = encoding.Substring(16) + encoding.Substring(0, 16);
|
||||||
|
MakeOp reversedMakeOp =
|
||||||
|
(InstDescriptor inst, ulong address, int opCode)
|
||||||
|
=> makeOp(inst, address, (int)BitOperations.RotateRight((uint)opCode, 16));
|
||||||
|
Set(reversedEncoding, AllInstT32, new InstDescriptor(name, emitter), reversedMakeOp);
|
||||||
}
|
}
|
||||||
|
|
||||||
private static void SetA64(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp)
|
private static void SetA64(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp)
|
||||||
{
|
{
|
||||||
Set(encoding, ExecutionMode.Aarch64, new InstDescriptor(name, emitter), makeOp);
|
Set(encoding, AllInstA64, new InstDescriptor(name, emitter), makeOp);
|
||||||
}
|
}
|
||||||
|
|
||||||
private static void Set(string encoding, ExecutionMode mode, InstDescriptor inst, MakeOp makeOp)
|
private static void Set(string encoding, List<InstInfo> list, InstDescriptor inst, MakeOp makeOp)
|
||||||
{
|
{
|
||||||
int bit = encoding.Length - 1;
|
int bit = encoding.Length - 1;
|
||||||
int value = 0;
|
int value = 0;
|
||||||
@ -1073,7 +1193,7 @@ namespace ARMeilleure.Decoders
|
|||||||
|
|
||||||
if (xBits == 0)
|
if (xBits == 0)
|
||||||
{
|
{
|
||||||
InsertInst(new InstInfo(xMask, value, inst, makeOp), mode);
|
list.Add(new InstInfo(xMask, value, inst, makeOp));
|
||||||
|
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
@ -1089,34 +1209,24 @@ namespace ARMeilleure.Decoders
|
|||||||
|
|
||||||
if (mask != blacklisted)
|
if (mask != blacklisted)
|
||||||
{
|
{
|
||||||
InsertInst(new InstInfo(xMask, value | mask, inst, makeOp), mode);
|
list.Add(new InstInfo(xMask, value | mask, inst, makeOp));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
private static void InsertInst(InstInfo info, ExecutionMode mode)
|
|
||||||
{
|
|
||||||
switch (mode)
|
|
||||||
{
|
|
||||||
case ExecutionMode.Aarch32Arm: AllInstA32.Add(info); break;
|
|
||||||
case ExecutionMode.Aarch32Thumb: AllInstT32.Add(info); break;
|
|
||||||
case ExecutionMode.Aarch64: AllInstA64.Add(info); break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
public static (InstDescriptor inst, MakeOp makeOp) GetInstA32(int opCode)
|
public static (InstDescriptor inst, MakeOp makeOp) GetInstA32(int opCode)
|
||||||
{
|
{
|
||||||
return GetInstFromList(InstA32FastLookup[ToFastLookupIndex(opCode)], opCode);
|
return GetInstFromList(InstA32FastLookup[ToFastLookupIndexA(opCode)], opCode);
|
||||||
}
|
}
|
||||||
|
|
||||||
public static (InstDescriptor inst, MakeOp makeOp) GetInstT32(int opCode)
|
public static (InstDescriptor inst, MakeOp makeOp) GetInstT32(int opCode)
|
||||||
{
|
{
|
||||||
return GetInstFromList(InstT32FastLookup[ToFastLookupIndex(opCode)], opCode);
|
return GetInstFromList(InstT32FastLookup[ToFastLookupIndexT(opCode)], opCode);
|
||||||
}
|
}
|
||||||
|
|
||||||
public static (InstDescriptor inst, MakeOp makeOp) GetInstA64(int opCode)
|
public static (InstDescriptor inst, MakeOp makeOp) GetInstA64(int opCode)
|
||||||
{
|
{
|
||||||
return GetInstFromList(InstA64FastLookup[ToFastLookupIndex(opCode)], opCode);
|
return GetInstFromList(InstA64FastLookup[ToFastLookupIndexA(opCode)], opCode);
|
||||||
}
|
}
|
||||||
|
|
||||||
private static (InstDescriptor inst, MakeOp makeOp) GetInstFromList(InstInfo[] insts, int opCode)
|
private static (InstDescriptor inst, MakeOp makeOp) GetInstFromList(InstInfo[] insts, int opCode)
|
||||||
@ -1132,9 +1242,14 @@ namespace ARMeilleure.Decoders
|
|||||||
return (new InstDescriptor(InstName.Und, InstEmit.Und), null);
|
return (new InstDescriptor(InstName.Und, InstEmit.Und), null);
|
||||||
}
|
}
|
||||||
|
|
||||||
private static int ToFastLookupIndex(int value)
|
private static int ToFastLookupIndexA(int value)
|
||||||
{
|
{
|
||||||
return ((value >> 10) & 0x00F) | ((value >> 18) & 0xFF0);
|
return ((value >> 10) & 0x00F) | ((value >> 18) & 0xFF0);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
private static int ToFastLookupIndexT(int value)
|
||||||
|
{
|
||||||
|
return (value >> 4) & 0xFFF;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -20,7 +20,7 @@ namespace ARMeilleure.Instructions
|
|||||||
|
|
||||||
Operand res = context.Add(n, m);
|
Operand res = context.Add(n, m);
|
||||||
|
|
||||||
if (op.SetFlags)
|
if (ShouldSetFlags(context))
|
||||||
{
|
{
|
||||||
EmitNZFlagsCheck(context, res);
|
EmitNZFlagsCheck(context, res);
|
||||||
|
|
||||||
@ -44,7 +44,7 @@ namespace ARMeilleure.Instructions
|
|||||||
|
|
||||||
res = context.Add(res, carry);
|
res = context.Add(res, carry);
|
||||||
|
|
||||||
if (op.SetFlags)
|
if (ShouldSetFlags(context))
|
||||||
{
|
{
|
||||||
EmitNZFlagsCheck(context, res);
|
EmitNZFlagsCheck(context, res);
|
||||||
|
|
||||||
@ -64,7 +64,7 @@ namespace ARMeilleure.Instructions
|
|||||||
|
|
||||||
Operand res = context.BitwiseAnd(n, m);
|
Operand res = context.BitwiseAnd(n, m);
|
||||||
|
|
||||||
if (op.SetFlags)
|
if (ShouldSetFlags(context))
|
||||||
{
|
{
|
||||||
EmitNZFlagsCheck(context, res);
|
EmitNZFlagsCheck(context, res);
|
||||||
}
|
}
|
||||||
@ -110,7 +110,7 @@ namespace ARMeilleure.Instructions
|
|||||||
|
|
||||||
Operand res = context.BitwiseAnd(n, context.BitwiseNot(m));
|
Operand res = context.BitwiseAnd(n, context.BitwiseNot(m));
|
||||||
|
|
||||||
if (op.SetFlags)
|
if (ShouldSetFlags(context))
|
||||||
{
|
{
|
||||||
EmitNZFlagsCheck(context, res);
|
EmitNZFlagsCheck(context, res);
|
||||||
}
|
}
|
||||||
@ -161,7 +161,7 @@ namespace ARMeilleure.Instructions
|
|||||||
|
|
||||||
Operand res = context.BitwiseExclusiveOr(n, m);
|
Operand res = context.BitwiseExclusiveOr(n, m);
|
||||||
|
|
||||||
if (op.SetFlags)
|
if (ShouldSetFlags(context))
|
||||||
{
|
{
|
||||||
EmitNZFlagsCheck(context, res);
|
EmitNZFlagsCheck(context, res);
|
||||||
}
|
}
|
||||||
@ -175,7 +175,7 @@ namespace ARMeilleure.Instructions
|
|||||||
|
|
||||||
Operand m = GetAluM(context);
|
Operand m = GetAluM(context);
|
||||||
|
|
||||||
if (op.SetFlags)
|
if (ShouldSetFlags(context))
|
||||||
{
|
{
|
||||||
EmitNZFlagsCheck(context, m);
|
EmitNZFlagsCheck(context, m);
|
||||||
}
|
}
|
||||||
@ -204,7 +204,7 @@ namespace ARMeilleure.Instructions
|
|||||||
|
|
||||||
Operand res = context.Multiply(n, m);
|
Operand res = context.Multiply(n, m);
|
||||||
|
|
||||||
if (op.SetFlags)
|
if (ShouldSetFlags(context))
|
||||||
{
|
{
|
||||||
EmitNZFlagsCheck(context, res);
|
EmitNZFlagsCheck(context, res);
|
||||||
}
|
}
|
||||||
@ -219,7 +219,7 @@ namespace ARMeilleure.Instructions
|
|||||||
|
|
||||||
Operand res = context.BitwiseNot(m);
|
Operand res = context.BitwiseNot(m);
|
||||||
|
|
||||||
if (op.SetFlags)
|
if (ShouldSetFlags(context))
|
||||||
{
|
{
|
||||||
EmitNZFlagsCheck(context, res);
|
EmitNZFlagsCheck(context, res);
|
||||||
}
|
}
|
||||||
@ -236,7 +236,24 @@ namespace ARMeilleure.Instructions
|
|||||||
|
|
||||||
Operand res = context.BitwiseOr(n, m);
|
Operand res = context.BitwiseOr(n, m);
|
||||||
|
|
||||||
if (op.SetFlags)
|
if (ShouldSetFlags(context))
|
||||||
|
{
|
||||||
|
EmitNZFlagsCheck(context, res);
|
||||||
|
}
|
||||||
|
|
||||||
|
EmitAluStore(context, res);
|
||||||
|
}
|
||||||
|
|
||||||
|
public static void Orn(ArmEmitterContext context)
|
||||||
|
{
|
||||||
|
IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
|
||||||
|
|
||||||
|
Operand n = GetAluN(context);
|
||||||
|
Operand m = GetAluM(context);
|
||||||
|
|
||||||
|
Operand res = context.BitwiseOr(n, context.BitwiseNot(m));
|
||||||
|
|
||||||
|
if (ShouldSetFlags(context))
|
||||||
{
|
{
|
||||||
EmitNZFlagsCheck(context, res);
|
EmitNZFlagsCheck(context, res);
|
||||||
}
|
}
|
||||||
@ -315,7 +332,7 @@ namespace ARMeilleure.Instructions
|
|||||||
|
|
||||||
res = context.Subtract(res, borrow);
|
res = context.Subtract(res, borrow);
|
||||||
|
|
||||||
if (op.SetFlags)
|
if (ShouldSetFlags(context))
|
||||||
{
|
{
|
||||||
EmitNZFlagsCheck(context, res);
|
EmitNZFlagsCheck(context, res);
|
||||||
|
|
||||||
@ -335,7 +352,7 @@ namespace ARMeilleure.Instructions
|
|||||||
|
|
||||||
Operand res = context.Subtract(m, n);
|
Operand res = context.Subtract(m, n);
|
||||||
|
|
||||||
if (op.SetFlags)
|
if (ShouldSetFlags(context))
|
||||||
{
|
{
|
||||||
EmitNZFlagsCheck(context, res);
|
EmitNZFlagsCheck(context, res);
|
||||||
|
|
||||||
@ -359,7 +376,7 @@ namespace ARMeilleure.Instructions
|
|||||||
|
|
||||||
res = context.Subtract(res, borrow);
|
res = context.Subtract(res, borrow);
|
||||||
|
|
||||||
if (op.SetFlags)
|
if (ShouldSetFlags(context))
|
||||||
{
|
{
|
||||||
EmitNZFlagsCheck(context, res);
|
EmitNZFlagsCheck(context, res);
|
||||||
|
|
||||||
@ -420,7 +437,7 @@ namespace ARMeilleure.Instructions
|
|||||||
|
|
||||||
Operand res = context.Subtract(n, m);
|
Operand res = context.Subtract(n, m);
|
||||||
|
|
||||||
if (op.SetFlags)
|
if (ShouldSetFlags(context))
|
||||||
{
|
{
|
||||||
EmitNZFlagsCheck(context, res);
|
EmitNZFlagsCheck(context, res);
|
||||||
|
|
||||||
@ -836,7 +853,7 @@ namespace ARMeilleure.Instructions
|
|||||||
{
|
{
|
||||||
IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
|
IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
|
||||||
|
|
||||||
EmitGenericAluStoreA32(context, op.Rd, op.SetFlags, value);
|
EmitGenericAluStoreA32(context, op.Rd, ShouldSetFlags(context), value);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -12,6 +12,18 @@ namespace ARMeilleure.Instructions
|
|||||||
{
|
{
|
||||||
static class InstEmitAluHelper
|
static class InstEmitAluHelper
|
||||||
{
|
{
|
||||||
|
public static bool ShouldSetFlags(ArmEmitterContext context)
|
||||||
|
{
|
||||||
|
IOpCode32HasSetFlags op = (IOpCode32HasSetFlags)context.CurrOp;
|
||||||
|
|
||||||
|
if (op.SetFlags == null)
|
||||||
|
{
|
||||||
|
return !context.IsInIfThenBlock;
|
||||||
|
}
|
||||||
|
|
||||||
|
return op.SetFlags.Value;
|
||||||
|
}
|
||||||
|
|
||||||
public static void EmitNZFlagsCheck(ArmEmitterContext context, Operand d)
|
public static void EmitNZFlagsCheck(ArmEmitterContext context, Operand d)
|
||||||
{
|
{
|
||||||
SetFlag(context, PState.NFlag, context.ICompareLess (d, Const(d.Type, 0)));
|
SetFlag(context, PState.NFlag, context.ICompareLess (d, Const(d.Type, 0)));
|
||||||
@ -116,7 +128,7 @@ namespace ARMeilleure.Instructions
|
|||||||
{
|
{
|
||||||
Debug.Assert(value.Type == OperandType.I32);
|
Debug.Assert(value.Type == OperandType.I32);
|
||||||
|
|
||||||
if (IsThumb(context.CurrOp))
|
if (((OpCode32)context.CurrOp).IsThumb())
|
||||||
{
|
{
|
||||||
bool isReturn = IsA32Return(context);
|
bool isReturn = IsA32Return(context);
|
||||||
if (!isReturn)
|
if (!isReturn)
|
||||||
@ -183,9 +195,9 @@ namespace ARMeilleure.Instructions
|
|||||||
switch (context.CurrOp)
|
switch (context.CurrOp)
|
||||||
{
|
{
|
||||||
// ARM32.
|
// ARM32.
|
||||||
case OpCode32AluImm op:
|
case IOpCode32AluImm op:
|
||||||
{
|
{
|
||||||
if (op.SetFlags && op.IsRotated)
|
if (ShouldSetFlags(context) && op.IsRotated && setCarry)
|
||||||
{
|
{
|
||||||
SetFlag(context, PState.CFlag, Const((uint)op.Immediate >> 31));
|
SetFlag(context, PState.CFlag, Const((uint)op.Immediate >> 31));
|
||||||
}
|
}
|
||||||
@ -195,10 +207,8 @@ namespace ARMeilleure.Instructions
|
|||||||
|
|
||||||
case OpCode32AluImm16 op: return Const(op.Immediate);
|
case OpCode32AluImm16 op: return Const(op.Immediate);
|
||||||
|
|
||||||
case OpCode32AluRsImm op: return GetMShiftedByImmediate(context, op, setCarry);
|
case IOpCode32AluRsImm op: return GetMShiftedByImmediate(context, op, setCarry);
|
||||||
case OpCode32AluRsReg op: return GetMShiftedByReg(context, op, setCarry);
|
case IOpCode32AluRsReg op: return GetMShiftedByReg(context, op, setCarry);
|
||||||
|
|
||||||
case OpCodeT16AluImm8 op: return Const(op.Immediate);
|
|
||||||
|
|
||||||
case IOpCode32AluReg op: return GetIntA32(context, op.Rm);
|
case IOpCode32AluReg op: return GetIntA32(context, op.Rm);
|
||||||
|
|
||||||
@ -249,7 +259,7 @@ namespace ARMeilleure.Instructions
|
|||||||
}
|
}
|
||||||
|
|
||||||
// ARM32 helpers.
|
// ARM32 helpers.
|
||||||
public static Operand GetMShiftedByImmediate(ArmEmitterContext context, OpCode32AluRsImm op, bool setCarry)
|
public static Operand GetMShiftedByImmediate(ArmEmitterContext context, IOpCode32AluRsImm op, bool setCarry)
|
||||||
{
|
{
|
||||||
Operand m = GetIntA32(context, op.Rm);
|
Operand m = GetIntA32(context, op.Rm);
|
||||||
|
|
||||||
@ -267,7 +277,7 @@ namespace ARMeilleure.Instructions
|
|||||||
|
|
||||||
if (shift != 0)
|
if (shift != 0)
|
||||||
{
|
{
|
||||||
setCarry &= op.SetFlags;
|
setCarry &= ShouldSetFlags(context);
|
||||||
|
|
||||||
switch (op.ShiftType)
|
switch (op.ShiftType)
|
||||||
{
|
{
|
||||||
@ -305,7 +315,7 @@ namespace ARMeilleure.Instructions
|
|||||||
return shift;
|
return shift;
|
||||||
}
|
}
|
||||||
|
|
||||||
public static Operand GetMShiftedByReg(ArmEmitterContext context, OpCode32AluRsReg op, bool setCarry)
|
public static Operand GetMShiftedByReg(ArmEmitterContext context, IOpCode32AluRsReg op, bool setCarry)
|
||||||
{
|
{
|
||||||
Operand m = GetIntA32(context, op.Rm);
|
Operand m = GetIntA32(context, op.Rm);
|
||||||
Operand s = context.ZeroExtend8(OperandType.I32, GetIntA32(context, op.Rs));
|
Operand s = context.ZeroExtend8(OperandType.I32, GetIntA32(context, op.Rs));
|
||||||
@ -314,7 +324,7 @@ namespace ARMeilleure.Instructions
|
|||||||
Operand zeroResult = m;
|
Operand zeroResult = m;
|
||||||
Operand shiftResult = m;
|
Operand shiftResult = m;
|
||||||
|
|
||||||
setCarry &= op.SetFlags;
|
setCarry &= ShouldSetFlags(context);
|
||||||
|
|
||||||
switch (op.ShiftType)
|
switch (op.ShiftType)
|
||||||
{
|
{
|
||||||
|
@ -9,18 +9,25 @@ namespace ARMeilleure.Instructions
|
|||||||
{
|
{
|
||||||
public static void Brk(ArmEmitterContext context)
|
public static void Brk(ArmEmitterContext context)
|
||||||
{
|
{
|
||||||
EmitExceptionCall(context, nameof(NativeInterface.Break));
|
OpCodeException op = (OpCodeException)context.CurrOp;
|
||||||
|
|
||||||
|
string name = nameof(NativeInterface.Break);
|
||||||
|
|
||||||
|
context.StoreToContext();
|
||||||
|
|
||||||
|
context.Call(typeof(NativeInterface).GetMethod(name), Const(op.Address), Const(op.Id));
|
||||||
|
|
||||||
|
context.LoadFromContext();
|
||||||
|
|
||||||
|
context.Return(Const(op.Address));
|
||||||
}
|
}
|
||||||
|
|
||||||
public static void Svc(ArmEmitterContext context)
|
public static void Svc(ArmEmitterContext context)
|
||||||
{
|
|
||||||
EmitExceptionCall(context, nameof(NativeInterface.SupervisorCall));
|
|
||||||
}
|
|
||||||
|
|
||||||
private static void EmitExceptionCall(ArmEmitterContext context, string name)
|
|
||||||
{
|
{
|
||||||
OpCodeException op = (OpCodeException)context.CurrOp;
|
OpCodeException op = (OpCodeException)context.CurrOp;
|
||||||
|
|
||||||
|
string name = nameof(NativeInterface.SupervisorCall);
|
||||||
|
|
||||||
context.StoreToContext();
|
context.StoreToContext();
|
||||||
|
|
||||||
context.Call(typeof(NativeInterface).GetMethod(name), Const(op.Address), Const(op.Id));
|
context.Call(typeof(NativeInterface).GetMethod(name), Const(op.Address), Const(op.Id));
|
||||||
@ -41,6 +48,8 @@ namespace ARMeilleure.Instructions
|
|||||||
context.Call(typeof(NativeInterface).GetMethod(name), Const(op.Address), Const(op.RawOpCode));
|
context.Call(typeof(NativeInterface).GetMethod(name), Const(op.Address), Const(op.RawOpCode));
|
||||||
|
|
||||||
context.LoadFromContext();
|
context.LoadFromContext();
|
||||||
|
|
||||||
|
context.Return(Const(op.Address));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
@ -10,25 +10,32 @@ namespace ARMeilleure.Instructions
|
|||||||
{
|
{
|
||||||
public static void Svc(ArmEmitterContext context)
|
public static void Svc(ArmEmitterContext context)
|
||||||
{
|
{
|
||||||
EmitExceptionCall(context, nameof(NativeInterface.SupervisorCall));
|
IOpCode32Exception op = (IOpCode32Exception)context.CurrOp;
|
||||||
}
|
|
||||||
|
|
||||||
public static void Trap(ArmEmitterContext context)
|
string name = nameof(NativeInterface.SupervisorCall);
|
||||||
{
|
|
||||||
EmitExceptionCall(context, nameof(NativeInterface.Break));
|
|
||||||
}
|
|
||||||
|
|
||||||
private static void EmitExceptionCall(ArmEmitterContext context, string name)
|
|
||||||
{
|
|
||||||
OpCode32Exception op = (OpCode32Exception)context.CurrOp;
|
|
||||||
|
|
||||||
context.StoreToContext();
|
context.StoreToContext();
|
||||||
|
|
||||||
context.Call(typeof(NativeInterface).GetMethod(name), Const(op.Address), Const(op.Id));
|
context.Call(typeof(NativeInterface).GetMethod(name), Const(((IOpCode)op).Address), Const(op.Id));
|
||||||
|
|
||||||
context.LoadFromContext();
|
context.LoadFromContext();
|
||||||
|
|
||||||
Translator.EmitSynchronization(context);
|
Translator.EmitSynchronization(context);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
public static void Trap(ArmEmitterContext context)
|
||||||
|
{
|
||||||
|
IOpCode32Exception op = (IOpCode32Exception)context.CurrOp;
|
||||||
|
|
||||||
|
string name = nameof(NativeInterface.Break);
|
||||||
|
|
||||||
|
context.StoreToContext();
|
||||||
|
|
||||||
|
context.Call(typeof(NativeInterface).GetMethod(name), Const(((IOpCode)op).Address), Const(op.Id));
|
||||||
|
|
||||||
|
context.LoadFromContext();
|
||||||
|
|
||||||
|
context.Return(Const(context.CurrOp.Address));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -34,7 +34,7 @@ namespace ARMeilleure.Instructions
|
|||||||
|
|
||||||
uint pc = op.GetPc();
|
uint pc = op.GetPc();
|
||||||
|
|
||||||
bool isThumb = IsThumb(context.CurrOp);
|
bool isThumb = ((OpCode32)context.CurrOp).IsThumb();
|
||||||
|
|
||||||
uint currentPc = isThumb
|
uint currentPc = isThumb
|
||||||
? pc | 1
|
? pc | 1
|
||||||
@ -61,17 +61,17 @@ namespace ARMeilleure.Instructions
|
|||||||
Operand addr = context.Copy(GetIntA32(context, op.Rm));
|
Operand addr = context.Copy(GetIntA32(context, op.Rm));
|
||||||
Operand bitOne = context.BitwiseAnd(addr, Const(1));
|
Operand bitOne = context.BitwiseAnd(addr, Const(1));
|
||||||
|
|
||||||
bool isThumb = IsThumb(context.CurrOp);
|
bool isThumb = ((OpCode32)context.CurrOp).IsThumb();
|
||||||
|
|
||||||
uint currentPc = isThumb
|
uint currentPc = isThumb
|
||||||
? pc | 1
|
? (pc - 2) | 1
|
||||||
: pc - 4;
|
: pc - 4;
|
||||||
|
|
||||||
SetIntA32(context, GetBankedRegisterAlias(context.Mode, RegisterAlias.Aarch32Lr), Const(currentPc));
|
SetIntA32(context, GetBankedRegisterAlias(context.Mode, RegisterAlias.Aarch32Lr), Const(currentPc));
|
||||||
|
|
||||||
SetFlag(context, PState.TFlag, bitOne);
|
SetFlag(context, PState.TFlag, bitOne);
|
||||||
|
|
||||||
EmitVirtualCall(context, addr);
|
EmitBxWritePc(context, addr);
|
||||||
}
|
}
|
||||||
|
|
||||||
public static void Bx(ArmEmitterContext context)
|
public static void Bx(ArmEmitterContext context)
|
||||||
@ -80,5 +80,32 @@ namespace ARMeilleure.Instructions
|
|||||||
|
|
||||||
EmitBxWritePc(context, GetIntA32(context, op.Rm), op.Rm);
|
EmitBxWritePc(context, GetIntA32(context, op.Rm), op.Rm);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
public static void Cbnz(ArmEmitterContext context) => EmitCb(context, onNotZero: true);
|
||||||
|
public static void Cbz(ArmEmitterContext context) => EmitCb(context, onNotZero: false);
|
||||||
|
|
||||||
|
private static void EmitCb(ArmEmitterContext context, bool onNotZero)
|
||||||
|
{
|
||||||
|
OpCodeT16BImmCmp op = (OpCodeT16BImmCmp)context.CurrOp;
|
||||||
|
|
||||||
|
Operand value = GetIntOrZR(context, op.Rn);
|
||||||
|
Operand lblTarget = context.GetLabel((ulong)op.Immediate);
|
||||||
|
|
||||||
|
if (onNotZero)
|
||||||
|
{
|
||||||
|
context.BranchIfTrue(lblTarget, value);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
context.BranchIfFalse(lblTarget, value);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
public static void It(ArmEmitterContext context)
|
||||||
|
{
|
||||||
|
OpCodeT16IfThen op = (OpCodeT16IfThen)context.CurrOp;
|
||||||
|
|
||||||
|
context.SetIfThenBlockState(op.IfThenBlockConds);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
@ -10,11 +10,6 @@ namespace ARMeilleure.Instructions
|
|||||||
{
|
{
|
||||||
static class InstEmitHelper
|
static class InstEmitHelper
|
||||||
{
|
{
|
||||||
public static bool IsThumb(OpCode op)
|
|
||||||
{
|
|
||||||
return op is OpCodeT16;
|
|
||||||
}
|
|
||||||
|
|
||||||
public static Operand GetExtendedM(ArmEmitterContext context, int rm, IntType type)
|
public static Operand GetExtendedM(ArmEmitterContext context, int rm, IntType type)
|
||||||
{
|
{
|
||||||
Operand value = GetIntOrZR(context, rm);
|
Operand value = GetIntOrZR(context, rm);
|
||||||
@ -186,7 +181,7 @@ namespace ARMeilleure.Instructions
|
|||||||
|
|
||||||
SetFlag(context, PState.TFlag, mode);
|
SetFlag(context, PState.TFlag, mode);
|
||||||
|
|
||||||
Operand addr = context.ConditionalSelect(mode, pc, context.BitwiseAnd(pc, Const(~3)));
|
Operand addr = context.ConditionalSelect(mode, context.BitwiseAnd(pc, Const(~1)), context.BitwiseAnd(pc, Const(~3)));
|
||||||
|
|
||||||
InstEmitFlowHelper.EmitVirtualJump(context, addr, isReturn);
|
InstEmitFlowHelper.EmitVirtualJump(context, addr, isReturn);
|
||||||
}
|
}
|
||||||
|
@ -32,7 +32,7 @@ namespace ARMeilleure.Instructions
|
|||||||
|
|
||||||
public static void Ldm(ArmEmitterContext context)
|
public static void Ldm(ArmEmitterContext context)
|
||||||
{
|
{
|
||||||
OpCode32MemMult op = (OpCode32MemMult)context.CurrOp;
|
IOpCode32MemMult op = (IOpCode32MemMult)context.CurrOp;
|
||||||
|
|
||||||
Operand n = GetIntA32(context, op.Rn);
|
Operand n = GetIntA32(context, op.Rn);
|
||||||
|
|
||||||
@ -95,7 +95,7 @@ namespace ARMeilleure.Instructions
|
|||||||
|
|
||||||
public static void Stm(ArmEmitterContext context)
|
public static void Stm(ArmEmitterContext context)
|
||||||
{
|
{
|
||||||
OpCode32MemMult op = (OpCode32MemMult)context.CurrOp;
|
IOpCode32MemMult op = (IOpCode32MemMult)context.CurrOp;
|
||||||
|
|
||||||
Operand n = context.Copy(GetIntA32(context, op.Rn));
|
Operand n = context.Copy(GetIntA32(context, op.Rn));
|
||||||
|
|
||||||
@ -151,7 +151,7 @@ namespace ARMeilleure.Instructions
|
|||||||
|
|
||||||
private static void EmitLoadOrStore(ArmEmitterContext context, int size, AccessType accType)
|
private static void EmitLoadOrStore(ArmEmitterContext context, int size, AccessType accType)
|
||||||
{
|
{
|
||||||
OpCode32Mem op = (OpCode32Mem)context.CurrOp;
|
IOpCode32Mem op = (IOpCode32Mem)context.CurrOp;
|
||||||
|
|
||||||
Operand n = context.Copy(GetIntA32AlignedPC(context, op.Rn));
|
Operand n = context.Copy(GetIntA32AlignedPC(context, op.Rn));
|
||||||
Operand m = GetMemM(context, setCarry: false);
|
Operand m = GetMemM(context, setCarry: false);
|
||||||
@ -255,5 +255,11 @@ namespace ARMeilleure.Instructions
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
public static void Adr(ArmEmitterContext context)
|
||||||
|
{
|
||||||
|
IOpCode32Adr op = (IOpCode32Adr)context.CurrOp;
|
||||||
|
SetIntA32(context, op.Rd, Const(op.Immediate));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
@ -549,9 +549,9 @@ namespace ARMeilleure.Instructions
|
|||||||
{
|
{
|
||||||
case OpCode32MemRsImm op: return GetMShiftedByImmediate(context, op, setCarry);
|
case OpCode32MemRsImm op: return GetMShiftedByImmediate(context, op, setCarry);
|
||||||
|
|
||||||
case OpCode32MemReg op: return GetIntA32(context, op.Rm);
|
case IOpCode32MemReg op: return GetIntA32(context, op.Rm);
|
||||||
|
|
||||||
case OpCode32Mem op: return Const(op.Immediate);
|
case IOpCode32Mem op: return Const(op.Immediate);
|
||||||
|
|
||||||
case OpCode32SimdMemImm op: return Const(op.Immediate);
|
case OpCode32SimdMemImm op: return Const(op.Immediate);
|
||||||
|
|
||||||
|
@ -33,7 +33,7 @@ namespace ARMeilleure.Instructions
|
|||||||
|
|
||||||
Operand res = context.Add(a, context.Multiply(n, m));
|
Operand res = context.Add(a, context.Multiply(n, m));
|
||||||
|
|
||||||
if (op.SetFlags)
|
if (ShouldSetFlags(context))
|
||||||
{
|
{
|
||||||
EmitNZFlagsCheck(context, res);
|
EmitNZFlagsCheck(context, res);
|
||||||
}
|
}
|
||||||
@ -250,13 +250,13 @@ namespace ARMeilleure.Instructions
|
|||||||
Operand hi = context.ConvertI64ToI32(context.ShiftRightUI(res, Const(32)));
|
Operand hi = context.ConvertI64ToI32(context.ShiftRightUI(res, Const(32)));
|
||||||
Operand lo = context.ConvertI64ToI32(res);
|
Operand lo = context.ConvertI64ToI32(res);
|
||||||
|
|
||||||
if (op.SetFlags)
|
if (ShouldSetFlags(context))
|
||||||
{
|
{
|
||||||
EmitNZFlagsCheck(context, res);
|
EmitNZFlagsCheck(context, res);
|
||||||
}
|
}
|
||||||
|
|
||||||
EmitGenericAluStoreA32(context, op.RdHi, op.SetFlags, hi);
|
EmitGenericAluStoreA32(context, op.RdHi, ShouldSetFlags(context), hi);
|
||||||
EmitGenericAluStoreA32(context, op.RdLo, op.SetFlags, lo);
|
EmitGenericAluStoreA32(context, op.RdLo, ShouldSetFlags(context), lo);
|
||||||
}
|
}
|
||||||
|
|
||||||
public static void Smulw_(ArmEmitterContext context)
|
public static void Smulw_(ArmEmitterContext context)
|
||||||
@ -320,13 +320,13 @@ namespace ARMeilleure.Instructions
|
|||||||
Operand hi = context.ConvertI64ToI32(context.ShiftRightUI(res, Const(32)));
|
Operand hi = context.ConvertI64ToI32(context.ShiftRightUI(res, Const(32)));
|
||||||
Operand lo = context.ConvertI64ToI32(res);
|
Operand lo = context.ConvertI64ToI32(res);
|
||||||
|
|
||||||
if (op.SetFlags)
|
if (ShouldSetFlags(context))
|
||||||
{
|
{
|
||||||
EmitNZFlagsCheck(context, res);
|
EmitNZFlagsCheck(context, res);
|
||||||
}
|
}
|
||||||
|
|
||||||
EmitGenericAluStoreA32(context, op.RdHi, op.SetFlags, hi);
|
EmitGenericAluStoreA32(context, op.RdHi, ShouldSetFlags(context), hi);
|
||||||
EmitGenericAluStoreA32(context, op.RdLo, op.SetFlags, lo);
|
EmitGenericAluStoreA32(context, op.RdLo, ShouldSetFlags(context), lo);
|
||||||
}
|
}
|
||||||
|
|
||||||
private static void EmitMlal(ArmEmitterContext context, bool signed)
|
private static void EmitMlal(ArmEmitterContext context, bool signed)
|
||||||
@ -356,13 +356,13 @@ namespace ARMeilleure.Instructions
|
|||||||
Operand hi = context.ConvertI64ToI32(context.ShiftRightUI(res, Const(32)));
|
Operand hi = context.ConvertI64ToI32(context.ShiftRightUI(res, Const(32)));
|
||||||
Operand lo = context.ConvertI64ToI32(res);
|
Operand lo = context.ConvertI64ToI32(res);
|
||||||
|
|
||||||
if (op.SetFlags)
|
if (ShouldSetFlags(context))
|
||||||
{
|
{
|
||||||
EmitNZFlagsCheck(context, res);
|
EmitNZFlagsCheck(context, res);
|
||||||
}
|
}
|
||||||
|
|
||||||
EmitGenericAluStoreA32(context, op.RdHi, op.SetFlags, hi);
|
EmitGenericAluStoreA32(context, op.RdHi, ShouldSetFlags(context), hi);
|
||||||
EmitGenericAluStoreA32(context, op.RdLo, op.SetFlags, lo);
|
EmitGenericAluStoreA32(context, op.RdLo, ShouldSetFlags(context), lo);
|
||||||
}
|
}
|
||||||
|
|
||||||
private static void UpdateQFlag(ArmEmitterContext context, Operand q)
|
private static void UpdateQFlag(ArmEmitterContext context, Operand q)
|
||||||
|
@ -12,7 +12,8 @@ namespace ARMeilleure.Instructions
|
|||||||
{
|
{
|
||||||
static partial class InstEmit
|
static partial class InstEmit
|
||||||
{
|
{
|
||||||
private const int DczSizeLog2 = 4;
|
private const int DczSizeLog2 = 4; // Log2 size in words
|
||||||
|
public const int DczSizeInBytes = 4 << DczSizeLog2;
|
||||||
|
|
||||||
public static void Hint(ArmEmitterContext context)
|
public static void Hint(ArmEmitterContext context)
|
||||||
{
|
{
|
||||||
@ -87,7 +88,7 @@ namespace ARMeilleure.Instructions
|
|||||||
// DC ZVA
|
// DC ZVA
|
||||||
Operand t = GetIntOrZR(context, op.Rt);
|
Operand t = GetIntOrZR(context, op.Rt);
|
||||||
|
|
||||||
for (long offset = 0; offset < (4 << DczSizeLog2); offset += 8)
|
for (long offset = 0; offset < DczSizeInBytes; offset += 8)
|
||||||
{
|
{
|
||||||
Operand address = context.Add(t, Const(offset));
|
Operand address = context.Add(t, Const(offset));
|
||||||
|
|
||||||
@ -98,7 +99,12 @@ namespace ARMeilleure.Instructions
|
|||||||
}
|
}
|
||||||
|
|
||||||
// No-op
|
// No-op
|
||||||
case 0b11_011_0111_1110_001: //DC CIVAC
|
case 0b11_011_0111_1110_001: // DC CIVAC
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 0b11_011_0111_0101_001: // IC IVAU
|
||||||
|
Operand target = Register(op.Rt, RegisterType.Integer, OperandType.I64);
|
||||||
|
context.Call(typeof(NativeInterface).GetMethod(nameof(NativeInterface.InvalidateCacheLine)), target);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -48,6 +48,7 @@ namespace ARMeilleure.Instructions
|
|||||||
Extr,
|
Extr,
|
||||||
Hint,
|
Hint,
|
||||||
Isb,
|
Isb,
|
||||||
|
It,
|
||||||
Ldar,
|
Ldar,
|
||||||
Ldaxp,
|
Ldaxp,
|
||||||
Ldaxr,
|
Ldaxr,
|
||||||
@ -512,6 +513,8 @@ namespace ARMeilleure.Instructions
|
|||||||
Mvn,
|
Mvn,
|
||||||
Pkh,
|
Pkh,
|
||||||
Pld,
|
Pld,
|
||||||
|
Pop,
|
||||||
|
Push,
|
||||||
Rev,
|
Rev,
|
||||||
Revsh,
|
Revsh,
|
||||||
Rsb,
|
Rsb,
|
||||||
|
@ -242,6 +242,11 @@ namespace ARMeilleure.Instructions
|
|||||||
return (ulong)function.FuncPtr.ToInt64();
|
return (ulong)function.FuncPtr.ToInt64();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
public static void InvalidateCacheLine(ulong address)
|
||||||
|
{
|
||||||
|
Context.Translator.InvalidateJitCacheRegion(address, InstEmit.DczSizeInBytes);
|
||||||
|
}
|
||||||
|
|
||||||
public static bool CheckSynchronization()
|
public static bool CheckSynchronization()
|
||||||
{
|
{
|
||||||
Statistics.PauseTimer();
|
Statistics.PauseTimer();
|
||||||
|
@ -43,6 +43,12 @@ namespace ARMeilleure.State
|
|||||||
public long TpidrEl0 { get; set; }
|
public long TpidrEl0 { get; set; }
|
||||||
public long Tpidr { get; set; }
|
public long Tpidr { get; set; }
|
||||||
|
|
||||||
|
public uint Pstate
|
||||||
|
{
|
||||||
|
get => _nativeContext.GetPstate();
|
||||||
|
set => _nativeContext.SetPstate(value);
|
||||||
|
}
|
||||||
|
|
||||||
public FPCR Fpcr { get; set; }
|
public FPCR Fpcr { get; set; }
|
||||||
public FPSR Fpsr { get; set; }
|
public FPSR Fpsr { get; set; }
|
||||||
public FPCR StandardFpcrValue => (Fpcr & (FPCR.Ahp)) | FPCR.Dn | FPCR.Fz;
|
public FPCR StandardFpcrValue => (Fpcr & (FPCR.Ahp)) | FPCR.Dn | FPCR.Fz;
|
||||||
|
@ -95,6 +95,25 @@ namespace ARMeilleure.State
|
|||||||
GetStorage().Flags[(int)flag] = value ? 1u : 0u;
|
GetStorage().Flags[(int)flag] = value ? 1u : 0u;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
public unsafe uint GetPstate()
|
||||||
|
{
|
||||||
|
uint value = 0;
|
||||||
|
for (int flag = 0; flag < RegisterConsts.FlagsCount; flag++)
|
||||||
|
{
|
||||||
|
value |= GetStorage().Flags[flag] != 0 ? 1u << flag : 0u;
|
||||||
|
}
|
||||||
|
return value;
|
||||||
|
}
|
||||||
|
|
||||||
|
public unsafe void SetPstate(uint value)
|
||||||
|
{
|
||||||
|
for (int flag = 0; flag < RegisterConsts.FlagsCount; flag++)
|
||||||
|
{
|
||||||
|
uint bit = 1u << flag;
|
||||||
|
GetStorage().Flags[flag] = (value & bit) == bit ? 1u : 0u;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
public unsafe bool GetFPStateFlag(FPState flag)
|
public unsafe bool GetFPStateFlag(FPState flag)
|
||||||
{
|
{
|
||||||
if ((uint)flag >= RegisterConsts.FpFlagsCount)
|
if ((uint)flag >= RegisterConsts.FpFlagsCount)
|
||||||
|
@ -54,6 +54,11 @@ namespace ARMeilleure.Translation
|
|||||||
public bool HighCq { get; }
|
public bool HighCq { get; }
|
||||||
public Aarch32Mode Mode { get; }
|
public Aarch32Mode Mode { get; }
|
||||||
|
|
||||||
|
private int _ifThenBlockStateIndex = 0;
|
||||||
|
private Condition[] _ifThenBlockState = { };
|
||||||
|
public bool IsInIfThenBlock => _ifThenBlockStateIndex < _ifThenBlockState.Length;
|
||||||
|
public Condition CurrentIfThenBlockCond => _ifThenBlockState[_ifThenBlockStateIndex];
|
||||||
|
|
||||||
public ArmEmitterContext(
|
public ArmEmitterContext(
|
||||||
IMemoryManager memory,
|
IMemoryManager memory,
|
||||||
EntryTable<uint> countTable,
|
EntryTable<uint> countTable,
|
||||||
@ -196,5 +201,19 @@ namespace ARMeilleure.Translation
|
|||||||
|
|
||||||
return default;
|
return default;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
public void SetIfThenBlockState(Condition[] state)
|
||||||
|
{
|
||||||
|
_ifThenBlockState = state;
|
||||||
|
_ifThenBlockStateIndex = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
public void AdvanceIfThenBlockState()
|
||||||
|
{
|
||||||
|
if (IsInIfThenBlock)
|
||||||
|
{
|
||||||
|
_ifThenBlockStateIndex++;
|
||||||
|
}
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
@ -114,6 +114,7 @@ namespace ARMeilleure.Translation
|
|||||||
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetFpscr))); // A32 only.
|
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetFpscr))); // A32 only.
|
||||||
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetFpsr)));
|
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetFpsr)));
|
||||||
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetFunctionAddress)));
|
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetFunctionAddress)));
|
||||||
|
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.InvalidateCacheLine)));
|
||||||
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetTpidr)));
|
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetTpidr)));
|
||||||
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetTpidr32))); // A32 only.
|
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetTpidr32))); // A32 only.
|
||||||
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetTpidrEl0)));
|
SetDelegateInfo(typeof(NativeInterface).GetMethod(nameof(NativeInterface.GetTpidrEl0)));
|
||||||
|
756
ARMeilleure/Translation/IntervalTree.cs
Normal file
756
ARMeilleure/Translation/IntervalTree.cs
Normal file
@ -0,0 +1,756 @@
|
|||||||
|
using System;
|
||||||
|
using System.Collections.Generic;
|
||||||
|
|
||||||
|
namespace ARMeilleure.Translation
|
||||||
|
{
|
||||||
|
/// <summary>
|
||||||
|
/// An Augmented Interval Tree based off of the "TreeDictionary"'s Red-Black Tree. Allows fast overlap checking of ranges.
|
||||||
|
/// </summary>
|
||||||
|
/// <typeparam name="K">Key</typeparam>
|
||||||
|
/// <typeparam name="V">Value</typeparam>
|
||||||
|
public class IntervalTree<K, V> where K : IComparable<K>
|
||||||
|
{
|
||||||
|
private const int ArrayGrowthSize = 32;
|
||||||
|
|
||||||
|
private const bool Black = true;
|
||||||
|
private const bool Red = false;
|
||||||
|
private IntervalTreeNode<K, V> _root = null;
|
||||||
|
private int _count = 0;
|
||||||
|
|
||||||
|
public int Count => _count;
|
||||||
|
|
||||||
|
public IntervalTree() { }
|
||||||
|
|
||||||
|
#region Public Methods
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// Gets the values of the interval whose key is <paramref name="key"/>.
|
||||||
|
/// </summary>
|
||||||
|
/// <param name="key">Key of the node value to get</param>
|
||||||
|
/// <param name="value">Value with the given <paramref name="key"/></param>
|
||||||
|
/// <returns>True if the key is on the dictionary, false otherwise</returns>
|
||||||
|
public bool TryGet(K key, out V value)
|
||||||
|
{
|
||||||
|
IntervalTreeNode<K, V> node = GetNode(key);
|
||||||
|
|
||||||
|
if (node == null)
|
||||||
|
{
|
||||||
|
value = default;
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
value = node.Value;
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// Returns the start addresses of the intervals whose start and end keys overlap the given range.
|
||||||
|
/// </summary>
|
||||||
|
/// <param name="start">Start of the range</param>
|
||||||
|
/// <param name="end">End of the range</param>
|
||||||
|
/// <param name="overlaps">Overlaps array to place results in</param>
|
||||||
|
/// <param name="overlapCount">Index to start writing results into the array. Defaults to 0</param>
|
||||||
|
/// <returns>Number of intervals found</returns>
|
||||||
|
public int Get(K start, K end, ref K[] overlaps, int overlapCount = 0)
|
||||||
|
{
|
||||||
|
GetValues(_root, start, end, ref overlaps, ref overlapCount);
|
||||||
|
|
||||||
|
return overlapCount;
|
||||||
|
}
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// Adds a new interval into the tree whose start is <paramref name="start"/>, end is <paramref name="end"/> and value is <paramref name="value"/>.
|
||||||
|
/// </summary>
|
||||||
|
/// <param name="start">Start of the range to add</param>
|
||||||
|
/// <param name="end">End of the range to insert</param>
|
||||||
|
/// <param name="value">Value to add</param>
|
||||||
|
/// <param name="updateFactoryCallback">Optional factory used to create a new value if <paramref name="start"/> is already on the tree</param>
|
||||||
|
/// <exception cref="ArgumentNullException"><paramref name="value"/> is null</exception>
|
||||||
|
/// <returns>True if the value was added, false if the start key was already in the dictionary</returns>
|
||||||
|
public bool AddOrUpdate(K start, K end, V value, Func<K, V, V> updateFactoryCallback)
|
||||||
|
{
|
||||||
|
if (value == null)
|
||||||
|
{
|
||||||
|
throw new ArgumentNullException(nameof(value));
|
||||||
|
}
|
||||||
|
|
||||||
|
return BSTInsert(start, end, value, updateFactoryCallback, out IntervalTreeNode<K, V> node);
|
||||||
|
}
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// Gets an existing or adds a new interval into the tree whose start is <paramref name="start"/>, end is <paramref name="end"/> and value is <paramref name="value"/>.
|
||||||
|
/// </summary>
|
||||||
|
/// <param name="start">Start of the range to add</param>
|
||||||
|
/// <param name="end">End of the range to insert</param>
|
||||||
|
/// <param name="value">Value to add</param>
|
||||||
|
/// <exception cref="ArgumentNullException"><paramref name="value"/> is null</exception>
|
||||||
|
/// <returns><paramref name="value"/> if <paramref name="start"/> is not yet on the tree, or the existing value otherwise</returns>
|
||||||
|
public V GetOrAdd(K start, K end, V value)
|
||||||
|
{
|
||||||
|
if (value == null)
|
||||||
|
{
|
||||||
|
throw new ArgumentNullException(nameof(value));
|
||||||
|
}
|
||||||
|
|
||||||
|
BSTInsert(start, end, value, null, out IntervalTreeNode<K, V> node);
|
||||||
|
return node.Value;
|
||||||
|
}
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// Removes a value from the tree, searching for it with <paramref name="key"/>.
|
||||||
|
/// </summary>
|
||||||
|
/// <param name="key">Key of the node to remove</param>
|
||||||
|
/// <returns>Number of deleted values</returns>
|
||||||
|
public int Remove(K key)
|
||||||
|
{
|
||||||
|
int removed = Delete(key);
|
||||||
|
|
||||||
|
_count -= removed;
|
||||||
|
|
||||||
|
return removed;
|
||||||
|
}
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// Adds all the nodes in the dictionary into <paramref name="list"/>.
|
||||||
|
/// </summary>
|
||||||
|
/// <returns>A list of all values sorted by Key Order</returns>
|
||||||
|
public List<V> AsList()
|
||||||
|
{
|
||||||
|
List<V> list = new List<V>();
|
||||||
|
|
||||||
|
AddToList(_root, list);
|
||||||
|
|
||||||
|
return list;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endregion
|
||||||
|
|
||||||
|
#region Private Methods (BST)
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// Adds all values that are children of or contained within <paramref name="node"/> into <paramref name="list"/>, in Key Order.
|
||||||
|
/// </summary>
|
||||||
|
/// <param name="node">The node to search for values within</param>
|
||||||
|
/// <param name="list">The list to add values to</param>
|
||||||
|
private void AddToList(IntervalTreeNode<K, V> node, List<V> list)
|
||||||
|
{
|
||||||
|
if (node == null)
|
||||||
|
{
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
AddToList(node.Left, list);
|
||||||
|
|
||||||
|
list.Add(node.Value);
|
||||||
|
|
||||||
|
AddToList(node.Right, list);
|
||||||
|
}
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// Retrieve the node reference whose key is <paramref name="key"/>, or null if no such node exists.
|
||||||
|
/// </summary>
|
||||||
|
/// <param name="key">Key of the node to get</param>
|
||||||
|
/// <exception cref="ArgumentNullException"><paramref name="key"/> is null</exception>
|
||||||
|
/// <returns>Node reference in the tree</returns>
|
||||||
|
private IntervalTreeNode<K, V> GetNode(K key)
|
||||||
|
{
|
||||||
|
if (key == null)
|
||||||
|
{
|
||||||
|
throw new ArgumentNullException(nameof(key));
|
||||||
|
}
|
||||||
|
|
||||||
|
IntervalTreeNode<K, V> node = _root;
|
||||||
|
while (node != null)
|
||||||
|
{
|
||||||
|
int cmp = key.CompareTo(node.Start);
|
||||||
|
if (cmp < 0)
|
||||||
|
{
|
||||||
|
node = node.Left;
|
||||||
|
}
|
||||||
|
else if (cmp > 0)
|
||||||
|
{
|
||||||
|
node = node.Right;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return node;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return null;
|
||||||
|
}
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// Retrieve all values that overlap the given start and end keys.
|
||||||
|
/// </summary>
|
||||||
|
/// <param name="start">Start of the range</param>
|
||||||
|
/// <param name="end">End of the range</param>
|
||||||
|
/// <param name="overlaps">Overlaps array to place results in</param>
|
||||||
|
/// <param name="overlapCount">Overlaps count to update</param>
|
||||||
|
private void GetValues(IntervalTreeNode<K, V> node, K start, K end, ref K[] overlaps, ref int overlapCount)
|
||||||
|
{
|
||||||
|
if (node == null || start.CompareTo(node.Max) >= 0)
|
||||||
|
{
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
GetValues(node.Left, start, end, ref overlaps, ref overlapCount);
|
||||||
|
|
||||||
|
bool endsOnRight = end.CompareTo(node.Start) > 0;
|
||||||
|
if (endsOnRight)
|
||||||
|
{
|
||||||
|
if (start.CompareTo(node.End) < 0)
|
||||||
|
{
|
||||||
|
if (overlaps.Length >= overlapCount)
|
||||||
|
{
|
||||||
|
Array.Resize(ref overlaps, overlapCount + ArrayGrowthSize);
|
||||||
|
}
|
||||||
|
|
||||||
|
overlaps[overlapCount++] = node.Start;
|
||||||
|
}
|
||||||
|
|
||||||
|
GetValues(node.Right, start, end, ref overlaps, ref overlapCount);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// Propagate an increase in max value starting at the given node, heading up the tree.
|
||||||
|
/// This should only be called if the max increases - not for rebalancing or removals.
|
||||||
|
/// </summary>
|
||||||
|
/// <param name="node">The node to start propagating from</param>
|
||||||
|
private void PropagateIncrease(IntervalTreeNode<K, V> node)
|
||||||
|
{
|
||||||
|
K max = node.Max;
|
||||||
|
IntervalTreeNode<K, V> ptr = node;
|
||||||
|
|
||||||
|
while ((ptr = ptr.Parent) != null)
|
||||||
|
{
|
||||||
|
if (max.CompareTo(ptr.Max) > 0)
|
||||||
|
{
|
||||||
|
ptr.Max = max;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// Propagate recalculating max value starting at the given node, heading up the tree.
|
||||||
|
/// This fully recalculates the max value from all children when there is potential for it to decrease.
|
||||||
|
/// </summary>
|
||||||
|
/// <param name="node">The node to start propagating from</param>
|
||||||
|
private void PropagateFull(IntervalTreeNode<K, V> node)
|
||||||
|
{
|
||||||
|
IntervalTreeNode<K, V> ptr = node;
|
||||||
|
|
||||||
|
do
|
||||||
|
{
|
||||||
|
K max = ptr.End;
|
||||||
|
|
||||||
|
if (ptr.Left != null && ptr.Left.Max.CompareTo(max) > 0)
|
||||||
|
{
|
||||||
|
max = ptr.Left.Max;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (ptr.Right != null && ptr.Right.Max.CompareTo(max) > 0)
|
||||||
|
{
|
||||||
|
max = ptr.Right.Max;
|
||||||
|
}
|
||||||
|
|
||||||
|
ptr.Max = max;
|
||||||
|
} while ((ptr = ptr.Parent) != null);
|
||||||
|
}
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// Insertion Mechanism for the interval tree. Similar to a BST insert, with the start of the range as the key.
|
||||||
|
/// Iterates the tree starting from the root and inserts a new node where all children in the left subtree are less than <paramref name="start"/>, and all children in the right subtree are greater than <paramref name="start"/>.
|
||||||
|
/// Each node can contain multiple values, and has an end address which is the maximum of all those values.
|
||||||
|
/// Post insertion, the "max" value of the node and all parents are updated.
|
||||||
|
/// </summary>
|
||||||
|
/// <param name="start">Start of the range to insert</param>
|
||||||
|
/// <param name="end">End of the range to insert</param>
|
||||||
|
/// <param name="value">Value to insert</param>
|
||||||
|
/// <param name="updateFactoryCallback">Optional factory used to create a new value if <paramref name="start"/> is already on the tree</param>
|
||||||
|
/// <param name="outNode">Node that was inserted or modified</param>
|
||||||
|
/// <returns>True if <paramref name="start"/> was not yet on the tree, false otherwise</returns>
|
||||||
|
private bool BSTInsert(K start, K end, V value, Func<K, V, V> updateFactoryCallback, out IntervalTreeNode<K, V> outNode)
|
||||||
|
{
|
||||||
|
IntervalTreeNode<K, V> parent = null;
|
||||||
|
IntervalTreeNode<K, V> node = _root;
|
||||||
|
|
||||||
|
while (node != null)
|
||||||
|
{
|
||||||
|
parent = node;
|
||||||
|
int cmp = start.CompareTo(node.Start);
|
||||||
|
if (cmp < 0)
|
||||||
|
{
|
||||||
|
node = node.Left;
|
||||||
|
}
|
||||||
|
else if (cmp > 0)
|
||||||
|
{
|
||||||
|
node = node.Right;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
outNode = node;
|
||||||
|
|
||||||
|
if (updateFactoryCallback != null)
|
||||||
|
{
|
||||||
|
// Replace
|
||||||
|
node.Value = updateFactoryCallback(start, node.Value);
|
||||||
|
|
||||||
|
int endCmp = end.CompareTo(node.End);
|
||||||
|
|
||||||
|
if (endCmp > 0)
|
||||||
|
{
|
||||||
|
node.End = end;
|
||||||
|
if (end.CompareTo(node.Max) > 0)
|
||||||
|
{
|
||||||
|
node.Max = end;
|
||||||
|
PropagateIncrease(node);
|
||||||
|
RestoreBalanceAfterInsertion(node);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else if (endCmp < 0)
|
||||||
|
{
|
||||||
|
node.End = end;
|
||||||
|
PropagateFull(node);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
IntervalTreeNode<K, V> newNode = new IntervalTreeNode<K, V>(start, end, value, parent);
|
||||||
|
if (newNode.Parent == null)
|
||||||
|
{
|
||||||
|
_root = newNode;
|
||||||
|
}
|
||||||
|
else if (start.CompareTo(parent.Start) < 0)
|
||||||
|
{
|
||||||
|
parent.Left = newNode;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
parent.Right = newNode;
|
||||||
|
}
|
||||||
|
|
||||||
|
PropagateIncrease(newNode);
|
||||||
|
_count++;
|
||||||
|
RestoreBalanceAfterInsertion(newNode);
|
||||||
|
outNode = newNode;
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// Removes the value from the dictionary after searching for it with <paramref name="key">.
|
||||||
|
/// </summary>
|
||||||
|
/// <param name="key">Key to search for</param>
|
||||||
|
/// <returns>Number of deleted values</returns>
|
||||||
|
private int Delete(K key)
|
||||||
|
{
|
||||||
|
IntervalTreeNode<K, V> nodeToDelete = GetNode(key);
|
||||||
|
|
||||||
|
if (nodeToDelete == null)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
IntervalTreeNode<K, V> replacementNode;
|
||||||
|
|
||||||
|
if (LeftOf(nodeToDelete) == null || RightOf(nodeToDelete) == null)
|
||||||
|
{
|
||||||
|
replacementNode = nodeToDelete;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
replacementNode = PredecessorOf(nodeToDelete);
|
||||||
|
}
|
||||||
|
|
||||||
|
IntervalTreeNode<K, V> tmp = LeftOf(replacementNode) ?? RightOf(replacementNode);
|
||||||
|
|
||||||
|
if (tmp != null)
|
||||||
|
{
|
||||||
|
tmp.Parent = ParentOf(replacementNode);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (ParentOf(replacementNode) == null)
|
||||||
|
{
|
||||||
|
_root = tmp;
|
||||||
|
}
|
||||||
|
else if (replacementNode == LeftOf(ParentOf(replacementNode)))
|
||||||
|
{
|
||||||
|
ParentOf(replacementNode).Left = tmp;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
ParentOf(replacementNode).Right = tmp;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (replacementNode != nodeToDelete)
|
||||||
|
{
|
||||||
|
nodeToDelete.Start = replacementNode.Start;
|
||||||
|
nodeToDelete.Value = replacementNode.Value;
|
||||||
|
nodeToDelete.End = replacementNode.End;
|
||||||
|
nodeToDelete.Max = replacementNode.Max;
|
||||||
|
}
|
||||||
|
|
||||||
|
PropagateFull(replacementNode);
|
||||||
|
|
||||||
|
if (tmp != null && ColorOf(replacementNode) == Black)
|
||||||
|
{
|
||||||
|
RestoreBalanceAfterRemoval(tmp);
|
||||||
|
}
|
||||||
|
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// Returns the node with the largest key where <paramref name="node"/> is considered the root node.
|
||||||
|
/// </summary>
|
||||||
|
/// <param name="node">Root Node</param>
|
||||||
|
/// <returns>Node with the maximum key in the tree of <paramref name="node"/></returns>
|
||||||
|
private static IntervalTreeNode<K, V> Maximum(IntervalTreeNode<K, V> node)
|
||||||
|
{
|
||||||
|
IntervalTreeNode<K, V> tmp = node;
|
||||||
|
while (tmp.Right != null)
|
||||||
|
{
|
||||||
|
tmp = tmp.Right;
|
||||||
|
}
|
||||||
|
|
||||||
|
return tmp;
|
||||||
|
}
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// Finds the node whose key is immediately less than <paramref name="node"/>.
|
||||||
|
/// </summary>
|
||||||
|
/// <param name="node">Node to find the predecessor of</param>
|
||||||
|
/// <returns>Predecessor of <paramref name="node"/></returns>
|
||||||
|
private static IntervalTreeNode<K, V> PredecessorOf(IntervalTreeNode<K, V> node)
|
||||||
|
{
|
||||||
|
if (node.Left != null)
|
||||||
|
{
|
||||||
|
return Maximum(node.Left);
|
||||||
|
}
|
||||||
|
IntervalTreeNode<K, V> parent = node.Parent;
|
||||||
|
while (parent != null && node == parent.Left)
|
||||||
|
{
|
||||||
|
node = parent;
|
||||||
|
parent = parent.Parent;
|
||||||
|
}
|
||||||
|
return parent;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endregion
|
||||||
|
|
||||||
|
#region Private Methods (RBL)
|
||||||
|
|
||||||
|
private void RestoreBalanceAfterRemoval(IntervalTreeNode<K, V> balanceNode)
|
||||||
|
{
|
||||||
|
IntervalTreeNode<K, V> ptr = balanceNode;
|
||||||
|
|
||||||
|
while (ptr != _root && ColorOf(ptr) == Black)
|
||||||
|
{
|
||||||
|
if (ptr == LeftOf(ParentOf(ptr)))
|
||||||
|
{
|
||||||
|
IntervalTreeNode<K, V> sibling = RightOf(ParentOf(ptr));
|
||||||
|
|
||||||
|
if (ColorOf(sibling) == Red)
|
||||||
|
{
|
||||||
|
SetColor(sibling, Black);
|
||||||
|
SetColor(ParentOf(ptr), Red);
|
||||||
|
RotateLeft(ParentOf(ptr));
|
||||||
|
sibling = RightOf(ParentOf(ptr));
|
||||||
|
}
|
||||||
|
if (ColorOf(LeftOf(sibling)) == Black && ColorOf(RightOf(sibling)) == Black)
|
||||||
|
{
|
||||||
|
SetColor(sibling, Red);
|
||||||
|
ptr = ParentOf(ptr);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if (ColorOf(RightOf(sibling)) == Black)
|
||||||
|
{
|
||||||
|
SetColor(LeftOf(sibling), Black);
|
||||||
|
SetColor(sibling, Red);
|
||||||
|
RotateRight(sibling);
|
||||||
|
sibling = RightOf(ParentOf(ptr));
|
||||||
|
}
|
||||||
|
SetColor(sibling, ColorOf(ParentOf(ptr)));
|
||||||
|
SetColor(ParentOf(ptr), Black);
|
||||||
|
SetColor(RightOf(sibling), Black);
|
||||||
|
RotateLeft(ParentOf(ptr));
|
||||||
|
ptr = _root;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
IntervalTreeNode<K, V> sibling = LeftOf(ParentOf(ptr));
|
||||||
|
|
||||||
|
if (ColorOf(sibling) == Red)
|
||||||
|
{
|
||||||
|
SetColor(sibling, Black);
|
||||||
|
SetColor(ParentOf(ptr), Red);
|
||||||
|
RotateRight(ParentOf(ptr));
|
||||||
|
sibling = LeftOf(ParentOf(ptr));
|
||||||
|
}
|
||||||
|
if (ColorOf(RightOf(sibling)) == Black && ColorOf(LeftOf(sibling)) == Black)
|
||||||
|
{
|
||||||
|
SetColor(sibling, Red);
|
||||||
|
ptr = ParentOf(ptr);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if (ColorOf(LeftOf(sibling)) == Black)
|
||||||
|
{
|
||||||
|
SetColor(RightOf(sibling), Black);
|
||||||
|
SetColor(sibling, Red);
|
||||||
|
RotateLeft(sibling);
|
||||||
|
sibling = LeftOf(ParentOf(ptr));
|
||||||
|
}
|
||||||
|
SetColor(sibling, ColorOf(ParentOf(ptr)));
|
||||||
|
SetColor(ParentOf(ptr), Black);
|
||||||
|
SetColor(LeftOf(sibling), Black);
|
||||||
|
RotateRight(ParentOf(ptr));
|
||||||
|
ptr = _root;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
SetColor(ptr, Black);
|
||||||
|
}
|
||||||
|
|
||||||
|
private void RestoreBalanceAfterInsertion(IntervalTreeNode<K, V> balanceNode)
|
||||||
|
{
|
||||||
|
SetColor(balanceNode, Red);
|
||||||
|
while (balanceNode != null && balanceNode != _root && ColorOf(ParentOf(balanceNode)) == Red)
|
||||||
|
{
|
||||||
|
if (ParentOf(balanceNode) == LeftOf(ParentOf(ParentOf(balanceNode))))
|
||||||
|
{
|
||||||
|
IntervalTreeNode<K, V> sibling = RightOf(ParentOf(ParentOf(balanceNode)));
|
||||||
|
|
||||||
|
if (ColorOf(sibling) == Red)
|
||||||
|
{
|
||||||
|
SetColor(ParentOf(balanceNode), Black);
|
||||||
|
SetColor(sibling, Black);
|
||||||
|
SetColor(ParentOf(ParentOf(balanceNode)), Red);
|
||||||
|
balanceNode = ParentOf(ParentOf(balanceNode));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if (balanceNode == RightOf(ParentOf(balanceNode)))
|
||||||
|
{
|
||||||
|
balanceNode = ParentOf(balanceNode);
|
||||||
|
RotateLeft(balanceNode);
|
||||||
|
}
|
||||||
|
SetColor(ParentOf(balanceNode), Black);
|
||||||
|
SetColor(ParentOf(ParentOf(balanceNode)), Red);
|
||||||
|
RotateRight(ParentOf(ParentOf(balanceNode)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
IntervalTreeNode<K, V> sibling = LeftOf(ParentOf(ParentOf(balanceNode)));
|
||||||
|
|
||||||
|
if (ColorOf(sibling) == Red)
|
||||||
|
{
|
||||||
|
SetColor(ParentOf(balanceNode), Black);
|
||||||
|
SetColor(sibling, Black);
|
||||||
|
SetColor(ParentOf(ParentOf(balanceNode)), Red);
|
||||||
|
balanceNode = ParentOf(ParentOf(balanceNode));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if (balanceNode == LeftOf(ParentOf(balanceNode)))
|
||||||
|
{
|
||||||
|
balanceNode = ParentOf(balanceNode);
|
||||||
|
RotateRight(balanceNode);
|
||||||
|
}
|
||||||
|
SetColor(ParentOf(balanceNode), Black);
|
||||||
|
SetColor(ParentOf(ParentOf(balanceNode)), Red);
|
||||||
|
RotateLeft(ParentOf(ParentOf(balanceNode)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
SetColor(_root, Black);
|
||||||
|
}
|
||||||
|
|
||||||
|
private void RotateLeft(IntervalTreeNode<K, V> node)
|
||||||
|
{
|
||||||
|
if (node != null)
|
||||||
|
{
|
||||||
|
IntervalTreeNode<K, V> right = RightOf(node);
|
||||||
|
node.Right = LeftOf(right);
|
||||||
|
if (node.Right != null)
|
||||||
|
{
|
||||||
|
node.Right.Parent = node;
|
||||||
|
}
|
||||||
|
IntervalTreeNode<K, V> nodeParent = ParentOf(node);
|
||||||
|
right.Parent = nodeParent;
|
||||||
|
if (nodeParent == null)
|
||||||
|
{
|
||||||
|
_root = right;
|
||||||
|
}
|
||||||
|
else if (node == LeftOf(nodeParent))
|
||||||
|
{
|
||||||
|
nodeParent.Left = right;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
nodeParent.Right = right;
|
||||||
|
}
|
||||||
|
right.Left = node;
|
||||||
|
node.Parent = right;
|
||||||
|
|
||||||
|
PropagateFull(node);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
private void RotateRight(IntervalTreeNode<K, V> node)
|
||||||
|
{
|
||||||
|
if (node != null)
|
||||||
|
{
|
||||||
|
IntervalTreeNode<K, V> left = LeftOf(node);
|
||||||
|
node.Left = RightOf(left);
|
||||||
|
if (node.Left != null)
|
||||||
|
{
|
||||||
|
node.Left.Parent = node;
|
||||||
|
}
|
||||||
|
IntervalTreeNode<K, V> nodeParent = ParentOf(node);
|
||||||
|
left.Parent = nodeParent;
|
||||||
|
if (nodeParent == null)
|
||||||
|
{
|
||||||
|
_root = left;
|
||||||
|
}
|
||||||
|
else if (node == RightOf(nodeParent))
|
||||||
|
{
|
||||||
|
nodeParent.Right = left;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
nodeParent.Left = left;
|
||||||
|
}
|
||||||
|
left.Right = node;
|
||||||
|
node.Parent = left;
|
||||||
|
|
||||||
|
PropagateFull(node);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#endregion
|
||||||
|
|
||||||
|
#region Safety-Methods
|
||||||
|
|
||||||
|
// These methods save memory by allowing us to forego sentinel nil nodes, as well as serve as protection against NullReferenceExceptions.
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// Returns the color of <paramref name="node"/>, or Black if it is null.
|
||||||
|
/// </summary>
|
||||||
|
/// <param name="node">Node</param>
|
||||||
|
/// <returns>The boolean color of <paramref name="node"/>, or black if null</returns>
|
||||||
|
private static bool ColorOf(IntervalTreeNode<K, V> node)
|
||||||
|
{
|
||||||
|
return node == null || node.Color;
|
||||||
|
}
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// Sets the color of <paramref name="node"/> node to <paramref name="color"/>.
|
||||||
|
/// <br></br>
|
||||||
|
/// This method does nothing if <paramref name="node"/> is null.
|
||||||
|
/// </summary>
|
||||||
|
/// <param name="node">Node to set the color of</param>
|
||||||
|
/// <param name="color">Color (Boolean)</param>
|
||||||
|
private static void SetColor(IntervalTreeNode<K, V> node, bool color)
|
||||||
|
{
|
||||||
|
if (node != null)
|
||||||
|
{
|
||||||
|
node.Color = color;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// This method returns the left node of <paramref name="node"/>, or null if <paramref name="node"/> is null.
|
||||||
|
/// </summary>
|
||||||
|
/// <param name="node">Node to retrieve the left child from</param>
|
||||||
|
/// <returns>Left child of <paramref name="node"/></returns>
|
||||||
|
private static IntervalTreeNode<K, V> LeftOf(IntervalTreeNode<K, V> node)
|
||||||
|
{
|
||||||
|
return node?.Left;
|
||||||
|
}
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// This method returns the right node of <paramref name="node"/>, or null if <paramref name="node"/> is null.
|
||||||
|
/// </summary>
|
||||||
|
/// <param name="node">Node to retrieve the right child from</param>
|
||||||
|
/// <returns>Right child of <paramref name="node"/></returns>
|
||||||
|
private static IntervalTreeNode<K, V> RightOf(IntervalTreeNode<K, V> node)
|
||||||
|
{
|
||||||
|
return node?.Right;
|
||||||
|
}
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// Returns the parent node of <paramref name="node"/>, or null if <paramref name="node"/> is null.
|
||||||
|
/// </summary>
|
||||||
|
/// <param name="node">Node to retrieve the parent from</param>
|
||||||
|
/// <returns>Parent of <paramref name="node"/></returns>
|
||||||
|
private static IntervalTreeNode<K, V> ParentOf(IntervalTreeNode<K, V> node)
|
||||||
|
{
|
||||||
|
return node?.Parent;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endregion
|
||||||
|
|
||||||
|
public bool ContainsKey(K key)
|
||||||
|
{
|
||||||
|
return GetNode(key) != null;
|
||||||
|
}
|
||||||
|
|
||||||
|
public void Clear()
|
||||||
|
{
|
||||||
|
_root = null;
|
||||||
|
_count = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// Represents a node in the IntervalTree which contains start and end keys of type K, and a value of generic type V.
|
||||||
|
/// </summary>
|
||||||
|
/// <typeparam name="K">Key type of the node</typeparam>
|
||||||
|
/// <typeparam name="V">Value type of the node</typeparam>
|
||||||
|
internal class IntervalTreeNode<K, V>
|
||||||
|
{
|
||||||
|
internal bool Color = true;
|
||||||
|
internal IntervalTreeNode<K, V> Left = null;
|
||||||
|
internal IntervalTreeNode<K, V> Right = null;
|
||||||
|
internal IntervalTreeNode<K, V> Parent = null;
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// The start of the range.
|
||||||
|
/// </summary>
|
||||||
|
internal K Start;
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// The end of the range.
|
||||||
|
/// </summary>
|
||||||
|
internal K End;
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// The maximum end value of this node and all its children.
|
||||||
|
/// </summary>
|
||||||
|
internal K Max;
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// Value stored on this node.
|
||||||
|
/// </summary>
|
||||||
|
internal V Value;
|
||||||
|
|
||||||
|
public IntervalTreeNode(K start, K end, V value, IntervalTreeNode<K, V> parent)
|
||||||
|
{
|
||||||
|
this.Start = start;
|
||||||
|
this.End = end;
|
||||||
|
this.Max = end;
|
||||||
|
this.Value = value;
|
||||||
|
this.Parent = parent;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
@ -27,7 +27,7 @@ namespace ARMeilleure.Translation.PTC
|
|||||||
private const string OuterHeaderMagicString = "PTCohd\0\0";
|
private const string OuterHeaderMagicString = "PTCohd\0\0";
|
||||||
private const string InnerHeaderMagicString = "PTCihd\0\0";
|
private const string InnerHeaderMagicString = "PTCihd\0\0";
|
||||||
|
|
||||||
private const uint InternalVersion = 3061; //! To be incremented manually for each change to the ARMeilleure project.
|
private const uint InternalVersion = 3179; //! To be incremented manually for each change to the ARMeilleure project.
|
||||||
|
|
||||||
private const string ActualDir = "0";
|
private const string ActualDir = "0";
|
||||||
private const string BackupDir = "1";
|
private const string BackupDir = "1";
|
||||||
@ -585,7 +585,7 @@ namespace ARMeilleure.Translation.PTC
|
|||||||
|
|
||||||
translator.RegisterFunction(infoEntry.Address, func);
|
translator.RegisterFunction(infoEntry.Address, func);
|
||||||
|
|
||||||
bool isAddressUnique = translator.Functions.TryAdd(infoEntry.Address, func);
|
bool isAddressUnique = translator.Functions.TryAdd(infoEntry.Address, infoEntry.GuestSize, func);
|
||||||
|
|
||||||
Debug.Assert(isAddressUnique, $"The address 0x{infoEntry.Address:X16} is not unique.");
|
Debug.Assert(isAddressUnique, $"The address 0x{infoEntry.Address:X16} is not unique.");
|
||||||
}
|
}
|
||||||
@ -815,7 +815,7 @@ namespace ARMeilleure.Translation.PTC
|
|||||||
|
|
||||||
TranslatedFunction func = translator.Translate(address, item.funcProfile.Mode, item.funcProfile.HighCq);
|
TranslatedFunction func = translator.Translate(address, item.funcProfile.Mode, item.funcProfile.HighCq);
|
||||||
|
|
||||||
bool isAddressUnique = translator.Functions.TryAdd(address, func);
|
bool isAddressUnique = translator.Functions.TryAdd(address, func.GuestSize, func);
|
||||||
|
|
||||||
Debug.Assert(isAddressUnique, $"The address 0x{address:X16} is not unique.");
|
Debug.Assert(isAddressUnique, $"The address 0x{address:X16} is not unique.");
|
||||||
|
|
||||||
|
@ -96,7 +96,7 @@ namespace ARMeilleure.Translation.PTC
|
|||||||
return address >= StaticCodeStart && address < StaticCodeStart + StaticCodeSize;
|
return address >= StaticCodeStart && address < StaticCodeStart + StaticCodeSize;
|
||||||
}
|
}
|
||||||
|
|
||||||
internal static ConcurrentQueue<(ulong address, FuncProfile funcProfile)> GetProfiledFuncsToTranslate(ConcurrentDictionary<ulong, TranslatedFunction> funcs)
|
internal static ConcurrentQueue<(ulong address, FuncProfile funcProfile)> GetProfiledFuncsToTranslate(TranslatorCache<TranslatedFunction> funcs)
|
||||||
{
|
{
|
||||||
var profiledFuncsToTranslate = new ConcurrentQueue<(ulong address, FuncProfile funcProfile)>();
|
var profiledFuncsToTranslate = new ConcurrentQueue<(ulong address, FuncProfile funcProfile)>();
|
||||||
|
|
||||||
|
@ -113,7 +113,7 @@ namespace ARMeilleure.Translation
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
Array.Clear(localDefs, 0, localDefs.Length);
|
Array.Clear(localDefs);
|
||||||
}
|
}
|
||||||
|
|
||||||
// Second pass, rename variables with definitions on different blocks.
|
// Second pass, rename variables with definitions on different blocks.
|
||||||
|
@ -49,7 +49,7 @@ namespace ARMeilleure.Translation
|
|||||||
private readonly AutoResetEvent _backgroundTranslatorEvent;
|
private readonly AutoResetEvent _backgroundTranslatorEvent;
|
||||||
private readonly ReaderWriterLock _backgroundTranslatorLock;
|
private readonly ReaderWriterLock _backgroundTranslatorLock;
|
||||||
|
|
||||||
internal ConcurrentDictionary<ulong, TranslatedFunction> Functions { get; }
|
internal TranslatorCache<TranslatedFunction> Functions { get; }
|
||||||
internal AddressTable<ulong> FunctionTable { get; }
|
internal AddressTable<ulong> FunctionTable { get; }
|
||||||
internal EntryTable<uint> CountTable { get; }
|
internal EntryTable<uint> CountTable { get; }
|
||||||
internal TranslatorStubs Stubs { get; }
|
internal TranslatorStubs Stubs { get; }
|
||||||
@ -75,7 +75,7 @@ namespace ARMeilleure.Translation
|
|||||||
JitCache.Initialize(allocator);
|
JitCache.Initialize(allocator);
|
||||||
|
|
||||||
CountTable = new EntryTable<uint>();
|
CountTable = new EntryTable<uint>();
|
||||||
Functions = new ConcurrentDictionary<ulong, TranslatedFunction>();
|
Functions = new TranslatorCache<TranslatedFunction>();
|
||||||
FunctionTable = new AddressTable<ulong>(for64Bits ? Levels64Bit : Levels32Bit);
|
FunctionTable = new AddressTable<ulong>(for64Bits ? Levels64Bit : Levels32Bit);
|
||||||
Stubs = new TranslatorStubs(this);
|
Stubs = new TranslatorStubs(this);
|
||||||
|
|
||||||
@ -93,12 +93,12 @@ namespace ARMeilleure.Translation
|
|||||||
{
|
{
|
||||||
_backgroundTranslatorLock.AcquireReaderLock(Timeout.Infinite);
|
_backgroundTranslatorLock.AcquireReaderLock(Timeout.Infinite);
|
||||||
|
|
||||||
if (_backgroundStack.TryPop(out RejitRequest request) &&
|
if (_backgroundStack.TryPop(out RejitRequest request) &&
|
||||||
_backgroundSet.TryRemove(request.Address, out _))
|
_backgroundSet.TryRemove(request.Address, out _))
|
||||||
{
|
{
|
||||||
TranslatedFunction func = Translate(request.Address, request.Mode, highCq: true);
|
TranslatedFunction func = Translate(request.Address, request.Mode, highCq: true);
|
||||||
|
|
||||||
Functions.AddOrUpdate(request.Address, func, (key, oldFunc) =>
|
Functions.AddOrUpdate(request.Address, func.GuestSize, func, (key, oldFunc) =>
|
||||||
{
|
{
|
||||||
EnqueueForDeletion(key, oldFunc);
|
EnqueueForDeletion(key, oldFunc);
|
||||||
return func;
|
return func;
|
||||||
@ -196,7 +196,7 @@ namespace ARMeilleure.Translation
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
public ulong ExecuteSingle(State.ExecutionContext context, ulong address)
|
private ulong ExecuteSingle(State.ExecutionContext context, ulong address)
|
||||||
{
|
{
|
||||||
TranslatedFunction func = GetOrTranslate(address, context.ExecutionMode);
|
TranslatedFunction func = GetOrTranslate(address, context.ExecutionMode);
|
||||||
|
|
||||||
@ -209,13 +209,24 @@ namespace ARMeilleure.Translation
|
|||||||
return nextAddr;
|
return nextAddr;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
public ulong Step(State.ExecutionContext context, ulong address)
|
||||||
|
{
|
||||||
|
TranslatedFunction func = Translate(address, context.ExecutionMode, highCq: false, singleStep: true);
|
||||||
|
|
||||||
|
address = func.Execute(context);
|
||||||
|
|
||||||
|
EnqueueForDeletion(address, func);
|
||||||
|
|
||||||
|
return address;
|
||||||
|
}
|
||||||
|
|
||||||
internal TranslatedFunction GetOrTranslate(ulong address, ExecutionMode mode)
|
internal TranslatedFunction GetOrTranslate(ulong address, ExecutionMode mode)
|
||||||
{
|
{
|
||||||
if (!Functions.TryGetValue(address, out TranslatedFunction func))
|
if (!Functions.TryGetValue(address, out TranslatedFunction func))
|
||||||
{
|
{
|
||||||
func = Translate(address, mode, highCq: false);
|
func = Translate(address, mode, highCq: false);
|
||||||
|
|
||||||
TranslatedFunction oldFunc = Functions.GetOrAdd(address, func);
|
TranslatedFunction oldFunc = Functions.GetOrAdd(address, func.GuestSize, func);
|
||||||
|
|
||||||
if (oldFunc != func)
|
if (oldFunc != func)
|
||||||
{
|
{
|
||||||
@ -242,7 +253,7 @@ namespace ARMeilleure.Translation
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
internal TranslatedFunction Translate(ulong address, ExecutionMode mode, bool highCq)
|
internal TranslatedFunction Translate(ulong address, ExecutionMode mode, bool highCq, bool singleStep = false)
|
||||||
{
|
{
|
||||||
var context = new ArmEmitterContext(
|
var context = new ArmEmitterContext(
|
||||||
Memory,
|
Memory,
|
||||||
@ -255,7 +266,7 @@ namespace ARMeilleure.Translation
|
|||||||
|
|
||||||
Logger.StartPass(PassName.Decoding);
|
Logger.StartPass(PassName.Decoding);
|
||||||
|
|
||||||
Block[] blocks = Decoder.Decode(Memory, address, mode, highCq, singleBlock: false);
|
Block[] blocks = Decoder.Decode(Memory, address, mode, highCq, singleStep ? DecoderMode.SingleInstruction : DecoderMode.MultipleBlocks);
|
||||||
|
|
||||||
Logger.EndPass(PassName.Decoding);
|
Logger.EndPass(PassName.Decoding);
|
||||||
|
|
||||||
@ -285,14 +296,14 @@ namespace ARMeilleure.Translation
|
|||||||
|
|
||||||
var options = highCq ? CompilerOptions.HighCq : CompilerOptions.None;
|
var options = highCq ? CompilerOptions.HighCq : CompilerOptions.None;
|
||||||
|
|
||||||
if (context.HasPtc)
|
if (context.HasPtc && !singleStep)
|
||||||
{
|
{
|
||||||
options |= CompilerOptions.Relocatable;
|
options |= CompilerOptions.Relocatable;
|
||||||
}
|
}
|
||||||
|
|
||||||
CompiledFunction compiledFunc = Compiler.Compile(cfg, argTypes, retType, options);
|
CompiledFunction compiledFunc = Compiler.Compile(cfg, argTypes, retType, options);
|
||||||
|
|
||||||
if (context.HasPtc)
|
if (context.HasPtc && !singleStep)
|
||||||
{
|
{
|
||||||
Hash128 hash = Ptc.ComputeHash(Memory, address, funcSize);
|
Hash128 hash = Ptc.ComputeHash(Memory, address, funcSize);
|
||||||
|
|
||||||
@ -380,6 +391,13 @@ namespace ARMeilleure.Translation
|
|||||||
|
|
||||||
Operand lblPredicateSkip = default;
|
Operand lblPredicateSkip = default;
|
||||||
|
|
||||||
|
if (context.IsInIfThenBlock && context.CurrentIfThenBlockCond != Condition.Al)
|
||||||
|
{
|
||||||
|
lblPredicateSkip = Label();
|
||||||
|
|
||||||
|
InstEmitFlowHelper.EmitCondBranch(context, lblPredicateSkip, context.CurrentIfThenBlockCond.Invert());
|
||||||
|
}
|
||||||
|
|
||||||
if (opCode is OpCode32 op && op.Cond < Condition.Al)
|
if (opCode is OpCode32 op && op.Cond < Condition.Al)
|
||||||
{
|
{
|
||||||
lblPredicateSkip = Label();
|
lblPredicateSkip = Label();
|
||||||
@ -400,6 +418,11 @@ namespace ARMeilleure.Translation
|
|||||||
{
|
{
|
||||||
context.MarkLabel(lblPredicateSkip);
|
context.MarkLabel(lblPredicateSkip);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (context.IsInIfThenBlock && opCode.Instruction.Name != InstName.It)
|
||||||
|
{
|
||||||
|
context.AdvanceIfThenBlockState();
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -459,7 +482,24 @@ namespace ARMeilleure.Translation
|
|||||||
// If rejit is running, stop it as it may be trying to rejit a function on the invalidated region.
|
// If rejit is running, stop it as it may be trying to rejit a function on the invalidated region.
|
||||||
ClearRejitQueue(allowRequeue: true);
|
ClearRejitQueue(allowRequeue: true);
|
||||||
|
|
||||||
// TODO: Completely remove functions overlapping the specified range from the cache.
|
ulong[] overlapAddresses = Array.Empty<ulong>();
|
||||||
|
|
||||||
|
int overlapsCount = Functions.GetOverlaps(address, size, ref overlapAddresses);
|
||||||
|
|
||||||
|
for (int index = 0; index < overlapsCount; index++)
|
||||||
|
{
|
||||||
|
ulong overlapAddress = overlapAddresses[index];
|
||||||
|
|
||||||
|
if (Functions.TryGetValue(overlapAddress, out TranslatedFunction overlap))
|
||||||
|
{
|
||||||
|
Functions.Remove(overlapAddress);
|
||||||
|
Volatile.Write(ref FunctionTable.GetValue(overlapAddress), FunctionTable.Fill);
|
||||||
|
EnqueueForDeletion(overlapAddress, overlap);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
// TODO: Remove overlapping functions from the JitCache aswell.
|
||||||
|
// This should be done safely, with a mechanism to ensure the function is not being executed.
|
||||||
}
|
}
|
||||||
|
|
||||||
internal void EnqueueForRejit(ulong guestAddress, ExecutionMode mode)
|
internal void EnqueueForRejit(ulong guestAddress, ExecutionMode mode)
|
||||||
@ -481,7 +521,9 @@ namespace ARMeilleure.Translation
|
|||||||
// Ensure no attempt will be made to compile new functions due to rejit.
|
// Ensure no attempt will be made to compile new functions due to rejit.
|
||||||
ClearRejitQueue(allowRequeue: false);
|
ClearRejitQueue(allowRequeue: false);
|
||||||
|
|
||||||
foreach (var func in Functions.Values)
|
List<TranslatedFunction> functions = Functions.AsList();
|
||||||
|
|
||||||
|
foreach (var func in functions)
|
||||||
{
|
{
|
||||||
JitCache.Unmap(func.FuncPtr);
|
JitCache.Unmap(func.FuncPtr);
|
||||||
|
|
||||||
|
95
ARMeilleure/Translation/TranslatorCache.cs
Normal file
95
ARMeilleure/Translation/TranslatorCache.cs
Normal file
@ -0,0 +1,95 @@
|
|||||||
|
using System;
|
||||||
|
using System.Collections.Generic;
|
||||||
|
using System.Threading;
|
||||||
|
|
||||||
|
namespace ARMeilleure.Translation
|
||||||
|
{
|
||||||
|
internal class TranslatorCache<T>
|
||||||
|
{
|
||||||
|
private readonly IntervalTree<ulong, T> _tree;
|
||||||
|
private readonly ReaderWriterLock _treeLock;
|
||||||
|
|
||||||
|
public int Count => _tree.Count;
|
||||||
|
|
||||||
|
public TranslatorCache()
|
||||||
|
{
|
||||||
|
_tree = new IntervalTree<ulong, T>();
|
||||||
|
_treeLock = new ReaderWriterLock();
|
||||||
|
}
|
||||||
|
|
||||||
|
public bool TryAdd(ulong address, ulong size, T value)
|
||||||
|
{
|
||||||
|
return AddOrUpdate(address, size, value, null);
|
||||||
|
}
|
||||||
|
|
||||||
|
public bool AddOrUpdate(ulong address, ulong size, T value, Func<ulong, T, T> updateFactoryCallback)
|
||||||
|
{
|
||||||
|
_treeLock.AcquireWriterLock(Timeout.Infinite);
|
||||||
|
bool result = _tree.AddOrUpdate(address, address + size, value, updateFactoryCallback);
|
||||||
|
_treeLock.ReleaseWriterLock();
|
||||||
|
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
|
||||||
|
public T GetOrAdd(ulong address, ulong size, T value)
|
||||||
|
{
|
||||||
|
_treeLock.AcquireWriterLock(Timeout.Infinite);
|
||||||
|
value = _tree.GetOrAdd(address, address + size, value);
|
||||||
|
_treeLock.ReleaseWriterLock();
|
||||||
|
|
||||||
|
return value;
|
||||||
|
}
|
||||||
|
|
||||||
|
public bool Remove(ulong address)
|
||||||
|
{
|
||||||
|
_treeLock.AcquireWriterLock(Timeout.Infinite);
|
||||||
|
bool removed = _tree.Remove(address) != 0;
|
||||||
|
_treeLock.ReleaseWriterLock();
|
||||||
|
|
||||||
|
return removed;
|
||||||
|
}
|
||||||
|
|
||||||
|
public void Clear()
|
||||||
|
{
|
||||||
|
_treeLock.AcquireWriterLock(Timeout.Infinite);
|
||||||
|
_tree.Clear();
|
||||||
|
_treeLock.ReleaseWriterLock();
|
||||||
|
}
|
||||||
|
|
||||||
|
public bool ContainsKey(ulong address)
|
||||||
|
{
|
||||||
|
_treeLock.AcquireReaderLock(Timeout.Infinite);
|
||||||
|
bool result = _tree.ContainsKey(address);
|
||||||
|
_treeLock.ReleaseReaderLock();
|
||||||
|
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
|
||||||
|
public bool TryGetValue(ulong address, out T value)
|
||||||
|
{
|
||||||
|
_treeLock.AcquireReaderLock(Timeout.Infinite);
|
||||||
|
bool result = _tree.TryGet(address, out value);
|
||||||
|
_treeLock.ReleaseReaderLock();
|
||||||
|
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
|
||||||
|
public int GetOverlaps(ulong address, ulong size, ref ulong[] overlaps)
|
||||||
|
{
|
||||||
|
_treeLock.AcquireReaderLock(Timeout.Infinite);
|
||||||
|
int count = _tree.Get(address, address + size, ref overlaps);
|
||||||
|
_treeLock.ReleaseReaderLock();
|
||||||
|
|
||||||
|
return count;
|
||||||
|
}
|
||||||
|
|
||||||
|
public List<T> AsList()
|
||||||
|
{
|
||||||
|
_treeLock.AcquireReaderLock(Timeout.Infinite);
|
||||||
|
List<T> list = _tree.AsList();
|
||||||
|
_treeLock.ReleaseReaderLock();
|
||||||
|
|
||||||
|
return list;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
@ -112,12 +112,12 @@ namespace Ryujinx.Audio.Renderer.Dsp.State
|
|||||||
|
|
||||||
private ReadOnlySpan<float> GetFdnDelayTimesByLateMode(ReverbLateMode lateMode)
|
private ReadOnlySpan<float> GetFdnDelayTimesByLateMode(ReverbLateMode lateMode)
|
||||||
{
|
{
|
||||||
return FdnDelayTimes.AsSpan().Slice((int)lateMode * 4, 4);
|
return FdnDelayTimes.AsSpan((int)lateMode * 4, 4);
|
||||||
}
|
}
|
||||||
|
|
||||||
private ReadOnlySpan<float> GetDecayDelayTimesByLateMode(ReverbLateMode lateMode)
|
private ReadOnlySpan<float> GetDecayDelayTimesByLateMode(ReverbLateMode lateMode)
|
||||||
{
|
{
|
||||||
return DecayDelayTimes.AsSpan().Slice((int)lateMode * 4, 4);
|
return DecayDelayTimes.AsSpan((int)lateMode * 4, 4);
|
||||||
}
|
}
|
||||||
|
|
||||||
public ReverbState(ref ReverbParameter parameter, ulong workBuffer, bool isLongSizePreDelaySupported)
|
public ReverbState(ref ReverbParameter parameter, ulong workBuffer, bool isLongSizePreDelaySupported)
|
||||||
|
@ -149,11 +149,21 @@ namespace Ryujinx.Audio.Renderer.Server.Performance
|
|||||||
|
|
||||||
Span<byte> targetSpan = performanceOutput.Slice(nextOffset);
|
Span<byte> targetSpan = performanceOutput.Slice(nextOffset);
|
||||||
|
|
||||||
|
// NOTE: We check for the space for two headers for the final blank header.
|
||||||
|
int requiredSpace = Unsafe.SizeOf<THeader>() + Unsafe.SizeOf<TEntry>() * inputHeader.GetEntryCount()
|
||||||
|
+ Unsafe.SizeOf<TEntryDetail>() * inputHeader.GetEntryDetailCount()
|
||||||
|
+ Unsafe.SizeOf<THeader>();
|
||||||
|
|
||||||
|
if (targetSpan.Length < requiredSpace)
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
ref THeader outputHeader = ref MemoryMarshal.Cast<byte, THeader>(targetSpan)[0];
|
ref THeader outputHeader = ref MemoryMarshal.Cast<byte, THeader>(targetSpan)[0];
|
||||||
|
|
||||||
nextOffset += Unsafe.SizeOf<THeader>();
|
nextOffset += Unsafe.SizeOf<THeader>();
|
||||||
|
|
||||||
Span<TEntry> outputEntries = MemoryMarshal.Cast<byte, TEntry>(targetSpan.Slice(nextOffset));
|
Span<TEntry> outputEntries = MemoryMarshal.Cast<byte, TEntry>(performanceOutput.Slice(nextOffset));
|
||||||
|
|
||||||
int totalProcessingTime = 0;
|
int totalProcessingTime = 0;
|
||||||
|
|
||||||
@ -175,7 +185,7 @@ namespace Ryujinx.Audio.Renderer.Server.Performance
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
Span<TEntryDetail> outputEntriesDetail = MemoryMarshal.Cast<byte, TEntryDetail>(targetSpan.Slice(nextOffset));
|
Span<TEntryDetail> outputEntriesDetail = MemoryMarshal.Cast<byte, TEntryDetail>(performanceOutput.Slice(nextOffset));
|
||||||
|
|
||||||
int effectiveEntryDetailCount = 0;
|
int effectiveEntryDetailCount = 0;
|
||||||
|
|
||||||
|
@ -459,7 +459,7 @@ namespace Ryujinx.Audio.Renderer.Server.Voice
|
|||||||
|
|
||||||
for (int i = 0; i < Constants.VoiceWaveBufferCount; i++)
|
for (int i = 0; i < Constants.VoiceWaveBufferCount; i++)
|
||||||
{
|
{
|
||||||
UpdateWaveBuffer(errorInfos.AsSpan().Slice(i * 2, 2), ref WaveBuffers[i], ref parameter.WaveBuffers[i], parameter.SampleFormat, voiceUpdateState.IsWaveBufferValid[i], ref mapper, ref behaviourContext);
|
UpdateWaveBuffer(errorInfos.AsSpan(i * 2, 2), ref WaveBuffers[i], ref parameter.WaveBuffers[i], parameter.SampleFormat, voiceUpdateState.IsWaveBufferValid[i], ref mapper, ref behaviourContext);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -34,6 +34,7 @@ namespace Ryujinx.Common.Configuration
|
|||||||
private const string DefaultModsDir = "mods";
|
private const string DefaultModsDir = "mods";
|
||||||
|
|
||||||
public static string CustomModsPath { get; set; }
|
public static string CustomModsPath { get; set; }
|
||||||
|
public static string CustomSdModsPath {get; set; }
|
||||||
public static string CustomNandPath { get; set; } // TODO: Actually implement this into VFS
|
public static string CustomNandPath { get; set; } // TODO: Actually implement this into VFS
|
||||||
public static string CustomSdCardPath { get; set; } // TODO: Actually implement this into VFS
|
public static string CustomSdCardPath { get; set; } // TODO: Actually implement this into VFS
|
||||||
|
|
||||||
@ -84,6 +85,7 @@ namespace Ryujinx.Common.Configuration
|
|||||||
Directory.CreateDirectory(KeysDirPath = Path.Combine(BaseDirPath, KeysDir));
|
Directory.CreateDirectory(KeysDirPath = Path.Combine(BaseDirPath, KeysDir));
|
||||||
}
|
}
|
||||||
|
|
||||||
public static string GetModsPath() => CustomModsPath ?? Directory.CreateDirectory(Path.Combine(BaseDirPath, DefaultModsDir)).FullName;
|
public static string GetModsPath() => CustomModsPath ?? Directory.CreateDirectory(Path.Combine(BaseDirPath, DefaultModsDir)).FullName;
|
||||||
|
public static string GetSdModsPath() => CustomSdModsPath ?? Directory.CreateDirectory(Path.Combine(BaseDirPath, DefaultSdcardDir, "atmosphere")).FullName;
|
||||||
}
|
}
|
||||||
}
|
}
|
@ -5,6 +5,7 @@
|
|||||||
public Stick Joystick { get; set; }
|
public Stick Joystick { get; set; }
|
||||||
public bool InvertStickX { get; set; }
|
public bool InvertStickX { get; set; }
|
||||||
public bool InvertStickY { get; set; }
|
public bool InvertStickY { get; set; }
|
||||||
|
public bool Rotate90CW { get; set; }
|
||||||
public Button StickButton { get; set; }
|
public Button StickButton { get; set; }
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -39,6 +39,7 @@ namespace Ryujinx.Common.Logging
|
|||||||
ServiceLm,
|
ServiceLm,
|
||||||
ServiceMii,
|
ServiceMii,
|
||||||
ServiceMm,
|
ServiceMm,
|
||||||
|
ServiceMnpp,
|
||||||
ServiceNfc,
|
ServiceNfc,
|
||||||
ServiceNfp,
|
ServiceNfp,
|
||||||
ServiceNgct,
|
ServiceNgct,
|
||||||
|
@ -9,6 +9,7 @@ namespace Ryujinx.Common.Logging
|
|||||||
Error,
|
Error,
|
||||||
Guest,
|
Guest,
|
||||||
AccessLog,
|
AccessLog,
|
||||||
Notice
|
Notice,
|
||||||
|
Trace
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -90,6 +90,7 @@ namespace Ryujinx.Common.Logging
|
|||||||
public static Log? Guest { get; private set; }
|
public static Log? Guest { get; private set; }
|
||||||
public static Log? AccessLog { get; private set; }
|
public static Log? AccessLog { get; private set; }
|
||||||
public static Log? Stub { get; private set; }
|
public static Log? Stub { get; private set; }
|
||||||
|
public static Log? Trace { get; private set; }
|
||||||
public static Log Notice { get; } // Always enabled
|
public static Log Notice { get; } // Always enabled
|
||||||
|
|
||||||
static Logger()
|
static Logger()
|
||||||
@ -117,6 +118,7 @@ namespace Ryujinx.Common.Logging
|
|||||||
Error = new Log(LogLevel.Error);
|
Error = new Log(LogLevel.Error);
|
||||||
Warning = new Log(LogLevel.Warning);
|
Warning = new Log(LogLevel.Warning);
|
||||||
Info = new Log(LogLevel.Info);
|
Info = new Log(LogLevel.Info);
|
||||||
|
Trace = new Log(LogLevel.Trace);
|
||||||
}
|
}
|
||||||
|
|
||||||
public static void RestartTime()
|
public static void RestartTime()
|
||||||
@ -172,7 +174,7 @@ namespace Ryujinx.Common.Logging
|
|||||||
|
|
||||||
public static IReadOnlyCollection<LogLevel> GetEnabledLevels()
|
public static IReadOnlyCollection<LogLevel> GetEnabledLevels()
|
||||||
{
|
{
|
||||||
var logs = new Log?[] { Debug, Info, Warning, Error, Guest, AccessLog, Stub };
|
var logs = new Log?[] { Debug, Info, Warning, Error, Guest, AccessLog, Stub, Trace };
|
||||||
List<LogLevel> levels = new List<LogLevel>(logs.Length);
|
List<LogLevel> levels = new List<LogLevel>(logs.Length);
|
||||||
foreach (var log in logs)
|
foreach (var log in logs)
|
||||||
{
|
{
|
||||||
@ -196,6 +198,7 @@ namespace Ryujinx.Common.Logging
|
|||||||
case LogLevel.Guest : Guest = enabled ? new Log(LogLevel.Guest) : new Log?(); break;
|
case LogLevel.Guest : Guest = enabled ? new Log(LogLevel.Guest) : new Log?(); break;
|
||||||
case LogLevel.AccessLog : AccessLog = enabled ? new Log(LogLevel.AccessLog): new Log?(); break;
|
case LogLevel.AccessLog : AccessLog = enabled ? new Log(LogLevel.AccessLog): new Log?(); break;
|
||||||
case LogLevel.Stub : Stub = enabled ? new Log(LogLevel.Stub) : new Log?(); break;
|
case LogLevel.Stub : Stub = enabled ? new Log(LogLevel.Stub) : new Log?(); break;
|
||||||
|
case LogLevel.Trace : Trace = enabled ? new Log(LogLevel.Trace) : new Log?(); break;
|
||||||
default: throw new ArgumentException("Unknown Log Level");
|
default: throw new ArgumentException("Unknown Log Level");
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -17,6 +17,7 @@ namespace Ryujinx.Common.Logging
|
|||||||
LogLevel.Error => ConsoleColor.Red,
|
LogLevel.Error => ConsoleColor.Red,
|
||||||
LogLevel.Stub => ConsoleColor.DarkGray,
|
LogLevel.Stub => ConsoleColor.DarkGray,
|
||||||
LogLevel.Notice => ConsoleColor.Cyan,
|
LogLevel.Notice => ConsoleColor.Cyan,
|
||||||
|
LogLevel.Trace => ConsoleColor.DarkCyan,
|
||||||
_ => ConsoleColor.Gray,
|
_ => ConsoleColor.Gray,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -1,10 +1,14 @@
|
|||||||
using System.Reflection;
|
using Ryujinx.Common.Configuration;
|
||||||
|
using System;
|
||||||
|
using System.Reflection;
|
||||||
|
|
||||||
namespace Ryujinx.Common
|
namespace Ryujinx.Common
|
||||||
{
|
{
|
||||||
// DO NOT EDIT, filled by CI
|
// DO NOT EDIT, filled by CI
|
||||||
public static class ReleaseInformations
|
public static class ReleaseInformations
|
||||||
{
|
{
|
||||||
|
private const string FlatHubChannelOwner = "flathub";
|
||||||
|
|
||||||
public static string BuildVersion = "%%RYUJINX_BUILD_VERSION%%";
|
public static string BuildVersion = "%%RYUJINX_BUILD_VERSION%%";
|
||||||
public static string BuildGitHash = "%%RYUJINX_BUILD_GIT_HASH%%";
|
public static string BuildGitHash = "%%RYUJINX_BUILD_GIT_HASH%%";
|
||||||
public static string ReleaseChannelName = "%%RYUJINX_TARGET_RELEASE_CHANNEL_NAME%%";
|
public static string ReleaseChannelName = "%%RYUJINX_TARGET_RELEASE_CHANNEL_NAME%%";
|
||||||
@ -19,6 +23,11 @@ namespace Ryujinx.Common
|
|||||||
!ReleaseChannelRepo.StartsWith("%%");
|
!ReleaseChannelRepo.StartsWith("%%");
|
||||||
}
|
}
|
||||||
|
|
||||||
|
public static bool IsFlatHubBuild()
|
||||||
|
{
|
||||||
|
return IsValid() && ReleaseChannelOwner.Equals(FlatHubChannelOwner);
|
||||||
|
}
|
||||||
|
|
||||||
public static string GetVersion()
|
public static string GetVersion()
|
||||||
{
|
{
|
||||||
if (IsValid())
|
if (IsValid())
|
||||||
@ -30,5 +39,15 @@ namespace Ryujinx.Common
|
|||||||
return Assembly.GetEntryAssembly().GetCustomAttribute<AssemblyInformationalVersionAttribute>().InformationalVersion;
|
return Assembly.GetEntryAssembly().GetCustomAttribute<AssemblyInformationalVersionAttribute>().InformationalVersion;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
public static string GetBaseApplicationDirectory()
|
||||||
|
{
|
||||||
|
if (IsFlatHubBuild())
|
||||||
|
{
|
||||||
|
return AppDataManager.BaseDirPath;
|
||||||
|
}
|
||||||
|
|
||||||
|
return AppDomain.CurrentDomain.BaseDirectory;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -1,11 +1,10 @@
|
|||||||
using System;
|
using System;
|
||||||
|
using System.Numerics;
|
||||||
|
|
||||||
namespace Ryujinx.Common
|
namespace Ryujinx.Common
|
||||||
{
|
{
|
||||||
public static class BitUtils
|
public static class BitUtils
|
||||||
{
|
{
|
||||||
private static ReadOnlySpan<byte> ClzNibbleTbl => new byte[] { 4, 3, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 };
|
|
||||||
|
|
||||||
public static uint AlignUp(uint value, int size)
|
public static uint AlignUp(uint value, int size)
|
||||||
{
|
{
|
||||||
return (uint)AlignUp((int)value, size);
|
return (uint)AlignUp((int)value, size);
|
||||||
@ -76,60 +75,7 @@ namespace Ryujinx.Common
|
|||||||
|
|
||||||
public static int Pow2RoundDown(int value)
|
public static int Pow2RoundDown(int value)
|
||||||
{
|
{
|
||||||
return IsPowerOfTwo32(value) ? value : Pow2RoundUp(value) >> 1;
|
return BitOperations.IsPow2(value) ? value : Pow2RoundUp(value) >> 1;
|
||||||
}
|
|
||||||
|
|
||||||
public static bool IsPowerOfTwo32(int value)
|
|
||||||
{
|
|
||||||
return value != 0 && (value & (value - 1)) == 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
public static bool IsPowerOfTwo64(long value)
|
|
||||||
{
|
|
||||||
return value != 0 && (value & (value - 1)) == 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
public static int CountLeadingZeros32(int value)
|
|
||||||
{
|
|
||||||
return (int)CountLeadingZeros((ulong)value, 32);
|
|
||||||
}
|
|
||||||
|
|
||||||
public static int CountLeadingZeros64(long value)
|
|
||||||
{
|
|
||||||
return (int)CountLeadingZeros((ulong)value, 64);
|
|
||||||
}
|
|
||||||
|
|
||||||
private static ulong CountLeadingZeros(ulong value, int size)
|
|
||||||
{
|
|
||||||
if (value == 0ul)
|
|
||||||
{
|
|
||||||
return (ulong)size;
|
|
||||||
}
|
|
||||||
|
|
||||||
int nibbleIdx = size;
|
|
||||||
int preCount, count = 0;
|
|
||||||
|
|
||||||
do
|
|
||||||
{
|
|
||||||
nibbleIdx -= 4;
|
|
||||||
preCount = ClzNibbleTbl[(int)(value >> nibbleIdx) & 0b1111];
|
|
||||||
count += preCount;
|
|
||||||
}
|
|
||||||
while (preCount == 4);
|
|
||||||
|
|
||||||
return (ulong)count;
|
|
||||||
}
|
|
||||||
|
|
||||||
public static int CountTrailingZeros32(int value)
|
|
||||||
{
|
|
||||||
int count = 0;
|
|
||||||
|
|
||||||
while (((value >> count) & 1) == 0)
|
|
||||||
{
|
|
||||||
count++;
|
|
||||||
}
|
|
||||||
|
|
||||||
return count;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
public static long ReverseBits64(long value)
|
public static long ReverseBits64(long value)
|
||||||
|
@ -28,5 +28,10 @@ namespace Ryujinx.Cpu
|
|||||||
{
|
{
|
||||||
_translator.Execute(context, address);
|
_translator.Execute(context, address);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
public void InvalidateCacheRegion(ulong address, ulong size)
|
||||||
|
{
|
||||||
|
_translator.InvalidateJitCacheRegion(address, size);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -1,11 +1,15 @@
|
|||||||
using Ryujinx.Graphics.Device;
|
using Ryujinx.Common;
|
||||||
|
using Ryujinx.Graphics.Device;
|
||||||
using Ryujinx.Graphics.GAL;
|
using Ryujinx.Graphics.GAL;
|
||||||
using Ryujinx.Graphics.Gpu.Engine.Types;
|
using Ryujinx.Graphics.Gpu.Engine.Types;
|
||||||
using Ryujinx.Graphics.Gpu.Image;
|
using Ryujinx.Graphics.Gpu.Image;
|
||||||
using Ryujinx.Graphics.Texture;
|
using Ryujinx.Graphics.Texture;
|
||||||
|
using Ryujinx.Memory;
|
||||||
using System;
|
using System;
|
||||||
using System.Collections.Generic;
|
using System.Collections.Generic;
|
||||||
using System.Runtime.CompilerServices;
|
using System.Runtime.CompilerServices;
|
||||||
|
using System.Runtime.InteropServices;
|
||||||
|
using System.Runtime.Intrinsics;
|
||||||
|
|
||||||
namespace Ryujinx.Graphics.Gpu.Engine.Twod
|
namespace Ryujinx.Graphics.Gpu.Engine.Twod
|
||||||
{
|
{
|
||||||
@ -44,6 +48,180 @@ namespace Ryujinx.Graphics.Gpu.Engine.Twod
|
|||||||
/// <param name="data">Data to be written</param>
|
/// <param name="data">Data to be written</param>
|
||||||
public void Write(int offset, int data) => _state.Write(offset, data);
|
public void Write(int offset, int data) => _state.Write(offset, data);
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// Determines if data is compatible between the source and destination texture.
|
||||||
|
/// The two textures must have the same size, layout, and bytes per pixel.
|
||||||
|
/// </summary>
|
||||||
|
/// <param name="lhs">Info for the first texture</param>
|
||||||
|
/// <param name="rhs">Info for the second texture</param>
|
||||||
|
/// <param name="lhsFormat">Format of the first texture</param>
|
||||||
|
/// <param name="rhsFormat">Format of the second texture</param>
|
||||||
|
/// <returns>True if the data is compatible, false otherwise</returns>
|
||||||
|
private bool IsDataCompatible(TwodTexture lhs, TwodTexture rhs, FormatInfo lhsFormat, FormatInfo rhsFormat)
|
||||||
|
{
|
||||||
|
if (lhsFormat.BytesPerPixel != rhsFormat.BytesPerPixel ||
|
||||||
|
lhs.Height != rhs.Height ||
|
||||||
|
lhs.Depth != rhs.Depth ||
|
||||||
|
lhs.LinearLayout != rhs.LinearLayout ||
|
||||||
|
lhs.MemoryLayout.Packed != rhs.MemoryLayout.Packed)
|
||||||
|
{
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (lhs.LinearLayout)
|
||||||
|
{
|
||||||
|
return lhs.Stride == rhs.Stride;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return lhs.Width == rhs.Width;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// Determine if the given region covers the full texture, also considering width alignment.
|
||||||
|
/// </summary>
|
||||||
|
/// <param name="texture">The texture to check</param>
|
||||||
|
/// <param name="formatInfo"></param>
|
||||||
|
/// <param name="x1">Region start x</param>
|
||||||
|
/// <param name="y1">Region start y</param>
|
||||||
|
/// <param name="x2">Region end x</param>
|
||||||
|
/// <param name="y2">Region end y</param>
|
||||||
|
/// <returns>True if the region covers the full texture, false otherwise</returns>
|
||||||
|
private bool IsCopyRegionComplete(TwodTexture texture, FormatInfo formatInfo, int x1, int y1, int x2, int y2)
|
||||||
|
{
|
||||||
|
if (x1 != 0 || y1 != 0 || y2 != texture.Height)
|
||||||
|
{
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
int width;
|
||||||
|
int widthAlignment;
|
||||||
|
|
||||||
|
if (texture.LinearLayout)
|
||||||
|
{
|
||||||
|
widthAlignment = 1;
|
||||||
|
width = texture.Stride / formatInfo.BytesPerPixel;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
widthAlignment = Constants.GobAlignment / formatInfo.BytesPerPixel;
|
||||||
|
width = texture.Width;
|
||||||
|
}
|
||||||
|
|
||||||
|
return width == BitUtils.AlignUp(x2, widthAlignment);
|
||||||
|
}
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// Performs a full data copy between two textures, reading and writing guest memory directly.
|
||||||
|
/// The textures must have a matching layout, size, and bytes per pixel.
|
||||||
|
/// </summary>
|
||||||
|
/// <param name="src">The source texture</param>
|
||||||
|
/// <param name="dst">The destination texture</param>
|
||||||
|
/// <param name="w">Copy width</param>
|
||||||
|
/// <param name="h">Copy height</param>
|
||||||
|
/// <param name="bpp">Bytes per pixel</param>
|
||||||
|
private void UnscaledFullCopy(TwodTexture src, TwodTexture dst, int w, int h, int bpp)
|
||||||
|
{
|
||||||
|
var srcCalculator = new OffsetCalculator(
|
||||||
|
w,
|
||||||
|
h,
|
||||||
|
src.Stride,
|
||||||
|
src.LinearLayout,
|
||||||
|
src.MemoryLayout.UnpackGobBlocksInY(),
|
||||||
|
src.MemoryLayout.UnpackGobBlocksInZ(),
|
||||||
|
bpp);
|
||||||
|
|
||||||
|
(int _, int srcSize) = srcCalculator.GetRectangleRange(0, 0, w, h);
|
||||||
|
|
||||||
|
var memoryManager = _channel.MemoryManager;
|
||||||
|
|
||||||
|
ulong srcGpuVa = src.Address.Pack();
|
||||||
|
ulong dstGpuVa = dst.Address.Pack();
|
||||||
|
|
||||||
|
ReadOnlySpan<byte> srcSpan = memoryManager.GetSpan(srcGpuVa, srcSize, true);
|
||||||
|
|
||||||
|
int width;
|
||||||
|
int height = src.Height;
|
||||||
|
if (src.LinearLayout)
|
||||||
|
{
|
||||||
|
width = src.Stride / bpp;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
width = src.Width;
|
||||||
|
}
|
||||||
|
|
||||||
|
// If the copy is not equal to the width and height of the texture, we will need to copy partially.
|
||||||
|
// It's worth noting that it has already been established that the src and dst are the same size.
|
||||||
|
|
||||||
|
if (w == width && h == height)
|
||||||
|
{
|
||||||
|
memoryManager.Write(dstGpuVa, srcSpan);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
using WritableRegion dstRegion = memoryManager.GetWritableRegion(dstGpuVa, srcSize, true);
|
||||||
|
Span<byte> dstSpan = dstRegion.Memory.Span;
|
||||||
|
|
||||||
|
if (src.LinearLayout)
|
||||||
|
{
|
||||||
|
int stride = src.Stride;
|
||||||
|
int offset = 0;
|
||||||
|
int lineSize = width * bpp;
|
||||||
|
|
||||||
|
for (int y = 0; y < height; y++)
|
||||||
|
{
|
||||||
|
srcSpan.Slice(offset, lineSize).CopyTo(dstSpan.Slice(offset));
|
||||||
|
|
||||||
|
offset += stride;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
// Copy with the block linear layout in mind.
|
||||||
|
// Recreate the offset calculate with bpp 1 for copy.
|
||||||
|
|
||||||
|
int stride = w * bpp;
|
||||||
|
|
||||||
|
srcCalculator = new OffsetCalculator(
|
||||||
|
stride,
|
||||||
|
h,
|
||||||
|
0,
|
||||||
|
false,
|
||||||
|
src.MemoryLayout.UnpackGobBlocksInY(),
|
||||||
|
src.MemoryLayout.UnpackGobBlocksInZ(),
|
||||||
|
1);
|
||||||
|
|
||||||
|
int strideTrunc = BitUtils.AlignDown(stride, 16);
|
||||||
|
|
||||||
|
ReadOnlySpan<Vector128<byte>> srcVec = MemoryMarshal.Cast<byte, Vector128<byte>>(srcSpan);
|
||||||
|
Span<Vector128<byte>> dstVec = MemoryMarshal.Cast<byte, Vector128<byte>>(dstSpan);
|
||||||
|
|
||||||
|
for (int y = 0; y < h; y++)
|
||||||
|
{
|
||||||
|
int x = 0;
|
||||||
|
|
||||||
|
srcCalculator.SetY(y);
|
||||||
|
|
||||||
|
for (; x < strideTrunc; x += 16)
|
||||||
|
{
|
||||||
|
int offset = srcCalculator.GetOffset(x) >> 4;
|
||||||
|
|
||||||
|
dstVec[offset] = srcVec[offset];
|
||||||
|
}
|
||||||
|
|
||||||
|
for (; x < stride; x++)
|
||||||
|
{
|
||||||
|
int offset = srcCalculator.GetOffset(x);
|
||||||
|
|
||||||
|
dstSpan[offset] = srcSpan[offset];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
/// <summary>
|
/// <summary>
|
||||||
/// Performs the blit operation, triggered by the register write.
|
/// Performs the blit operation, triggered by the register write.
|
||||||
/// </summary>
|
/// </summary>
|
||||||
@ -114,16 +292,31 @@ namespace Ryujinx.Graphics.Gpu.Engine.Twod
|
|||||||
srcX1 = 0;
|
srcX1 = 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
FormatInfo dstCopyTextureFormat = dstCopyTexture.Format.Convert();
|
||||||
|
|
||||||
|
bool canDirectCopy = GraphicsConfig.Fast2DCopy &&
|
||||||
|
srcX2 == dstX2 && srcY2 == dstY2 &&
|
||||||
|
IsDataCompatible(srcCopyTexture, dstCopyTexture, srcCopyTextureFormat, dstCopyTextureFormat) &&
|
||||||
|
IsCopyRegionComplete(srcCopyTexture, srcCopyTextureFormat, srcX1, srcY1, srcX2, srcY2) &&
|
||||||
|
IsCopyRegionComplete(dstCopyTexture, dstCopyTextureFormat, dstX1, dstY1, dstX2, dstY2);
|
||||||
|
|
||||||
var srcTexture = memoryManager.Physical.TextureCache.FindOrCreateTexture(
|
var srcTexture = memoryManager.Physical.TextureCache.FindOrCreateTexture(
|
||||||
memoryManager,
|
memoryManager,
|
||||||
srcCopyTexture,
|
srcCopyTexture,
|
||||||
offset,
|
offset,
|
||||||
srcCopyTextureFormat,
|
srcCopyTextureFormat,
|
||||||
|
!canDirectCopy,
|
||||||
false,
|
false,
|
||||||
srcHint);
|
srcHint);
|
||||||
|
|
||||||
if (srcTexture == null)
|
if (srcTexture == null)
|
||||||
{
|
{
|
||||||
|
if (canDirectCopy)
|
||||||
|
{
|
||||||
|
// Directly copy the data on CPU.
|
||||||
|
UnscaledFullCopy(srcCopyTexture, dstCopyTexture, srcX2, srcY2, srcCopyTextureFormat.BytesPerPixel);
|
||||||
|
}
|
||||||
|
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -132,7 +325,6 @@ namespace Ryujinx.Graphics.Gpu.Engine.Twod
|
|||||||
// When the source texture that was found has a depth format,
|
// When the source texture that was found has a depth format,
|
||||||
// we must enforce the target texture also has a depth format,
|
// we must enforce the target texture also has a depth format,
|
||||||
// as copies between depth and color formats are not allowed.
|
// as copies between depth and color formats are not allowed.
|
||||||
FormatInfo dstCopyTextureFormat;
|
|
||||||
|
|
||||||
if (srcTexture.Format.IsDepthOrStencil())
|
if (srcTexture.Format.IsDepthOrStencil())
|
||||||
{
|
{
|
||||||
@ -148,6 +340,7 @@ namespace Ryujinx.Graphics.Gpu.Engine.Twod
|
|||||||
dstCopyTexture,
|
dstCopyTexture,
|
||||||
0,
|
0,
|
||||||
dstCopyTextureFormat,
|
dstCopyTextureFormat,
|
||||||
|
true,
|
||||||
srcTexture.ScaleMode == TextureScaleMode.Scaled,
|
srcTexture.ScaleMode == TextureScaleMode.Scaled,
|
||||||
dstHint);
|
dstHint);
|
||||||
|
|
||||||
|
@ -28,6 +28,14 @@ namespace Ryujinx.Graphics.Gpu
|
|||||||
/// </summary>
|
/// </summary>
|
||||||
public static bool FastGpuTime = true;
|
public static bool FastGpuTime = true;
|
||||||
|
|
||||||
|
/// <summary>
|
||||||
|
/// Enables or disables fast 2d engine texture copies entirely on CPU when possible.
|
||||||
|
/// Reduces stuttering and # of textures in games that copy textures around for streaming,
|
||||||
|
/// as textures will not need to be created for the copy, and the data does not need to be
|
||||||
|
/// flushed from GPU.
|
||||||
|
/// </summary>
|
||||||
|
public static bool Fast2DCopy = true;
|
||||||
|
|
||||||
/// <summary>
|
/// <summary>
|
||||||
/// Enables or disables the Just-in-Time compiler for GPU Macro code.
|
/// Enables or disables the Just-in-Time compiler for GPU Macro code.
|
||||||
/// </summary>
|
/// </summary>
|
||||||
|
@ -40,6 +40,7 @@ namespace Ryujinx.Graphics.Gpu.Image
|
|||||||
private readonly PhysicalMemory _physicalMemory;
|
private readonly PhysicalMemory _physicalMemory;
|
||||||
|
|
||||||
private readonly MultiRangeList<Texture> _textures;
|
private readonly MultiRangeList<Texture> _textures;
|
||||||
|
private readonly HashSet<Texture> _partiallyMappedTextures;
|
||||||
|
|
||||||
private Texture[] _textureOverlaps;
|
private Texture[] _textureOverlaps;
|
||||||
private OverlapInfo[] _overlapInfo;
|
private OverlapInfo[] _overlapInfo;
|
||||||
@ -57,6 +58,7 @@ namespace Ryujinx.Graphics.Gpu.Image
|
|||||||
_physicalMemory = physicalMemory;
|
_physicalMemory = physicalMemory;
|
||||||
|
|
||||||
_textures = new MultiRangeList<Texture>();
|
_textures = new MultiRangeList<Texture>();
|
||||||
|
_partiallyMappedTextures = new HashSet<Texture>();
|
||||||
|
|
||||||
_textureOverlaps = new Texture[OverlapsBufferInitialCapacity];
|
_textureOverlaps = new Texture[OverlapsBufferInitialCapacity];
|
||||||
_overlapInfo = new OverlapInfo[OverlapsBufferInitialCapacity];
|
_overlapInfo = new OverlapInfo[OverlapsBufferInitialCapacity];
|
||||||
@ -74,17 +76,7 @@ namespace Ryujinx.Graphics.Gpu.Image
|
|||||||
Texture[] overlaps = new Texture[10];
|
Texture[] overlaps = new Texture[10];
|
||||||
int overlapCount;
|
int overlapCount;
|
||||||
|
|
||||||
MultiRange unmapped;
|
MultiRange unmapped = ((MemoryManager)sender).GetPhysicalRegions(e.Address, e.Size);
|
||||||
|
|
||||||
try
|
|
||||||
{
|
|
||||||
unmapped = ((MemoryManager)sender).GetPhysicalRegions(e.Address, e.Size);
|
|
||||||
}
|
|
||||||
catch (InvalidMemoryRegionException)
|
|
||||||
{
|
|
||||||
// This event fires on Map in case any mappings are overwritten. In that case, there may not be an existing mapping.
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
lock (_textures)
|
lock (_textures)
|
||||||
{
|
{
|
||||||
@ -95,6 +87,24 @@ namespace Ryujinx.Graphics.Gpu.Image
|
|||||||
{
|
{
|
||||||
overlaps[i].Unmapped(unmapped);
|
overlaps[i].Unmapped(unmapped);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
// If any range was previously unmapped, we also need to purge
|
||||||
|
// all partially mapped texture, as they might be fully mapped now.
|
||||||
|
for (int i = 0; i < unmapped.Count; i++)
|
||||||
|
{
|
||||||
|
if (unmapped.GetSubRange(i).Address == MemoryManager.PteUnmapped)
|
||||||
|
{
|
||||||
|
lock (_partiallyMappedTextures)
|
||||||
|
{
|
||||||
|
foreach (var texture in _partiallyMappedTextures)
|
||||||
|
{
|
||||||
|
texture.Unmapped(unmapped);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/// <summary>
|
/// <summary>
|
||||||
@ -194,6 +204,7 @@ namespace Ryujinx.Graphics.Gpu.Image
|
|||||||
TwodTexture copyTexture,
|
TwodTexture copyTexture,
|
||||||
ulong offset,
|
ulong offset,
|
||||||
FormatInfo formatInfo,
|
FormatInfo formatInfo,
|
||||||
|
bool shouldCreate,
|
||||||
bool preferScaling = true,
|
bool preferScaling = true,
|
||||||
Size? sizeHint = null)
|
Size? sizeHint = null)
|
||||||
{
|
{
|
||||||
@ -234,6 +245,11 @@ namespace Ryujinx.Graphics.Gpu.Image
|
|||||||
flags |= TextureSearchFlags.WithUpscale;
|
flags |= TextureSearchFlags.WithUpscale;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (!shouldCreate)
|
||||||
|
{
|
||||||
|
flags |= TextureSearchFlags.NoCreate;
|
||||||
|
}
|
||||||
|
|
||||||
Texture texture = FindOrCreateTexture(memoryManager, flags, info, 0, sizeHint);
|
Texture texture = FindOrCreateTexture(memoryManager, flags, info, 0, sizeHint);
|
||||||
|
|
||||||
texture?.SynchronizeMemory();
|
texture?.SynchronizeMemory();
|
||||||
@ -480,15 +496,29 @@ namespace Ryujinx.Graphics.Gpu.Image
|
|||||||
|
|
||||||
return texture;
|
return texture;
|
||||||
}
|
}
|
||||||
|
else if (flags.HasFlag(TextureSearchFlags.NoCreate))
|
||||||
|
{
|
||||||
|
return null;
|
||||||
|
}
|
||||||
|
|
||||||
// Calculate texture sizes, used to find all overlapping textures.
|
// Calculate texture sizes, used to find all overlapping textures.
|
||||||
SizeInfo sizeInfo = info.CalculateSizeInfo(layerSize);
|
SizeInfo sizeInfo = info.CalculateSizeInfo(layerSize);
|
||||||
|
|
||||||
ulong size = (ulong)sizeInfo.TotalSize;
|
ulong size = (ulong)sizeInfo.TotalSize;
|
||||||
|
bool partiallyMapped = false;
|
||||||
|
|
||||||
if (range == null)
|
if (range == null)
|
||||||
{
|
{
|
||||||
range = memoryManager.GetPhysicalRegions(info.GpuAddress, size);
|
range = memoryManager.GetPhysicalRegions(info.GpuAddress, size);
|
||||||
|
|
||||||
|
for (int i = 0; i < range.Value.Count; i++)
|
||||||
|
{
|
||||||
|
if (range.Value.GetSubRange(i).Address == MemoryManager.PteUnmapped)
|
||||||
|
{
|
||||||
|
partiallyMapped = true;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
// Find view compatible matches.
|
// Find view compatible matches.
|
||||||
@ -658,7 +688,7 @@ namespace Ryujinx.Graphics.Gpu.Image
|
|||||||
else
|
else
|
||||||
{
|
{
|
||||||
bool dataOverlaps = texture.DataOverlaps(overlap, compatibility);
|
bool dataOverlaps = texture.DataOverlaps(overlap, compatibility);
|
||||||
|
|
||||||
if (!overlap.IsView && dataOverlaps && !incompatibleOverlaps.Exists(incompatible => incompatible.Group == overlap.Group))
|
if (!overlap.IsView && dataOverlaps && !incompatibleOverlaps.Exists(incompatible => incompatible.Group == overlap.Group))
|
||||||
{
|
{
|
||||||
incompatibleOverlaps.Add(new TextureIncompatibleOverlap(overlap.Group, compatibility));
|
incompatibleOverlaps.Add(new TextureIncompatibleOverlap(overlap.Group, compatibility));
|
||||||
@ -774,6 +804,14 @@ namespace Ryujinx.Graphics.Gpu.Image
|
|||||||
_textures.Add(texture);
|
_textures.Add(texture);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (partiallyMapped)
|
||||||
|
{
|
||||||
|
lock (_partiallyMappedTextures)
|
||||||
|
{
|
||||||
|
_partiallyMappedTextures.Add(texture);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
ShrinkOverlapsBufferIfNeeded();
|
ShrinkOverlapsBufferIfNeeded();
|
||||||
|
|
||||||
for (int i = 0; i < overlapsCount; i++)
|
for (int i = 0; i < overlapsCount; i++)
|
||||||
@ -1069,6 +1107,11 @@ namespace Ryujinx.Graphics.Gpu.Image
|
|||||||
{
|
{
|
||||||
_textures.Remove(texture);
|
_textures.Remove(texture);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
lock (_partiallyMappedTextures)
|
||||||
|
{
|
||||||
|
_partiallyMappedTextures.Remove(texture);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/// <summary>
|
/// <summary>
|
||||||
|
@ -236,7 +236,7 @@ namespace Ryujinx.Graphics.Gpu.Image
|
|||||||
}
|
}
|
||||||
|
|
||||||
/// <summary>
|
/// <summary>
|
||||||
/// Synchronize memory for a given texture.
|
/// Synchronize memory for a given texture.
|
||||||
/// If overlapping tracking handles are dirty, fully or partially synchronize the texture data.
|
/// If overlapping tracking handles are dirty, fully or partially synchronize the texture data.
|
||||||
/// </summary>
|
/// </summary>
|
||||||
/// <param name="texture">The texture being used</param>
|
/// <param name="texture">The texture being used</param>
|
||||||
@ -280,7 +280,7 @@ namespace Ryujinx.Graphics.Gpu.Image
|
|||||||
|
|
||||||
// Evaluate if any copy dependencies need to be fulfilled. A few rules:
|
// Evaluate if any copy dependencies need to be fulfilled. A few rules:
|
||||||
// If the copy handle needs to be synchronized, prefer our own state.
|
// If the copy handle needs to be synchronized, prefer our own state.
|
||||||
// If we need to be synchronized and there is a copy present, prefer the copy.
|
// If we need to be synchronized and there is a copy present, prefer the copy.
|
||||||
|
|
||||||
if (group.NeedsCopy && group.Copy(_context))
|
if (group.NeedsCopy && group.Copy(_context))
|
||||||
{
|
{
|
||||||
@ -618,7 +618,7 @@ namespace Ryujinx.Graphics.Gpu.Image
|
|||||||
}
|
}
|
||||||
|
|
||||||
/// <summary>
|
/// <summary>
|
||||||
/// Evaluate the range of tracking handles which a view texture overlaps with,
|
/// Evaluate the range of tracking handles which a view texture overlaps with,
|
||||||
/// using the view's position and slice/level counts.
|
/// using the view's position and slice/level counts.
|
||||||
/// </summary>
|
/// </summary>
|
||||||
/// <param name="firstLayer">The first layer of the texture</param>
|
/// <param name="firstLayer">The first layer of the texture</param>
|
||||||
@ -879,7 +879,7 @@ namespace Ryujinx.Graphics.Gpu.Image
|
|||||||
int sliceStart = Math.Clamp(offset, 0, subRangeSize);
|
int sliceStart = Math.Clamp(offset, 0, subRangeSize);
|
||||||
int sliceEnd = Math.Clamp(endOffset, 0, subRangeSize);
|
int sliceEnd = Math.Clamp(endOffset, 0, subRangeSize);
|
||||||
|
|
||||||
if (sliceStart != sliceEnd)
|
if (sliceStart != sliceEnd && item.Address != MemoryManager.PteUnmapped)
|
||||||
{
|
{
|
||||||
result.Add(GenerateHandle(item.Address + (ulong)sliceStart, (ulong)(sliceEnd - sliceStart)));
|
result.Add(GenerateHandle(item.Address + (ulong)sliceStart, (ulong)(sliceEnd - sliceStart)));
|
||||||
}
|
}
|
||||||
@ -1097,11 +1097,20 @@ namespace Ryujinx.Graphics.Gpu.Image
|
|||||||
{
|
{
|
||||||
// Single dirty region.
|
// Single dirty region.
|
||||||
var cpuRegionHandles = new CpuRegionHandle[TextureRange.Count];
|
var cpuRegionHandles = new CpuRegionHandle[TextureRange.Count];
|
||||||
|
int count = 0;
|
||||||
|
|
||||||
for (int i = 0; i < TextureRange.Count; i++)
|
for (int i = 0; i < TextureRange.Count; i++)
|
||||||
{
|
{
|
||||||
var currentRange = TextureRange.GetSubRange(i);
|
var currentRange = TextureRange.GetSubRange(i);
|
||||||
cpuRegionHandles[i] = GenerateHandle(currentRange.Address, currentRange.Size);
|
if (currentRange.Address != MemoryManager.PteUnmapped)
|
||||||
|
{
|
||||||
|
cpuRegionHandles[count++] = GenerateHandle(currentRange.Address, currentRange.Size);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (count != TextureRange.Count)
|
||||||
|
{
|
||||||
|
Array.Resize(ref cpuRegionHandles, count);
|
||||||
}
|
}
|
||||||
|
|
||||||
var groupHandle = new TextureGroupHandle(this, 0, Storage.Size, _views, 0, 0, 0, _allOffsets.Length, cpuRegionHandles);
|
var groupHandle = new TextureGroupHandle(this, 0, Storage.Size, _views, 0, 0, 0, _allOffsets.Length, cpuRegionHandles);
|
||||||
@ -1277,7 +1286,7 @@ namespace Ryujinx.Graphics.Gpu.Image
|
|||||||
TextureInfo info = Storage.Info;
|
TextureInfo info = Storage.Info;
|
||||||
TextureInfo otherInfo = other.Storage.Info;
|
TextureInfo otherInfo = other.Storage.Info;
|
||||||
|
|
||||||
if (TextureCompatibility.ViewLayoutCompatible(info, otherInfo, level, otherLevel) &&
|
if (TextureCompatibility.ViewLayoutCompatible(info, otherInfo, level, otherLevel) &&
|
||||||
TextureCompatibility.CopySizeMatches(info, otherInfo, level, otherLevel))
|
TextureCompatibility.CopySizeMatches(info, otherInfo, level, otherLevel))
|
||||||
{
|
{
|
||||||
// These textures are copy compatible. Create the dependency.
|
// These textures are copy compatible. Create the dependency.
|
||||||
|
@ -12,6 +12,7 @@ namespace Ryujinx.Graphics.Gpu.Image
|
|||||||
Strict = 1 << 0,
|
Strict = 1 << 0,
|
||||||
ForSampler = 1 << 1,
|
ForSampler = 1 << 1,
|
||||||
ForCopy = 1 << 2,
|
ForCopy = 1 << 2,
|
||||||
WithUpscale = 1 << 3
|
WithUpscale = 1 << 3,
|
||||||
|
NoCreate = 1 << 4
|
||||||
}
|
}
|
||||||
}
|
}
|
@ -17,6 +17,8 @@ namespace Ryujinx.Graphics.Gpu.Memory
|
|||||||
private const ulong BufferAlignmentSize = 0x1000;
|
private const ulong BufferAlignmentSize = 0x1000;
|
||||||
private const ulong BufferAlignmentMask = BufferAlignmentSize - 1;
|
private const ulong BufferAlignmentMask = BufferAlignmentSize - 1;
|
||||||
|
|
||||||
|
private const ulong MaxDynamicGrowthSize = 0x100000;
|
||||||
|
|
||||||
private readonly GpuContext _context;
|
private readonly GpuContext _context;
|
||||||
private readonly PhysicalMemory _physicalMemory;
|
private readonly PhysicalMemory _physicalMemory;
|
||||||
|
|
||||||
@ -166,10 +168,35 @@ namespace Ryujinx.Graphics.Gpu.Memory
|
|||||||
// Otherwise, we must delete the overlapping buffers and create a bigger buffer
|
// Otherwise, we must delete the overlapping buffers and create a bigger buffer
|
||||||
// that fits all the data we need. We also need to copy the contents from the
|
// that fits all the data we need. We also need to copy the contents from the
|
||||||
// old buffer(s) to the new buffer.
|
// old buffer(s) to the new buffer.
|
||||||
|
|
||||||
ulong endAddress = address + size;
|
ulong endAddress = address + size;
|
||||||
|
|
||||||
if (_bufferOverlaps[0].Address > address || _bufferOverlaps[0].EndAddress < endAddress)
|
if (_bufferOverlaps[0].Address > address || _bufferOverlaps[0].EndAddress < endAddress)
|
||||||
{
|
{
|
||||||
|
// Check if the following conditions are met:
|
||||||
|
// - We have a single overlap.
|
||||||
|
// - The overlap starts at or before the requested range. That is, the overlap happens at the end.
|
||||||
|
// - The size delta between the new, merged buffer and the old one is of at most 2 pages.
|
||||||
|
// In this case, we attempt to extend the buffer further than the requested range,
|
||||||
|
// this can potentially avoid future resizes if the application keeps using overlapping
|
||||||
|
// sequential memory.
|
||||||
|
// Allowing for 2 pages (rather than just one) is necessary to catch cases where the
|
||||||
|
// range crosses a page, and after alignment, ends having a size of 2 pages.
|
||||||
|
if (overlapsCount == 1 &&
|
||||||
|
address >= _bufferOverlaps[0].Address &&
|
||||||
|
endAddress - _bufferOverlaps[0].EndAddress <= BufferAlignmentSize * 2)
|
||||||
|
{
|
||||||
|
// Try to grow the buffer by 1.5x of its current size.
|
||||||
|
// This improves performance in the cases where the buffer is resized often by small amounts.
|
||||||
|
ulong existingSize = _bufferOverlaps[0].Size;
|
||||||
|
ulong growthSize = (existingSize + Math.Min(existingSize >> 1, MaxDynamicGrowthSize)) & ~BufferAlignmentMask;
|
||||||
|
|
||||||
|
size = Math.Max(size, growthSize);
|
||||||
|
endAddress = address + size;
|
||||||
|
|
||||||
|
overlapsCount = _buffers.FindOverlapsNonOverlapping(address, size, ref _bufferOverlaps);
|
||||||
|
}
|
||||||
|
|
||||||
for (int index = 0; index < overlapsCount; index++)
|
for (int index = 0; index < overlapsCount; index++)
|
||||||
{
|
{
|
||||||
Buffer buffer = _bufferOverlaps[index];
|
Buffer buffer = _bufferOverlaps[index];
|
||||||
@ -183,7 +210,9 @@ namespace Ryujinx.Graphics.Gpu.Memory
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
Buffer newBuffer = new Buffer(_context, _physicalMemory, address, endAddress - address, _bufferOverlaps.Take(overlapsCount));
|
ulong newSize = endAddress - address;
|
||||||
|
|
||||||
|
Buffer newBuffer = new Buffer(_context, _physicalMemory, address, newSize, _bufferOverlaps.Take(overlapsCount));
|
||||||
|
|
||||||
lock (_buffers)
|
lock (_buffers)
|
||||||
{
|
{
|
||||||
@ -202,7 +231,7 @@ namespace Ryujinx.Graphics.Gpu.Memory
|
|||||||
buffer.DisposeData();
|
buffer.DisposeData();
|
||||||
}
|
}
|
||||||
|
|
||||||
newBuffer.SynchronizeMemory(address, endAddress - address);
|
newBuffer.SynchronizeMemory(address, newSize);
|
||||||
|
|
||||||
// Existing buffers were modified, we need to rebind everything.
|
// Existing buffers were modified, we need to rebind everything.
|
||||||
NotifyBuffersModified?.Invoke();
|
NotifyBuffersModified?.Invoke();
|
||||||
|
@ -28,7 +28,7 @@ namespace Ryujinx.Graphics.Gpu.Memory
|
|||||||
private const int PtLvl1Bit = PtPageBits;
|
private const int PtLvl1Bit = PtPageBits;
|
||||||
private const int AddressSpaceBits = PtPageBits + PtLvl1Bits + PtLvl0Bits;
|
private const int AddressSpaceBits = PtPageBits + PtLvl1Bits + PtLvl0Bits;
|
||||||
|
|
||||||
public const ulong PteUnmapped = 0xffffffff_ffffffff;
|
public const ulong PteUnmapped = ulong.MaxValue;
|
||||||
|
|
||||||
private readonly ulong[][] _pageTable;
|
private readonly ulong[][] _pageTable;
|
||||||
|
|
||||||
@ -154,14 +154,15 @@ namespace Ryujinx.Graphics.Gpu.Memory
|
|||||||
/// <summary>
|
/// <summary>
|
||||||
/// Gets a writable region from GPU mapped memory.
|
/// Gets a writable region from GPU mapped memory.
|
||||||
/// </summary>
|
/// </summary>
|
||||||
/// <param name="address">Start address of the range</param>
|
/// <param name="va">Start address of the range</param>
|
||||||
/// <param name="size">Size in bytes to be range</param>
|
/// <param name="size">Size in bytes to be range</param>
|
||||||
|
/// <param name="tracked">True if write tracking is triggered on the span</param>
|
||||||
/// <returns>A writable region with the data at the specified memory location</returns>
|
/// <returns>A writable region with the data at the specified memory location</returns>
|
||||||
public WritableRegion GetWritableRegion(ulong va, int size)
|
public WritableRegion GetWritableRegion(ulong va, int size, bool tracked = false)
|
||||||
{
|
{
|
||||||
if (IsContiguous(va, size))
|
if (IsContiguous(va, size))
|
||||||
{
|
{
|
||||||
return Physical.GetWritableRegion(Translate(va), size);
|
return Physical.GetWritableRegion(Translate(va), size, tracked);
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
@ -169,7 +170,7 @@ namespace Ryujinx.Graphics.Gpu.Memory
|
|||||||
|
|
||||||
GetSpan(va, size).CopyTo(memory.Span);
|
GetSpan(va, size).CopyTo(memory.Span);
|
||||||
|
|
||||||
return new WritableRegion(this, va, memory);
|
return new WritableRegion(this, va, memory, tracked);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -339,7 +340,6 @@ namespace Ryujinx.Graphics.Gpu.Memory
|
|||||||
/// <param name="va">Virtual address of the range</param>
|
/// <param name="va">Virtual address of the range</param>
|
||||||
/// <param name="size">Size of the range</param>
|
/// <param name="size">Size of the range</param>
|
||||||
/// <returns>Multi-range with the physical regions</returns>
|
/// <returns>Multi-range with the physical regions</returns>
|
||||||
/// <exception cref="InvalidMemoryRegionException">The memory region specified by <paramref name="va"/> and <paramref name="size"/> is not fully mapped</exception>
|
|
||||||
public MultiRange GetPhysicalRegions(ulong va, ulong size)
|
public MultiRange GetPhysicalRegions(ulong va, ulong size)
|
||||||
{
|
{
|
||||||
if (IsContiguous(va, (int)size))
|
if (IsContiguous(va, (int)size))
|
||||||
@ -347,11 +347,6 @@ namespace Ryujinx.Graphics.Gpu.Memory
|
|||||||
return new MultiRange(Translate(va), size);
|
return new MultiRange(Translate(va), size);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (!IsMapped(va))
|
|
||||||
{
|
|
||||||
throw new InvalidMemoryRegionException($"The specified GPU virtual address 0x{va:X} is not mapped.");
|
|
||||||
}
|
|
||||||
|
|
||||||
ulong regionStart = Translate(va);
|
ulong regionStart = Translate(va);
|
||||||
ulong regionSize = Math.Min(size, PageSize - (va & PageMask));
|
ulong regionSize = Math.Min(size, PageSize - (va & PageMask));
|
||||||
|
|
||||||
@ -366,14 +361,10 @@ namespace Ryujinx.Graphics.Gpu.Memory
|
|||||||
|
|
||||||
for (int page = 0; page < pages - 1; page++)
|
for (int page = 0; page < pages - 1; page++)
|
||||||
{
|
{
|
||||||
if (!IsMapped(va + PageSize))
|
ulong currPa = Translate(va);
|
||||||
{
|
|
||||||
throw new InvalidMemoryRegionException($"The specified GPU virtual memory range 0x{va:X}..0x{(va + size):X} is not fully mapped.");
|
|
||||||
}
|
|
||||||
|
|
||||||
ulong newPa = Translate(va + PageSize);
|
ulong newPa = Translate(va + PageSize);
|
||||||
|
|
||||||
if (Translate(va) + PageSize != newPa)
|
if ((currPa != PteUnmapped || newPa != PteUnmapped) && currPa + PageSize != newPa)
|
||||||
{
|
{
|
||||||
regions.Add(new MemoryRange(regionStart, regionSize));
|
regions.Add(new MemoryRange(regionStart, regionSize));
|
||||||
regionStart = newPa;
|
regionStart = newPa;
|
||||||
@ -404,18 +395,35 @@ namespace Ryujinx.Graphics.Gpu.Memory
|
|||||||
{
|
{
|
||||||
MemoryRange currentRange = range.GetSubRange(i);
|
MemoryRange currentRange = range.GetSubRange(i);
|
||||||
|
|
||||||
ulong address = currentRange.Address & ~PageMask;
|
if (currentRange.Address != PteUnmapped)
|
||||||
ulong endAddress = (currentRange.EndAddress + PageMask) & ~PageMask;
|
|
||||||
|
|
||||||
while (address < endAddress)
|
|
||||||
{
|
{
|
||||||
if (Translate(va) != address)
|
ulong address = currentRange.Address & ~PageMask;
|
||||||
{
|
ulong endAddress = (currentRange.EndAddress + PageMask) & ~PageMask;
|
||||||
return false;
|
|
||||||
}
|
|
||||||
|
|
||||||
va += PageSize;
|
while (address < endAddress)
|
||||||
address += PageSize;
|
{
|
||||||
|
if (Translate(va) != address)
|
||||||
|
{
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
va += PageSize;
|
||||||
|
address += PageSize;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
ulong endVa = va + (((currentRange.Size) + PageMask) & ~PageMask);
|
||||||
|
|
||||||
|
while (va < endVa)
|
||||||
|
{
|
||||||
|
if (Translate(va) != PteUnmapped)
|
||||||
|
{
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
va += PageSize;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -7,8 +7,6 @@ using Ryujinx.Memory.Range;
|
|||||||
using Ryujinx.Memory.Tracking;
|
using Ryujinx.Memory.Tracking;
|
||||||
using System;
|
using System;
|
||||||
using System.Collections.Generic;
|
using System.Collections.Generic;
|
||||||
using System.Runtime.CompilerServices;
|
|
||||||
using System.Runtime.InteropServices;
|
|
||||||
using System.Threading;
|
using System.Threading;
|
||||||
|
|
||||||
namespace Ryujinx.Graphics.Gpu.Memory
|
namespace Ryujinx.Graphics.Gpu.Memory
|
||||||
@ -19,8 +17,6 @@ namespace Ryujinx.Graphics.Gpu.Memory
|
|||||||
/// </summary>
|
/// </summary>
|
||||||
class PhysicalMemory : IDisposable
|
class PhysicalMemory : IDisposable
|
||||||
{
|
{
|
||||||
public const int PageSize = 0x1000;
|
|
||||||
|
|
||||||
private readonly GpuContext _context;
|
private readonly GpuContext _context;
|
||||||
private IVirtualMemoryManagerTracked _cpuMemory;
|
private IVirtualMemoryManagerTracked _cpuMemory;
|
||||||
private int _referenceCount;
|
private int _referenceCount;
|
||||||
@ -103,24 +99,28 @@ namespace Ryujinx.Graphics.Gpu.Memory
|
|||||||
if (range.Count == 1)
|
if (range.Count == 1)
|
||||||
{
|
{
|
||||||
var singleRange = range.GetSubRange(0);
|
var singleRange = range.GetSubRange(0);
|
||||||
return _cpuMemory.GetSpan(singleRange.Address, (int)singleRange.Size, tracked);
|
if (singleRange.Address != MemoryManager.PteUnmapped)
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
Span<byte> data = new byte[range.GetSize()];
|
|
||||||
|
|
||||||
int offset = 0;
|
|
||||||
|
|
||||||
for (int i = 0; i < range.Count; i++)
|
|
||||||
{
|
{
|
||||||
var currentRange = range.GetSubRange(i);
|
return _cpuMemory.GetSpan(singleRange.Address, (int)singleRange.Size, tracked);
|
||||||
int size = (int)currentRange.Size;
|
|
||||||
_cpuMemory.GetSpan(currentRange.Address, size, tracked).CopyTo(data.Slice(offset, size));
|
|
||||||
offset += size;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
return data;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
Span<byte> data = new byte[range.GetSize()];
|
||||||
|
|
||||||
|
int offset = 0;
|
||||||
|
|
||||||
|
for (int i = 0; i < range.Count; i++)
|
||||||
|
{
|
||||||
|
var currentRange = range.GetSubRange(i);
|
||||||
|
int size = (int)currentRange.Size;
|
||||||
|
if (currentRange.Address != MemoryManager.PteUnmapped)
|
||||||
|
{
|
||||||
|
_cpuMemory.GetSpan(currentRange.Address, size, tracked).CopyTo(data.Slice(offset, size));
|
||||||
|
}
|
||||||
|
offset += size;
|
||||||
|
}
|
||||||
|
|
||||||
|
return data;
|
||||||
}
|
}
|
||||||
|
|
||||||
/// <summary>
|
/// <summary>
|
||||||
@ -156,11 +156,13 @@ namespace Ryujinx.Graphics.Gpu.Memory
|
|||||||
int offset = 0;
|
int offset = 0;
|
||||||
for (int i = 0; i < range.Count; i++)
|
for (int i = 0; i < range.Count; i++)
|
||||||
{
|
{
|
||||||
MemoryRange subrange = range.GetSubRange(i);
|
var currentRange = range.GetSubRange(i);
|
||||||
|
int size = (int)currentRange.Size;
|
||||||
GetSpan(subrange.Address, (int)subrange.Size).CopyTo(memory.Span.Slice(offset, (int)subrange.Size));
|
if (currentRange.Address != MemoryManager.PteUnmapped)
|
||||||
|
{
|
||||||
offset += (int)subrange.Size;
|
GetSpan(currentRange.Address, size).CopyTo(memory.Span.Slice(offset, size));
|
||||||
|
}
|
||||||
|
offset += size;
|
||||||
}
|
}
|
||||||
|
|
||||||
return new WritableRegion(new MultiRangeWritableBlock(range, this), 0, memory, tracked);
|
return new WritableRegion(new MultiRangeWritableBlock(range, this), 0, memory, tracked);
|
||||||
@ -253,7 +255,10 @@ namespace Ryujinx.Graphics.Gpu.Memory
|
|||||||
if (range.Count == 1)
|
if (range.Count == 1)
|
||||||
{
|
{
|
||||||
var singleRange = range.GetSubRange(0);
|
var singleRange = range.GetSubRange(0);
|
||||||
writeCallback(singleRange.Address, data);
|
if (singleRange.Address != MemoryManager.PteUnmapped)
|
||||||
|
{
|
||||||
|
writeCallback(singleRange.Address, data);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
@ -263,7 +268,10 @@ namespace Ryujinx.Graphics.Gpu.Memory
|
|||||||
{
|
{
|
||||||
var currentRange = range.GetSubRange(i);
|
var currentRange = range.GetSubRange(i);
|
||||||
int size = (int)currentRange.Size;
|
int size = (int)currentRange.Size;
|
||||||
writeCallback(currentRange.Address, data.Slice(offset, size));
|
if (currentRange.Address != MemoryManager.PteUnmapped)
|
||||||
|
{
|
||||||
|
writeCallback(currentRange.Address, data.Slice(offset, size));
|
||||||
|
}
|
||||||
offset += size;
|
offset += size;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -288,11 +296,20 @@ namespace Ryujinx.Graphics.Gpu.Memory
|
|||||||
public GpuRegionHandle BeginTracking(MultiRange range)
|
public GpuRegionHandle BeginTracking(MultiRange range)
|
||||||
{
|
{
|
||||||
var cpuRegionHandles = new CpuRegionHandle[range.Count];
|
var cpuRegionHandles = new CpuRegionHandle[range.Count];
|
||||||
|
int count = 0;
|
||||||
|
|
||||||
for (int i = 0; i < range.Count; i++)
|
for (int i = 0; i < range.Count; i++)
|
||||||
{
|
{
|
||||||
var currentRange = range.GetSubRange(i);
|
var currentRange = range.GetSubRange(i);
|
||||||
cpuRegionHandles[i] = _cpuMemory.BeginTracking(currentRange.Address, currentRange.Size);
|
if (currentRange.Address != MemoryManager.PteUnmapped)
|
||||||
|
{
|
||||||
|
cpuRegionHandles[count++] = _cpuMemory.BeginTracking(currentRange.Address, currentRange.Size);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (count != range.Count)
|
||||||
|
{
|
||||||
|
Array.Resize(ref cpuRegionHandles, count);
|
||||||
}
|
}
|
||||||
|
|
||||||
return new GpuRegionHandle(cpuRegionHandles);
|
return new GpuRegionHandle(cpuRegionHandles);
|
||||||
|
@ -113,7 +113,7 @@ namespace Ryujinx.Graphics.Gpu.Shader.Cache
|
|||||||
dataSpan[i++] = hash;
|
dataSpan[i++] = hash;
|
||||||
}
|
}
|
||||||
|
|
||||||
manifestHeader.UpdateChecksum(data.AsSpan().Slice(Unsafe.SizeOf<CacheManifestHeader>()));
|
manifestHeader.UpdateChecksum(data.AsSpan(Unsafe.SizeOf<CacheManifestHeader>()));
|
||||||
|
|
||||||
MemoryMarshal.Write(data, ref manifestHeader);
|
MemoryMarshal.Write(data, ref manifestHeader);
|
||||||
|
|
||||||
@ -447,12 +447,12 @@ namespace Ryujinx.Graphics.Gpu.Shader.Cache
|
|||||||
|
|
||||||
if (cb1DataAddress != 0 && cb1DataSize != 0)
|
if (cb1DataAddress != 0 && cb1DataSize != 0)
|
||||||
{
|
{
|
||||||
memoryManager.Physical.GetSpan(cb1DataAddress, cb1DataSize).CopyTo(code.AsSpan().Slice(size, cb1DataSize));
|
memoryManager.Physical.GetSpan(cb1DataAddress, cb1DataSize).CopyTo(code.AsSpan(size, cb1DataSize));
|
||||||
}
|
}
|
||||||
|
|
||||||
if (translatorContext2 != null)
|
if (translatorContext2 != null)
|
||||||
{
|
{
|
||||||
memoryManager.GetSpan(translatorContext2.Address, sizeA).CopyTo(code.AsSpan().Slice(size + cb1DataSize, sizeA));
|
memoryManager.GetSpan(translatorContext2.Address, sizeA).CopyTo(code.AsSpan(size + cb1DataSize, sizeA));
|
||||||
}
|
}
|
||||||
|
|
||||||
GuestGpuAccessorHeader gpuAccessorHeader = CreateGuestGpuAccessorCache(context.GpuAccessor);
|
GuestGpuAccessorHeader gpuAccessorHeader = CreateGuestGpuAccessorCache(context.GpuAccessor);
|
||||||
|
@ -40,7 +40,7 @@ namespace Ryujinx.Graphics.Gpu.Shader
|
|||||||
/// <summary>
|
/// <summary>
|
||||||
/// Version of the codegen (to be changed when codegen or guest format change).
|
/// Version of the codegen (to be changed when codegen or guest format change).
|
||||||
/// </summary>
|
/// </summary>
|
||||||
private const ulong ShaderCodeGenVersion = 3063;
|
private const ulong ShaderCodeGenVersion = 3054;
|
||||||
|
|
||||||
// Progress reporting helpers
|
// Progress reporting helpers
|
||||||
private volatile int _shaderCount;
|
private volatile int _shaderCount;
|
||||||
@ -206,7 +206,7 @@ namespace Ryujinx.Graphics.Gpu.Shader
|
|||||||
program = new ShaderProgram(entry.Header.Stage, "");
|
program = new ShaderProgram(entry.Header.Stage, "");
|
||||||
shaderProgramInfo = hostShaderEntries[0].ToShaderProgramInfo();
|
shaderProgramInfo = hostShaderEntries[0].ToShaderProgramInfo();
|
||||||
|
|
||||||
byte[] code = entry.Code.AsSpan().Slice(0, entry.Header.Size - entry.Header.Cb1DataSize).ToArray();
|
byte[] code = entry.Code.AsSpan(0, entry.Header.Size - entry.Header.Cb1DataSize).ToArray();
|
||||||
|
|
||||||
ShaderCodeHolder shader = new ShaderCodeHolder(program, shaderProgramInfo, code);
|
ShaderCodeHolder shader = new ShaderCodeHolder(program, shaderProgramInfo, code);
|
||||||
|
|
||||||
@ -244,7 +244,7 @@ namespace Ryujinx.Graphics.Gpu.Shader
|
|||||||
return true; // Exit early, the decoding step failed.
|
return true; // Exit early, the decoding step failed.
|
||||||
}
|
}
|
||||||
|
|
||||||
byte[] code = entry.Code.AsSpan().Slice(0, entry.Header.Size - entry.Header.Cb1DataSize).ToArray();
|
byte[] code = entry.Code.AsSpan(0, entry.Header.Size - entry.Header.Cb1DataSize).ToArray();
|
||||||
|
|
||||||
ShaderCodeHolder shader = new ShaderCodeHolder(program, shaderProgramInfo, code);
|
ShaderCodeHolder shader = new ShaderCodeHolder(program, shaderProgramInfo, code);
|
||||||
|
|
||||||
@ -394,8 +394,8 @@ namespace Ryujinx.Graphics.Gpu.Shader
|
|||||||
}
|
}
|
||||||
|
|
||||||
// NOTE: Vertex B comes first in the shader cache.
|
// NOTE: Vertex B comes first in the shader cache.
|
||||||
byte[] code = entry.Code.AsSpan().Slice(0, entry.Header.Size - entry.Header.Cb1DataSize).ToArray();
|
byte[] code = entry.Code.AsSpan(0, entry.Header.Size - entry.Header.Cb1DataSize).ToArray();
|
||||||
byte[] code2 = entry.Header.SizeA != 0 ? entry.Code.AsSpan().Slice(entry.Header.Size, entry.Header.SizeA).ToArray() : null;
|
byte[] code2 = entry.Header.SizeA != 0 ? entry.Code.AsSpan(entry.Header.Size, entry.Header.SizeA).ToArray() : null;
|
||||||
|
|
||||||
shaders[i] = new ShaderCodeHolder(program, shaderProgramInfo, code, code2);
|
shaders[i] = new ShaderCodeHolder(program, shaderProgramInfo, code, code2);
|
||||||
|
|
||||||
|
@ -124,7 +124,7 @@ namespace Ryujinx.Graphics.OpenGL
|
|||||||
|
|
||||||
GL.GetProgramBinary(Handle, size, out _, out BinaryFormat binFormat, data);
|
GL.GetProgramBinary(Handle, size, out _, out BinaryFormat binFormat, data);
|
||||||
|
|
||||||
BinaryPrimitives.WriteInt32LittleEndian(data.AsSpan().Slice(size, 4), (int)binFormat);
|
BinaryPrimitives.WriteInt32LittleEndian(data.AsSpan(size, 4), (int)binFormat);
|
||||||
|
|
||||||
return data;
|
return data;
|
||||||
}
|
}
|
||||||
|
@ -308,7 +308,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
|
|||||||
int attr = offset + elemIndex * 4;
|
int attr = offset + elemIndex * 4;
|
||||||
if (attr >= AttributeConsts.UserAttributeBase && attr < AttributeConsts.UserAttributeEnd)
|
if (attr >= AttributeConsts.UserAttributeBase && attr < AttributeConsts.UserAttributeEnd)
|
||||||
{
|
{
|
||||||
int index = (attr - AttributeConsts.UserAttributeBase) / 16;
|
int userAttr = attr - AttributeConsts.UserAttributeBase;
|
||||||
|
int index = userAttr / 16;
|
||||||
|
|
||||||
if (isStore)
|
if (isStore)
|
||||||
{
|
{
|
||||||
@ -316,7 +317,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
|
|||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
config.SetInputUserAttribute(index, perPatch);
|
config.SetInputUserAttribute(index, (userAttr >> 2) & 3, perPatch);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -54,6 +54,11 @@ namespace Ryujinx.Graphics.Shader.Translation
|
|||||||
private int _nextUsedInputAttributes;
|
private int _nextUsedInputAttributes;
|
||||||
private int _thisUsedInputAttributes;
|
private int _thisUsedInputAttributes;
|
||||||
|
|
||||||
|
public UInt128 NextInputAttributesComponents { get; private set; }
|
||||||
|
public UInt128 ThisInputAttributesComponents { get; private set; }
|
||||||
|
public UInt128 NextInputAttributesPerPatchComponents { get; private set; }
|
||||||
|
public UInt128 ThisInputAttributesPerPatchComponents { get; private set; }
|
||||||
|
|
||||||
private int _usedConstantBuffers;
|
private int _usedConstantBuffers;
|
||||||
private int _usedStorageBuffers;
|
private int _usedStorageBuffers;
|
||||||
private int _usedStorageBuffersWrite;
|
private int _usedStorageBuffersWrite;
|
||||||
@ -227,11 +232,12 @@ namespace Ryujinx.Graphics.Shader.Translation
|
|||||||
UsedOutputAttributes |= 1 << index;
|
UsedOutputAttributes |= 1 << index;
|
||||||
}
|
}
|
||||||
|
|
||||||
public void SetInputUserAttribute(int index, bool perPatch)
|
public void SetInputUserAttribute(int index, int component, bool perPatch)
|
||||||
{
|
{
|
||||||
if (perPatch)
|
if (perPatch)
|
||||||
{
|
{
|
||||||
UsedInputAttributesPerPatch |= 1 << index;
|
UsedInputAttributesPerPatch |= 1 << index;
|
||||||
|
ThisInputAttributesPerPatchComponents |= UInt128.Pow2(index * 4 + component);
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
@ -239,6 +245,7 @@ namespace Ryujinx.Graphics.Shader.Translation
|
|||||||
|
|
||||||
UsedInputAttributes |= mask;
|
UsedInputAttributes |= mask;
|
||||||
_thisUsedInputAttributes |= mask;
|
_thisUsedInputAttributes |= mask;
|
||||||
|
ThisInputAttributesComponents |= UInt128.Pow2(index * 4 + component);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -256,6 +263,8 @@ namespace Ryujinx.Graphics.Shader.Translation
|
|||||||
|
|
||||||
public void MergeFromtNextStage(ShaderConfig config)
|
public void MergeFromtNextStage(ShaderConfig config)
|
||||||
{
|
{
|
||||||
|
NextInputAttributesComponents = config.ThisInputAttributesComponents;
|
||||||
|
NextInputAttributesPerPatchComponents = config.ThisInputAttributesPerPatchComponents;
|
||||||
NextUsesFixedFuncAttributes = config.UsedFeatures.HasFlag(FeatureFlags.FixedFuncAttr);
|
NextUsesFixedFuncAttributes = config.UsedFeatures.HasFlag(FeatureFlags.FixedFuncAttr);
|
||||||
MergeOutputUserAttributes(config.UsedInputAttributes, config.UsedInputAttributesPerPatch);
|
MergeOutputUserAttributes(config.UsedInputAttributes, config.UsedInputAttributesPerPatch);
|
||||||
}
|
}
|
||||||
@ -319,6 +328,7 @@ namespace Ryujinx.Graphics.Shader.Translation
|
|||||||
public void SetAllInputUserAttributes()
|
public void SetAllInputUserAttributes()
|
||||||
{
|
{
|
||||||
UsedInputAttributes |= Constants.AllAttributesMask;
|
UsedInputAttributes |= Constants.AllAttributesMask;
|
||||||
|
ThisInputAttributesComponents |= ~UInt128.Zero >> (128 - Constants.MaxAttributes * 4);
|
||||||
}
|
}
|
||||||
|
|
||||||
public void SetAllOutputUserAttributes()
|
public void SetAllOutputUserAttributes()
|
||||||
@ -369,7 +379,7 @@ namespace Ryujinx.Graphics.Shader.Translation
|
|||||||
inst &= Instruction.Mask;
|
inst &= Instruction.Mask;
|
||||||
bool isImage = inst == Instruction.ImageLoad || inst == Instruction.ImageStore || inst == Instruction.ImageAtomic;
|
bool isImage = inst == Instruction.ImageLoad || inst == Instruction.ImageStore || inst == Instruction.ImageAtomic;
|
||||||
bool isWrite = inst == Instruction.ImageStore || inst == Instruction.ImageAtomic;
|
bool isWrite = inst == Instruction.ImageStore || inst == Instruction.ImageAtomic;
|
||||||
bool accurateType = inst != Instruction.Lod;
|
bool accurateType = inst != Instruction.Lod && inst != Instruction.TextureSize;
|
||||||
bool coherent = flags.HasFlag(TextureFlags.Coherent);
|
bool coherent = flags.HasFlag(TextureFlags.Coherent);
|
||||||
|
|
||||||
if (isImage)
|
if (isImage)
|
||||||
|
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user