Compare commits
3 Commits
Author | SHA1 | Date | |
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2099a3e84b | ||
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7d26e4ac7b | ||
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8d41402fa6 |
44
ARMeilleure/Decoders/OpCode32SimdCvtTB.cs
Normal file
44
ARMeilleure/Decoders/OpCode32SimdCvtTB.cs
Normal file
@@ -0,0 +1,44 @@
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namespace ARMeilleure.Decoders
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{
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class OpCode32SimdCvtTB : OpCode32, IOpCode32Simd
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{
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public int Vd { get; }
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public int Vm { get; }
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public bool Op { get; } // Convert to Half / Convert from Half
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public bool T { get; } // Top / Bottom
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public int Size { get; } // Double / Single
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public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCvtTB(inst, address, opCode, false);
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public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdCvtTB(inst, address, opCode, true);
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public OpCode32SimdCvtTB(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
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{
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IsThumb = isThumb;
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Op = ((opCode >> 16) & 0x1) != 0;
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T = ((opCode >> 7) & 0x1) != 0;
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Size = ((opCode >> 8) & 0x1);
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RegisterSize = Size == 1 ? RegisterSize.Int64 : RegisterSize.Int32;
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if (Size == 1)
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{
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if (Op)
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{
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Vm = ((opCode >> 1) & 0x10) | ((opCode >> 0) & 0xf);
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Vd = ((opCode >> 22) & 0x1) | ((opCode >> 11) & 0x1e);
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}
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else
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{
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Vm = ((opCode >> 5) & 0x1) | ((opCode << 1) & 0x1e);
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Vd = ((opCode >> 18) & 0x10) | ((opCode >> 12) & 0xf);
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}
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}
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else
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{
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Vm = ((opCode >> 5) & 0x1) | ((opCode << 1) & 0x1e);
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Vd = ((opCode >> 22) & 0x1) | ((opCode >> 11) & 0x1e);
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}
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}
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}
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}
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@@ -828,6 +828,7 @@ namespace ARMeilleure.Decoders
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SetVfp("<<<<11101x11110xxxxx101x11x0xxxx", InstName.Vcvt, InstEmit32.Vcvt_FI, OpCode32SimdCvtFI.Create, OpCode32SimdCvtFI.CreateT32); // FP32 to int.
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SetVfp("<<<<11101x11110xxxxx101x11x0xxxx", InstName.Vcvt, InstEmit32.Vcvt_FI, OpCode32SimdCvtFI.Create, OpCode32SimdCvtFI.CreateT32); // FP32 to int.
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SetVfp("<<<<11101x111000xxxx101xx1x0xxxx", InstName.Vcvt, InstEmit32.Vcvt_FI, OpCode32SimdCvtFI.Create, OpCode32SimdCvtFI.CreateT32); // Int to FP32.
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SetVfp("<<<<11101x111000xxxx101xx1x0xxxx", InstName.Vcvt, InstEmit32.Vcvt_FI, OpCode32SimdCvtFI.Create, OpCode32SimdCvtFI.CreateT32); // Int to FP32.
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SetVfp("111111101x1111xxxxxx101xx1x0xxxx", InstName.Vcvt, InstEmit32.Vcvt_RM, OpCode32SimdCvtFI.Create, OpCode32SimdCvtFI.CreateT32); // The many FP32 to int encodings (fp).
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SetVfp("111111101x1111xxxxxx101xx1x0xxxx", InstName.Vcvt, InstEmit32.Vcvt_RM, OpCode32SimdCvtFI.Create, OpCode32SimdCvtFI.CreateT32); // The many FP32 to int encodings (fp).
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SetVfp("<<<<11101x11001xxxxx101xx1x0xxxx", InstName.Vcvt, InstEmit32.Vcvt_TB, OpCode32SimdCvtTB.Create, OpCode32SimdCvtTB.CreateT32);
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SetVfp("<<<<11101x00xxxxxxxx101xx0x0xxxx", InstName.Vdiv, InstEmit32.Vdiv_S, OpCode32SimdRegS.Create, OpCode32SimdRegS.CreateT32);
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SetVfp("<<<<11101x00xxxxxxxx101xx0x0xxxx", InstName.Vdiv, InstEmit32.Vdiv_S, OpCode32SimdRegS.Create, OpCode32SimdRegS.CreateT32);
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SetVfp("<<<<11101xx0xxxxxxxx1011x0x10000", InstName.Vdup, InstEmit32.Vdup, OpCode32SimdDupGP.Create, OpCode32SimdDupGP.CreateT32);
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SetVfp("<<<<11101xx0xxxxxxxx1011x0x10000", InstName.Vdup, InstEmit32.Vdup, OpCode32SimdDupGP.Create, OpCode32SimdDupGP.CreateT32);
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SetVfp("<<<<11101x10xxxxxxxx101xx0x0xxxx", InstName.Vfma, InstEmit32.Vfma_S, OpCode32SimdRegS.Create, OpCode32SimdRegS.CreateT32);
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SetVfp("<<<<11101x10xxxxxxxx101xx0x0xxxx", InstName.Vfma, InstEmit32.Vfma_S, OpCode32SimdRegS.Create, OpCode32SimdRegS.CreateT32);
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@@ -261,6 +261,68 @@ namespace ARMeilleure.Instructions
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}
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}
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}
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}
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public static void Vcvt_TB(ArmEmitterContext context)
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{
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OpCode32SimdCvtTB op = (OpCode32SimdCvtTB)context.CurrOp;
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if (Optimizations.UseF16c)
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{
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Debug.Assert(!Optimizations.ForceLegacySse);
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if (op.Op)
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{
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Operand res = ExtractScalar(context, op.Size == 1 ? OperandType.FP64 : OperandType.FP32, op.Vm);
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if (op.Size == 1)
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{
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res = context.AddIntrinsic(Intrinsic.X86Cvtsd2ss, context.VectorZero(), res);
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}
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res = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, res, Const(X86GetRoundControl(FPRoundingMode.ToNearest)));
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res = context.VectorExtract16(res, 0);
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InsertScalar16(context, op.Vd, op.T, res);
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}
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else
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{
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Operand res = context.VectorCreateScalar(ExtractScalar16(context, op.Vm, op.T));
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res = context.AddIntrinsic(Intrinsic.X86Vcvtph2ps, res);
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if (op.Size == 1)
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{
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res = context.AddIntrinsic(Intrinsic.X86Cvtss2sd, context.VectorZero(), res);
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}
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res = context.VectorExtract(op.Size == 1 ? OperandType.I64 : OperandType.I32, res, 0);
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InsertScalar(context, op.Vd, res);
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}
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}
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else
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{
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if (op.Op)
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{
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// Convert to half
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Operand src = ExtractScalar(context, op.Size == 1 ? OperandType.FP64 : OperandType.FP32, op.Vm);
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MethodInfo method = op.Size == 1
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? typeof(SoftFloat64_16).GetMethod(nameof(SoftFloat64_16.FPConvert))
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: typeof(SoftFloat32_16).GetMethod(nameof(SoftFloat32_16.FPConvert));
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Operand res = context.Call(method, src);
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InsertScalar16(context, op.Vd, op.T, res);
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}
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else
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{
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// Convert from half
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Operand src = ExtractScalar16(context, op.Vm, op.T);
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MethodInfo method = op.Size == 1
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? typeof(SoftFloat16_64).GetMethod(nameof(SoftFloat16_64.FPConvert))
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: typeof(SoftFloat16_32).GetMethod(nameof(SoftFloat16_32.FPConvert));
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Operand res = context.Call(method, src);
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InsertScalar(context, op.Vd, res);
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}
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}
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}
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// VRINTA/M/N/P (floating-point).
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// VRINTA/M/N/P (floating-point).
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public static void Vrint_RM(ArmEmitterContext context)
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public static void Vrint_RM(ArmEmitterContext context)
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{
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{
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@@ -70,6 +70,22 @@ namespace ARMeilleure.Instructions
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context.Copy(vec, insert);
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context.Copy(vec, insert);
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}
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}
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public static Operand ExtractScalar16(ArmEmitterContext context, int reg, bool top)
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{
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return context.VectorExtract16(GetVecA32(reg >> 2), ((reg & 3) << 1) | (top ? 1 : 0));
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}
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public static void InsertScalar16(ArmEmitterContext context, int reg, bool top, Operand value)
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{
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Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.I32);
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Operand vec, insert;
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vec = GetVecA32(reg >> 2);
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insert = context.VectorInsert16(vec, value, ((reg & 3) << 1) | (top ? 1 : 0));
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context.Copy(vec, insert);
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}
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public static Operand ExtractElement(ArmEmitterContext context, int reg, int size, bool signed)
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public static Operand ExtractElement(ArmEmitterContext context, int reg, int size, bool signed)
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{
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{
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return EmitVectorExtract32(context, reg >> (4 - size), reg & ((16 >> size) - 1), size, signed);
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return EmitVectorExtract32(context, reg >> (4 - size), reg & ((16 >> size) - 1), size, signed);
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@@ -5,22 +5,48 @@ namespace Ryujinx.HLE.HOS.Services.Nfc.NfcManager
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class INfc : IpcService
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class INfc : IpcService
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{
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{
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private NfcPermissionLevel _permissionLevel;
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private NfcPermissionLevel _permissionLevel;
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private State _state;
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public INfc(NfcPermissionLevel permissionLevel)
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public INfc(NfcPermissionLevel permissionLevel)
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{
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{
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_permissionLevel = permissionLevel;
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_permissionLevel = permissionLevel;
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_state = State.NonInitialized;
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}
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}
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[CommandHipc(0)]
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[CommandHipc(0)]
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[CommandHipc(400)] // 4.0.0+
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[CommandHipc(400)] // 4.0.0+
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// Initialize()
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// Initialize(u64, u64, pid, buffer<unknown, 5>)
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public ResultCode Initialize(ServiceCtx context)
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public ResultCode Initialize(ServiceCtx context)
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{
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{
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_state = State.Initialized;
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Logger.Stub?.PrintStub(LogClass.ServiceNfc, new { _permissionLevel });
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Logger.Stub?.PrintStub(LogClass.ServiceNfc, new { _permissionLevel });
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return ResultCode.Success;
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return ResultCode.Success;
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}
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}
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[CommandHipc(1)]
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[CommandHipc(401)] // 4.0.0+
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// Finalize()
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public ResultCode Finalize(ServiceCtx context)
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{
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_state = State.NonInitialized;
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Logger.Stub?.PrintStub(LogClass.ServiceNfc, new { _permissionLevel });
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return ResultCode.Success;
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}
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[CommandHipc(2)]
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[CommandHipc(402)] // 4.0.0+
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// GetState() -> u32
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public ResultCode GetState(ServiceCtx context)
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{
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context.ResponseData.Write((int)_state);
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return ResultCode.Success;
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}
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[CommandHipc(3)]
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[CommandHipc(3)]
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[CommandHipc(403)] // 4.0.0+
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[CommandHipc(403)] // 4.0.0+
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// IsNfcEnabled() -> b8
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// IsNfcEnabled() -> b8
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8
Ryujinx.HLE/HOS/Services/Nfc/NfcManager/Types/State.cs
Normal file
8
Ryujinx.HLE/HOS/Services/Nfc/NfcManager/Types/State.cs
Normal file
@@ -0,0 +1,8 @@
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namespace Ryujinx.HLE.HOS.Services.Nfc.NfcManager
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{
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enum State
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{
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NonInitialized,
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Initialized
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}
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}
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@@ -92,5 +92,31 @@ namespace Ryujinx.Memory.Tests
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}
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}
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}
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}
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}
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}
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[Test]
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public void Test_AliasMapLeak()
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{
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if (OperatingSystem.IsMacOS())
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{
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// Memory aliasing tests fail on CI at the moment.
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return;
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}
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ulong pageSize = 4096;
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ulong size = 100000 * pageSize; // The mappings limit on Linux is usually around 65K, so let's make sure we are above that.
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using MemoryBlock backing = new MemoryBlock(pageSize, MemoryAllocationFlags.Mirrorable);
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using MemoryBlock toAlias = new MemoryBlock(size, MemoryAllocationFlags.Reserve | MemoryAllocationFlags.ViewCompatible);
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for (ulong offset = 0; offset < size; offset += pageSize)
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{
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toAlias.MapView(backing, 0, offset, pageSize);
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toAlias.Write(offset, 0xbadc0de);
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Assert.AreEqual(0xbadc0de, backing.Read<int>(0));
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toAlias.UnmapView(backing, offset, pageSize);
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}
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}
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}
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}
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}
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}
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@@ -177,7 +177,7 @@ namespace Ryujinx.Memory
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public static void UnmapView(IntPtr location, ulong size)
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public static void UnmapView(IntPtr location, ulong size)
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{
|
{
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mmap(location, size, MmapProts.PROT_NONE, MmapFlags.MAP_FIXED, -1, 0);
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mmap(location, size, MmapProts.PROT_NONE, MmapFlags.MAP_FIXED | MmapFlags.MAP_PRIVATE | MmapFlags.MAP_ANONYMOUS | MmapFlags.MAP_NORESERVE, -1, 0);
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}
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}
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}
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}
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}
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}
|
@@ -339,6 +339,93 @@ namespace Ryujinx.Tests.Cpu
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CompareAgainstUnicorn();
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CompareAgainstUnicorn();
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}
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}
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[Explicit]
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[Test, Pairwise, Description("VCVT<top>.F16.F32 <Sd>, <Dm>")]
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public void Vcvt_F32_F16([Values(0u, 1u, 2u, 3u)] uint rd,
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[Values(0u, 1u, 2u, 3u)] uint rm,
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[ValueSource(nameof(_1S_))] [Random(RndCnt)] uint s0,
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[ValueSource(nameof(_1S_))] [Random(RndCnt)] uint s1,
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[ValueSource(nameof(_1S_))] [Random(RndCnt)] uint s2,
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||||||
|
[ValueSource(nameof(_1S_))] [Random(RndCnt)] uint s3,
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||||||
|
[Values] bool top)
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||||||
|
{
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|
uint opcode = 0xeeb30a40; // VCVTB.F16.F32 S0, D0
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|
|
||||||
|
if (top)
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|
{
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|
opcode |= 1 << 7;
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|
}
|
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|
|
||||||
|
opcode |= ((rd & 0x1e) << 11) | ((rd & 0x1) << 22);
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|
opcode |= ((rm & 0x1e) >> 1) | ((rm & 0x1) << 5);
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||||||
|
|
||||||
|
V128 v0 = MakeVectorE0E1E2E3(s0, s1, s2, s3);
|
||||||
|
|
||||||
|
SingleOpcode(opcode, v0: v0);
|
||||||
|
|
||||||
|
CompareAgainstUnicorn();
|
||||||
|
}
|
||||||
|
|
||||||
|
[Explicit]
|
||||||
|
[Test, Pairwise, Description("VCVT<top>.F16.F64 <Sd>, <Dm>")]
|
||||||
|
public void Vcvt_F64_F16([Values(0u, 1u, 2u, 3u)] uint rd,
|
||||||
|
[Values(0u, 1u)] uint rm,
|
||||||
|
[ValueSource(nameof(_1D_F_))] ulong d0,
|
||||||
|
[ValueSource(nameof(_1D_F_))] ulong d1,
|
||||||
|
[Values] bool top)
|
||||||
|
{
|
||||||
|
uint opcode = 0xeeb30b40; // VCVTB.F16.F64 S0, D0
|
||||||
|
|
||||||
|
if (top)
|
||||||
|
{
|
||||||
|
opcode |= 1 << 7;
|
||||||
|
}
|
||||||
|
|
||||||
|
opcode |= ((rd & 0x1e) << 11) | ((rd & 0x1) << 22);
|
||||||
|
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
|
||||||
|
|
||||||
|
V128 v0 = MakeVectorE0E1(d0, d1);
|
||||||
|
|
||||||
|
SingleOpcode(opcode, v0: v0);
|
||||||
|
|
||||||
|
CompareAgainstUnicorn();
|
||||||
|
}
|
||||||
|
|
||||||
|
[Explicit]
|
||||||
|
[Test, Pairwise, Description("VCVT<top>.F<size>.F16 <Vd>, <Sm>")]
|
||||||
|
public void Vcvt_F16_Fx([Values(0u, 1u, 2u, 3u)] uint rd,
|
||||||
|
[Values(0u, 1u, 2u, 3u)] uint rm,
|
||||||
|
[ValueSource(nameof(_1D_F_))] ulong d0,
|
||||||
|
[ValueSource(nameof(_1D_F_))] ulong d1,
|
||||||
|
[Values] bool top,
|
||||||
|
[Values] bool sz)
|
||||||
|
{
|
||||||
|
uint opcode = 0xeeb20a40; // VCVTB.F32.F16 S0, S0
|
||||||
|
|
||||||
|
if (top)
|
||||||
|
{
|
||||||
|
opcode |= 1 << 7;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (sz)
|
||||||
|
{
|
||||||
|
opcode |= 1 << 8;
|
||||||
|
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
opcode |= ((rd & 0x1e) << 11) | ((rd & 0x1) << 22);
|
||||||
|
}
|
||||||
|
|
||||||
|
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
|
||||||
|
|
||||||
|
V128 v0 = MakeVectorE0E1(d0, d1);
|
||||||
|
|
||||||
|
SingleOpcode(opcode, v0: v0);
|
||||||
|
|
||||||
|
CompareAgainstUnicorn();
|
||||||
|
}
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
Reference in New Issue
Block a user