ARMeilleure: Add gfni acceleration (#3669)

* ARMeilleure: Add `GFNI` detection

This is intended for utilizing the `gf2p8affineqb` instruction

* ARMeilleure: Add `gf2p8affineqb`

Not using the VEX or EVEX-form of this instruction is intentional. There
are `GFNI`-chips that do not support AVX(so no VEX encoding) such as
Tremont(Lakefield) chips as well as Jasper Lake.

13df339fe7/GenuineIntel/GenuineIntel00806A1_Lakefield_LC_InstLatX64.txt (L1297-L1299)

13df339fe7/GenuineIntel/GenuineIntel00906C0_JasperLake_InstLatX64.txt (L1252-L1254)

* ARMeilleure: Add `gfni` acceleration of `Rbit_V`

Passes all `Rbit_V*` unit tests on my `i9-11900k`

* ARMeilleure: Add `gfni` acceleration of `S{l,r}i_V`

Also added a fast-path for when the shift amount is greater than the
size of the element.

* ARMeilleure: Add `gfni` acceleration of `Shl_V` and `Sshr_V`

* ARMeilleure: Increment InternalVersion

* ARMeilleure: Fix Intrinsic and Assembler Table alignment

`gf2p8affineqb` is the longest instruction name I know of. It shouldn't
get any wider than this.

* ARMeilleure: Remove SSE2+SHA requirement for GFNI

* ARMeilleure Add `X86GetGf2p8LogicalShiftLeft`

Used to generate GF(2^8) 8x8 bit-matrices for bit-shifting for the `gf2p8affineqb` instruction.

* ARMeilleure: Append `FeatureInfo7Ecx` to `FeatureInfo`

ARMeilleure/CodeGen/X86/AssemblerTable.cs

@@ -113,6 +113,7 @@ namespace ARMeilleure.CodeGen.X86
             Add(X86Instruction.Divps,         new InstructionInfo(BadOp,      BadOp,      BadOp,      BadOp,      0x00000f5e, InstructionFlags.Vex));
             Add(X86Instruction.Divsd,         new InstructionInfo(BadOp,      BadOp,      BadOp,      BadOp,      0x00000f5e, InstructionFlags.Vex | InstructionFlags.PrefixF2));
             Add(X86Instruction.Divss,         new InstructionInfo(BadOp,      BadOp,      BadOp,      BadOp,      0x00000f5e, InstructionFlags.Vex | InstructionFlags.PrefixF3));
+            Add(X86Instruction.Gf2p8affineqb, new InstructionInfo(BadOp,      BadOp,      BadOp,      BadOp,      0x000f3ace, InstructionFlags.Prefix66));
             Add(X86Instruction.Haddpd,        new InstructionInfo(BadOp,      BadOp,      BadOp,      BadOp,      0x00000f7c, InstructionFlags.Vex | InstructionFlags.Prefix66));
             Add(X86Instruction.Haddps,        new InstructionInfo(BadOp,      BadOp,      BadOp,      BadOp,      0x00000f7c, InstructionFlags.Vex | InstructionFlags.PrefixF2));
             Add(X86Instruction.Idiv,          new InstructionInfo(BadOp,      BadOp,      BadOp,      BadOp,      0x070000f7, InstructionFlags.None));

ARMeilleure/CodeGen/X86/HardwareCapabilities.cs

@@ -20,8 +20,9 @@ namespace ARMeilleure.CodeGen.X86
 
             if (maxNum >= 7)
             {
-                (_, int ebx7, _, _) = X86Base.CpuId(0x00000007, 0x00000000);
+                (_, int ebx7, int ecx7, _) = X86Base.CpuId(0x00000007, 0x00000000);
                 FeatureInfo7Ebx = (FeatureFlags7Ebx)ebx7;
+                FeatureInfo7Ecx = (FeatureFlags7Ecx)ecx7;
             }
         }
 
@@ -54,9 +55,16 @@ namespace ARMeilleure.CodeGen.X86
             Sha = 1 << 29
         }
 
+        [Flags]
+        public enum FeatureFlags7Ecx
+        {
+            Gfni = 1 << 8,
+        }
+
         public static FeatureFlags1Edx FeatureInfo1Edx { get; }
         public static FeatureFlags1Ecx FeatureInfo1Ecx { get; }
         public static FeatureFlags7Ebx FeatureInfo7Ebx { get; } = 0;
+        public static FeatureFlags7Ecx FeatureInfo7Ecx { get; } = 0;
 
         public static bool SupportsSse => FeatureInfo1Edx.HasFlag(FeatureFlags1Edx.Sse);
         public static bool SupportsSse2 => FeatureInfo1Edx.HasFlag(FeatureFlags1Edx.Sse2);
@@ -72,6 +80,7 @@ namespace ARMeilleure.CodeGen.X86
         public static bool SupportsAvx2 => FeatureInfo7Ebx.HasFlag(FeatureFlags7Ebx.Avx2) && SupportsAvx;
         public static bool SupportsF16c => FeatureInfo1Ecx.HasFlag(FeatureFlags1Ecx.F16c);
         public static bool SupportsSha => FeatureInfo7Ebx.HasFlag(FeatureFlags7Ebx.Sha);
+        public static bool SupportsGfni => FeatureInfo7Ecx.HasFlag(FeatureFlags7Ecx.Gfni);
 
         public static bool ForceLegacySse { get; set; }
 

ARMeilleure/CodeGen/X86/IntrinsicTable.cs

@@ -58,6 +58,7 @@ namespace ARMeilleure.CodeGen.X86
             Add(Intrinsic.X86Divps,         new IntrinsicInfo(X86Instruction.Divps,         IntrinsicType.Binary));
             Add(Intrinsic.X86Divsd,         new IntrinsicInfo(X86Instruction.Divsd,         IntrinsicType.Binary));
             Add(Intrinsic.X86Divss,         new IntrinsicInfo(X86Instruction.Divss,         IntrinsicType.Binary));
+            Add(Intrinsic.X86Gf2p8affineqb, new IntrinsicInfo(X86Instruction.Gf2p8affineqb, IntrinsicType.TernaryImm));
             Add(Intrinsic.X86Haddpd,        new IntrinsicInfo(X86Instruction.Haddpd,        IntrinsicType.Binary));
             Add(Intrinsic.X86Haddps,        new IntrinsicInfo(X86Instruction.Haddps,        IntrinsicType.Binary));
             Add(Intrinsic.X86Insertps,      new IntrinsicInfo(X86Instruction.Insertps,      IntrinsicType.TernaryImm));

ARMeilleure/CodeGen/X86/X86Instruction.cs

@@ -54,6 +54,7 @@ namespace ARMeilleure.CodeGen.X86
         Divps,
         Divsd,
         Divss,
+        Gf2p8affineqb,
         Haddpd,
         Haddps,
         Idiv,

ARMeilleure/Instructions/InstEmitSimdHelper.cs

@@ -243,6 +243,21 @@ namespace ARMeilleure.Instructions
             throw new ArgumentException($"Invalid rounding mode \"{roundMode}\".");
         }
 
+        public static ulong X86GetGf2p8LogicalShiftLeft(int shift)
+        {
+            ulong identity = 
+                (0b00000001UL << 56) |
+                (0b00000010UL << 48) |
+                (0b00000100UL << 40) |
+                (0b00001000UL << 32) |
+                (0b00010000UL << 24) |
+                (0b00100000UL << 16) |
+                (0b01000000UL <<  8) |
+                (0b10000000UL <<  0);
+
+            return shift >= 0 ? identity >> (shift * 8) : identity << (-shift * 8);
+        }
+
         public static Operand EmitCountSetBits8(ArmEmitterContext context, Operand op) // "size" is 8 (SIMD&FP Inst.).
         {
             Debug.Assert(op.Type == OperandType.I32 || op.Type == OperandType.I64);

ARMeilleure/Instructions/InstEmitSimdLogical.cs

@@ -336,8 +336,32 @@ namespace ARMeilleure.Instructions
         {
             OpCodeSimd op = (OpCodeSimd)context.CurrOp;
 
-            Operand res = context.VectorZero();
+            if (Optimizations.UseGfni)
+            {
+                const long bitMatrix =
+                    (0b10000000L << 56) |
+                    (0b01000000L << 48) |
+                    (0b00100000L << 40) |
+                    (0b00010000L << 32) |
+                    (0b00001000L << 24) |
+                    (0b00000100L << 16) |
+                    (0b00000010L <<  8) |
+                    (0b00000001L <<  0);
 
+                Operand vBitMatrix = X86GetAllElements(context, bitMatrix);
+
+                Operand res = context.AddIntrinsic(Intrinsic.X86Gf2p8affineqb, GetVec(op.Rn), vBitMatrix, Const(0));
+
+                if (op.RegisterSize == RegisterSize.Simd64)
+                {
+                    res = context.VectorZeroUpper64(res);
+                }
+
+                context.Copy(GetVec(op.Rd), res);
+            }
+            else
+            {
+                Operand res = context.VectorZero();
                 int elems = op.RegisterSize == RegisterSize.Simd128 ? 16 : 8;
 
                 for (int index = 0; index < elems; index++)
@@ -351,6 +375,7 @@ namespace ARMeilleure.Instructions
 
                 context.Copy(GetVec(op.Rd), res);
             }
+        }
 
         private static Operand EmitReverseBits8Op(ArmEmitterContext context, Operand op)
         {

ARMeilleure/Instructions/InstEmitSimdShift.cs

@@ -88,8 +88,35 @@ namespace ARMeilleure.Instructions
             OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp;
 
             int shift = GetImmShl(op);
+            int eSize = 8 << op.Size;
 
-            if (Optimizations.UseSse2 && op.Size > 0)
+            if (shift >= eSize)
+            {
+                if ((op.RegisterSize == RegisterSize.Simd64))
+                {
+                    Operand res = context.VectorZeroUpper64(GetVec(op.Rd));
+
+                    context.Copy(GetVec(op.Rd), res);
+                }
+            }
+            else if (Optimizations.UseGfni && op.Size == 0)
+            {
+                Operand n = GetVec(op.Rn);
+
+                ulong bitMatrix = X86GetGf2p8LogicalShiftLeft(shift);
+
+                Operand vBitMatrix = X86GetElements(context, bitMatrix, bitMatrix);
+
+                Operand res = context.AddIntrinsic(Intrinsic.X86Gf2p8affineqb, n, vBitMatrix, Const(0));
+
+                if (op.RegisterSize == RegisterSize.Simd64)
+                {
+                    res = context.VectorZeroUpper64(res);
+                }
+
+                context.Copy(GetVec(op.Rd), res);
+            }
+            else if (Optimizations.UseSse2 && op.Size > 0)
             {
                 Operand n = GetVec(op.Rn);
 
@@ -396,10 +423,40 @@ namespace ARMeilleure.Instructions
         {
             OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp;
 
-            if (Optimizations.UseSse2 && op.Size > 0 && op.Size < 3)
-            {
             int shift = GetImmShr(op);
 
+            if (Optimizations.UseGfni && op.Size == 0)
+            {
+                Operand n = GetVec(op.Rn);
+
+                ulong bitMatrix;
+
+                if (shift < 8)
+                {
+                    bitMatrix = X86GetGf2p8LogicalShiftLeft(-shift);
+
+                    // Extend sign-bit
+                    bitMatrix |= 0x8080808080808080UL >> (64 - shift * 8);
+                }
+                else
+                {
+                    // Replicate sign-bit into all bits
+                    bitMatrix = 0x8080808080808080UL;
+                }
+
+                Operand vBitMatrix = X86GetElements(context, bitMatrix, bitMatrix);
+
+                Operand res = context.AddIntrinsic(Intrinsic.X86Gf2p8affineqb, n, vBitMatrix, Const(0));
+
+                if (op.RegisterSize == RegisterSize.Simd64)
+                {
+                    res = context.VectorZeroUpper64(res);
+                }
+
+                context.Copy(GetVec(op.Rd), res);
+            }
+            else if (Optimizations.UseSse2 && op.Size > 0 && op.Size < 3)
+            {
                 Operand n = GetVec(op.Rn);
 
                 Intrinsic sraInst = X86PsraInstruction[op.Size];
@@ -929,10 +986,44 @@ namespace ARMeilleure.Instructions
             OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp;
 
             int shift = GetImmShl(op);
+            int eSize = 8 << op.Size;
 
             ulong mask = shift != 0 ? ulong.MaxValue >> (64 - shift) : 0UL;
 
-            if (Optimizations.UseSse2 && op.Size > 0)
+            if (shift >= eSize)
+            {
+                if ((op.RegisterSize == RegisterSize.Simd64) || scalar)
+                {
+                    Operand res = context.VectorZeroUpper64(GetVec(op.Rd));
+
+                    context.Copy(GetVec(op.Rd), res);
+                }
+            }
+            else if (Optimizations.UseGfni && op.Size == 0)
+            {
+                Operand d = GetVec(op.Rd);
+                Operand n = GetVec(op.Rn);
+
+                ulong bitMatrix = X86GetGf2p8LogicalShiftLeft(shift);
+
+                Operand vBitMatrix = X86GetElements(context, bitMatrix, bitMatrix);
+
+                Operand nShifted = context.AddIntrinsic(Intrinsic.X86Gf2p8affineqb, n, vBitMatrix, Const(0));
+
+                Operand dMask = X86GetAllElements(context, (long)mask * _masks_SliSri[op.Size]);
+
+                Operand dMasked = context.AddIntrinsic(Intrinsic.X86Pand, d, dMask);
+
+                Operand res = context.AddIntrinsic(Intrinsic.X86Por, nShifted, dMasked);
+
+                if ((op.RegisterSize == RegisterSize.Simd64) || scalar)
+                {
+                    res = context.VectorZeroUpper64(res);
+                }
+
+                context.Copy(d, res);
+            }
+            else if (Optimizations.UseSse2 && op.Size > 0)
             {
                 Operand d = GetVec(op.Rd);
                 Operand n = GetVec(op.Rn);
@@ -988,7 +1079,40 @@ namespace ARMeilleure.Instructions
 
             ulong mask = (ulong.MaxValue << (eSize - shift)) & (ulong.MaxValue >> (64 - eSize));
 
-            if (Optimizations.UseSse2 && op.Size > 0)
+            if (shift >= eSize)
+            {
+                if ((op.RegisterSize == RegisterSize.Simd64) || scalar)
+                {
+                    Operand res = context.VectorZeroUpper64(GetVec(op.Rd));
+
+                    context.Copy(GetVec(op.Rd), res);
+                }
+            }
+            else if (Optimizations.UseGfni && op.Size == 0)
+            {
+                Operand d = GetVec(op.Rd);
+                Operand n = GetVec(op.Rn);
+
+                ulong bitMatrix = X86GetGf2p8LogicalShiftLeft(-shift);
+
+                Operand vBitMatrix = X86GetElements(context, bitMatrix, bitMatrix);
+
+                Operand nShifted = context.AddIntrinsic(Intrinsic.X86Gf2p8affineqb, n, vBitMatrix, Const(0));
+
+                Operand dMask = X86GetAllElements(context, (long)mask * _masks_SliSri[op.Size]);
+
+                Operand dMasked = context.AddIntrinsic(Intrinsic.X86Pand, d, dMask);
+
+                Operand res = context.AddIntrinsic(Intrinsic.X86Por, nShifted, dMasked);
+
+                if ((op.RegisterSize == RegisterSize.Simd64) || scalar)
+                {
+                    res = context.VectorZeroUpper64(res);
+                }
+
+                context.Copy(d, res);
+            }
+            else if (Optimizations.UseSse2 && op.Size > 0)
             {
                 Operand d = GetVec(op.Rd);
                 Operand n = GetVec(op.Rn);

ARMeilleure/IntermediateRepresentation/Intrinsic.cs

@@ -47,6 +47,7 @@ namespace ARMeilleure.IntermediateRepresentation
         X86Divps,
         X86Divsd,
         X86Divss,
+        X86Gf2p8affineqb,
         X86Haddpd,
         X86Haddps,
         X86Insertps,

ARMeilleure/Optimizations.cs

@@ -22,6 +22,7 @@ namespace ARMeilleure
         public static bool UseAesniIfAvailable     { get; set; } = true;
         public static bool UsePclmulqdqIfAvailable { get; set; } = true;
         public static bool UseShaIfAvailable       { get; set; } = true;
+        public static bool UseGfniIfAvailable      { get; set; } = true;
 
         public static bool ForceLegacySse
         {
@@ -42,5 +43,6 @@ namespace ARMeilleure
         internal static bool UseAesni     => UseAesniIfAvailable     && HardwareCapabilities.SupportsAesni;
         internal static bool UsePclmulqdq => UsePclmulqdqIfAvailable && HardwareCapabilities.SupportsPclmulqdq;
         internal static bool UseSha       => UseShaIfAvailable       && HardwareCapabilities.SupportsSha;
+        internal static bool UseGfni      => UseGfniIfAvailable      && HardwareCapabilities.SupportsGfni;
     }
 }

ARMeilleure/Translation/PTC/Ptc.cs

@@ -27,7 +27,7 @@ namespace ARMeilleure.Translation.PTC
         private const string OuterHeaderMagicString = "PTCohd\0\0";
         private const string InnerHeaderMagicString = "PTCihd\0\0";
 
-        private const uint InternalVersion = 3703; //! To be incremented manually for each change to the ARMeilleure project.
+        private const uint InternalVersion = 3710; //! To be incremented manually for each change to the ARMeilleure project.
 
         private const string ActualDir = "0";
         private const string BackupDir = "1";
@@ -951,7 +951,8 @@ namespace ARMeilleure.Translation.PTC
             return new FeatureInfo(
                 (uint)HardwareCapabilities.FeatureInfo1Ecx,
                 (uint)HardwareCapabilities.FeatureInfo1Edx,
-                (uint)HardwareCapabilities.FeatureInfo7Ebx);
+                (uint)HardwareCapabilities.FeatureInfo7Ebx,
+                (uint)HardwareCapabilities.FeatureInfo7Ecx);
         }
 
         private static byte GetMemoryManagerMode()
@@ -971,7 +972,7 @@ namespace ARMeilleure.Translation.PTC
             return osPlatform;
         }
 
-        [StructLayout(LayoutKind.Sequential, Pack = 1/*, Size = 54*/)]
+        [StructLayout(LayoutKind.Sequential, Pack = 1/*, Size = 58*/)]
         private struct OuterHeader
         {
             public ulong Magic;
@@ -1002,8 +1003,8 @@ namespace ARMeilleure.Translation.PTC
             }
         }
 
-        [StructLayout(LayoutKind.Sequential, Pack = 1/*, Size = 12*/)]
+        [StructLayout(LayoutKind.Sequential, Pack = 1/*, Size = 16*/)]
-        private record struct FeatureInfo(uint FeatureInfo0, uint FeatureInfo1, uint FeatureInfo2);
+        private record struct FeatureInfo(uint FeatureInfo0, uint FeatureInfo1, uint FeatureInfo2, uint FeatureInfo3);
 
         [StructLayout(LayoutKind.Sequential, Pack = 1/*, Size = 128*/)]
         private struct InnerHeader

Ryujinx.Common/Logging/LogClass.cs

@@ -30,6 +30,7 @@ namespace Ryujinx.Common.Logging
         ServiceBsd,
         ServiceBtm,
         ServiceCaps,
+        ServiceFatal,
         ServiceFriend,
         ServiceFs,
         ServiceHid,

Ryujinx.Graphics.Gpu/Shader/DiskCache/DiskCacheHostStorage.cs

@@ -22,7 +22,7 @@ namespace Ryujinx.Graphics.Gpu.Shader.DiskCache
         private const ushort FileFormatVersionMajor = 1;
         private const ushort FileFormatVersionMinor = 2;
         private const uint FileFormatVersionPacked = ((uint)FileFormatVersionMajor << 16) | FileFormatVersionMinor;
-        private const uint CodeGenVersion = 3697;
+        private const uint CodeGenVersion = 3728;
 
         private const string SharedTocFileName = "shared.toc";
         private const string SharedDataFileName = "shared.data";

Ryujinx.Graphics.Shader/CodeGen/Glsl/Declarations.cs

@@ -2,6 +2,7 @@ using Ryujinx.Common;
 using Ryujinx.Graphics.Shader.StructuredIr;
 using Ryujinx.Graphics.Shader.Translation;
 using System;
+using System.Collections.Generic;
 using System.Linq;
 using System.Numerics;
 
@@ -163,9 +164,17 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
                 }
                 else if (context.Config.Stage == ShaderStage.TessellationEvaluation)
                 {
+                    bool tessCw = context.Config.GpuAccessor.QueryTessCw();
+
+                    if (context.Config.Options.TargetApi == TargetApi.Vulkan)
+                    {
+                        // We invert the front face on Vulkan backend, so we need to do that here aswell.
+                        tessCw = !tessCw;
+                    }
+
                     string patchType = context.Config.GpuAccessor.QueryTessPatchType().ToGlsl();
                     string spacing = context.Config.GpuAccessor.QueryTessSpacing().ToGlsl();
-                    string windingOrder = context.Config.GpuAccessor.QueryTessCw() ? "cw" : "ccw";
+                    string windingOrder = tessCw ? "cw" : "ccw";
 
                     context.AppendLine($"layout ({patchType}, {spacing}, {windingOrder}) in;");
                     context.AppendLine();
@@ -185,14 +194,14 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
                     context.AppendLine();
                 }
 
-                if (context.Config.UsedInputAttributesPerPatch != 0)
+                if (context.Config.UsedInputAttributesPerPatch.Count != 0)
                 {
                     DeclareInputAttributesPerPatch(context, context.Config.UsedInputAttributesPerPatch);
 
                     context.AppendLine();
                 }
 
-                if (context.Config.UsedOutputAttributesPerPatch != 0)
+                if (context.Config.UsedOutputAttributesPerPatch.Count != 0)
                 {
                     DeclareUsedOutputAttributesPerPatch(context, context.Config.UsedOutputAttributesPerPatch);
 
@@ -509,13 +518,11 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
             }
         }
 
-        private static void DeclareInputAttributesPerPatch(CodeGenContext context, int usedAttributes)
+        private static void DeclareInputAttributesPerPatch(CodeGenContext context, HashSet<int> attrs)
         {
-            while (usedAttributes != 0)
+            foreach (int attr in attrs.OrderBy(x => x))
             {
-                int index = BitOperations.TrailingZeroCount(usedAttributes);
+                DeclareInputAttributePerPatch(context, attr);
-                DeclareInputAttributePerPatch(context, index);
-                usedAttributes &= ~(1 << index);
             }
         }
 
@@ -566,16 +573,10 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
 
         private static void DeclareInputAttributePerPatch(CodeGenContext context, int attr)
         {
-            string layout = string.Empty;
+            int location = context.Config.GetPerPatchAttributeLocation(attr);
-
-            if (context.Config.Options.TargetApi == TargetApi.Vulkan)
-            {
-                layout = $"layout (location = {32 + attr}) ";
-            }
-
             string name = $"{DefaultNames.PerPatchAttributePrefix}{attr}";
 
-            context.AppendLine($"{layout}patch in vec4 {name};");
+            context.AppendLine($"layout (location = {location}) patch in vec4 {name};");
         }
 
         private static void DeclareOutputAttributes(CodeGenContext context, StructuredProgramInfo info)
@@ -624,28 +625,20 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
             }
         }
 
-        private static void DeclareUsedOutputAttributesPerPatch(CodeGenContext context, int usedAttributes)
+        private static void DeclareUsedOutputAttributesPerPatch(CodeGenContext context, HashSet<int> attrs)
         {
-            while (usedAttributes != 0)
+            foreach (int attr in attrs.OrderBy(x => x))
             {
-                int index = BitOperations.TrailingZeroCount(usedAttributes);
+                DeclareOutputAttributePerPatch(context, attr);
-                DeclareOutputAttributePerPatch(context, index);
-                usedAttributes &= ~(1 << index);
             }
         }
 
         private static void DeclareOutputAttributePerPatch(CodeGenContext context, int attr)
         {
-            string layout = string.Empty;
+            int location = context.Config.GetPerPatchAttributeLocation(attr);
-
-            if (context.Config.Options.TargetApi == TargetApi.Vulkan)
-            {
-                layout = $"layout (location = {32 + attr}) ";
-            }
-
             string name = $"{DefaultNames.PerPatchAttributePrefix}{attr}";
 
-            context.AppendLine($"{layout}patch out vec4 {name};");
+            context.AppendLine($"layout (location = {location}) patch out vec4 {name};");
         }
 
         private static void DeclareSupportUniformBlock(CodeGenContext context, ShaderStage stage, int scaleElements)

Ryujinx.Graphics.Shader/CodeGen/Glsl/OperandManager.cs

@@ -28,12 +28,6 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
 
         private static Dictionary<int, BuiltInAttribute> _builtInAttributes = new Dictionary<int, BuiltInAttribute>()
         {
-            { AttributeConsts.TessLevelOuter0, new BuiltInAttribute("gl_TessLevelOuter[0]", VariableType.F32)  },
-            { AttributeConsts.TessLevelOuter1, new BuiltInAttribute("gl_TessLevelOuter[1]", VariableType.F32)  },
-            { AttributeConsts.TessLevelOuter2, new BuiltInAttribute("gl_TessLevelOuter[2]", VariableType.F32)  },
-            { AttributeConsts.TessLevelOuter3, new BuiltInAttribute("gl_TessLevelOuter[3]", VariableType.F32)  },
-            { AttributeConsts.TessLevelInner0, new BuiltInAttribute("gl_TessLevelInner[0]", VariableType.F32)  },
-            { AttributeConsts.TessLevelInner1, new BuiltInAttribute("gl_TessLevelInner[1]", VariableType.F32)  },
             { AttributeConsts.Layer,         new BuiltInAttribute("gl_Layer",           VariableType.S32)  },
             { AttributeConsts.PointSize,     new BuiltInAttribute("gl_PointSize",       VariableType.F32)  },
             { AttributeConsts.PositionX,     new BuiltInAttribute("gl_Position.x",      VariableType.F32)  },
@@ -170,7 +164,29 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
             value &= AttributeConsts.Mask & ~3;
             char swzMask = GetSwizzleMask((value >> 2) & 3);
 
-            if (value >= AttributeConsts.UserAttributeBase && value < AttributeConsts.UserAttributeEnd)
+            if (perPatch)
+            {
+                if (value >= AttributeConsts.UserAttributePerPatchBase && value < AttributeConsts.UserAttributePerPatchEnd)
+                {
+                    value -= AttributeConsts.UserAttributePerPatchBase;
+
+                    return $"{DefaultNames.PerPatchAttributePrefix}{(value >> 4)}.{swzMask}";
+                }
+                else if (value < AttributeConsts.UserAttributePerPatchBase)
+                {
+                    return value switch
+                    {
+                        AttributeConsts.TessLevelOuter0 => "gl_TessLevelOuter[0]",
+                        AttributeConsts.TessLevelOuter1 => "gl_TessLevelOuter[1]",
+                        AttributeConsts.TessLevelOuter2 => "gl_TessLevelOuter[2]",
+                        AttributeConsts.TessLevelOuter3 => "gl_TessLevelOuter[3]",
+                        AttributeConsts.TessLevelInner0 => "gl_TessLevelInner[0]",
+                        AttributeConsts.TessLevelInner1 => "gl_TessLevelInner[1]",
+                        _ => null
+                    };
+                }
+            }
+            else if (value >= AttributeConsts.UserAttributeBase && value < AttributeConsts.UserAttributeEnd)
             {
                 value -= AttributeConsts.UserAttributeBase;
 
@@ -180,11 +196,6 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
 
                 bool indexable = config.UsedFeatures.HasFlag(isOutAttr ? FeatureFlags.OaIndexing : FeatureFlags.IaIndexing);
 
-                if (!indexable && perPatch)
-                {
-                    prefix = DefaultNames.PerPatchAttributePrefix;
-                }
-
                 if (indexable)
                 {
                     string name = prefix;
@@ -202,7 +213,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
                 {
                     string name = $"{prefix}{(value >> 4)}_{swzMask}";
 
-                    if (!perPatch && AttributeInfo.IsArrayAttributeGlsl(config.Stage, isOutAttr))
+                    if (AttributeInfo.IsArrayAttributeGlsl(config.Stage, isOutAttr))
                     {
                         name += isOutAttr ? "[gl_InvocationID]" : $"[{indexExpr}]";
                     }
@@ -213,7 +224,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
                 {
                     string name = $"{prefix}{(value >> 4)}";
 
-                    if (!perPatch && AttributeInfo.IsArrayAttributeGlsl(config.Stage, isOutAttr))
+                    if (AttributeInfo.IsArrayAttributeGlsl(config.Stage, isOutAttr))
                     {
                         name += isOutAttr ? "[gl_InvocationID]" : $"[{indexExpr}]";
                     }
@@ -277,7 +288,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Glsl
 
                     string name = builtInAttr.Name;
 
-                    if (!perPatch && AttributeInfo.IsArrayAttributeGlsl(config.Stage, isOutAttr) && AttributeInfo.IsArrayBuiltIn(value))
+                    if (AttributeInfo.IsArrayAttributeGlsl(config.Stage, isOutAttr) && AttributeInfo.IsArrayBuiltIn(value))
                     {
                         name = isOutAttr ? $"gl_out[gl_InvocationID].{name}" : $"gl_in[{indexExpr}].{name}";
                     }

Ryujinx.Graphics.Shader/CodeGen/Spirv/CodeGenContext.cs

@@ -382,17 +382,13 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
         public Instruction GetAttributePerPatchElemPointer(int attr, bool isOutAttr, out AggregateType elemType)
         {
             var storageClass = isOutAttr ? StorageClass.Output : StorageClass.Input;
-            var attrInfo = AttributeInfo.From(Config, attr, isOutAttr);
+            var attrInfo = AttributeInfo.FromPatch(Config, attr, isOutAttr);
 
             int attrOffset = attrInfo.BaseValue;
-            Instruction ioVariable;
+            Instruction ioVariable = isOutAttr ? OutputsPerPatch[attrOffset] : InputsPerPatch[attrOffset];
-
-            bool isUserAttr = attr >= AttributeConsts.UserAttributeBase && attr < AttributeConsts.UserAttributeEnd;
 
             elemType = attrInfo.Type & AggregateType.ElementTypeMask;
 
-            ioVariable = isOutAttr ? OutputsPerPatch[attrOffset] : InputsPerPatch[attrOffset];
-
             if ((attrInfo.Type & (AggregateType.Array | AggregateType.Vector)) == 0)
             {
                 return ioVariable;
@@ -404,7 +400,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
 
         public Instruction GetAttributePerPatch(AggregateType type, int attr, bool isOutAttr)
         {
-            if (!AttributeInfo.Validate(Config, attr, isOutAttr: false))
+            if (!AttributeInfo.ValidatePerPatch(Config, attr, isOutAttr: false))
             {
                 return GetConstant(type, new AstOperand(IrOperandType.Constant, 0));
             }

Ryujinx.Graphics.Shader/CodeGen/Spirv/Declarations.cs

@@ -403,7 +403,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
 
             foreach (int attr in inputs)
             {
-                if (!AttributeInfo.Validate(context.Config, attr, isOutAttr: false))
+                if (!AttributeInfo.Validate(context.Config, attr, isOutAttr: false, perPatch))
                 {
                     continue;
                 }
@@ -459,7 +459,7 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
 
             foreach (int attr in outputs)
             {
-                if (!AttributeInfo.Validate(context.Config, attr, isOutAttr: true))
+                if (!AttributeInfo.Validate(context.Config, attr, isOutAttr: true, perPatch))
                 {
                     continue;
                 }
@@ -519,7 +519,9 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
                 ? (isOutAttr ? context.OutputsPerPatch : context.InputsPerPatch)
                 : (isOutAttr ? context.Outputs : context.Inputs);
 
-            var attrInfo = AttributeInfo.From(context.Config, attr, isOutAttr);
+            var attrInfo = perPatch
+                ? AttributeInfo.FromPatch(context.Config, attr, isOutAttr)
+                : AttributeInfo.From(context.Config, attr, isOutAttr);
 
             if (dict.ContainsKey(attrInfo.BaseValue))
             {
@@ -544,11 +546,6 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
             var spvType = context.TypePointer(storageClass, attrType);
             var spvVar = context.Variable(spvType, storageClass);
 
-            if (perPatch)
-            {
-                context.Decorate(spvVar, Decoration.Patch);
-            }
-
             if (builtInPassthrough)
             {
                 context.Decorate(spvVar, Decoration.PassthroughNV);
@@ -556,6 +553,11 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
 
             if (attrInfo.IsBuiltin)
             {
+                if (perPatch)
+                {
+                    context.Decorate(spvVar, Decoration.Patch);
+                }
+
                 context.Decorate(spvVar, Decoration.BuiltIn, (LiteralInteger)GetBuiltIn(context, attrInfo.BaseValue));
 
                 if (context.Config.TransformFeedbackEnabled && context.Config.LastInVertexPipeline && isOutAttr)
@@ -569,6 +571,14 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
                     }
                 }
             }
+            else if (perPatch)
+            {
+                context.Decorate(spvVar, Decoration.Patch);
+
+                int location = context.Config.GetPerPatchAttributeLocation((attr - AttributeConsts.UserAttributePerPatchBase) / 16);
+
+                context.Decorate(spvVar, Decoration.Location, (LiteralInteger)location);
+            }
             else if (isUserAttr)
             {
                 int location = (attr - AttributeConsts.UserAttributeBase) / 16;

Ryujinx.Graphics.Shader/CodeGen/Spirv/Instructions.cs

@@ -882,7 +882,8 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
             if (src2 is AstOperand operand && operand.Type == OperandType.Constant)
             {
                 int attrOffset = (baseAttr.Value & AttributeConsts.Mask) + (operand.Value << 2);
-                return new OperationResult(resultType, context.GetAttribute(resultType, attrOffset, isOutAttr: false, index));
+                bool isOutAttr = (baseAttr.Value & AttributeConsts.LoadOutputMask) != 0;
+                return new OperationResult(resultType, context.GetAttribute(resultType, attrOffset, isOutAttr, index));
             }
             else
             {

Ryujinx.Graphics.Shader/CodeGen/Spirv/SpirvGenerator.cs

@@ -191,7 +191,15 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
                             break;
                     }
 
-                    if (context.Config.GpuAccessor.QueryTessCw())
+                    bool tessCw = context.Config.GpuAccessor.QueryTessCw();
+
+                    if (context.Config.Options.TargetApi == TargetApi.Vulkan)
+                    {
+                        // We invert the front face on Vulkan backend, so we need to do that here aswell.
+                        tessCw = !tessCw;
+                    }
+
+                    if (tessCw)
                     {
                         context.AddExecutionMode(spvFunc, ExecutionMode.VertexOrderCw);
                     }
@@ -374,10 +382,11 @@ namespace Ryujinx.Graphics.Shader.CodeGen.Spirv
                         context.Store(context.GetLocalPointer(dest), source);
                     }
                     else if (dest.Type == OperandType.Attribute || dest.Type == OperandType.AttributePerPatch)
-                    {
-                        if (AttributeInfo.Validate(context.Config, dest.Value, isOutAttr: true))
                     {
                         bool perPatch = dest.Type == OperandType.AttributePerPatch;
+
+                        if (AttributeInfo.Validate(context.Config, dest.Value, isOutAttr: true, perPatch))
+                        {
                             AggregateType elemType;
 
                             var elemPointer = perPatch

Ryujinx.Graphics.Shader/Decoders/Decoder.cs

@@ -306,18 +306,36 @@ namespace Ryujinx.Graphics.Shader.Decoders
                 for (int elemIndex = 0; elemIndex < count; elemIndex++)
                 {
                     int attr = offset + elemIndex * 4;
-                    if (attr >= AttributeConsts.UserAttributeBase && attr < AttributeConsts.UserAttributeEnd)
+
+                    if (perPatch)
+                    {
+                        if (attr >= AttributeConsts.UserAttributePerPatchBase && attr < AttributeConsts.UserAttributePerPatchEnd)
+                        {
+                            int userAttr = attr - AttributeConsts.UserAttributePerPatchBase;
+                            int index = userAttr / 16;
+
+                            if (isStore)
+                            {
+                                config.SetOutputUserAttributePerPatch(index);
+                            }
+                            else
+                            {
+                                config.SetInputUserAttributePerPatch(index);
+                            }
+                        }
+                    }
+                    else if (attr >= AttributeConsts.UserAttributeBase && attr < AttributeConsts.UserAttributeEnd)
                     {
                         int userAttr = attr - AttributeConsts.UserAttributeBase;
                         int index = userAttr / 16;
 
                         if (isStore)
                         {
-                            config.SetOutputUserAttribute(index, perPatch);
+                            config.SetOutputUserAttribute(index);
                         }
                         else
                         {
-                            config.SetInputUserAttribute(index, (userAttr >> 2) & 3, perPatch);
+                            config.SetInputUserAttribute(index, (userAttr >> 2) & 3);
                         }
                     }
 

Ryujinx.Graphics.Shader/Instructions/InstEmitAttribute.cs

@@ -46,7 +46,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
 
                     context.FlagAttributeRead(offset);
 
-                    if (op.O)
+                    if (op.O && CanLoadOutput(offset))
                     {
                         offset |= AttributeConsts.LoadOutputMask;
                     }
@@ -61,7 +61,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
 
                     context.FlagAttributeRead(offset);
 
-                    if (op.O)
+                    if (op.O && CanLoadOutput(offset))
                     {
                         offset |= AttributeConsts.LoadOutputMask;
                     }
@@ -241,6 +241,11 @@ namespace Ryujinx.Graphics.Shader.Instructions
             }
         }
 
+        private static bool CanLoadOutput(int attr)
+        {
+            return attr != AttributeConsts.TessCoordX && attr != AttributeConsts.TessCoordY;
+        }
+
         private static bool TryFixedFuncToUserAttributeIpa(EmitterContext context, int attr, out Operand selectedAttr)
         {
             if (attr >= AttributeConsts.FrontColorDiffuseR && attr < AttributeConsts.BackColorDiffuseR)

Ryujinx.Graphics.Shader/StructuredIr/StructuredProgram.cs

@@ -97,9 +97,17 @@ namespace Ryujinx.Graphics.Shader.StructuredIr
                 if (src1.Type == OperandType.Constant && src2.Type == OperandType.Constant)
                 {
                     int attrOffset = (src1.Value & AttributeConsts.Mask) + (src2.Value << 2);
+
+                    if ((src1.Value & AttributeConsts.LoadOutputMask) != 0)
+                    {
+                        context.Info.Outputs.Add(attrOffset);
+                    }
+                    else
+                    {
                         context.Info.Inputs.Add(attrOffset);
                     }
                 }
+            }
 
             int sourcesCount = operation.SourcesCount;
             int outDestsCount = operation.DestsCount != 0 ? operation.DestsCount - 1 : 0;

Ryujinx.Graphics.Shader/Translation/AttributeConsts.cs

@@ -54,6 +54,9 @@ namespace Ryujinx.Graphics.Shader.Translation
         public const int UserAttributeBase   = 0x80;
         public const int UserAttributeEnd    = UserAttributeBase + UserAttributesCount * 16;
 
+        public const int UserAttributePerPatchBase = 0x18;
+        public const int UserAttributePerPatchEnd  = 0x200;
+
         public const int LoadOutputMask = 1 << 30;
         public const int Mask = 0x3fffffff;
 

Ryujinx.Graphics.Shader/Translation/AttributeInfo.cs

@@ -4,14 +4,8 @@ namespace Ryujinx.Graphics.Shader.Translation
 {
     struct AttributeInfo
     {
-        private static readonly Dictionary<int, AttributeInfo> BuiltInAttributes = new Dictionary<int, AttributeInfo>()
+        private static readonly Dictionary<int, AttributeInfo> _builtInAttributes = new Dictionary<int, AttributeInfo>()
         {
-            { AttributeConsts.TessLevelOuter0, new AttributeInfo(AttributeConsts.TessLevelOuter0, 0, 4, AggregateType.Array  | AggregateType.FP32) },
-            { AttributeConsts.TessLevelOuter1, new AttributeInfo(AttributeConsts.TessLevelOuter0, 1, 4, AggregateType.Array  | AggregateType.FP32) },
-            { AttributeConsts.TessLevelOuter2, new AttributeInfo(AttributeConsts.TessLevelOuter0, 2, 4, AggregateType.Array  | AggregateType.FP32) },
-            { AttributeConsts.TessLevelOuter3, new AttributeInfo(AttributeConsts.TessLevelOuter0, 3, 4, AggregateType.Array  | AggregateType.FP32) },
-            { AttributeConsts.TessLevelInner0, new AttributeInfo(AttributeConsts.TessLevelInner0, 0, 2, AggregateType.Array  | AggregateType.FP32) },
-            { AttributeConsts.TessLevelInner1, new AttributeInfo(AttributeConsts.TessLevelInner0, 1, 2, AggregateType.Array  | AggregateType.FP32) },
             { AttributeConsts.Layer,         new AttributeInfo(AttributeConsts.Layer,         0, 1, AggregateType.S32) },
             { AttributeConsts.ViewportIndex, new AttributeInfo(AttributeConsts.ViewportIndex, 0, 1, AggregateType.S32) },
             { AttributeConsts.PointSize,     new AttributeInfo(AttributeConsts.PointSize,     0, 1, AggregateType.FP32) },
@@ -29,8 +23,8 @@ namespace Ryujinx.Graphics.Shader.Translation
             { AttributeConsts.ClipDistance7, new AttributeInfo(AttributeConsts.ClipDistance0, 7, 8, AggregateType.Array  | AggregateType.FP32) },
             { AttributeConsts.PointCoordX,   new AttributeInfo(AttributeConsts.PointCoordX,   0, 2, AggregateType.Vector | AggregateType.FP32) },
             { AttributeConsts.PointCoordY,   new AttributeInfo(AttributeConsts.PointCoordX,   1, 2, AggregateType.Vector | AggregateType.FP32) },
-            { AttributeConsts.TessCoordX,      new AttributeInfo(AttributeConsts.TessCoordX,      0, 2, AggregateType.Vector | AggregateType.FP32) },
+            { AttributeConsts.TessCoordX,    new AttributeInfo(AttributeConsts.TessCoordX,    0, 3, AggregateType.Vector | AggregateType.FP32) },
-            { AttributeConsts.TessCoordY,      new AttributeInfo(AttributeConsts.TessCoordX,      1, 2, AggregateType.Vector | AggregateType.FP32) },
+            { AttributeConsts.TessCoordY,    new AttributeInfo(AttributeConsts.TessCoordX,    1, 3, AggregateType.Vector | AggregateType.FP32) },
             { AttributeConsts.InstanceId,    new AttributeInfo(AttributeConsts.InstanceId,    0, 1, AggregateType.S32) },
             { AttributeConsts.VertexId,      new AttributeInfo(AttributeConsts.VertexId,      0, 1, AggregateType.S32) },
             { AttributeConsts.FrontFacing,   new AttributeInfo(AttributeConsts.FrontFacing,   0, 1, AggregateType.Bool) },
@@ -55,6 +49,16 @@ namespace Ryujinx.Graphics.Shader.Translation
             { AttributeConsts.LtMask,              new AttributeInfo(AttributeConsts.LtMask,              0, 4, AggregateType.Vector | AggregateType.U32) },
         };
 
+        private static readonly Dictionary<int, AttributeInfo> _builtInAttributesPerPatch = new Dictionary<int, AttributeInfo>()
+        {
+            { AttributeConsts.TessLevelOuter0, new AttributeInfo(AttributeConsts.TessLevelOuter0, 0, 4, AggregateType.Array | AggregateType.FP32) },
+            { AttributeConsts.TessLevelOuter1, new AttributeInfo(AttributeConsts.TessLevelOuter0, 1, 4, AggregateType.Array | AggregateType.FP32) },
+            { AttributeConsts.TessLevelOuter2, new AttributeInfo(AttributeConsts.TessLevelOuter0, 2, 4, AggregateType.Array | AggregateType.FP32) },
+            { AttributeConsts.TessLevelOuter3, new AttributeInfo(AttributeConsts.TessLevelOuter0, 3, 4, AggregateType.Array | AggregateType.FP32) },
+            { AttributeConsts.TessLevelInner0, new AttributeInfo(AttributeConsts.TessLevelInner0, 0, 2, AggregateType.Array | AggregateType.FP32) },
+            { AttributeConsts.TessLevelInner1, new AttributeInfo(AttributeConsts.TessLevelInner0, 1, 2, AggregateType.Array | AggregateType.FP32) },
+        };
+
         public int BaseValue { get; }
         public int Value { get; }
         public int Length { get; }
@@ -76,6 +80,11 @@ namespace Ryujinx.Graphics.Shader.Translation
             return (Value - BaseValue) / 4;
         }
 
+        public static bool Validate(ShaderConfig config, int value, bool isOutAttr, bool perPatch)
+        {
+            return perPatch ? ValidatePerPatch(config, value, isOutAttr) : Validate(config, value, isOutAttr);
+        }
+
         public static bool Validate(ShaderConfig config, int value, bool isOutAttr)
         {
             if (value == AttributeConsts.ViewportIndex && !config.GpuAccessor.QueryHostSupportsViewportIndex())
@@ -86,6 +95,11 @@ namespace Ryujinx.Graphics.Shader.Translation
             return From(config, value, isOutAttr).IsValid;
         }
 
+        public static bool ValidatePerPatch(ShaderConfig config, int value, bool isOutAttr)
+        {
+            return FromPatch(config, value, isOutAttr).IsValid;
+        }
+
         public static AttributeInfo From(ShaderConfig config, int value, bool isOutAttr)
         {
             value &= ~3;
@@ -115,7 +129,24 @@ namespace Ryujinx.Graphics.Shader.Translation
             {
                 return new AttributeInfo(value, 0, 1, AggregateType.FP32);
             }
-            else if (BuiltInAttributes.TryGetValue(value, out AttributeInfo info))
+            else if (_builtInAttributes.TryGetValue(value, out AttributeInfo info))
+            {
+                return info;
+            }
+
+            return new AttributeInfo(value, 0, 0, AggregateType.Invalid);
+        }
+
+        public static AttributeInfo FromPatch(ShaderConfig config, int value, bool isOutAttr)
+        {
+            value &= ~3;
+
+            if (value >= AttributeConsts.UserAttributePerPatchBase && value < AttributeConsts.UserAttributePerPatchEnd)
+            {
+                int offset = (value - AttributeConsts.UserAttributePerPatchBase) & 0xf;
+                return new AttributeInfo(value - offset, offset >> 2, 4, AggregateType.Vector | AggregateType.FP32, false);
+            }
+            else if (_builtInAttributesPerPatch.TryGetValue(value, out AttributeInfo info))
             {
                 return info;
             }

Ryujinx.Graphics.Shader/Translation/EmitterContext.cs

@@ -261,7 +261,7 @@ namespace Ryujinx.Graphics.Shader.Translation
                         {
                             int index = BitOperations.TrailingZeroCount(passthroughAttributes);
                             WriteOutput(AttributeConsts.UserAttributeBase + index * 16, primIndex);
-                            Config.SetOutputUserAttribute(index, perPatch: false);
+                            Config.SetOutputUserAttribute(index);
                             passthroughAttributes &= ~(1 << index);
                         }
 
@@ -364,7 +364,7 @@ namespace Ryujinx.Graphics.Shader.Translation
                     bool targetEnabled = (Config.OmapTargets & (0xf << (rtIndex * 4))) != 0;
                     if (targetEnabled)
                     {
-                        Config.SetOutputUserAttribute(rtIndex, perPatch: false);
+                        Config.SetOutputUserAttribute(rtIndex);
                         regIndexBase += 4;
                     }
                 }

Ryujinx.Graphics.Shader/Translation/ShaderConfig.cs

@@ -50,16 +50,16 @@ namespace Ryujinx.Graphics.Shader.Translation
         public bool NextUsesFixedFuncAttributes { get; private set; }
         public int UsedInputAttributes { get; private set; }
         public int UsedOutputAttributes { get; private set; }
-        public int UsedInputAttributesPerPatch { get; private set; }
+        public HashSet<int> UsedInputAttributesPerPatch { get; }
-        public int UsedOutputAttributesPerPatch { get; private set; }
+        public HashSet<int> UsedOutputAttributesPerPatch { get; }
+        public HashSet<int> NextUsedInputAttributesPerPatch { get; private set; }
         public int PassthroughAttributes { get; private set; }
         private int _nextUsedInputAttributes;
         private int _thisUsedInputAttributes;
+        private Dictionary<int, int> _perPatchAttributeLocations;
 
         public UInt128 NextInputAttributesComponents { get; private set; }
         public UInt128 ThisInputAttributesComponents { get; private set; }
-        public UInt128 NextInputAttributesPerPatchComponents { get; private set; }
-        public UInt128 ThisInputAttributesPerPatchComponents { get; private set; }
 
         private int _usedConstantBuffers;
         private int _usedStorageBuffers;
@@ -122,6 +122,10 @@ namespace Ryujinx.Graphics.Shader.Translation
             Stage       = ShaderStage.Compute;
             GpuAccessor = gpuAccessor;
             Options     = options;
+
+            UsedInputAttributesPerPatch  = new HashSet<int>();
+            UsedOutputAttributesPerPatch = new HashSet<int>();
+
             _usedTextures = new Dictionary<TextureInfo, TextureMeta>();
             _usedImages   = new Dictionary<TextureInfo, TextureMeta>();
         }
@@ -244,14 +248,7 @@ namespace Ryujinx.Graphics.Shader.Translation
             UsedOutputAttributes |= 1 << index;
         }
 
-        public void SetInputUserAttribute(int index, int component, bool perPatch)
+        public void SetInputUserAttribute(int index, int component)
-        {
-            if (perPatch)
-            {
-                UsedInputAttributesPerPatch |= 1 << index;
-                ThisInputAttributesPerPatchComponents |= UInt128.Pow2(index * 4 + component);
-            }
-            else
         {
             int mask = 1 << index;
 
@@ -259,34 +256,63 @@ namespace Ryujinx.Graphics.Shader.Translation
             _thisUsedInputAttributes |= mask;
             ThisInputAttributesComponents |= UInt128.Pow2(index * 4 + component);
         }
+
+        public void SetInputUserAttributePerPatch(int index)
+        {
+            UsedInputAttributesPerPatch.Add(index);
         }
 
-        public void SetOutputUserAttribute(int index, bool perPatch)
+        public void SetOutputUserAttribute(int index)
-        {
-            if (perPatch)
-            {
-                UsedOutputAttributesPerPatch |= 1 << index;
-            }
-            else
         {
             UsedOutputAttributes |= 1 << index;
         }
+
+        public void SetOutputUserAttributePerPatch(int index)
+        {
+            UsedOutputAttributesPerPatch.Add(index);
         }
 
         public void MergeFromtNextStage(ShaderConfig config)
         {
             NextInputAttributesComponents = config.ThisInputAttributesComponents;
-            NextInputAttributesPerPatchComponents = config.ThisInputAttributesPerPatchComponents;
+            NextUsedInputAttributesPerPatch = config.UsedInputAttributesPerPatch;
             NextUsesFixedFuncAttributes = config.UsedFeatures.HasFlag(FeatureFlags.FixedFuncAttr);
             MergeOutputUserAttributes(config.UsedInputAttributes, config.UsedInputAttributesPerPatch);
 
+            if (UsedOutputAttributesPerPatch.Count != 0)
+            {
+                // Regular and per-patch input/output locations can't overlap,
+                // so we must assign on our location using unused regular input/output locations.
+
+                Dictionary<int, int> locationsMap = new Dictionary<int, int>();
+
+                int freeMask = ~UsedOutputAttributes;
+
+                foreach (int attr in UsedOutputAttributesPerPatch)
+                {
+                    int location = BitOperations.TrailingZeroCount(freeMask);
+                    if (location == 32)
+                    {
+                        config.GpuAccessor.Log($"No enough free locations for patch input/output 0x{attr:X}.");
+                        break;
+                    }
+
+                    locationsMap.Add(attr, location);
+                    freeMask &= ~(1 << location);
+                }
+
+                // Both stages must agree on the locations, so use the same "map" for both.
+                _perPatchAttributeLocations = locationsMap;
+                config._perPatchAttributeLocations = locationsMap;
+            }
+
             if (config.Stage != ShaderStage.Fragment)
             {
                 LastInVertexPipeline = false;
             }
         }
 
-        public void MergeOutputUserAttributes(int mask, int maskPerPatch)
+        public void MergeOutputUserAttributes(int mask, IEnumerable<int> perPatch)
         {
             _nextUsedInputAttributes = mask;
 
@@ -297,10 +323,20 @@ namespace Ryujinx.Graphics.Shader.Translation
             else
             {
                 UsedOutputAttributes |= mask;
-                UsedOutputAttributesPerPatch |= maskPerPatch;
+                UsedOutputAttributesPerPatch.UnionWith(perPatch);
             }
         }
 
+        public int GetPerPatchAttributeLocation(int index)
+        {
+            if (_perPatchAttributeLocations == null || !_perPatchAttributeLocations.TryGetValue(index, out int location))
+            {
+                return index;
+            }
+
+            return location;
+        }
+
         public bool IsUsedOutputAttribute(int attr)
         {
             // The check for fixed function attributes on the next stage is conservative,

Ryujinx.Graphics.Shader/Translation/Translator.cs

@@ -204,14 +204,12 @@ namespace Ryujinx.Graphics.Shader.Translation
                 InitializeOutputComponent(context, AttributeConsts.UserAttributeBase + index * 4, perPatch: false);
             }
 
-            UInt128 usedAttributesPerPatch = context.Config.NextInputAttributesPerPatchComponents;
+            if (context.Config.NextUsedInputAttributesPerPatch != null)
-            while (usedAttributesPerPatch != UInt128.Zero)
             {
-                int index = usedAttributesPerPatch.TrailingZeroCount();
+                foreach (int vecIndex in context.Config.NextUsedInputAttributesPerPatch.OrderBy(x => x))
-
+                {
-                InitializeOutputComponent(context, AttributeConsts.UserAttributeBase + index * 4, perPatch: true);
+                    InitializeOutput(context, AttributeConsts.UserAttributePerPatchBase + vecIndex * 16, perPatch: true);
-
+                }
-                usedAttributesPerPatch &= ~UInt128.Pow2(index);
             }
 
             if (config.NextUsesFixedFuncAttributes)
@@ -236,7 +234,7 @@ namespace Ryujinx.Graphics.Shader.Translation
             for (int c = 0; c < 4; c++)
             {
                 int attrOffset = baseAttr + c * 4;
-                context.Copy(perPatch ? AttributePerPatch(attrOffset) : Attribute(attrOffset), ConstF(c == 3 ? 1f : 0f));
+                InitializeOutputComponent(context, attrOffset, perPatch);
             }
         }
 

Ryujinx.Graphics.Shader/Translation/TranslatorContext.cs

@@ -1,6 +1,7 @@
 using Ryujinx.Graphics.Shader.Decoders;
 using Ryujinx.Graphics.Shader.IntermediateRepresentation;
 using System.Collections.Generic;
+using System.Linq;
 
 using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
 using static Ryujinx.Graphics.Shader.Translation.Translator;
@@ -137,7 +138,7 @@ namespace Ryujinx.Graphics.Shader.Translation
 
             if (other != null)
             {
-                other._config.MergeOutputUserAttributes(_config.UsedOutputAttributes, 0);
+                other._config.MergeOutputUserAttributes(_config.UsedOutputAttributes, Enumerable.Empty<int>());
 
                 FunctionCode[] otherCode = EmitShader(other._program, other._config, initializeOutputs: true, out int aStart);
 

Ryujinx.Graphics.Vulkan/Shader.cs

@@ -9,17 +9,19 @@ using System.Threading.Tasks;
 
 namespace Ryujinx.Graphics.Vulkan
 {
-    class Shader
+    class Shader : IDisposable
     {
         // The shaderc.net dependency's Options constructor and dispose are not thread safe.
         // Take this lock when using them.
         private static object _shaderOptionsLock = new object();
 
+        private static readonly IntPtr _ptrMainEntryPointName = Marshal.StringToHGlobalAnsi("main");
+
         private readonly Vk _api;
         private readonly Device _device;
         private readonly ShaderStageFlags _stage;
 
-        private IntPtr _entryPointName;
+        private bool _disposed;
         private ShaderModule _module;
 
         public ShaderStageFlags StageFlags => _stage;
@@ -39,7 +41,6 @@ namespace Ryujinx.Graphics.Vulkan
             CompileStatus = ProgramLinkStatus.Incomplete;
 
             _stage = shaderSource.Stage.Convert();
-            _entryPointName = Marshal.StringToHGlobalAnsi("main");
 
             CompileTask = Task.Run(() =>
             {
@@ -145,7 +146,7 @@ namespace Ryujinx.Graphics.Vulkan
                 SType = StructureType.PipelineShaderStageCreateInfo,
                 Stage = _stage,
                 Module = _module,
-                PName = (byte*)_entryPointName
+                PName = (byte*)_ptrMainEntryPointName
             };
         }
 
@@ -156,11 +157,10 @@ namespace Ryujinx.Graphics.Vulkan
 
         public unsafe void Dispose()
         {
-            if (_entryPointName != IntPtr.Zero)
+            if (!_disposed)
             {
                 _api.DestroyShaderModule(_device, _module, null);
-                Marshal.FreeHGlobal(_entryPointName);
+                _disposed = true;
-                _entryPointName = IntPtr.Zero;
             }
         }
     }

Ryujinx.HLE/HOS/Services/Fatal/IService.cs

@@ -1,8 +1,147 @@
-namespace Ryujinx.HLE.HOS.Services.Fatal
+using Ryujinx.Common.Logging;
+using Ryujinx.HLE.HOS.Services.Fatal.Types;
+using System;
+using System.Runtime.InteropServices;
+using System.Text;
+
+namespace Ryujinx.HLE.HOS.Services.Fatal
 {
     [Service("fatal:u")]
     class IService : IpcService
     {
         public IService(ServiceCtx context) { }
+
+        [CommandHipc(0)]
+        // ThrowFatal(u64 result_code, u64 pid)
+        public ResultCode ThrowFatal(ServiceCtx context)
+        {
+            ResultCode resultCode = (ResultCode)context.RequestData.ReadUInt64();
+            ulong      pid        = context.Request.HandleDesc.PId;
+
+            return ThrowFatalWithCpuContextImpl(context, resultCode, pid, FatalPolicy.ErrorReportAndErrorScreen, null);
+        }
+
+        [CommandHipc(1)]
+        // ThrowFatalWithPolicy(u64 result_code, u32 fatal_policy, u64 pid)
+        public ResultCode ThrowFatalWithPolicy(ServiceCtx context)
+        {
+            ResultCode  resultCode  = (ResultCode)context.RequestData.ReadUInt64();
+            FatalPolicy fatalPolicy = (FatalPolicy)context.RequestData.ReadUInt32();
+            ulong       pid         = context.Request.HandleDesc.PId;
+
+            return ThrowFatalWithCpuContextImpl(context, resultCode, pid, fatalPolicy, null);
+        }
+
+        [CommandHipc(2)]
+        // ThrowFatalWithCpuContext(u64 result_code, u32 fatal_policy, u64 pid, buffer<bytes, 0x15> cpu_context)
+        public ResultCode ThrowFatalWithCpuContext(ServiceCtx context)
+        {
+            ResultCode  resultCode  = (ResultCode)context.RequestData.ReadUInt64();
+            FatalPolicy fatalPolicy = (FatalPolicy)context.RequestData.ReadUInt32();
+            ulong       pid         = context.Request.HandleDesc.PId;
+
+            ulong cpuContextPosition = context.Request.SendBuff[0].Position;
+            ulong cpuContextSize     = context.Request.SendBuff[0].Size;
+
+            ReadOnlySpan<byte> cpuContextData = context.Memory.GetSpan(cpuContextPosition, (int)cpuContextSize);
+
+            return ThrowFatalWithCpuContextImpl(context, resultCode, pid, fatalPolicy, cpuContextData);
+        }
+
+        private ResultCode ThrowFatalWithCpuContextImpl(ServiceCtx context, ResultCode resultCode, ulong pid, FatalPolicy fatalPolicy, ReadOnlySpan<byte> cpuContext)
+        {
+            StringBuilder errorReport = new StringBuilder();
+
+            errorReport.AppendLine();
+            errorReport.AppendLine("ErrorReport log:");
+
+            errorReport.AppendLine($"\tTitleId: {context.Device.Application.TitleId:x16}");
+            errorReport.AppendLine($"\tPid: {pid}");
+            errorReport.AppendLine($"\tResultCode: {((int)resultCode & 0x1FF) + 2000}-{((int)resultCode >> 9) & 0x3FFF:d4}");
+            errorReport.AppendLine($"\tFatalPolicy: {fatalPolicy}");
+
+            if (cpuContext != null)
+            {
+                errorReport.AppendLine("CPU Context:");
+
+                if (context.Device.Application.TitleIs64Bit)
+                {
+                    CpuContext64 cpuContext64 = MemoryMarshal.Cast<byte, CpuContext64>(cpuContext)[0];
+
+                    errorReport.AppendLine($"\tStartAddress: 0x{cpuContext64.StartAddress:x16}");
+                    errorReport.AppendLine($"\tRegisterSetFlags: {cpuContext64.RegisterSetFlags}");
+
+                    if (cpuContext64.StackTraceSize > 0)
+                    {
+                        errorReport.AppendLine("\tStackTrace:");
+
+                        for (int i = 0; i < cpuContext64.StackTraceSize; i++)
+                        {
+                            errorReport.AppendLine($"\t\t0x{cpuContext64.StackTrace[i]:x16}");
+                        }
+                    }
+
+                    errorReport.AppendLine("\tRegisters:");
+
+                    for (int i = 0; i < cpuContext64.X.Length; i++)
+                    {
+                        errorReport.AppendLine($"\t\tX[{i:d2}]:\t0x{cpuContext64.X[i]:x16}");
+                    }
+
+                    errorReport.AppendLine();
+                    errorReport.AppendLine($"\t\tFP:\t0x{cpuContext64.FP:x16}");
+                    errorReport.AppendLine($"\t\tLR:\t0x{cpuContext64.LR:x16}");
+                    errorReport.AppendLine($"\t\tSP:\t0x{cpuContext64.SP:x16}");
+                    errorReport.AppendLine($"\t\tPC:\t0x{cpuContext64.PC:x16}");
+                    errorReport.AppendLine($"\t\tPState:\t0x{cpuContext64.PState:x16}");
+                    errorReport.AppendLine($"\t\tAfsr0:\t0x{cpuContext64.Afsr0:x16}");
+                    errorReport.AppendLine($"\t\tAfsr1:\t0x{cpuContext64.Afsr1:x16}");
+                    errorReport.AppendLine($"\t\tEsr:\t0x{cpuContext64.Esr:x16}");
+                    errorReport.AppendLine($"\t\tFar:\t0x{cpuContext64.Far:x16}");
+                }
+                else
+                {
+                    CpuContext32 cpuContext32 = MemoryMarshal.Cast<byte, CpuContext32>(cpuContext)[0];
+
+                    errorReport.AppendLine($"\tStartAddress: 0x{cpuContext32.StartAddress:16}");
+                    errorReport.AppendLine($"\tRegisterSetFlags: {cpuContext32.RegisterSetFlags}");
+
+                    if (cpuContext32.StackTraceSize > 0)
+                    {
+                        errorReport.AppendLine("\tStackTrace:");
+
+                        for (int i = 0; i < cpuContext32.StackTraceSize; i++)
+                        {
+                            errorReport.AppendLine($"\t\t0x{cpuContext32.StackTrace[i]:x16}");
+                        }
+                    }
+
+                    errorReport.AppendLine("\tRegisters:");
+
+                    for (int i = 0; i < cpuContext32.X.Length; i++)
+                    {
+                        errorReport.AppendLine($"\t\tX[{i:d2}]:\t0x{cpuContext32.X[i]:x16}");
+                    }
+
+                    errorReport.AppendLine();
+                    errorReport.AppendLine($"\t\tFP:\t0x{cpuContext32.FP:x16}");
+                    errorReport.AppendLine($"\t\tFP:\t0x{cpuContext32.IP:x16}");
+                    errorReport.AppendLine($"\t\tSP:\t0x{cpuContext32.SP:x16}");
+                    errorReport.AppendLine($"\t\tLR:\t0x{cpuContext32.LR:x16}");
+                    errorReport.AppendLine($"\t\tPC:\t0x{cpuContext32.PC:x16}");
+                    errorReport.AppendLine($"\t\tPState:\t0x{cpuContext32.PState:x16}");
+                    errorReport.AppendLine($"\t\tAfsr0:\t0x{cpuContext32.Afsr0:x16}");
+                    errorReport.AppendLine($"\t\tAfsr1:\t0x{cpuContext32.Afsr1:x16}");
+                    errorReport.AppendLine($"\t\tEsr:\t0x{cpuContext32.Esr:x16}");
+                    errorReport.AppendLine($"\t\tFar:\t0x{cpuContext32.Far:x16}");
+                }
+            }
+
+            Logger.Info?.Print(LogClass.ServiceFatal, errorReport.ToString());
+
+            context.Device.System.KernelContext.Syscall.Break((ulong)resultCode);
+
+            return ResultCode.Success;
+        }
     }
 }

Ryujinx.HLE/HOS/Services/Fatal/Types/CpuContext32.cs

@@ -0,0 +1,25 @@
+using Ryujinx.Common.Memory;
+
+namespace Ryujinx.HLE.HOS.Services.Fatal.Types
+{
+    public struct CpuContext32
+    {
+        public Array11<uint> X;
+        public uint FP;
+        public uint IP;
+        public uint SP;
+        public uint LR;
+        public uint PC;
+
+        public uint PState;
+        public uint Afsr0;
+        public uint Afsr1;
+        public uint Esr;
+        public uint Far;
+
+        public Array32<uint> StackTrace;
+        public uint StackTraceSize;
+        public uint StartAddress;
+        public uint RegisterSetFlags;
+    }
+}

Ryujinx.HLE/HOS/Services/Fatal/Types/CpuContext64.cs

@@ -0,0 +1,24 @@
+using Ryujinx.Common.Memory;
+
+namespace Ryujinx.HLE.HOS.Services.Fatal.Types
+{
+    public struct CpuContext64
+    {
+        public Array29<ulong> X;
+        public ulong FP;
+        public ulong LR;
+        public ulong SP;
+        public ulong PC;
+
+        public ulong PState;
+        public ulong Afsr0;
+        public ulong Afsr1;
+        public ulong Esr;
+        public ulong Far;
+
+        public Array32<ulong> StackTrace;
+        public ulong StartAddress;
+        public ulong RegisterSetFlags;
+        public uint  StackTraceSize;
+    }
+}

Ryujinx.HLE/HOS/Services/Fatal/Types/FatalPolicy.cs

@@ -0,0 +1,9 @@
+namespace Ryujinx.HLE.HOS.Services.Fatal.Types
+{
+    enum FatalPolicy
+    {
+        ErrorReportAndErrorScreen,
+        ErrorReport,
+        ErrorScreen
+    }
+}