[ARMeilleure] Address dotnet-format issues (#5357)
* dotnet format style --severity info Some changes were manually reverted. * dotnet format analyzers --serverity info Some changes have been minimally adapted. * Restore a few unused methods and variables * Silence dotnet format IDE0060 warnings * Silence dotnet format IDE0052 warnings * Address or silence dotnet format IDE1006 warnings * Address or silence dotnet format CA2208 warnings * Address dotnet format CA1822 warnings * Address or silence dotnet format CA1069 warnings * Silence CA1806 and CA1834 issues * Address dotnet format CA1401 warnings * Fix new dotnet-format issues after rebase * Address review comments * Address dotnet format CA2208 warnings properly * Fix formatting for switch expressions * Address most dotnet format whitespace warnings * Apply dotnet format whitespace formatting A few of them have been manually reverted and the corresponding warning was silenced * Add previously silenced warnings back I have no clue how these disappeared * Revert formatting changes for OpCodeTable.cs * Enable formatting for a few cases again * Format if-blocks correctly * Enable formatting for a few more cases again * Fix inline comment alignment * Run dotnet format after rebase and remove unused usings - analyzers - style - whitespace * Disable 'prefer switch expression' rule * Add comments to disabled warnings * Remove a few unused parameters * Adjust namespaces * Simplify properties and array initialization, Use const when possible, Remove trailing commas * Start working on disabled warnings * Fix and silence a few dotnet-format warnings again * Address IDE0251 warnings * Address a few disabled IDE0060 warnings * Silence IDE0060 in .editorconfig * Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas" This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e. * dotnet format whitespace after rebase * First dotnet format pass * Remove unnecessary formatting exclusion * Add unsafe dotnet format changes * Change visibility of JitSupportDarwin to internal
This commit is contained in:
TSRBerry
GitHub
@ -6,7 +6,6 @@ using ARMeilleure.Translation;
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using System;
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using System.Diagnostics;
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using System.Reflection;
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using static ARMeilleure.Instructions.InstEmitHelper;
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using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
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@ -18,19 +17,19 @@ namespace ARMeilleure.Instructions
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static class InstEmitSimdHelper
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{
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#region "Masks"
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#region "Masks"
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public static readonly long[] EvenMasks = new long[]
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{
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14L << 56 | 12L << 48 | 10L << 40 | 08L << 32 | 06L << 24 | 04L << 16 | 02L << 8 | 00L << 0, // B
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13L << 56 | 12L << 48 | 09L << 40 | 08L << 32 | 05L << 24 | 04L << 16 | 01L << 8 | 00L << 0, // H
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11L << 56 | 10L << 48 | 09L << 40 | 08L << 32 | 03L << 24 | 02L << 16 | 01L << 8 | 00L << 0 // S
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11L << 56 | 10L << 48 | 09L << 40 | 08L << 32 | 03L << 24 | 02L << 16 | 01L << 8 | 00L << 0, // S
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};
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public static readonly long[] OddMasks = new long[]
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{
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15L << 56 | 13L << 48 | 11L << 40 | 09L << 32 | 07L << 24 | 05L << 16 | 03L << 8 | 01L << 0, // B
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15L << 56 | 14L << 48 | 11L << 40 | 10L << 32 | 07L << 24 | 06L << 16 | 03L << 8 | 02L << 0, // H
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15L << 56 | 14L << 48 | 13L << 40 | 12L << 32 | 07L << 24 | 06L << 16 | 05L << 8 | 04L << 0 // S
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15L << 56 | 14L << 48 | 13L << 40 | 12L << 32 | 07L << 24 | 06L << 16 | 05L << 8 | 04L << 0, // S
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};
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public static readonly long ZeroMask = 128L << 56 | 128L << 48 | 128L << 40 | 128L << 32 | 128L << 24 | 128L << 16 | 128L << 8 | 128L << 0;
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@ -38,19 +37,19 @@ namespace ARMeilleure.Instructions
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public static ulong X86GetGf2p8LogicalShiftLeft(int shift)
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{
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ulong identity = (0b00000001UL << 56) | (0b00000010UL << 48) | (0b00000100UL << 40) | (0b00001000UL << 32) |
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(0b00010000UL << 24) | (0b00100000UL << 16) | (0b01000000UL << 8) | (0b10000000UL << 0);
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(0b00010000UL << 24) | (0b00100000UL << 16) | (0b01000000UL << 8) | (0b10000000UL << 0);
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return shift >= 0 ? identity >> (shift * 8) : identity << (-shift * 8);
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}
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#endregion
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#endregion
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#region "X86 SSE Intrinsics"
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#region "X86 SSE Intrinsics"
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public static readonly Intrinsic[] X86PaddInstruction = new Intrinsic[]
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{
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Intrinsic.X86Paddb,
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Intrinsic.X86Paddw,
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Intrinsic.X86Paddd,
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Intrinsic.X86Paddq
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Intrinsic.X86Paddq,
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};
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public static readonly Intrinsic[] X86PcmpeqInstruction = new Intrinsic[]
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@ -58,7 +57,7 @@ namespace ARMeilleure.Instructions
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Intrinsic.X86Pcmpeqb,
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Intrinsic.X86Pcmpeqw,
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Intrinsic.X86Pcmpeqd,
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Intrinsic.X86Pcmpeqq
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Intrinsic.X86Pcmpeqq,
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};
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public static readonly Intrinsic[] X86PcmpgtInstruction = new Intrinsic[]
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@ -66,49 +65,49 @@ namespace ARMeilleure.Instructions
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Intrinsic.X86Pcmpgtb,
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Intrinsic.X86Pcmpgtw,
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Intrinsic.X86Pcmpgtd,
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Intrinsic.X86Pcmpgtq
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Intrinsic.X86Pcmpgtq,
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};
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public static readonly Intrinsic[] X86PmaxsInstruction = new Intrinsic[]
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{
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Intrinsic.X86Pmaxsb,
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Intrinsic.X86Pmaxsw,
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Intrinsic.X86Pmaxsd
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Intrinsic.X86Pmaxsd,
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};
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public static readonly Intrinsic[] X86PmaxuInstruction = new Intrinsic[]
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{
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Intrinsic.X86Pmaxub,
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Intrinsic.X86Pmaxuw,
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Intrinsic.X86Pmaxud
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Intrinsic.X86Pmaxud,
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};
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public static readonly Intrinsic[] X86PminsInstruction = new Intrinsic[]
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{
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Intrinsic.X86Pminsb,
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Intrinsic.X86Pminsw,
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Intrinsic.X86Pminsd
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Intrinsic.X86Pminsd,
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};
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public static readonly Intrinsic[] X86PminuInstruction = new Intrinsic[]
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{
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Intrinsic.X86Pminub,
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Intrinsic.X86Pminuw,
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Intrinsic.X86Pminud
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Intrinsic.X86Pminud,
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};
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public static readonly Intrinsic[] X86PmovsxInstruction = new Intrinsic[]
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{
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Intrinsic.X86Pmovsxbw,
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Intrinsic.X86Pmovsxwd,
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Intrinsic.X86Pmovsxdq
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Intrinsic.X86Pmovsxdq,
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};
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public static readonly Intrinsic[] X86PmovzxInstruction = new Intrinsic[]
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{
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Intrinsic.X86Pmovzxbw,
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Intrinsic.X86Pmovzxwd,
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Intrinsic.X86Pmovzxdq
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Intrinsic.X86Pmovzxdq,
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};
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public static readonly Intrinsic[] X86PsllInstruction = new Intrinsic[]
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@ -116,14 +115,14 @@ namespace ARMeilleure.Instructions
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0,
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Intrinsic.X86Psllw,
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Intrinsic.X86Pslld,
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Intrinsic.X86Psllq
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Intrinsic.X86Psllq,
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};
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public static readonly Intrinsic[] X86PsraInstruction = new Intrinsic[]
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{
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0,
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Intrinsic.X86Psraw,
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Intrinsic.X86Psrad
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Intrinsic.X86Psrad,
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};
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public static readonly Intrinsic[] X86PsrlInstruction = new Intrinsic[]
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@ -131,7 +130,7 @@ namespace ARMeilleure.Instructions
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0,
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Intrinsic.X86Psrlw,
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Intrinsic.X86Psrld,
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Intrinsic.X86Psrlq
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Intrinsic.X86Psrlq,
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};
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public static readonly Intrinsic[] X86PsubInstruction = new Intrinsic[]
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@ -139,7 +138,7 @@ namespace ARMeilleure.Instructions
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Intrinsic.X86Psubb,
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Intrinsic.X86Psubw,
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Intrinsic.X86Psubd,
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Intrinsic.X86Psubq
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Intrinsic.X86Psubq,
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};
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public static readonly Intrinsic[] X86PunpckhInstruction = new Intrinsic[]
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@ -147,7 +146,7 @@ namespace ARMeilleure.Instructions
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Intrinsic.X86Punpckhbw,
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Intrinsic.X86Punpckhwd,
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Intrinsic.X86Punpckhdq,
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Intrinsic.X86Punpckhqdq
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Intrinsic.X86Punpckhqdq,
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};
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public static readonly Intrinsic[] X86PunpcklInstruction = new Intrinsic[]
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@ -155,9 +154,9 @@ namespace ARMeilleure.Instructions
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Intrinsic.X86Punpcklbw,
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Intrinsic.X86Punpcklwd,
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Intrinsic.X86Punpckldq,
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Intrinsic.X86Punpcklqdq
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Intrinsic.X86Punpcklqdq,
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};
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#endregion
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#endregion
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public static void EnterArmFpMode(EmitterContext context, Func<FPState, Operand> getFpFlag)
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{
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@ -310,15 +309,16 @@ namespace ARMeilleure.Instructions
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public static int X86GetRoundControl(FPRoundingMode roundMode)
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{
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switch (roundMode)
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return roundMode switch
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{
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case FPRoundingMode.ToNearest: return 8 | 0; // even
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case FPRoundingMode.TowardsPlusInfinity: return 8 | 2;
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case FPRoundingMode.TowardsMinusInfinity: return 8 | 1;
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case FPRoundingMode.TowardsZero: return 8 | 3;
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}
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throw new ArgumentException($"Invalid rounding mode \"{roundMode}\".");
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#pragma warning disable IDE0055 // Disable formatting
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FPRoundingMode.ToNearest => 8 | 0, // even
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FPRoundingMode.TowardsPlusInfinity => 8 | 2,
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FPRoundingMode.TowardsMinusInfinity => 8 | 1,
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FPRoundingMode.TowardsZero => 8 | 3,
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_ => throw new ArgumentException($"Invalid rounding mode \"{roundMode}\"."),
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#pragma warning restore IDE0055
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};
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}
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public static Operand EmitSse41RoundToNearestWithTiesToAwayOpF(ArmEmitterContext context, Operand n, bool scalar)
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@ -334,11 +334,11 @@ namespace ARMeilleure.Instructions
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if ((op.Size & 1) == 0)
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{
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Operand signMask = scalar ? X86GetScalar(context, int.MinValue) : X86GetAllElements(context, int.MinValue);
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signMask = context.AddIntrinsic(Intrinsic.X86Pand, signMask, nCopy);
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signMask = context.AddIntrinsic(Intrinsic.X86Pand, signMask, nCopy);
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// 0x3EFFFFFF == BitConverter.SingleToInt32Bits(0.5f) - 1
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Operand valueMask = scalar ? X86GetScalar(context, 0x3EFFFFFF) : X86GetAllElements(context, 0x3EFFFFFF);
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valueMask = context.AddIntrinsic(Intrinsic.X86Por, valueMask, signMask);
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valueMask = context.AddIntrinsic(Intrinsic.X86Por, valueMask, signMask);
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nCopy = context.AddIntrinsic(scalar ? Intrinsic.X86Addss : Intrinsic.X86Addps, nCopy, valueMask);
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@ -347,11 +347,11 @@ namespace ARMeilleure.Instructions
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else
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{
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Operand signMask = scalar ? X86GetScalar(context, long.MinValue) : X86GetAllElements(context, long.MinValue);
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signMask = context.AddIntrinsic(Intrinsic.X86Pand, signMask, nCopy);
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signMask = context.AddIntrinsic(Intrinsic.X86Pand, signMask, nCopy);
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// 0x3FDFFFFFFFFFFFFFL == BitConverter.DoubleToInt64Bits(0.5d) - 1L
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Operand valueMask = scalar ? X86GetScalar(context, 0x3FDFFFFFFFFFFFFFL) : X86GetAllElements(context, 0x3FDFFFFFFFFFFFFFL);
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valueMask = context.AddIntrinsic(Intrinsic.X86Por, valueMask, signMask);
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valueMask = context.AddIntrinsic(Intrinsic.X86Por, valueMask, signMask);
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nCopy = context.AddIntrinsic(scalar ? Intrinsic.X86Addsd : Intrinsic.X86Addpd, nCopy, valueMask);
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@ -461,7 +461,7 @@ namespace ARMeilleure.Instructions
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MethodInfo info = (op.Size & 1) == 0
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? typeof(MathF).GetMethod(name, new Type[] { typeof(float) })
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: typeof(Math). GetMethod(name, new Type[] { typeof(double) });
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: typeof(Math).GetMethod(name, new Type[] { typeof(double) });
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return context.Call(info, n);
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}
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@ -473,8 +473,8 @@ namespace ARMeilleure.Instructions
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string name = nameof(Math.Round);
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MethodInfo info = (op.Size & 1) == 0
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? typeof(MathF).GetMethod(name, new Type[] { typeof(float), typeof(MidpointRounding) })
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: typeof(Math). GetMethod(name, new Type[] { typeof(double), typeof(MidpointRounding) });
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? typeof(MathF).GetMethod(name, new Type[] { typeof(float), typeof(MidpointRounding) })
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: typeof(Math).GetMethod(name, new Type[] { typeof(double), typeof(MidpointRounding) });
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return context.Call(info, n, Const((int)roundMode));
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}
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@ -482,7 +482,7 @@ namespace ARMeilleure.Instructions
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public static Operand EmitGetRoundingMode(ArmEmitterContext context)
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{
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Operand rMode = context.ShiftLeft(GetFpFlag(FPState.RMode1Flag), Const(1));
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rMode = context.BitwiseOr(rMode, GetFpFlag(FPState.RMode0Flag));
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rMode = context.BitwiseOr(rMode, GetFpFlag(FPState.RMode0Flag));
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return rMode;
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}
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@ -1015,8 +1015,8 @@ namespace ARMeilleure.Instructions
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for (int index = 0; index < elems; index++)
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{
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Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size + 1, signed);
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Operand me = EmitVectorExtract(context, op.Rm, part + index, op.Size, signed);
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Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size + 1, signed);
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Operand me = EmitVectorExtract(context, op.Rm, part + index, op.Size, signed);
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res = EmitVectorInsert(context, res, emit(ne, me), index, op.Size + 1);
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}
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@ -1077,9 +1077,9 @@ namespace ARMeilleure.Instructions
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for (int index = 0; index < elems; index++)
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{
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Operand de = EmitVectorExtract(context, op.Rd, index, op.Size + 1, signed);
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Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed);
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Operand me = EmitVectorExtract(context, op.Rm, part + index, op.Size, signed);
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Operand de = EmitVectorExtract(context, op.Rd, index, op.Size + 1, signed);
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Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed);
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Operand me = EmitVectorExtract(context, op.Rm, part + index, op.Size, signed);
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res = EmitVectorInsert(context, res, emit(de, ne, me), index, op.Size + 1);
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}
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@ -1143,8 +1143,8 @@ namespace ARMeilleure.Instructions
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for (int index = 0; index < elems; index++)
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{
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Operand de = EmitVectorExtract(context, op.Rd, index, op.Size + 1, signed);
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Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed);
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Operand de = EmitVectorExtract(context, op.Rd, index, op.Size + 1, signed);
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Operand ne = EmitVectorExtract(context, op.Rn, part + index, op.Size, signed);
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res = EmitVectorInsert(context, res, emit(de, ne, me), index, op.Size + 1);
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}
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@ -1174,13 +1174,13 @@ namespace ARMeilleure.Instructions
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{
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int pairIndex = index << 1;
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Operand n0 = EmitVectorExtract(context, op.Rn, pairIndex, op.Size, signed);
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Operand n0 = EmitVectorExtract(context, op.Rn, pairIndex, op.Size, signed);
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Operand n1 = EmitVectorExtract(context, op.Rn, pairIndex + 1, op.Size, signed);
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Operand m0 = EmitVectorExtract(context, op.Rm, pairIndex, op.Size, signed);
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Operand m0 = EmitVectorExtract(context, op.Rm, pairIndex, op.Size, signed);
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Operand m1 = EmitVectorExtract(context, op.Rm, pairIndex + 1, op.Size, signed);
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res = EmitVectorInsert(context, res, emit(n0, n1), index, op.Size);
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res = EmitVectorInsert(context, res, emit(n0, n1), index, op.Size);
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res = EmitVectorInsert(context, res, emit(m0, m1), pairs + index, op.Size);
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}
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@ -1197,11 +1197,11 @@ namespace ARMeilleure.Instructions
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if (op.RegisterSize == RegisterSize.Simd64)
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{
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Operand zeroEvenMask = X86GetElements(context, ZeroMask, EvenMasks[op.Size]);
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Operand zeroOddMask = X86GetElements(context, ZeroMask, OddMasks [op.Size]);
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Operand zeroOddMask = X86GetElements(context, ZeroMask, OddMasks[op.Size]);
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Operand mN = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, n, m); // m:n
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Operand left = context.AddIntrinsic(Intrinsic.X86Pshufb, mN, zeroEvenMask); // 0:even from m:n
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Operand left = context.AddIntrinsic(Intrinsic.X86Pshufb, mN, zeroEvenMask); // 0:even from m:n
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Operand right = context.AddIntrinsic(Intrinsic.X86Pshufb, mN, zeroOddMask); // 0:odd from m:n
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context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst[op.Size], left, right));
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@ -1213,14 +1213,14 @@ namespace ARMeilleure.Instructions
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Operand oddEvenN = context.AddIntrinsic(Intrinsic.X86Pshufb, n, oddEvenMask); // odd:even from n
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Operand oddEvenM = context.AddIntrinsic(Intrinsic.X86Pshufb, m, oddEvenMask); // odd:even from m
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Operand left = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, oddEvenN, oddEvenM);
|
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Operand left = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, oddEvenN, oddEvenM);
|
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Operand right = context.AddIntrinsic(Intrinsic.X86Punpckhqdq, oddEvenN, oddEvenM);
|
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context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst[op.Size], left, right));
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}
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else
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{
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Operand left = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, n, m);
|
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Operand left = context.AddIntrinsic(Intrinsic.X86Punpcklqdq, n, m);
|
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Operand right = context.AddIntrinsic(Intrinsic.X86Punpckhqdq, n, m);
|
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context.Copy(GetVec(op.Rd), context.AddIntrinsic(inst[3], left, right));
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@ -1381,7 +1381,7 @@ namespace ARMeilleure.Instructions
|
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Operand m0 = context.VectorExtract(type, GetVec(op.Rm), pairIndex);
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Operand m1 = context.VectorExtract(type, GetVec(op.Rm), pairIndex + 1);
|
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res = context.VectorInsert(res, emit(n0, n1), index);
|
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res = context.VectorInsert(res, emit(n0, n1), index);
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res = context.VectorInsert(res, emit(m0, m1), pairs + index);
|
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}
|
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|
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@ -1433,18 +1433,18 @@ namespace ARMeilleure.Instructions
|
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public enum CmpCondition
|
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{
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// Legacy Sse.
|
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Equal = 0, // Ordered, non-signaling.
|
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LessThan = 1, // Ordered, signaling.
|
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LessThanOrEqual = 2, // Ordered, signaling.
|
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UnorderedQ = 3, // Non-signaling.
|
||||
NotLessThan = 5, // Unordered, signaling.
|
||||
Equal = 0, // Ordered, non-signaling.
|
||||
LessThan = 1, // Ordered, signaling.
|
||||
LessThanOrEqual = 2, // Ordered, signaling.
|
||||
UnorderedQ = 3, // Non-signaling.
|
||||
NotLessThan = 5, // Unordered, signaling.
|
||||
NotLessThanOrEqual = 6, // Unordered, signaling.
|
||||
OrderedQ = 7, // Non-signaling.
|
||||
OrderedQ = 7, // Non-signaling.
|
||||
|
||||
// Vex.
|
||||
GreaterThanOrEqual = 13, // Ordered, signaling.
|
||||
GreaterThan = 14, // Ordered, signaling.
|
||||
OrderedS = 23 // Signaling.
|
||||
GreaterThan = 14, // Ordered, signaling.
|
||||
OrderedS = 23, // Signaling.
|
||||
}
|
||||
|
||||
[Flags]
|
||||
@ -1459,7 +1459,7 @@ namespace ARMeilleure.Instructions
|
||||
Add = 1 << 3,
|
||||
Sub = 1 << 4,
|
||||
|
||||
Accumulate = 1 << 5
|
||||
Accumulate = 1 << 5,
|
||||
}
|
||||
|
||||
public static void EmitScalarSaturatingUnaryOpSx(ArmEmitterContext context, Func1I emit)
|
||||
@ -1579,7 +1579,7 @@ namespace ARMeilleure.Instructions
|
||||
{
|
||||
Operand de;
|
||||
Operand ne = EmitVectorExtract(context, op.Rn, index, op.Size, !signed);
|
||||
Operand me = EmitVectorExtract(context, op.Rd, index, op.Size, signed);
|
||||
Operand me = EmitVectorExtract(context, op.Rd, index, op.Size, signed);
|
||||
|
||||
if (op.Size <= 2)
|
||||
{
|
||||
@ -1627,7 +1627,7 @@ namespace ARMeilleure.Instructions
|
||||
[Flags]
|
||||
public enum SaturatingNarrowFlags
|
||||
{
|
||||
Scalar = 1 << 0,
|
||||
Scalar = 1 << 0,
|
||||
SignedSrc = 1 << 1,
|
||||
SignedDst = 1 << 2,
|
||||
|
||||
@ -1637,14 +1637,14 @@ namespace ARMeilleure.Instructions
|
||||
|
||||
VectorSxSx = SignedSrc | SignedDst,
|
||||
VectorSxZx = SignedSrc,
|
||||
VectorZxZx = 0
|
||||
VectorZxZx = 0,
|
||||
}
|
||||
|
||||
public static void EmitSaturatingNarrowOp(ArmEmitterContext context, SaturatingNarrowFlags flags)
|
||||
{
|
||||
OpCodeSimd op = (OpCodeSimd)context.CurrOp;
|
||||
|
||||
bool scalar = (flags & SaturatingNarrowFlags.Scalar) != 0;
|
||||
bool scalar = (flags & SaturatingNarrowFlags.Scalar) != 0;
|
||||
bool signedSrc = (flags & SaturatingNarrowFlags.SignedSrc) != 0;
|
||||
bool signedDst = (flags & SaturatingNarrowFlags.SignedDst) != 0;
|
||||
|
||||
@ -2034,18 +2034,30 @@ namespace ARMeilleure.Instructions
|
||||
{
|
||||
switch (size)
|
||||
{
|
||||
case 0: res = context.SignExtend8 (OperandType.I64, res); break;
|
||||
case 1: res = context.SignExtend16(OperandType.I64, res); break;
|
||||
case 2: res = context.SignExtend32(OperandType.I64, res); break;
|
||||
case 0:
|
||||
res = context.SignExtend8(OperandType.I64, res);
|
||||
break;
|
||||
case 1:
|
||||
res = context.SignExtend16(OperandType.I64, res);
|
||||
break;
|
||||
case 2:
|
||||
res = context.SignExtend32(OperandType.I64, res);
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
switch (size)
|
||||
{
|
||||
case 0: res = context.ZeroExtend8 (OperandType.I64, res); break;
|
||||
case 1: res = context.ZeroExtend16(OperandType.I64, res); break;
|
||||
case 2: res = context.ZeroExtend32(OperandType.I64, res); break;
|
||||
case 0:
|
||||
res = context.ZeroExtend8(OperandType.I64, res);
|
||||
break;
|
||||
case 1:
|
||||
res = context.ZeroExtend16(OperandType.I64, res);
|
||||
break;
|
||||
case 2:
|
||||
res = context.ZeroExtend32(OperandType.I64, res);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -2063,10 +2075,18 @@ namespace ARMeilleure.Instructions
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0: vector = context.VectorInsert8 (vector, value, index); break;
|
||||
case 1: vector = context.VectorInsert16(vector, value, index); break;
|
||||
case 2: vector = context.VectorInsert (vector, value, index); break;
|
||||
case 3: vector = context.VectorInsert (vector, value, index); break;
|
||||
case 0:
|
||||
vector = context.VectorInsert8(vector, value, index);
|
||||
break;
|
||||
case 1:
|
||||
vector = context.VectorInsert16(vector, value, index);
|
||||
break;
|
||||
case 2:
|
||||
vector = context.VectorInsert(vector, value, index);
|
||||
break;
|
||||
case 3:
|
||||
vector = context.VectorInsert(vector, value, index);
|
||||
break;
|
||||
}
|
||||
|
||||
return vector;
|
||||
|
||||
Reference in New Issue
Block a user