[Ryujinx.Tests] Address dotnet-format issues (#5389)

* dotnet format style --severity info

Some changes were manually reverted.

* dotnet format analyzers --serverity info

Some changes have been minimally adapted.

* Restore a few unused methods and variables

* Fix new dotnet-format issues after rebase

* Address review comments

* Address most dotnet format whitespace warnings

* Apply dotnet format whitespace formatting

A few of them have been manually reverted and the corresponding warning was silenced

* Format if-blocks correctly

* Run dotnet format after rebase and remove unused usings

- analyzers
- style
- whitespace

* Add comments to disabled warnings

* Simplify properties and array initialization, Use const when possible, Remove trailing commas

* cpu tests: Disable CA2211 for CodeBaseAddress and DataBaseAddress

* Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas"

This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e.

* dotnet format whitespace after rebase

* Apply suggestions from code review

Co-authored-by: Ac_K <Acoustik666@gmail.com>

* First dotnet format pass

* Fix naming rule violations

* Remove naming rule violation exceptions

* Fix comment style

* Use targeted new

* Remove redundant code

* Remove comment alignment

* Remove naming rule exceptions

* Add trailing commas

* Use nameof expression

* Reformat to add remaining trailing commas

---------

Co-authored-by: Ac_K <Acoustik666@gmail.com>

src/Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs

@@ -12,41 +12,53 @@ namespace Ryujinx.Tests.Cpu
     {
 #if SimdShImm
 
-#region "ValueSource (Types)"
+        #region "ValueSource (Types)"
         private static ulong[] _1D_()
         {
-            return new[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
-                           0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
+            return new[] {
+                0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
+                0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul,
+            };
         }
 
         private static ulong[] _1H_()
         {
-            return new[] { 0x0000000000000000ul, 0x0000000000007FFFul,
-                           0x0000000000008000ul, 0x000000000000FFFFul };
+            return new[] {
+                0x0000000000000000ul, 0x0000000000007FFFul,
+                0x0000000000008000ul, 0x000000000000FFFFul,
+            };
         }
 
         private static ulong[] _1S_()
         {
-            return new[] { 0x0000000000000000ul, 0x000000007FFFFFFFul,
-                           0x0000000080000000ul, 0x00000000FFFFFFFFul };
+            return new[] {
+                0x0000000000000000ul, 0x000000007FFFFFFFul,
+                0x0000000080000000ul, 0x00000000FFFFFFFFul,
+            };
         }
 
         private static ulong[] _2S_()
         {
-            return new[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
-                           0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
+            return new[] {
+                0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
+                0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul,
+            };
         }
 
         private static ulong[] _4H_()
         {
-            return new[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
-                           0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
+            return new[] {
+                0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
+                0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul,
+            };
         }
 
         private static ulong[] _8B_()
         {
-            return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
-                           0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
+            return new[] {
+                0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
+                0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul,
+            };
         }
 
         private static IEnumerable<ulong> _2S_F_W_()
@@ -73,19 +85,19 @@ namespace Ryujinx.Tests.Cpu
             yield return 0x007FFFFF007FFFFFul; // +Max Subnormal
             yield return 0x0000000100000001ul; // +Min Subnormal (float.Epsilon)
 
-            if (!NoZeros)
+            if (!_noZeros)
             {
                 yield return 0x8000000080000000ul; // -Zero
                 yield return 0x0000000000000000ul; // +Zero
             }
 
-            if (!NoInfs)
+            if (!_noInfs)
             {
                 yield return 0xFF800000FF800000ul; // -Infinity
                 yield return 0x7F8000007F800000ul; // +Infinity
             }
 
-            if (!NoNaNs)
+            if (!_noNaNs)
             {
                 yield return 0xFFC00000FFC00000ul; // -QNaN (all zeros payload) (float.NaN)
                 yield return 0xFFBFFFFFFFBFFFFFul; // -SNaN (all ones  payload)
@@ -133,19 +145,19 @@ namespace Ryujinx.Tests.Cpu
             yield return 0x000FFFFFFFFFFFFFul; // +Max Subnormal
             yield return 0x0000000000000001ul; // +Min Subnormal (double.Epsilon)
 
-            if (!NoZeros)
+            if (!_noZeros)
             {
                 yield return 0x8000000000000000ul; // -Zero
                 yield return 0x0000000000000000ul; // +Zero
             }
 
-            if (!NoInfs)
+            if (!_noInfs)
             {
                 yield return 0xFFF0000000000000ul; // -Infinity
                 yield return 0x7FF0000000000000ul; // +Infinity
             }
 
-            if (!NoNaNs)
+            if (!_noNaNs)
             {
                 yield return 0xFFF8000000000000ul; // -QNaN (all zeros payload) (double.NaN)
                 yield return 0xFFF7FFFFFFFFFFFFul; // -SNaN (all ones  payload)
@@ -170,15 +182,15 @@ namespace Ryujinx.Tests.Cpu
                 yield return rnd4;
             }
         }
-#endregion
+        #endregion
 
-#region "ValueSource (Opcodes)"
+        #region "ValueSource (Opcodes)"
         private static uint[] _F_Cvt_Z_SU_V_Fixed_2S_4S_()
         {
             return new[]
             {
                 0x0F20FC00u, // FCVTZS V0.2S, V0.2S, #32
-                0x2F20FC00u  // FCVTZU V0.2S, V0.2S, #32
+                0x2F20FC00u, // FCVTZU V0.2S, V0.2S, #32
             };
         }
 
@@ -187,7 +199,7 @@ namespace Ryujinx.Tests.Cpu
             return new[]
             {
                 0x4F40FC00u, // FCVTZS V0.2D, V0.2D, #64
-                0x6F40FC00u  // FCVTZU V0.2D, V0.2D, #64
+                0x6F40FC00u, // FCVTZU V0.2D, V0.2D, #64
             };
         }
 
@@ -196,7 +208,7 @@ namespace Ryujinx.Tests.Cpu
             return new[]
             {
                 0x5F20E420u, // SCVTF S0, S1, #32
-                0x7F20E420u  // UCVTF S0, S1, #32
+                0x7F20E420u, // UCVTF S0, S1, #32
             };
         }
 
@@ -205,7 +217,7 @@ namespace Ryujinx.Tests.Cpu
             return new[]
             {
                 0x5F40E420u, // SCVTF D0, D1, #64
-                0x7F40E420u  // UCVTF D0, D1, #64
+                0x7F40E420u, // UCVTF D0, D1, #64
             };
         }
 
@@ -214,7 +226,7 @@ namespace Ryujinx.Tests.Cpu
             return new[]
             {
                 0x0F20E400u, // SCVTF V0.2S, V0.2S, #32
-                0x2F20E400u  // UCVTF V0.2S, V0.2S, #32
+                0x2F20E400u, // UCVTF V0.2S, V0.2S, #32
             };
         }
 
@@ -223,7 +235,7 @@ namespace Ryujinx.Tests.Cpu
             return new[]
             {
                 0x4F40E400u, // SCVTF V0.2D, V0.2D, #64
-                0x6F40E400u  // UCVTF V0.2D, V0.2D, #64
+                0x6F40E400u, // UCVTF V0.2D, V0.2D, #64
             };
         }
 
@@ -232,7 +244,7 @@ namespace Ryujinx.Tests.Cpu
             return new[]
             {
                 0x5F405400u, // SHL D0, D0, #0
-                0x7F405400u  // SLI D0, D0, #0
+                0x7F405400u, // SLI D0, D0, #0
             };
         }
 
@@ -241,7 +253,7 @@ namespace Ryujinx.Tests.Cpu
             return new[]
             {
                 0x0F085400u, // SHL V0.8B, V0.8B, #0
-                0x2F085400u  // SLI V0.8B, V0.8B, #0
+                0x2F085400u, // SLI V0.8B, V0.8B, #0
             };
         }
 
@@ -250,7 +262,7 @@ namespace Ryujinx.Tests.Cpu
             return new[]
             {
                 0x0F105400u, // SHL V0.4H, V0.4H, #0
-                0x2F105400u  // SLI V0.4H, V0.4H, #0
+                0x2F105400u, // SLI V0.4H, V0.4H, #0
             };
         }
 
@@ -259,7 +271,7 @@ namespace Ryujinx.Tests.Cpu
             return new[]
             {
                 0x0F205400u, // SHL V0.2S, V0.2S, #0
-                0x2F205400u  // SLI V0.2S, V0.2S, #0
+                0x2F205400u, // SLI V0.2S, V0.2S, #0
             };
         }
 
@@ -268,7 +280,7 @@ namespace Ryujinx.Tests.Cpu
             return new[]
             {
                 0x4F405400u, // SHL V0.2D, V0.2D, #0
-                0x6F405400u  // SLI V0.2D, V0.2D, #0
+                0x6F405400u, // SLI V0.2D, V0.2D, #0
             };
         }
 
@@ -277,7 +289,7 @@ namespace Ryujinx.Tests.Cpu
             return new[]
             {
                 0x0F08A400u, // SSHLL V0.8H, V0.8B, #0
-                0x2F08A400u  // USHLL V0.8H, V0.8B, #0
+                0x2F08A400u, // USHLL V0.8H, V0.8B, #0
             };
         }
 
@@ -286,7 +298,7 @@ namespace Ryujinx.Tests.Cpu
             return new[]
             {
                 0x0F10A400u, // SSHLL V0.4S, V0.4H, #0
-                0x2F10A400u  // USHLL V0.4S, V0.4H, #0
+                0x2F10A400u, // USHLL V0.4S, V0.4H, #0
             };
         }
 
@@ -295,7 +307,7 @@ namespace Ryujinx.Tests.Cpu
             return new[]
             {
                 0x0F20A400u, // SSHLL V0.2D, V0.2S, #0
-                0x2F20A400u  // USHLL V0.2D, V0.2S, #0
+                0x2F20A400u, // USHLL V0.2D, V0.2S, #0
             };
         }
 
@@ -311,7 +323,7 @@ namespace Ryujinx.Tests.Cpu
                 0x7F402400u, // URSHR D0, D0, #64
                 0x7F403400u, // URSRA D0, D0, #64
                 0x7F400400u, // USHR  D0, D0, #64
-                0x7F401400u  // USRA  D0, D0, #64
+                0x7F401400u, // USRA  D0, D0, #64
             };
         }
 
@@ -327,7 +339,7 @@ namespace Ryujinx.Tests.Cpu
                 0x2F082400u, // URSHR V0.8B, V0.8B, #8
                 0x2F083400u, // URSRA V0.8B, V0.8B, #8
                 0x2F080400u, // USHR  V0.8B, V0.8B, #8
-                0x2F081400u  // USRA  V0.8B, V0.8B, #8
+                0x2F081400u, // USRA  V0.8B, V0.8B, #8
             };
         }
 
@@ -343,7 +355,7 @@ namespace Ryujinx.Tests.Cpu
                 0x2F102400u, // URSHR V0.4H, V0.4H, #16
                 0x2F103400u, // URSRA V0.4H, V0.4H, #16
                 0x2F100400u, // USHR  V0.4H, V0.4H, #16
-                0x2F101400u  // USRA  V0.4H, V0.4H, #16
+                0x2F101400u, // USRA  V0.4H, V0.4H, #16
             };
         }
 
@@ -359,7 +371,7 @@ namespace Ryujinx.Tests.Cpu
                 0x2F202400u, // URSHR V0.2S, V0.2S, #32
                 0x2F203400u, // URSRA V0.2S, V0.2S, #32
                 0x2F200400u, // USHR  V0.2S, V0.2S, #32
-                0x2F201400u  // USRA  V0.2S, V0.2S, #32
+                0x2F201400u, // USRA  V0.2S, V0.2S, #32
             };
         }
 
@@ -375,7 +387,7 @@ namespace Ryujinx.Tests.Cpu
                 0x6F402400u, // URSHR V0.2D, V0.2D, #64
                 0x6F403400u, // URSRA V0.2D, V0.2D, #64
                 0x6F400400u, // USHR  V0.2D, V0.2D, #64
-                0x6F401400u  // USRA  V0.2D, V0.2D, #64
+                0x6F401400u, // USRA  V0.2D, V0.2D, #64
             };
         }
 
@@ -384,7 +396,7 @@ namespace Ryujinx.Tests.Cpu
             return new[]
             {
                 0x0F088C00u, // RSHRN V0.8B, V0.8H, #8
-                0x0F088400u  // SHRN  V0.8B, V0.8H, #8
+                0x0F088400u, // SHRN  V0.8B, V0.8H, #8
             };
         }
 
@@ -393,7 +405,7 @@ namespace Ryujinx.Tests.Cpu
             return new[]
             {
                 0x0F108C00u, // RSHRN V0.4H, V0.4S, #16
-                0x0F108400u  // SHRN  V0.4H, V0.4S, #16
+                0x0F108400u, // SHRN  V0.4H, V0.4S, #16
             };
         }
 
@@ -402,7 +414,7 @@ namespace Ryujinx.Tests.Cpu
             return new[]
             {
                 0x0F208C00u, // RSHRN V0.2S, V0.2D, #32
-                0x0F208400u  // SHRN  V0.2S, V0.2D, #32
+                0x0F208400u, // SHRN  V0.2S, V0.2D, #32
             };
         }
 
@@ -415,7 +427,7 @@ namespace Ryujinx.Tests.Cpu
                 0x7F088C00u, // SQRSHRUN B0, H0, #8
                 0x5F089400u, // SQSHRN   B0, H0, #8
                 0x7F089400u, // UQSHRN   B0, H0, #8
-                0x7F088400u  // SQSHRUN  B0, H0, #8
+                0x7F088400u, // SQSHRUN  B0, H0, #8
             };
         }
 
@@ -428,7 +440,7 @@ namespace Ryujinx.Tests.Cpu
                 0x7F108C00u, // SQRSHRUN H0, S0, #16
                 0x5F109400u, // SQSHRN   H0, S0, #16
                 0x7F109400u, // UQSHRN   H0, S0, #16
-                0x7F108400u  // SQSHRUN  H0, S0, #16
+                0x7F108400u, // SQSHRUN  H0, S0, #16
             };
         }
 
@@ -441,7 +453,7 @@ namespace Ryujinx.Tests.Cpu
                 0x7F208C00u, // SQRSHRUN S0, D0, #32
                 0x5F209400u, // SQSHRN   S0, D0, #32
                 0x7F209400u, // UQSHRN   S0, D0, #32
-                0x7F208400u  // SQSHRUN  S0, D0, #32
+                0x7F208400u, // SQSHRUN  S0, D0, #32
             };
         }
 
@@ -454,7 +466,7 @@ namespace Ryujinx.Tests.Cpu
                 0x2F088C00u, // SQRSHRUN V0.8B, V0.8H, #8
                 0x0F089400u, // SQSHRN   V0.8B, V0.8H, #8
                 0x2F089400u, // UQSHRN   V0.8B, V0.8H, #8
-                0x2F088400u  // SQSHRUN  V0.8B, V0.8H, #8
+                0x2F088400u, // SQSHRUN  V0.8B, V0.8H, #8
             };
         }
 
@@ -467,7 +479,7 @@ namespace Ryujinx.Tests.Cpu
                 0x2F108C00u, // SQRSHRUN V0.4H, V0.4S, #16
                 0x0F109400u, // SQSHRN   V0.4H, V0.4S, #16
                 0x2F109400u, // UQSHRN   V0.4H, V0.4S, #16
-                0x2F108400u  // SQSHRUN  V0.4H, V0.4S, #16
+                0x2F108400u, // SQSHRUN  V0.4H, V0.4S, #16
             };
         }
 
@@ -480,20 +492,21 @@ namespace Ryujinx.Tests.Cpu
                 0x2F208C00u, // SQRSHRUN V0.2S, V0.2D, #32
                 0x0F209400u, // SQSHRN   V0.2S, V0.2D, #32
                 0x2F209400u, // UQSHRN   V0.2S, V0.2D, #32
-                0x2F208400u  // SQSHRUN  V0.2S, V0.2D, #32
+                0x2F208400u, // SQSHRUN  V0.2S, V0.2D, #32
             };
         }
-#endregion
+        #endregion
 
-        private const int RndCnt      = 2;
+        private const int RndCnt = 2;
 
-        private static readonly bool NoZeros = false;
-        private static readonly bool NoInfs  = false;
-        private static readonly bool NoNaNs  = false;
+        private static readonly bool _noZeros = false;
+        private static readonly bool _noInfs = false;
+        private static readonly bool _noNaNs = false;
 
-        [Test, Pairwise] [Explicit]
+        [Test, Pairwise]
+        [Explicit]
         public void F_Cvt_Z_SU_V_Fixed_2S_4S([ValueSource(nameof(_F_Cvt_Z_SU_V_Fixed_2S_4S_))] uint opcodes,
-                                             [Values(0u)]     uint rd,
+                                             [Values(0u)] uint rd,
                                              [Values(1u, 0u)] uint rn,
                                              [ValueSource(nameof(_2S_F_W_))] ulong z,
                                              [ValueSource(nameof(_2S_F_W_))] ulong a,
@@ -514,9 +527,10 @@ namespace Ryujinx.Tests.Cpu
             CompareAgainstUnicorn();
         }
 
-        [Test, Pairwise] [Explicit]
+        [Test, Pairwise]
+        [Explicit]
         public void F_Cvt_Z_SU_V_Fixed_2D([ValueSource(nameof(_F_Cvt_Z_SU_V_Fixed_2D_))] uint opcodes,
-                                          [Values(0u)]     uint rd,
+                                          [Values(0u)] uint rd,
                                           [Values(1u, 0u)] uint rn,
                                           [ValueSource(nameof(_1D_F_X_))] ulong z,
                                           [ValueSource(nameof(_1D_F_X_))] ulong a,
@@ -535,7 +549,8 @@ namespace Ryujinx.Tests.Cpu
             CompareAgainstUnicorn();
         }
 
-        [Test, Pairwise] [Explicit]
+        [Test, Pairwise]
+        [Explicit]
         public void SU_Cvt_F_S_Fixed_S([ValueSource(nameof(_SU_Cvt_F_S_Fixed_S_))] uint opcodes,
                                        [ValueSource(nameof(_1S_))] ulong a,
                                        [Values(1u, 32u)] uint fBits)
@@ -553,7 +568,8 @@ namespace Ryujinx.Tests.Cpu
             CompareAgainstUnicorn();
         }
 
-        [Test, Pairwise] [Explicit]
+        [Test, Pairwise]
+        [Explicit]
         public void SU_Cvt_F_S_Fixed_D([ValueSource(nameof(_SU_Cvt_F_S_Fixed_D_))] uint opcodes,
                                        [ValueSource(nameof(_1D_))] ulong a,
                                        [Values(1u, 64u)] uint fBits)
@@ -571,9 +587,10 @@ namespace Ryujinx.Tests.Cpu
             CompareAgainstUnicorn();
         }
 
-        [Test, Pairwise] [Explicit]
+        [Test, Pairwise]
+        [Explicit]
         public void SU_Cvt_F_V_Fixed_2S_4S([ValueSource(nameof(_SU_Cvt_F_V_Fixed_2S_4S_))] uint opcodes,
-                                           [Values(0u)]     uint rd,
+                                           [Values(0u)] uint rd,
                                            [Values(1u, 0u)] uint rn,
                                            [ValueSource(nameof(_2S_))] ulong z,
                                            [ValueSource(nameof(_2S_))] ulong a,
@@ -594,9 +611,10 @@ namespace Ryujinx.Tests.Cpu
             CompareAgainstUnicorn();
         }
 
-        [Test, Pairwise] [Explicit]
+        [Test, Pairwise]
+        [Explicit]
         public void SU_Cvt_F_V_Fixed_2D([ValueSource(nameof(_SU_Cvt_F_V_Fixed_2D_))] uint opcodes,
-                                        [Values(0u)]     uint rd,
+                                        [Values(0u)] uint rd,
                                         [Values(1u, 0u)] uint rn,
                                         [ValueSource(nameof(_1D_))] ulong z,
                                         [ValueSource(nameof(_1D_))] ulong a,
@@ -617,7 +635,7 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Pairwise]
         public void Shl_Sli_S_D([ValueSource(nameof(_Shl_Sli_S_D_))] uint opcodes,
-                                [Values(0u)]     uint rd,
+                                [Values(0u)] uint rd,
                                 [Values(1u, 0u)] uint rn,
                                 [ValueSource(nameof(_1D_))] ulong z,
                                 [ValueSource(nameof(_1D_))] ulong a,
@@ -638,7 +656,7 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Pairwise]
         public void Shl_Sli_V_8B_16B([ValueSource(nameof(_Shl_Sli_V_8B_16B_))] uint opcodes,
-                                     [Values(0u)]     uint rd,
+                                     [Values(0u)] uint rd,
                                      [Values(1u, 0u)] uint rn,
                                      [ValueSource(nameof(_8B_))] ulong z,
                                      [ValueSource(nameof(_8B_))] ulong a,
@@ -661,7 +679,7 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Pairwise]
         public void Shl_Sli_V_4H_8H([ValueSource(nameof(_Shl_Sli_V_4H_8H_))] uint opcodes,
-                                    [Values(0u)]     uint rd,
+                                    [Values(0u)] uint rd,
                                     [Values(1u, 0u)] uint rn,
                                     [ValueSource(nameof(_4H_))] ulong z,
                                     [ValueSource(nameof(_4H_))] ulong a,
@@ -684,7 +702,7 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Pairwise]
         public void Shl_Sli_V_2S_4S([ValueSource(nameof(_Shl_Sli_V_2S_4S_))] uint opcodes,
-                                    [Values(0u)]     uint rd,
+                                    [Values(0u)] uint rd,
                                     [Values(1u, 0u)] uint rn,
                                     [ValueSource(nameof(_2S_))] ulong z,
                                     [ValueSource(nameof(_2S_))] ulong a,
@@ -707,7 +725,7 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Pairwise]
         public void Shl_Sli_V_2D([ValueSource(nameof(_Shl_Sli_V_2D_))] uint opcodes,
-                                 [Values(0u)]     uint rd,
+                                 [Values(0u)] uint rd,
                                  [Values(1u, 0u)] uint rn,
                                  [ValueSource(nameof(_1D_))] ulong z,
                                  [ValueSource(nameof(_1D_))] ulong a,
@@ -728,7 +746,7 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Pairwise]
         public void SU_Shll_V_8B8H_16B8H([ValueSource(nameof(_SU_Shll_V_8B8H_16B8H_))] uint opcodes,
-                                         [Values(0u)]     uint rd,
+                                         [Values(0u)] uint rd,
                                          [Values(1u, 0u)] uint rn,
                                          [ValueSource(nameof(_8B_))] ulong z,
                                          [ValueSource(nameof(_8B_))] ulong a,
@@ -751,7 +769,7 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Pairwise]
         public void SU_Shll_V_4H4S_8H4S([ValueSource(nameof(_SU_Shll_V_4H4S_8H4S_))] uint opcodes,
-                                        [Values(0u)]     uint rd,
+                                        [Values(0u)] uint rd,
                                         [Values(1u, 0u)] uint rn,
                                         [ValueSource(nameof(_4H_))] ulong z,
                                         [ValueSource(nameof(_4H_))] ulong a,
@@ -774,7 +792,7 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Pairwise]
         public void SU_Shll_V_2S2D_4S2D([ValueSource(nameof(_SU_Shll_V_2S2D_4S2D_))] uint opcodes,
-                                        [Values(0u)]     uint rd,
+                                        [Values(0u)] uint rd,
                                         [Values(1u, 0u)] uint rn,
                                         [ValueSource(nameof(_2S_))] ulong z,
                                         [ValueSource(nameof(_2S_))] ulong a,
@@ -797,7 +815,7 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Pairwise]
         public void ShrImm_Sri_S_D([ValueSource(nameof(_ShrImm_Sri_S_D_))] uint opcodes,
-                                   [Values(0u)]     uint rd,
+                                   [Values(0u)] uint rd,
                                    [Values(1u, 0u)] uint rn,
                                    [ValueSource(nameof(_1D_))] ulong z,
                                    [ValueSource(nameof(_1D_))] ulong a,
@@ -818,7 +836,7 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Pairwise]
         public void ShrImm_Sri_V_8B_16B([ValueSource(nameof(_ShrImm_Sri_V_8B_16B_))] uint opcodes,
-                                        [Values(0u)]     uint rd,
+                                        [Values(0u)] uint rd,
                                         [Values(1u, 0u)] uint rn,
                                         [ValueSource(nameof(_8B_))] ulong z,
                                         [ValueSource(nameof(_8B_))] ulong a,
@@ -841,7 +859,7 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Pairwise]
         public void ShrImm_Sri_V_4H_8H([ValueSource(nameof(_ShrImm_Sri_V_4H_8H_))] uint opcodes,
-                                       [Values(0u)]     uint rd,
+                                       [Values(0u)] uint rd,
                                        [Values(1u, 0u)] uint rn,
                                        [ValueSource(nameof(_4H_))] ulong z,
                                        [ValueSource(nameof(_4H_))] ulong a,
@@ -864,7 +882,7 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Pairwise]
         public void ShrImm_Sri_V_2S_4S([ValueSource(nameof(_ShrImm_Sri_V_2S_4S_))] uint opcodes,
-                                       [Values(0u)]     uint rd,
+                                       [Values(0u)] uint rd,
                                        [Values(1u, 0u)] uint rn,
                                        [ValueSource(nameof(_2S_))] ulong z,
                                        [ValueSource(nameof(_2S_))] ulong a,
@@ -887,7 +905,7 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Pairwise]
         public void ShrImm_Sri_V_2D([ValueSource(nameof(_ShrImm_Sri_V_2D_))] uint opcodes,
-                                    [Values(0u)]     uint rd,
+                                    [Values(0u)] uint rd,
                                     [Values(1u, 0u)] uint rn,
                                     [ValueSource(nameof(_1D_))] ulong z,
                                     [ValueSource(nameof(_1D_))] ulong a,
@@ -908,7 +926,7 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Pairwise]
         public void ShrImmNarrow_V_8H8B_8H16B([ValueSource(nameof(_ShrImmNarrow_V_8H8B_8H16B_))] uint opcodes,
-                                              [Values(0u)]     uint rd,
+                                              [Values(0u)] uint rd,
                                               [Values(1u, 0u)] uint rn,
                                               [ValueSource(nameof(_4H_))] ulong z,
                                               [ValueSource(nameof(_4H_))] ulong a,
@@ -931,7 +949,7 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Pairwise]
         public void ShrImmNarrow_V_4S4H_4S8H([ValueSource(nameof(_ShrImmNarrow_V_4S4H_4S8H_))] uint opcodes,
-                                             [Values(0u)]     uint rd,
+                                             [Values(0u)] uint rd,
                                              [Values(1u, 0u)] uint rn,
                                              [ValueSource(nameof(_2S_))] ulong z,
                                              [ValueSource(nameof(_2S_))] ulong a,
@@ -954,7 +972,7 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Pairwise]
         public void ShrImmNarrow_V_2D2S_2D4S([ValueSource(nameof(_ShrImmNarrow_V_2D2S_2D4S_))] uint opcodes,
-                                             [Values(0u)]     uint rd,
+                                             [Values(0u)] uint rd,
                                              [Values(1u, 0u)] uint rn,
                                              [ValueSource(nameof(_1D_))] ulong z,
                                              [ValueSource(nameof(_1D_))] ulong a,
@@ -977,7 +995,7 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Pairwise]
         public void ShrImmSaturatingNarrow_S_HB([ValueSource(nameof(_ShrImmSaturatingNarrow_S_HB_))] uint opcodes,
-                                                [Values(0u)]     uint rd,
+                                                [Values(0u)] uint rd,
                                                 [Values(1u, 0u)] uint rn,
                                                 [ValueSource(nameof(_1H_))] ulong z,
                                                 [ValueSource(nameof(_1H_))] ulong a,
@@ -998,7 +1016,7 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Pairwise]
         public void ShrImmSaturatingNarrow_S_SH([ValueSource(nameof(_ShrImmSaturatingNarrow_S_SH_))] uint opcodes,
-                                                [Values(0u)]     uint rd,
+                                                [Values(0u)] uint rd,
                                                 [Values(1u, 0u)] uint rn,
                                                 [ValueSource(nameof(_1S_))] ulong z,
                                                 [ValueSource(nameof(_1S_))] ulong a,
@@ -1019,7 +1037,7 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Pairwise]
         public void ShrImmSaturatingNarrow_S_DS([ValueSource(nameof(_ShrImmSaturatingNarrow_S_DS_))] uint opcodes,
-                                                [Values(0u)]     uint rd,
+                                                [Values(0u)] uint rd,
                                                 [Values(1u, 0u)] uint rn,
                                                 [ValueSource(nameof(_1D_))] ulong z,
                                                 [ValueSource(nameof(_1D_))] ulong a,
@@ -1040,7 +1058,7 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Pairwise]
         public void ShrImmSaturatingNarrow_V_8H8B_8H16B([ValueSource(nameof(_ShrImmSaturatingNarrow_V_8H8B_8H16B_))] uint opcodes,
-                                                        [Values(0u)]     uint rd,
+                                                        [Values(0u)] uint rd,
                                                         [Values(1u, 0u)] uint rn,
                                                         [ValueSource(nameof(_4H_))] ulong z,
                                                         [ValueSource(nameof(_4H_))] ulong a,
@@ -1063,7 +1081,7 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Pairwise]
         public void ShrImmSaturatingNarrow_V_4S4H_4S8H([ValueSource(nameof(_ShrImmSaturatingNarrow_V_4S4H_4S8H_))] uint opcodes,
-                                                       [Values(0u)]     uint rd,
+                                                       [Values(0u)] uint rd,
                                                        [Values(1u, 0u)] uint rn,
                                                        [ValueSource(nameof(_2S_))] ulong z,
                                                        [ValueSource(nameof(_2S_))] ulong a,
@@ -1086,7 +1104,7 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Pairwise]
         public void ShrImmSaturatingNarrow_V_2D2S_2D4S([ValueSource(nameof(_ShrImmSaturatingNarrow_V_2D2S_2D4S_))] uint opcodes,
-                                                       [Values(0u)]     uint rd,
+                                                       [Values(0u)] uint rd,
                                                        [Values(1u, 0u)] uint rn,
                                                        [ValueSource(nameof(_1D_))] ulong z,
                                                        [ValueSource(nameof(_1D_))] ulong a,
@@ -1108,4 +1126,4 @@ namespace Ryujinx.Tests.Cpu
         }
 #endif
     }
-}
+}