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PPTC & Pool Enhancements.

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This commit is contained in:
LDj3SNuD
2021-01-27 06:21:37 +01:00
parent c4f56c5704
commit d31479a633
15 changed files with 624 additions and 406 deletions
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76
ARMeilleure/CodeGen/RegisterAllocators/LinearScanAllocator.cs
View File

@@ -50,6 +50,8 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
StackAlloc = stackAlloc;
Masks = masks;
BitMapPool.PrepareBitMapPool();
Active = BitMapPool.Allocate(intervalsCount);
Inactive = BitMapPool.Allocate(intervalsCount);
}
@@ -73,7 +75,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
public void Dispose()
{
BitMapPool.Release();
BitMapPool.ResetBitMapPool();
}
}
@@ -84,57 +86,51 @@ namespace ARMeilleure.CodeGen.RegisterAllocators
{
NumberLocals(cfg);
AllocationContext context = new AllocationContext(stackAlloc, regMasks, _intervals.Count);
BuildIntervals(cfg, context);
for (int index = 0; index < _intervals.Count; index++)
using (AllocationContext context = new AllocationContext(stackAlloc, regMasks, _intervals.Count))
{
LiveInterval current = _intervals[index];
BuildIntervals(cfg, context);
if (current.IsEmpty)
for (int index = 0; index < _intervals.Count; index++)
{
continue;
}
LiveInterval current = _intervals[index];
if (current.IsFixed)
{
context.Active.Set(index);
if (current.Register.Type == RegisterType.Integer)
if (current.IsEmpty)
{
context.IntUsedRegisters |= 1 << current.Register.Index;
}
else /* if (interval.Register.Type == RegisterType.Vector) */
{
context.VecUsedRegisters |= 1 << current.Register.Index;
continue;
}
continue;
if (current.IsFixed)
{
context.Active.Set(index);
if (current.Register.Type == RegisterType.Integer)
{
context.IntUsedRegisters |= 1 << current.Register.Index;
}
else /* if (interval.Register.Type == RegisterType.Vector) */
{
context.VecUsedRegisters |= 1 << current.Register.Index;
}
continue;
}
AllocateInterval(context, current, index);
}
AllocateInterval(context, current, index);
}
for (int index = RegistersCount * 2; index < _intervals.Count; index++)
{
if (!_intervals[index].IsSpilled)
for (int index = RegistersCount * 2; index < _intervals.Count; index++)
{
ReplaceLocalWithRegister(_intervals[index]);
if (!_intervals[index].IsSpilled)
{
ReplaceLocalWithRegister(_intervals[index]);
}
}
InsertSplitCopies();
InsertSplitCopiesAtEdges(cfg);
return new AllocationResult(context.IntUsedRegisters, context.VecUsedRegisters, context.StackAlloc.TotalSize);
}
InsertSplitCopies();
InsertSplitCopiesAtEdges(cfg);
AllocationResult result = new AllocationResult(
context.IntUsedRegisters,
context.VecUsedRegisters,
context.StackAlloc.TotalSize);
context.Dispose();
return result;
}
private void AllocateInterval(AllocationContext context, LiveInterval current, int cIndex)

7
ARMeilleure/CodeGen/X86/CodeGenContext.cs
View File

@@ -2,6 +2,7 @@ using ARMeilleure.CodeGen.RegisterAllocators;
using ARMeilleure.Common;
using ARMeilleure.IntermediateRepresentation;
using ARMeilleure.Translation.PTC;
using System;
using System.Collections.Generic;
using System.Diagnostics;
using System.IO;
@@ -301,7 +302,7 @@ namespace ARMeilleure.CodeGen.X86
{
Assembler assembler = new Assembler(codeStream, _ptcInfo);
byte[] buffer;
Span<byte> buffer;
for (int index = 0; index < _jumps.Count; index++)
{
@@ -309,7 +310,7 @@ namespace ARMeilleure.CodeGen.X86
buffer = new byte[jump.JumpPosition - _stream.Position];
_stream.Read(buffer, 0, buffer.Length);
_stream.Read(buffer);
_stream.Seek(_ptcDisabled ? ReservedBytesForJump : jump.InstSize, SeekOrigin.Current);
codeStream.Write(buffer);
@@ -326,7 +327,7 @@ namespace ARMeilleure.CodeGen.X86
buffer = new byte[_stream.Length - _stream.Position];
_stream.Read(buffer, 0, buffer.Length);
_stream.Read(buffer);
codeStream.Write(buffer);