Fix Sshl_V; Add S/Uqrshl_V, S/Uqshl_V, S/Urshl_V; Add Tests. (#516)
* Update OpCodeTable.cs * Update InstEmitSimdShift.cs * Update SoftFallback.cs * Update CpuTestSimdReg.cs * Nit. * Update SoftFallback.cs * Update Optimizations.cs * Update InstEmitSimdLogical.cs * Update InstEmitSimdArithmetic.cs
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@ -10,8 +10,8 @@ namespace ChocolArm64.Decoders
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public OpCodeSimdFcond64(Inst inst, long position, int opCode) : base(inst, position, opCode)
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{
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Nzcv = (opCode >> 0) & 0xf;
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Nzcv = (opCode >> 0) & 0xf;
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Cond = (Cond)((opCode >> 12) & 0xf);
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}
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}
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}
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}
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