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Add a new JIT compiler for CPU code (#693)

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* Start of the ARMeilleure project

* Refactoring around the old IRAdapter, now renamed to PreAllocator

* Optimize the LowestBitSet method

* Add CLZ support and fix CLS implementation

* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks

* Implement the ByteSwap IR instruction, and some refactoring on the assembler

* Implement the DivideUI IR instruction and fix 64-bits IDIV

* Correct constant operand type on CSINC

* Move division instructions implementation to InstEmitDiv

* Fix destination type for the ConditionalSelect IR instruction

* Implement UMULH and SMULH, with new IR instructions

* Fix some issues with shift instructions

* Fix constant types for BFM instructions

* Fix up new tests using the new V128 struct

* Update tests

* Move DIV tests to a separate file

* Add support for calls, and some instructions that depends on them

* Start adding support for SIMD & FP types, along with some of the related ARM instructions

* Fix some typos and the divide instruction with FP operands

* Fix wrong method call on Clz_V

* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes

* Implement SIMD logical instructions and more misc. fixes

* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations

* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes

* Implement SIMD shift instruction and fix Dup_V

* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table

* Fix check with tolerance on tester

* Implement FP & SIMD comparison instructions, and some fixes

* Update FCVT (Scalar) encoding on the table to support the Half-float variants

* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes

* Use old memory access methods, made a start on SIMD memory insts support, some fixes

* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes

* Fix arguments count with struct return values, other fixes

* More instructions

* Misc. fixes and integrate LDj3SNuD fixes

* Update tests

* Add a faster linear scan allocator, unwinding support on windows, and other changes

* Update Ryujinx.HLE

* Update Ryujinx.Graphics

* Fix V128 return pointer passing, RCX is clobbered

* Update Ryujinx.Tests

* Update ITimeZoneService

* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks

* Use generic GetFunctionPointerForDelegate method and other tweaks

* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics

* Remove some unused code on the assembler

* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler

* Add hardware capability detection

* Fix regression on Sha1h and revert Fcm** changes

* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator

* Fix silly mistake introduced on last commit on CpuId

* Generate inline stack probes when the stack allocation is too large

* Initial support for the System-V ABI

* Support multiple destination operands

* Fix SSE2 VectorInsert8 path, and other fixes

* Change placement of XMM callee save and restore code to match other compilers

* Rename Dest to Destination and Inst to Instruction

* Fix a regression related to calls and the V128 type

* Add an extra space on comments to match code style

* Some refactoring

* Fix vector insert FP32 SSE2 path

* Port over the ARM32 instructions

* Avoid memory protection races on JIT Cache

* Another fix on VectorInsert FP32 (thanks to LDj3SNuD

* Float operands don't need to use the same register when VEX is supported

* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks

* Some nits, small improvements on the pre allocator

* CpuThreadState is gone

* Allow changing CPU emulators with a config entry

* Add runtime identifiers on the ARMeilleure project

* Allow switching between CPUs through a config entry (pt. 2)

* Change win10-x64 to win-x64 on projects

* Update the Ryujinx project to use ARMeilleure

* Ensure that the selected register is valid on the hybrid allocator

* Allow exiting on returns to 0 (should fix test regression)

* Remove register assignments for most used variables on the hybrid allocator

* Do not use fixed registers as spill temp

* Add missing namespace and remove unneeded using

* Address PR feedback

* Fix types, etc

* Enable AssumeStrictAbiCompliance by default

* Ensure that Spill and Fill don't load or store any more than necessary
This commit is contained in:
gdkchan
2019-08-08 15:56:22 -03:00
committed by emmauss
parent 1ba58e9942
commit a731ab3a2a
310 changed files with 37389 additions and 2086 deletions
Download Patch File Download Diff File Expand all files Collapse all files

204
Ryujinx.Tests.Unicorn/UnicornAArch64.cs
View File

@ -1,8 +1,5 @@
using Ryujinx.Tests.Unicorn.Native;
using System;
using System.Diagnostics.Contracts;
using System.Runtime.Intrinsics;
using System.Runtime.Intrinsics.X86;
namespace Ryujinx.Tests.Unicorn
{
@ -15,95 +12,96 @@ namespace Ryujinx.Tests.Unicorn
get
{
return new IndexedProperty<int, ulong>(
(int i) => GetX(i),
(int i) => GetX(i),
(int i, ulong value) => SetX(i, value));
}
}
public IndexedProperty<int, Vector128<float>> Q
public IndexedProperty<int, SimdValue> Q
{
get
{
return new IndexedProperty<int, Vector128<float>>(
(int i) => GetQ(i),
(int i, Vector128<float> value) => SetQ(i, value));
return new IndexedProperty<int, SimdValue>(
(int i) => GetQ(i),
(int i, SimdValue value) => SetQ(i, value));
}
}
public ulong LR
{
get { return GetRegister(ArmRegister.LR); }
set { SetRegister(ArmRegister.LR, value); }
get => GetRegister(ArmRegister.LR);
set => SetRegister(ArmRegister.LR, value);
}
public ulong SP
{
get { return GetRegister(ArmRegister.SP); }
set { SetRegister(ArmRegister.SP, value); }
get => GetRegister(ArmRegister.SP);
set => SetRegister(ArmRegister.SP, value);
}
public ulong PC
{
get { return GetRegister(ArmRegister.PC); }
set { SetRegister(ArmRegister.PC, value); }
get => GetRegister(ArmRegister.PC);
set => SetRegister(ArmRegister.PC, value);
}
public uint Pstate
{
get { return (uint)GetRegister(ArmRegister.PSTATE); }
set { SetRegister(ArmRegister.PSTATE, (uint)value); }
get => (uint)GetRegister(ArmRegister.PSTATE);
set => SetRegister(ArmRegister.PSTATE, (uint)value);
}
public int Fpcr
{
get { return (int)GetRegister(ArmRegister.FPCR); }
set { SetRegister(ArmRegister.FPCR, (uint)value); }
get => (int)GetRegister(ArmRegister.FPCR);
set => SetRegister(ArmRegister.FPCR, (uint)value);
}
public int Fpsr
{
get { return (int)GetRegister(ArmRegister.FPSR); }
set { SetRegister(ArmRegister.FPSR, (uint)value); }
get => (int)GetRegister(ArmRegister.FPSR);
set => SetRegister(ArmRegister.FPSR, (uint)value);
}
public bool OverflowFlag
{
get { return (Pstate & 0x10000000u) != 0; }
set { Pstate = (Pstate & ~0x10000000u) | (value ? 0x10000000u : 0u); }
get => (Pstate & 0x10000000u) != 0;
set => Pstate = (Pstate & ~0x10000000u) | (value ? 0x10000000u : 0u);
}
public bool CarryFlag
{
get { return (Pstate & 0x20000000u) != 0; }
set { Pstate = (Pstate & ~0x20000000u) | (value ? 0x20000000u : 0u); }
get => (Pstate & 0x20000000u) != 0;
set => Pstate = (Pstate & ~0x20000000u) | (value ? 0x20000000u : 0u);
}
public bool ZeroFlag
{
get { return (Pstate & 0x40000000u) != 0; }
set { Pstate = (Pstate & ~0x40000000u) | (value ? 0x40000000u : 0u); }
get => (Pstate & 0x40000000u) != 0;
set => Pstate = (Pstate & ~0x40000000u) | (value ? 0x40000000u : 0u);
}
public bool NegativeFlag
{
get { return (Pstate & 0x80000000u) != 0; }
set { Pstate = (Pstate & ~0x80000000u) | (value ? 0x80000000u : 0u); }
get => (Pstate & 0x80000000u) != 0;
set => Pstate = (Pstate & ~0x80000000u) | (value ? 0x80000000u : 0u);
}
public UnicornAArch64()
{
Interface.Checked(Interface.uc_open((uint)UnicornArch.UC_ARCH_ARM64, (uint)UnicornMode.UC_MODE_LITTLE_ENDIAN, out uc));
Interface.Checked(Interface.uc_open(UnicornArch.UC_ARCH_ARM64, UnicornMode.UC_MODE_LITTLE_ENDIAN, out uc));
SetRegister(ArmRegister.CPACR_EL1, 0x00300000);
}
~UnicornAArch64()
{
Interface.Checked(Interface.uc_close(uc));
Interface.Checked(Native.Interface.uc_close(uc));
}
public void RunForCount(ulong count)
{
Interface.Checked(Interface.uc_emu_start(uc, PC, 0xFFFFFFFFFFFFFFFFu, 0, count));
Interface.Checked(Native.Interface.uc_emu_start(uc, this.PC, 0xFFFFFFFFFFFFFFFFu, 0, count));
}
public void Step()
@ -111,7 +109,7 @@ namespace Ryujinx.Tests.Unicorn
RunForCount(1);
}
internal static ArmRegister[] X_registers = new ArmRegister[31]
private static ArmRegister[] XRegisters = new ArmRegister[31]
{
ArmRegister.X0,
ArmRegister.X1,
@ -146,7 +144,7 @@ namespace Ryujinx.Tests.Unicorn
ArmRegister.X30,
};
internal static ArmRegister[] Q_registers = new ArmRegister[32]
private static ArmRegister[] QRegisters = new ArmRegister[32]
{
ArmRegister.Q0,
ArmRegister.Q1,
@ -182,97 +180,104 @@ namespace Ryujinx.Tests.Unicorn
ArmRegister.Q31,
};
internal ulong GetRegister(ArmRegister register)
{
byte[] value_bytes = new byte[8];
Interface.Checked(Interface.uc_reg_read(uc, (int)register, value_bytes));
return (ulong)BitConverter.ToInt64(value_bytes, 0);
}
internal void SetRegister(ArmRegister register, ulong value)
{
byte[] value_bytes = BitConverter.GetBytes(value);
Interface.Checked(Interface.uc_reg_write(uc, (int)register, value_bytes));
}
internal Vector128<float> GetVector(ArmRegister register)
{
byte[] value_bytes = new byte[16];
Interface.Checked(Interface.uc_reg_read(uc, (int)register, value_bytes));
unsafe
{
fixed (byte* p = &value_bytes[0])
{
return Sse.LoadVector128((float*)p);
}
}
}
internal void SetVector(ArmRegister register, Vector128<float> value)
{
byte[] value_bytes = new byte[16];
unsafe
{
fixed (byte* p = &value_bytes[0])
{
Sse.Store((float*)p, value);
}
}
Interface.Checked(Interface.uc_reg_write(uc, (int)register, value_bytes));
}
public ulong GetX(int index)
{
Contract.Requires(index <= 30, "invalid register");
if ((uint)index > 30)
{
throw new ArgumentOutOfRangeException(nameof(index));
}
return GetRegister(X_registers[index]);
return GetRegister(XRegisters[index]);
}
public void SetX(int index, ulong value)
{
Contract.Requires(index <= 30, "invalid register");
if ((uint)index > 30)
{
throw new ArgumentOutOfRangeException(nameof(index));
}
SetRegister(X_registers[index], value);
SetRegister(XRegisters[index], value);
}
public Vector128<float> GetQ(int index)
public SimdValue GetQ(int index)
{
Contract.Requires(index <= 31, "invalid vector");
if ((uint)index > 31)
{
throw new ArgumentOutOfRangeException(nameof(index));
}
return GetVector(Q_registers[index]);
return GetVector(QRegisters[index]);
}
public void SetQ(int index, Vector128<float> value)
public void SetQ(int index, SimdValue value)
{
Contract.Requires(index <= 31, "invalid vector");
if ((uint)index > 31)
{
throw new ArgumentOutOfRangeException(nameof(index));
}
SetVector(Q_registers[index], value);
SetVector(QRegisters[index], value);
}
private ulong GetRegister(ArmRegister register)
{
byte[] data = new byte[8];
Interface.Checked(Native.Interface.uc_reg_read(uc, (int)register, data));
return (ulong)BitConverter.ToInt64(data, 0);
}
private void SetRegister(ArmRegister register, ulong value)
{
byte[] data = BitConverter.GetBytes(value);
Interface.Checked(Interface.uc_reg_write(uc, (int)register, data));
}
private SimdValue GetVector(ArmRegister register)
{
byte[] data = new byte[16];
Interface.Checked(Interface.uc_reg_read(uc, (int)register, data));
return new SimdValue(data);
}
private void SetVector(ArmRegister register, SimdValue value)
{
byte[] data = value.ToArray();
Interface.Checked(Interface.uc_reg_write(uc, (int)register, data));
}
public byte[] MemoryRead(ulong address, ulong size)
{
byte[] value = new byte[size];
Interface.Checked(Interface.uc_mem_read(uc, address, value, size));
return value;
}
public byte MemoryRead8 (ulong address) { return MemoryRead(address, 1)[0]; }
public UInt16 MemoryRead16(ulong address) { return (UInt16)BitConverter.ToInt16(MemoryRead(address, 2), 0); }
public UInt32 MemoryRead32(ulong address) { return (UInt32)BitConverter.ToInt32(MemoryRead(address, 4), 0); }
public UInt64 MemoryRead64(ulong address) { return (UInt64)BitConverter.ToInt64(MemoryRead(address, 8), 0); }
public byte MemoryRead8 (ulong address) => MemoryRead(address, 1)[0];
public UInt16 MemoryRead16(ulong address) => (UInt16)BitConverter.ToInt16(MemoryRead(address, 2), 0);
public UInt32 MemoryRead32(ulong address) => (UInt32)BitConverter.ToInt32(MemoryRead(address, 4), 0);
public UInt64 MemoryRead64(ulong address) => (UInt64)BitConverter.ToInt64(MemoryRead(address, 8), 0);
public void MemoryWrite(ulong address, byte[] value)
{
Interface.Checked(Interface.uc_mem_write(uc, address, value, (ulong)value.Length));
}
public void MemoryWrite8 (ulong address, byte value) { MemoryWrite(address, new byte[]{value}); }
public void MemoryWrite16(ulong address, Int16 value) { MemoryWrite(address, BitConverter.GetBytes(value)); }
public void MemoryWrite16(ulong address, UInt16 value) { MemoryWrite(address, BitConverter.GetBytes(value)); }
public void MemoryWrite32(ulong address, Int32 value) { MemoryWrite(address, BitConverter.GetBytes(value)); }
public void MemoryWrite32(ulong address, UInt32 value) { MemoryWrite(address, BitConverter.GetBytes(value)); }
public void MemoryWrite64(ulong address, Int64 value) { MemoryWrite(address, BitConverter.GetBytes(value)); }
public void MemoryWrite64(ulong address, UInt64 value) { MemoryWrite(address, BitConverter.GetBytes(value)); }
public void MemoryWrite8 (ulong address, byte value) => MemoryWrite(address, new byte[]{value});
public void MemoryWrite16(ulong address, Int16 value) => MemoryWrite(address, BitConverter.GetBytes(value));
public void MemoryWrite16(ulong address, UInt16 value) => MemoryWrite(address, BitConverter.GetBytes(value));
public void MemoryWrite32(ulong address, Int32 value) => MemoryWrite(address, BitConverter.GetBytes(value));
public void MemoryWrite32(ulong address, UInt32 value) => MemoryWrite(address, BitConverter.GetBytes(value));
public void MemoryWrite64(ulong address, Int64 value) => MemoryWrite(address, BitConverter.GetBytes(value));
public void MemoryWrite64(ulong address, UInt64 value) => MemoryWrite(address, BitConverter.GetBytes(value));
public void MemoryMap(ulong address, ulong size, MemoryPermission permissions)
{
@ -289,21 +294,12 @@ namespace Ryujinx.Tests.Unicorn
Interface.Checked(Interface.uc_mem_protect(uc, address, size, (uint)permissions));
}
public void DumpMemoryInformation()
{
Interface.Checked(Interface.uc_mem_regions(uc, out IntPtr regions_raw, out uint length));
Interface.MarshalArrayOf<UnicornMemoryRegion>(regions_raw, (int)length, out var regions);
foreach (var region in regions)
{
Console.WriteLine("region: begin {0:X16} end {1:X16} perms {2:X8}", region.begin, region.end, region.perms);
}
}
public static bool IsAvailable()
{
try
{
Interface.uc_version(out uint major, out uint minor);
Interface.uc_version(out _, out _);
return true;
}
catch (DllNotFoundException)