CPU: A32: Add Vadd & Vsub Wide (S/U_8/16/32) Inst.s with Test. (#1390)

2020-07-17 06:21:40 +02:00
parent 9f6b24edfd
commit 88619d71b8
7 changed files with 103 additions and 55 deletions
--- a/ARMeilleure/Decoders/OpCode32SimdRegWide.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdRegWide.cs
@ -0,0 +1,17 @@
+namespace ARMeilleure.Decoders
+{
+    sealed class OpCode32SimdRegWide : OpCode32SimdReg
+    {
+        public OpCode32SimdRegWide(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+        {
+            Q = false;
+            RegisterSize = RegisterSize.Simd64;
+
+            // Subclasses have their own handling of Vx to account for before checking.
+            if (GetType() == typeof(OpCode32SimdRegWide) && DecoderHelper.VectorArgumentsInvalid(true, Vd, Vn))
+            {
+                Instruction = InstDescriptor.Undefined;
+            }
+        }
+    }
+}