Fix vote and shuffle shader instructions on AMD GPUs (#5540)
* Move shuffle handling out of the backend to a transform pass * Handle subgroup sizes higher than 32 * Stop using the subgroup size control extension * Make GenerateShuffleFunction static * Shader cache version bump
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@@ -50,20 +50,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
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InstVote op = context.GetOp<InstVote>();
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Operand pred = GetPredicate(context, op.SrcPred, op.SrcPredInv);
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Operand res = null;
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switch (op.VoteMode)
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{
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case VoteMode.All:
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res = context.VoteAll(pred);
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break;
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case VoteMode.Any:
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res = context.VoteAny(pred);
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break;
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case VoteMode.Eq:
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res = context.VoteAllEqual(pred);
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break;
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}
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Operand res = EmitVote(context, op.VoteMode, pred);
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if (res != null)
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{
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@@ -76,7 +63,81 @@ namespace Ryujinx.Graphics.Shader.Instructions
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if (op.Dest != RegisterConsts.RegisterZeroIndex)
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{
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context.Copy(GetDest(op.Dest), context.Ballot(pred));
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context.Copy(GetDest(op.Dest), EmitBallot(context, pred));
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}
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}
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private static Operand EmitVote(EmitterContext context, VoteMode voteMode, Operand pred)
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{
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int subgroupSize = context.TranslatorContext.GpuAccessor.QueryHostSubgroupSize();
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if (subgroupSize <= 32)
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{
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return voteMode switch
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{
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VoteMode.All => context.VoteAll(pred),
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VoteMode.Any => context.VoteAny(pred),
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VoteMode.Eq => context.VoteAllEqual(pred),
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_ => null,
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};
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}
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// Emulate vote with ballot masks.
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// We do that when the GPU thread count is not 32,
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// since the shader code assumes it is 32.
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// allInvocations => ballot(pred) == ballot(true),
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// anyInvocation => ballot(pred) != 0,
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// allInvocationsEqual => ballot(pred) == balot(true) || ballot(pred) == 0
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Operand ballotMask = EmitBallot(context, pred);
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Operand AllTrue() => context.ICompareEqual(ballotMask, EmitBallot(context, Const(IrConsts.True)));
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return voteMode switch
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{
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VoteMode.All => AllTrue(),
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VoteMode.Any => context.ICompareNotEqual(ballotMask, Const(0)),
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VoteMode.Eq => context.BitwiseOr(AllTrue(), context.ICompareEqual(ballotMask, Const(0))),
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_ => null,
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};
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}
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private static Operand EmitBallot(EmitterContext context, Operand pred)
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{
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int subgroupSize = context.TranslatorContext.GpuAccessor.QueryHostSubgroupSize();
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if (subgroupSize <= 32)
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{
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return context.Ballot(pred, 0);
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}
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else if (subgroupSize == 64)
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{
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// TODO: Add support for vector destination and do that with a single operation.
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Operand laneId = context.Load(StorageKind.Input, IoVariable.SubgroupLaneId);
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Operand low = context.Ballot(pred, 0);
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Operand high = context.Ballot(pred, 1);
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return context.ConditionalSelect(context.BitwiseAnd(laneId, Const(32)), high, low);
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}
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else
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{
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// TODO: Add support for vector destination and do that with a single operation.
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Operand laneId = context.Load(StorageKind.Input, IoVariable.SubgroupLaneId);
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Operand element = context.ShiftRightU32(laneId, Const(5));
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Operand res = context.Ballot(pred, 0);
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res = context.ConditionalSelect(
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context.ICompareEqual(element, Const(1)),
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context.Ballot(pred, 1), res);
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res = context.ConditionalSelect(
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context.ICompareEqual(element, Const(2)),
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context.Ballot(pred, 2), res);
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res = context.ConditionalSelect(
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context.ICompareEqual(element, Const(3)),
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context.Ballot(pred, 3), res);
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return res;
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}
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}
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}
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