Add SQADD, UQADD, SQSUB, UQSUB, SUQADD, USQADD, SQABS, SQNEG (Scalar, Vector) instructions; add 24 Tests. Most saturation instructions now on ASoftFallback. (#314)
* Update AOpCodeTable.cs * Update AInstEmitSimdHelper.cs * Update AInstEmitSimdArithmetic.cs * Update Pseudocode.cs * Update Instructions.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update AInstEmitSimdHelper.cs * Update AInstEmitSimdHelper.cs * Update AInstEmitSimdHelper.cs * Update AInstEmitSimdHelper.cs * Update ASoftFallback.cs * Update AInstEmitSimdHelper.cs * Update ASoftFallback.cs * Update AInstEmitSimdHelper.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update ASoftFallback.cs * Update AInstEmitSimdHelper.cs * Opt. (retest).
This commit is contained in:
LDj3SNuD
gdkchan
@ -22,6 +22,17 @@ namespace Ryujinx.Tests.Cpu
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}
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#region "ValueSource"
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private static ulong[] _1B1H1S1D_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x000000000000007Ful,
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0x0000000000000080ul, 0x00000000000000FFul,
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0x0000000000007FFFul, 0x0000000000008000ul,
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0x000000000000FFFFul, 0x000000007FFFFFFFul,
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0x0000000080000000ul, 0x00000000FFFFFFFFul,
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0x7FFFFFFFFFFFFFFFul, 0x8000000000000000ul,
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0xFFFFFFFFFFFFFFFFul };
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}
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private static ulong[] _1D_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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@ -1126,6 +1137,192 @@ namespace Ryujinx.Tests.Cpu
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});
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}
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[Test, Description("SQABS <V><d>, <V><n>")]
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public void Sqabs_S_B_H_S_D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
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[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <B, H, S, D>
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{
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uint Opcode = 0x5E207800; // SQABS B0, B0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.V(1, new Bits(A));
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Shared.FPSR = new Bits((uint)Fpsr);
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SimdFp.Sqabs_S(Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
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}
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[Test, Description("SQABS <Vd>.<T>, <Vn>.<T>")]
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public void Sqabs_V_8B_4H_2S([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
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{
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uint Opcode = 0x0E207800; // SQABS V0.8B, V0.8B
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.V(1, new Bits(A));
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Shared.FPSR = new Bits((uint)Fpsr);
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SimdFp.Sqabs_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
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}
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[Test, Description("SQABS <Vd>.<T>, <Vn>.<T>")]
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public void Sqabs_V_16B_8H_4S_2D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
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[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
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{
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uint Opcode = 0x4E207800; // SQABS V0.16B, V0.16B
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
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Shared.FPSR = new Bits((uint)Fpsr);
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SimdFp.Sqabs_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
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}
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[Test, Description("SQNEG <V><d>, <V><n>")]
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public void Sqneg_S_B_H_S_D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
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[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <B, H, S, D>
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{
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uint Opcode = 0x7E207800; // SQNEG B0, B0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.V(1, new Bits(A));
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Shared.FPSR = new Bits((uint)Fpsr);
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SimdFp.Sqneg_S(Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
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}
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[Test, Description("SQNEG <Vd>.<T>, <Vn>.<T>")]
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public void Sqneg_V_8B_4H_2S([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
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[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
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{
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uint Opcode = 0x2E207800; // SQNEG V0.8B, V0.8B
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.V(1, new Bits(A));
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Shared.FPSR = new Bits((uint)Fpsr);
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SimdFp.Sqneg_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
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}
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[Test, Description("SQNEG <Vd>.<T>, <Vn>.<T>")]
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public void Sqneg_V_16B_8H_4S_2D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
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[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
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[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
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{
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uint Opcode = 0x6E207800; // SQNEG V0.16B, V0.16B
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
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Shared.FPSR = new Bits((uint)Fpsr);
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SimdFp.Sqneg_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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{
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
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}
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[Test, Description("SQXTN <Vb><d>, <Va><n>")]
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public void Sqxtn_S_HB_SH_DS([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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@ -1138,12 +1335,15 @@ namespace Ryujinx.Tests.Cpu
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.V(1, new Bits(A));
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Shared.FPSR = new Bits((uint)Fpsr);
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SimdFp.Sqxtn_S(Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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@ -1151,7 +1351,7 @@ namespace Ryujinx.Tests.Cpu
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
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Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
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}
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[Test, Description("SQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
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@ -1166,12 +1366,15 @@ namespace Ryujinx.Tests.Cpu
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
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Shared.FPSR = new Bits((uint)Fpsr);
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SimdFp.Sqxtn_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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@ -1179,7 +1382,7 @@ namespace Ryujinx.Tests.Cpu
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
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Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
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}
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[Test, Description("SQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
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@ -1194,12 +1397,15 @@ namespace Ryujinx.Tests.Cpu
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
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Shared.FPSR = new Bits((uint)Fpsr);
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SimdFp.Sqxtn_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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@ -1207,7 +1413,7 @@ namespace Ryujinx.Tests.Cpu
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
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Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
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}
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[Test, Description("SQXTUN <Vb><d>, <Va><n>")]
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@ -1222,12 +1428,15 @@ namespace Ryujinx.Tests.Cpu
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Opcode |= ((size & 3) << 22);
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Bits Op = new Bits(Opcode);
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int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
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AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
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AArch64.V(1, new Bits(A));
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Shared.FPSR = new Bits((uint)Fpsr);
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SimdFp.Sqxtun_S(Op[23, 22], Op[9, 5], Op[4, 0]);
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Assert.Multiple(() =>
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@ -1235,7 +1444,7 @@ namespace Ryujinx.Tests.Cpu
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Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
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Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
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});
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Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
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Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
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}
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||||
[Test, Description("SQXTUN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
|
||||
@ -1250,12 +1459,15 @@ namespace Ryujinx.Tests.Cpu
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Sqxtun_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
@ -1263,7 +1475,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Description("SQXTUN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
|
||||
@ -1278,12 +1490,15 @@ namespace Ryujinx.Tests.Cpu
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Sqxtun_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
@ -1291,7 +1506,100 @@ namespace Ryujinx.Tests.Cpu
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Description("SUQADD <V><d>, <V><n>")]
|
||||
public void Suqadd_S_B_H_S_D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <B, H, S, D>
|
||||
{
|
||||
uint Opcode = 0x5E203800; // SUQADD B0, B0
|
||||
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.V(1, new Bits(A));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Suqadd_S(Op[23, 22], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Description("SUQADD <Vd>.<T>, <Vn>.<T>")]
|
||||
public void Suqadd_V_8B_4H_2S([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
|
||||
{
|
||||
uint Opcode = 0x0E203800; // SUQADD V0.8B, V0.8B
|
||||
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.V(1, new Bits(A));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Suqadd_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Description("SUQADD <Vd>.<T>, <Vn>.<T>")]
|
||||
public void Suqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
|
||||
{
|
||||
uint Opcode = 0x4E203800; // SUQADD V0.16B, V0.16B
|
||||
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Suqadd_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Description("UQXTN <Vb><d>, <Va><n>")]
|
||||
@ -1306,12 +1614,15 @@ namespace Ryujinx.Tests.Cpu
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.V(1, new Bits(A));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Uqxtn_S(Op[23, 22], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
@ -1319,7 +1630,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Description("UQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
|
||||
@ -1334,12 +1645,15 @@ namespace Ryujinx.Tests.Cpu
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Uqxtn_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
@ -1347,7 +1661,7 @@ namespace Ryujinx.Tests.Cpu
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Description("UQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
|
||||
@ -1362,12 +1676,15 @@ namespace Ryujinx.Tests.Cpu
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Uqxtn_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
@ -1375,7 +1692,100 @@ namespace Ryujinx.Tests.Cpu
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27]));
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Description("USQADD <V><d>, <V><n>")]
|
||||
public void Usqadd_S_B_H_S_D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <B, H, S, D>
|
||||
{
|
||||
uint Opcode = 0x7E203800; // USQADD B0, B0
|
||||
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.V(1, new Bits(A));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Usqadd_S(Op[23, 22], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Description("USQADD <Vd>.<T>, <Vn>.<T>")]
|
||||
public void Usqadd_V_8B_4H_2S([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
|
||||
{
|
||||
uint Opcode = 0x2E203800; // USQADD V0.8B, V0.8B
|
||||
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.V(1, new Bits(A));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Usqadd_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Description("USQADD <Vd>.<T>, <Vn>.<T>")]
|
||||
public void Usqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
|
||||
{
|
||||
uint Opcode = 0x6E203800; // USQADD V0.16B, V0.16B
|
||||
Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Usqadd_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Description("XTN{2} <Vd>.<Tb>, <Vn>.<Ta>")]
|
||||
|
||||
@ -22,6 +22,17 @@ namespace Ryujinx.Tests.Cpu
|
||||
}
|
||||
|
||||
#region "ValueSource"
|
||||
private static ulong[] _1B1H1S1D_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x000000000000007Ful,
|
||||
0x0000000000000080ul, 0x00000000000000FFul,
|
||||
0x0000000000007FFFul, 0x0000000000008000ul,
|
||||
0x000000000000FFFFul, 0x000000007FFFFFFFul,
|
||||
0x0000000080000000ul, 0x00000000FFFFFFFFul,
|
||||
0x7FFFFFFFFFFFFFFFul, 0x8000000000000000ul,
|
||||
0xFFFFFFFFFFFFFFFFul };
|
||||
}
|
||||
|
||||
private static ulong[] _1D_()
|
||||
{
|
||||
return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
|
||||
@ -1721,6 +1732,216 @@ namespace Ryujinx.Tests.Cpu
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SQADD <V><d>, <V><n>, <V><m>")]
|
||||
public void Sqadd_S_B_H_S_D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <B, H, S, D>
|
||||
{
|
||||
uint Opcode = 0x5E200C00; // SQADD B0, B0, B0
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.V(1, new Bits(A));
|
||||
AArch64.V(2, new Bits(B));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Sqadd_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Sqadd_V_8B_4H_2S([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
|
||||
{
|
||||
uint Opcode = 0x0E200C00; // SQADD V0.8B, V0.8B, V0.8B
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.V(1, new Bits(A));
|
||||
AArch64.V(2, new Bits(B));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Sqadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Sqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
|
||||
{
|
||||
uint Opcode = 0x4E200C00; // SQADD V0.16B, V0.16B, V0.16B
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B, B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
||||
AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Sqadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SQSUB <V><d>, <V><n>, <V><m>")]
|
||||
public void Sqsub_S_B_H_S_D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <B, H, S, D>
|
||||
{
|
||||
uint Opcode = 0x5E202C00; // SQSUB B0, B0, B0
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.V(1, new Bits(A));
|
||||
AArch64.V(2, new Bits(B));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Sqsub_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Sqsub_V_8B_4H_2S([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
|
||||
{
|
||||
uint Opcode = 0x0E202C00; // SQSUB V0.8B, V0.8B, V0.8B
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.V(1, new Bits(A));
|
||||
AArch64.V(2, new Bits(B));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Sqsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Sqsub_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
|
||||
{
|
||||
uint Opcode = 0x4E202C00; // SQSUB V0.16B, V0.16B, V0.16B
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B, B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
||||
AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Sqsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("SSUBW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")]
|
||||
public void Ssubw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
@ -2370,6 +2591,216 @@ namespace Ryujinx.Tests.Cpu
|
||||
});
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("UQADD <V><d>, <V><n>, <V><m>")]
|
||||
public void Uqadd_S_B_H_S_D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <B, H, S, D>
|
||||
{
|
||||
uint Opcode = 0x7E200C00; // UQADD B0, B0, B0
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.V(1, new Bits(A));
|
||||
AArch64.V(2, new Bits(B));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Uqadd_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("UQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Uqadd_V_8B_4H_2S([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
|
||||
{
|
||||
uint Opcode = 0x2E200C00; // UQADD V0.8B, V0.8B, V0.8B
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.V(1, new Bits(A));
|
||||
AArch64.V(2, new Bits(B));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Uqadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("UQADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Uqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
|
||||
{
|
||||
uint Opcode = 0x6E200C00; // UQADD V0.16B, V0.16B, V0.16B
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B, B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
||||
AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Uqadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("UQSUB <V><d>, <V><n>, <V><m>")]
|
||||
public void Uqsub_S_B_H_S_D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <B, H, S, D>
|
||||
{
|
||||
uint Opcode = 0x7E202C00; // UQSUB B0, B0, B0
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.V(1, new Bits(A));
|
||||
AArch64.V(2, new Bits(B));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Uqsub_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("UQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Uqsub_V_8B_4H_2S([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
|
||||
{
|
||||
uint Opcode = 0x2E202C00; // UQSUB V0.8B, V0.8B, V0.8B
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0(A);
|
||||
Vector128<float> V2 = MakeVectorE0(B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.V(1, new Bits(A));
|
||||
AArch64.V(2, new Bits(B));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Uqsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("UQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
|
||||
public void Uqsub_V_16B_8H_4S_2D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
[Values(2u, 0u)] uint Rm,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A,
|
||||
[ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong B,
|
||||
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
|
||||
{
|
||||
uint Opcode = 0x6E202C00; // UQSUB V0.16B, V0.16B, V0.16B
|
||||
Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
|
||||
Opcode |= ((size & 3) << 22);
|
||||
Bits Op = new Bits(Opcode);
|
||||
|
||||
int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt();
|
||||
|
||||
Vector128<float> V0 = MakeVectorE0E1(Z, Z);
|
||||
Vector128<float> V1 = MakeVectorE0E1(A, A);
|
||||
Vector128<float> V2 = MakeVectorE0E1(B, B);
|
||||
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr);
|
||||
|
||||
AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
|
||||
AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
|
||||
AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
|
||||
Shared.FPSR = new Bits((uint)Fpsr);
|
||||
SimdFp.Uqsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
|
||||
|
||||
Assert.Multiple(() =>
|
||||
{
|
||||
Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
|
||||
Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
|
||||
});
|
||||
Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
|
||||
}
|
||||
|
||||
[Test, Pairwise, Description("USUBW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")]
|
||||
public void Usubw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint Rd,
|
||||
[Values(1u, 0u)] uint Rn,
|
||||
|
||||
@ -3060,6 +3060,210 @@ namespace Ryujinx.Tests.Cpu.Tester
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// sqabs_advsimd.html#SQABS_asisdmisc_R
|
||||
public static void Sqabs_S(Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = false;
|
||||
|
||||
/* Decode Scalar */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = esize;
|
||||
int elements = 1;
|
||||
|
||||
bool neg = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand = V(datasize, n);
|
||||
BigInteger element;
|
||||
bool sat;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
element = SInt(Elem(operand, e, esize));
|
||||
|
||||
if (neg)
|
||||
{
|
||||
element = -element;
|
||||
}
|
||||
else
|
||||
{
|
||||
element = Abs(element);
|
||||
}
|
||||
|
||||
(Bits _result, bool _sat) = SignedSatQ(element, esize);
|
||||
Elem(result, e, esize, _result);
|
||||
sat = _sat;
|
||||
|
||||
if (sat)
|
||||
{
|
||||
/* FPSR.QC = '1'; */
|
||||
FPSR[27] = true; // TODO: Add named fields.
|
||||
}
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// sqabs_advsimd.html#SQABS_asimdmisc_R
|
||||
public static void Sqabs_V(bool Q, Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = false;
|
||||
|
||||
/* Decode Vector */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
|
||||
/* if size:Q == '110' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = (Q ? 128 : 64);
|
||||
int elements = datasize / esize;
|
||||
|
||||
bool neg = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand = V(datasize, n);
|
||||
BigInteger element;
|
||||
bool sat;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
element = SInt(Elem(operand, e, esize));
|
||||
|
||||
if (neg)
|
||||
{
|
||||
element = -element;
|
||||
}
|
||||
else
|
||||
{
|
||||
element = Abs(element);
|
||||
}
|
||||
|
||||
(Bits _result, bool _sat) = SignedSatQ(element, esize);
|
||||
Elem(result, e, esize, _result);
|
||||
sat = _sat;
|
||||
|
||||
if (sat)
|
||||
{
|
||||
/* FPSR.QC = '1'; */
|
||||
FPSR[27] = true; // TODO: Add named fields.
|
||||
}
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// sqneg_advsimd.html#SQNEG_asisdmisc_R
|
||||
public static void Sqneg_S(Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = true;
|
||||
|
||||
/* Decode Scalar */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = esize;
|
||||
int elements = 1;
|
||||
|
||||
bool neg = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand = V(datasize, n);
|
||||
BigInteger element;
|
||||
bool sat;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
element = SInt(Elem(operand, e, esize));
|
||||
|
||||
if (neg)
|
||||
{
|
||||
element = -element;
|
||||
}
|
||||
else
|
||||
{
|
||||
element = Abs(element);
|
||||
}
|
||||
|
||||
(Bits _result, bool _sat) = SignedSatQ(element, esize);
|
||||
Elem(result, e, esize, _result);
|
||||
sat = _sat;
|
||||
|
||||
if (sat)
|
||||
{
|
||||
/* FPSR.QC = '1'; */
|
||||
FPSR[27] = true; // TODO: Add named fields.
|
||||
}
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// sqneg_advsimd.html#SQNEG_asimdmisc_R
|
||||
public static void Sqneg_V(bool Q, Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = true;
|
||||
|
||||
/* Decode Vector */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
|
||||
/* if size:Q == '110' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = (Q ? 128 : 64);
|
||||
int elements = datasize / esize;
|
||||
|
||||
bool neg = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand = V(datasize, n);
|
||||
BigInteger element;
|
||||
bool sat;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
element = SInt(Elem(operand, e, esize));
|
||||
|
||||
if (neg)
|
||||
{
|
||||
element = -element;
|
||||
}
|
||||
else
|
||||
{
|
||||
element = Abs(element);
|
||||
}
|
||||
|
||||
(Bits _result, bool _sat) = SignedSatQ(element, esize);
|
||||
Elem(result, e, esize, _result);
|
||||
sat = _sat;
|
||||
|
||||
if (sat)
|
||||
{
|
||||
/* FPSR.QC = '1'; */
|
||||
FPSR[27] = true; // TODO: Add named fields.
|
||||
}
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// sqxtn_advsimd.html#SQXTN_asisdmisc_N
|
||||
public static void Sqxtn_S(Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
@ -3228,6 +3432,96 @@ namespace Ryujinx.Tests.Cpu.Tester
|
||||
Vpart(d, part, result);
|
||||
}
|
||||
|
||||
// suqadd_advsimd.html#SUQADD_asisdmisc_R
|
||||
public static void Suqadd_S(Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = false;
|
||||
|
||||
/* Decode Scalar */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = esize;
|
||||
int elements = 1;
|
||||
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand = V(datasize, n);
|
||||
Bits operand2 = V(datasize, d);
|
||||
BigInteger op1;
|
||||
BigInteger op2;
|
||||
bool sat;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
op1 = Int(Elem(operand, e, esize), !unsigned);
|
||||
op2 = Int(Elem(operand2, e, esize), unsigned);
|
||||
|
||||
(Bits _result, bool _sat) = SatQ(op1 + op2, esize, unsigned);
|
||||
Elem(result, e, esize, _result);
|
||||
sat = _sat;
|
||||
|
||||
if (sat)
|
||||
{
|
||||
/* FPSR.QC = '1'; */
|
||||
FPSR[27] = true; // TODO: Add named fields.
|
||||
}
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// suqadd_advsimd.html#SUQADD_asimdmisc_R
|
||||
public static void Suqadd_V(bool Q, Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = false;
|
||||
|
||||
/* Decode Vector */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
|
||||
/* if size:Q == '110' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = (Q ? 128 : 64);
|
||||
int elements = datasize / esize;
|
||||
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand = V(datasize, n);
|
||||
Bits operand2 = V(datasize, d);
|
||||
BigInteger op1;
|
||||
BigInteger op2;
|
||||
bool sat;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
op1 = Int(Elem(operand, e, esize), !unsigned);
|
||||
op2 = Int(Elem(operand2, e, esize), unsigned);
|
||||
|
||||
(Bits _result, bool _sat) = SatQ(op1 + op2, esize, unsigned);
|
||||
Elem(result, e, esize, _result);
|
||||
sat = _sat;
|
||||
|
||||
if (sat)
|
||||
{
|
||||
/* FPSR.QC = '1'; */
|
||||
FPSR[27] = true; // TODO: Add named fields.
|
||||
}
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// uqxtn_advsimd.html#UQXTN_asisdmisc_N
|
||||
public static void Uqxtn_S(Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
@ -3316,6 +3610,96 @@ namespace Ryujinx.Tests.Cpu.Tester
|
||||
Vpart(d, part, result);
|
||||
}
|
||||
|
||||
// usqadd_advsimd.html#USQADD_asisdmisc_R
|
||||
public static void Usqadd_S(Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = true;
|
||||
|
||||
/* Decode Scalar */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = esize;
|
||||
int elements = 1;
|
||||
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand = V(datasize, n);
|
||||
Bits operand2 = V(datasize, d);
|
||||
BigInteger op1;
|
||||
BigInteger op2;
|
||||
bool sat;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
op1 = Int(Elem(operand, e, esize), !unsigned);
|
||||
op2 = Int(Elem(operand2, e, esize), unsigned);
|
||||
|
||||
(Bits _result, bool _sat) = SatQ(op1 + op2, esize, unsigned);
|
||||
Elem(result, e, esize, _result);
|
||||
sat = _sat;
|
||||
|
||||
if (sat)
|
||||
{
|
||||
/* FPSR.QC = '1'; */
|
||||
FPSR[27] = true; // TODO: Add named fields.
|
||||
}
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// usqadd_advsimd.html#USQADD_asimdmisc_R
|
||||
public static void Usqadd_V(bool Q, Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = true;
|
||||
|
||||
/* Decode Vector */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
|
||||
/* if size:Q == '110' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = (Q ? 128 : 64);
|
||||
int elements = datasize / esize;
|
||||
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand = V(datasize, n);
|
||||
Bits operand2 = V(datasize, d);
|
||||
BigInteger op1;
|
||||
BigInteger op2;
|
||||
bool sat;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
op1 = Int(Elem(operand, e, esize), !unsigned);
|
||||
op2 = Int(Elem(operand2, e, esize), unsigned);
|
||||
|
||||
(Bits _result, bool _sat) = SatQ(op1 + op2, esize, unsigned);
|
||||
Elem(result, e, esize, _result);
|
||||
sat = _sat;
|
||||
|
||||
if (sat)
|
||||
{
|
||||
/* FPSR.QC = '1'; */
|
||||
FPSR[27] = true; // TODO: Add named fields.
|
||||
}
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// xtn_advsimd.html
|
||||
public static void Xtn_V(bool Q, Bits size, Bits Rn, Bits Rd)
|
||||
{
|
||||
@ -4593,6 +4977,202 @@ namespace Ryujinx.Tests.Cpu.Tester
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// sqadd_advsimd.html#SQADD_asisdsame_only
|
||||
public static void Sqadd_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = false;
|
||||
|
||||
/* Decode Scalar */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = esize;
|
||||
int elements = 1;
|
||||
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand1 = V(datasize, n);
|
||||
Bits operand2 = V(datasize, m);
|
||||
BigInteger element1;
|
||||
BigInteger element2;
|
||||
BigInteger sum;
|
||||
bool sat;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
element1 = Int(Elem(operand1, e, esize), unsigned);
|
||||
element2 = Int(Elem(operand2, e, esize), unsigned);
|
||||
|
||||
sum = element1 + element2;
|
||||
|
||||
(Bits _result, bool _sat) = SatQ(sum, esize, unsigned);
|
||||
Elem(result, e, esize, _result);
|
||||
sat = _sat;
|
||||
|
||||
if (sat)
|
||||
{
|
||||
/* FPSR.QC = '1'; */
|
||||
FPSR[27] = true; // TODO: Add named fields.
|
||||
}
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// sqadd_advsimd.html#SQADD_asimdsame_only
|
||||
public static void Sqadd_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = false;
|
||||
|
||||
/* Decode Vector */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
/* if size:Q == '110' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = (Q ? 128 : 64);
|
||||
int elements = datasize / esize;
|
||||
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand1 = V(datasize, n);
|
||||
Bits operand2 = V(datasize, m);
|
||||
BigInteger element1;
|
||||
BigInteger element2;
|
||||
BigInteger sum;
|
||||
bool sat;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
element1 = Int(Elem(operand1, e, esize), unsigned);
|
||||
element2 = Int(Elem(operand2, e, esize), unsigned);
|
||||
|
||||
sum = element1 + element2;
|
||||
|
||||
(Bits _result, bool _sat) = SatQ(sum, esize, unsigned);
|
||||
Elem(result, e, esize, _result);
|
||||
sat = _sat;
|
||||
|
||||
if (sat)
|
||||
{
|
||||
/* FPSR.QC = '1'; */
|
||||
FPSR[27] = true; // TODO: Add named fields.
|
||||
}
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// sqsub_advsimd.html#SQSUB_asisdsame_only
|
||||
public static void Sqsub_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = false;
|
||||
|
||||
/* Decode Scalar */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = esize;
|
||||
int elements = 1;
|
||||
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand1 = V(datasize, n);
|
||||
Bits operand2 = V(datasize, m);
|
||||
BigInteger element1;
|
||||
BigInteger element2;
|
||||
BigInteger diff;
|
||||
bool sat;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
element1 = Int(Elem(operand1, e, esize), unsigned);
|
||||
element2 = Int(Elem(operand2, e, esize), unsigned);
|
||||
|
||||
diff = element1 - element2;
|
||||
|
||||
(Bits _result, bool _sat) = SatQ(diff, esize, unsigned);
|
||||
Elem(result, e, esize, _result);
|
||||
sat = _sat;
|
||||
|
||||
if (sat)
|
||||
{
|
||||
/* FPSR.QC = '1'; */
|
||||
FPSR[27] = true; // TODO: Add named fields.
|
||||
}
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// sqsub_advsimd.html#SQSUB_asimdsame_only
|
||||
public static void Sqsub_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = false;
|
||||
|
||||
/* Decode Vector */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
/* if size:Q == '110' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = (Q ? 128 : 64);
|
||||
int elements = datasize / esize;
|
||||
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand1 = V(datasize, n);
|
||||
Bits operand2 = V(datasize, m);
|
||||
BigInteger element1;
|
||||
BigInteger element2;
|
||||
BigInteger diff;
|
||||
bool sat;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
element1 = Int(Elem(operand1, e, esize), unsigned);
|
||||
element2 = Int(Elem(operand2, e, esize), unsigned);
|
||||
|
||||
diff = element1 - element2;
|
||||
|
||||
(Bits _result, bool _sat) = SatQ(diff, esize, unsigned);
|
||||
Elem(result, e, esize, _result);
|
||||
sat = _sat;
|
||||
|
||||
if (sat)
|
||||
{
|
||||
/* FPSR.QC = '1'; */
|
||||
FPSR[27] = true; // TODO: Add named fields.
|
||||
}
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// ssubw_advsimd.html
|
||||
public static void Ssubw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
@ -5085,6 +5665,202 @@ namespace Ryujinx.Tests.Cpu.Tester
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// uqadd_advsimd.html#UQADD_asisdsame_only
|
||||
public static void Uqadd_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = true;
|
||||
|
||||
/* Decode Scalar */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = esize;
|
||||
int elements = 1;
|
||||
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand1 = V(datasize, n);
|
||||
Bits operand2 = V(datasize, m);
|
||||
BigInteger element1;
|
||||
BigInteger element2;
|
||||
BigInteger sum;
|
||||
bool sat;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
element1 = Int(Elem(operand1, e, esize), unsigned);
|
||||
element2 = Int(Elem(operand2, e, esize), unsigned);
|
||||
|
||||
sum = element1 + element2;
|
||||
|
||||
(Bits _result, bool _sat) = SatQ(sum, esize, unsigned);
|
||||
Elem(result, e, esize, _result);
|
||||
sat = _sat;
|
||||
|
||||
if (sat)
|
||||
{
|
||||
/* FPSR.QC = '1'; */
|
||||
FPSR[27] = true; // TODO: Add named fields.
|
||||
}
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// uqadd_advsimd.html#UQADD_asimdsame_only
|
||||
public static void Uqadd_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = true;
|
||||
|
||||
/* Decode Vector */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
/* if size:Q == '110' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = (Q ? 128 : 64);
|
||||
int elements = datasize / esize;
|
||||
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand1 = V(datasize, n);
|
||||
Bits operand2 = V(datasize, m);
|
||||
BigInteger element1;
|
||||
BigInteger element2;
|
||||
BigInteger sum;
|
||||
bool sat;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
element1 = Int(Elem(operand1, e, esize), unsigned);
|
||||
element2 = Int(Elem(operand2, e, esize), unsigned);
|
||||
|
||||
sum = element1 + element2;
|
||||
|
||||
(Bits _result, bool _sat) = SatQ(sum, esize, unsigned);
|
||||
Elem(result, e, esize, _result);
|
||||
sat = _sat;
|
||||
|
||||
if (sat)
|
||||
{
|
||||
/* FPSR.QC = '1'; */
|
||||
FPSR[27] = true; // TODO: Add named fields.
|
||||
}
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// uqsub_advsimd.html#UQSUB_asisdsame_only
|
||||
public static void Uqsub_S(Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = true;
|
||||
|
||||
/* Decode Scalar */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = esize;
|
||||
int elements = 1;
|
||||
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand1 = V(datasize, n);
|
||||
Bits operand2 = V(datasize, m);
|
||||
BigInteger element1;
|
||||
BigInteger element2;
|
||||
BigInteger diff;
|
||||
bool sat;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
element1 = Int(Elem(operand1, e, esize), unsigned);
|
||||
element2 = Int(Elem(operand2, e, esize), unsigned);
|
||||
|
||||
diff = element1 - element2;
|
||||
|
||||
(Bits _result, bool _sat) = SatQ(diff, esize, unsigned);
|
||||
Elem(result, e, esize, _result);
|
||||
sat = _sat;
|
||||
|
||||
if (sat)
|
||||
{
|
||||
/* FPSR.QC = '1'; */
|
||||
FPSR[27] = true; // TODO: Add named fields.
|
||||
}
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// uqsub_advsimd.html#UQSUB_asimdsame_only
|
||||
public static void Uqsub_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
const bool U = true;
|
||||
|
||||
/* Decode Vector */
|
||||
int d = (int)UInt(Rd);
|
||||
int n = (int)UInt(Rn);
|
||||
int m = (int)UInt(Rm);
|
||||
|
||||
/* if size:Q == '110' then ReservedValue(); */
|
||||
|
||||
int esize = 8 << (int)UInt(size);
|
||||
int datasize = (Q ? 128 : 64);
|
||||
int elements = datasize / esize;
|
||||
|
||||
bool unsigned = (U == true);
|
||||
|
||||
/* Operation */
|
||||
/* CheckFPAdvSIMDEnabled64(); */
|
||||
|
||||
Bits result = new Bits(datasize);
|
||||
Bits operand1 = V(datasize, n);
|
||||
Bits operand2 = V(datasize, m);
|
||||
BigInteger element1;
|
||||
BigInteger element2;
|
||||
BigInteger diff;
|
||||
bool sat;
|
||||
|
||||
for (int e = 0; e <= elements - 1; e++)
|
||||
{
|
||||
element1 = Int(Elem(operand1, e, esize), unsigned);
|
||||
element2 = Int(Elem(operand2, e, esize), unsigned);
|
||||
|
||||
diff = element1 - element2;
|
||||
|
||||
(Bits _result, bool _sat) = SatQ(diff, esize, unsigned);
|
||||
Elem(result, e, esize, _result);
|
||||
sat = _sat;
|
||||
|
||||
if (sat)
|
||||
{
|
||||
/* FPSR.QC = '1'; */
|
||||
FPSR[27] = true; // TODO: Add named fields.
|
||||
}
|
||||
}
|
||||
|
||||
V(d, result);
|
||||
}
|
||||
|
||||
// usubw_advsimd.html
|
||||
public static void Usubw_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
|
||||
{
|
||||
|
||||
@ -1193,9 +1193,9 @@ namespace Ryujinx.Tests.Cpu.Tester
|
||||
result = BigInteger.Pow(2, N) - 1;
|
||||
saturated = true;
|
||||
}
|
||||
else if (i < 0)
|
||||
else if (i < (BigInteger)0)
|
||||
{
|
||||
result = 0;
|
||||
result = (BigInteger)0;
|
||||
saturated = true;
|
||||
}
|
||||
else
|
||||
|
||||
Reference in New Issue
Block a user