Add MUL (vector by element), fix FCVTN, make svcs use MakeError too
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@ -4,9 +4,9 @@ namespace ChocolArm64.Decoder
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{
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class AOpCodeSimdReg : AOpCodeSimd
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{
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public bool Bit3 { get; private set; }
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public int Ra { get; private set; }
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public int Rm { get; private set; }
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public bool Bit3 { get; private set; }
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public int Ra { get; private set; }
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public int Rm { get; protected set; }
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public AOpCodeSimdReg(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode)
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{
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