vleeuwenmenno/Ryujinx
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Implements some 32-bit instructions (VBIC, VTST, VSRA) (#1192)

Browse Source 
* Added some 32 bits instructions:

* VBIC
* VTST
* VSRA

* Incremented the PTC

* Add tests and fix implementation

* Fixed VBIC immediate opcode mapping

* Hey hey!

* Nit.

Co-authored-by: gdkchan <gab.dark.100@gmail.com>
Co-authored-by: LDj3SNuD <dvitiello@gmail.com>
Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
This commit is contained in:
Valentin PONS
2020-07-19 14:11:58 -04:00
committed by GitHub
parent 9d65de74fc
commit 3af2ce74ec
10 changed files with 361 additions and 66 deletions
Download Patch File Download Diff File Expand all files Collapse all files

120
Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs
View File

@ -11,11 +11,22 @@ namespace Ryujinx.Tests.Cpu
{
#if SimdLogical32
#region "ValueSource (Types)"
private static ulong[] _8B4H2S_()
{
return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
}
#endregion
#region "ValueSource (Opcodes)"
private static uint[] _Vbif_Vbit_Vbsl_Vand_Vorr_Veor_()
private static uint[] _Vbic_Vbif_Vbit_Vbsl_Vand_Vorr_Veor_I_()
{
return new uint[]
{
0xf2100110u, // VBIC D0, D0, D0
0xf3300110u, // VBIF D0, D0, D0
0xf3200110u, // VBIT D0, D0, D0
0xf3100110u, // VBSL D0, D0, D0
@ -24,68 +35,121 @@ namespace Ryujinx.Tests.Cpu
0xf3000110u // VEOR D0, D0, D0
};
}
private static uint[] _Vbic_Vorr_II_()
{
return new uint[]
{
0xf2800130u, // VBIC.I32 D0, #0 (A1)
0xf2800930u, // VBIC.I16 D0, #0 (A2)
0xf2800110u, // VORR.I32 D0, #0 (A1)
0xf2800910u // VORR.I16 D0, #0 (A2)
};
}
#endregion
private const int RndCnt = 2;
[Test, Pairwise]
public void Vbif_Vbit_Vbsl_Vand_Vorr_Veor([ValueSource("_Vbif_Vbit_Vbsl_Vand_Vorr_Veor_")] uint opcode,
[Range(0u, 4u)] uint rd,
[Range(0u, 4u)] uint rn,
[Range(0u, 4u)] uint rm,
[Random(RndCnt)] ulong z,
[Random(RndCnt)] ulong a,
[Random(RndCnt)] ulong b,
[Values] bool q)
public void Vbic_Vbif_Vbit_Vbsl_Vand_Vorr_Veor_I([ValueSource("_Vbic_Vbif_Vbit_Vbsl_Vand_Vorr_Veor_I_")] uint opcode,
[Range(0u, 5u)] uint rd,
[Range(0u, 5u)] uint rn,
[Range(0u, 5u)] uint rm,
[Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong z,
[Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong a,
[Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong b,
[Values] bool q)
{
if (q)
{
opcode |= 1 << 6;
rm <<= 1;
rn <<= 1;
rd <<= 1;
rd >>= 1; rd <<= 1;
rn >>= 1; rn <<= 1;
rm >>= 1; rm <<= 1;
}
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
V128 v0 = MakeVectorE0E1(z, z);
V128 v1 = MakeVectorE0E1(a, z);
V128 v2 = MakeVectorE0E1(b, z);
V128 v0 = MakeVectorE0E1(z, ~z);
V128 v1 = MakeVectorE0E1(a, ~a);
V128 v2 = MakeVectorE0E1(b, ~b);
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("VORR.I32 <Vd>, #<imm>")]
public void Vorr_II([Range(0u, 4u)] uint rd,
[Random(RndCnt)] ulong z,
[Random(RndCnt)] byte imm,
[Values(0u, 1u, 2u, 3u)] uint cMode,
[Values] bool q)
[Test, Pairwise]
public void Vbic_Vorr_II([ValueSource("_Vbic_Vorr_II_")] uint opcode,
[Values(0u, 1u)] uint rd,
[Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong z,
[Values(byte.MinValue, byte.MaxValue)] [Random(RndCnt)] byte imm,
[Values(0u, 1u, 2u, 3u)] uint cMode,
[Values] bool q)
{
uint opcode = 0xf2800110u; // VORR.I32 D0, #0
if ((opcode & 0x800) != 0) // cmode<3> == '1' (A2)
{
cMode &= 1;
}
if (q)
{
opcode |= 1 << 6;
rd <<= 1;
rd >>= 1; rd <<= 1;
}
opcode |= (uint)(imm & 0xf) << 0;
opcode |= (uint)(imm & 0x70) << 12;
opcode |= (uint)(imm & 0x80) << 17;
opcode |= ((uint)imm & 0xf) << 0;
opcode |= ((uint)imm & 0x70) << 12;
opcode |= ((uint)imm & 0x80) << 17;
opcode |= (cMode & 0x3) << 9;
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
V128 v0 = MakeVectorE0E1(z, z);
V128 v0 = MakeVectorE0E1(z, ~z);
SingleOpcode(opcode, v0: v0);
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("VTST.<dt> <Vd>, <Vn>, <Vm>")]
public void Vtst([Range(0u, 5u)] uint rd,
[Range(0u, 5u)] uint rn,
[Range(0u, 5u)] uint rm,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong z,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong a,
[ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong b,
[Values(0u, 1u, 2u)] uint size,
[Values] bool q)
{
uint opcode = 0xf2000810u; // VTST.8 D0, D0, D0
if (q)
{
opcode |= 1 << 6;
rd >>= 1; rd <<= 1;
rn >>= 1; rn <<= 1;
rm >>= 1; rm <<= 1;
}
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
opcode |= ((rn & 0xf) << 16) | ((rn & 0x10) << 3);
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
opcode |= (size & 0x3) << 20;
V128 v0 = MakeVectorE0E1(z, ~z);
V128 v1 = MakeVectorE0E1(a, ~a);
V128 v2 = MakeVectorE0E1(b, ~b);
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
CompareAgainstUnicorn();
}
#endif
}
}

6
Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs
View File

@ -28,7 +28,7 @@ namespace Ryujinx.Tests.Cpu
{
0xf3000d00u, // VPADD.F32 D0, D0, D0
0xf3000f00u, // VPMAX.F32 D0, D0, D0
0xf3200f00u // VPMIN.F32 D0, D0, D0
0xf3200f00u // VPMIN.F32 D0, D0, D0
};
}
@ -41,7 +41,7 @@ namespace Ryujinx.Tests.Cpu
{
VpaddI8,
0xf2000a00u, // VPMAX.S8 D0, D0, D0
0xf2000a10u // VPMIN.S8 D0, D0, D0
0xf2000a10u // VPMIN.S8 D0, D0, D0
};
}
#endregion
@ -189,7 +189,7 @@ namespace Ryujinx.Tests.Cpu
[Explicit]
[Test, Pairwise, Description("VADD.f32 V0, V0, V0")]
public void Vadd_f32([Values(0u)] uint rd,
public void Vadd_f32([Values(0u)] uint rd,
[Values(0u, 1u)] uint rn,
[Values(0u, 2u)] uint rm,
[ValueSource("_2S_F_")] ulong z0,

170
Ryujinx.Tests/Cpu/CpuTestSimdShImm32.cs
View File

@ -9,50 +9,162 @@ namespace Ryujinx.Tests.Cpu
public sealed class CpuTestSimdShImm32 : CpuTest32
{
#if SimdShImm32
#region "ValueSource (Types)"
private static ulong[] _1D_()
{
return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
}
private static ulong[] _2S_()
{
return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
}
private static ulong[] _4H_()
{
return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
}
private static ulong[] _8B_()
{
return new ulong[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
}
#endregion
#region "ValueSource (Opcodes)"
private static uint[] _Vshr_Imm_SU8_()
{
return new uint[]
{
0xf2880110u, // VSRA.S8 D0, D0, #8
0xf2880210u, // VRSHR.S8 D0, D0, #8
0xf2880010u // VSHR.S8 D0, D0, #8
};
}
private static uint[] _Vshr_Imm_SU16_()
{
return new uint[]
{
0xf2900110u, // VSRA.S16 D0, D0, #16
0xf2900210u, // VRSHR.S16 D0, D0, #16
0xf2900010u // VSHR.S16 D0, D0, #16
};
}
private static uint[] _Vshr_Imm_SU32_()
{
return new uint[]
{
0xf2a00110u, // VSRA.S32 D0, D0, #32
0xf2a00210u, // VRSHR.S32 D0, D0, #32
0xf2a00010u // VSHR.S32 D0, D0, #32
};
}
private static uint[] _Vshr_Imm_SU64_()
{
return new uint[]
{
0xf2800190u, // VSRA.S64 D0, D0, #64
0xf2800290u, // VRSHR.S64 D0, D0, #64
0xf2800090u // VSHR.S64 D0, D0, #64
};
}
#endregion
private const int RndCnt = 2;
private const int RndCntShiftImm = 2;
[Test, Pairwise]
public void Vrshr_Vshr_Imm([Values(0u)] uint rd,
[Values(2u, 0u)] uint rm,
[Values(0u, 1u, 2u, 3u)] uint size,
[Random(RndCnt), Values(0u)] uint shiftImm,
[Random(RndCnt)] ulong z,
[Random(RndCnt)] ulong a,
[Random(RndCnt)] ulong b,
[Values] bool u,
[Values] bool q,
[Values] bool round)
public void Vshr_Imm_SU8([ValueSource("_Vshr_Imm_SU8_")] uint opcode,
[Range(0u, 3u)] uint rd,
[Range(0u, 3u)] uint rm,
[ValueSource("_8B_")] [Random(RndCnt)] ulong z,
[ValueSource("_8B_")] [Random(RndCnt)] ulong b,
[Values(1u, 8u)] [Random(2u, 7u, RndCntShiftImm)] uint shiftImm,
[Values] bool u,
[Values] bool q)
{
uint opcode = 0xf2800010u; // VMOV.I32 D0, #0 (immediate value changes it into SHR)
if (q)
{
opcode |= 1 << 6;
rm <<= 1;
rd <<= 1;
}
uint imm6 = 16 - shiftImm;
if (round)
{
opcode |= 1 << 9; // Turn into VRSHR
}
Vshr_Imm_SU(opcode, rd, rm, z, b, imm6, u, q);
}
[Test, Pairwise]
public void Vshr_Imm_SU16([ValueSource("_Vshr_Imm_SU16_")] uint opcode,
[Range(0u, 3u)] uint rd,
[Range(0u, 3u)] uint rm,
[ValueSource("_4H_")] [Random(RndCnt)] ulong z,
[ValueSource("_4H_")] [Random(RndCnt)] ulong b,
[Values(1u, 16u)] [Random(2u, 15u, RndCntShiftImm)] uint shiftImm,
[Values] bool u,
[Values] bool q)
{
uint imm6 = 32 - shiftImm;
Vshr_Imm_SU(opcode, rd, rm, z, b, imm6, u, q);
}
[Test, Pairwise]
public void Vshr_Imm_SU32([ValueSource("_Vshr_Imm_SU32_")] uint opcode,
[Range(0u, 3u)] uint rd,
[Range(0u, 3u)] uint rm,
[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
[ValueSource("_2S_")] [Random(RndCnt)] ulong b,
[Values(1u, 32u)] [Random(2u, 31u, RndCntShiftImm)] uint shiftImm,
[Values] bool u,
[Values] bool q)
{
uint imm6 = 64 - shiftImm;
Vshr_Imm_SU(opcode, rd, rm, z, b, imm6, u, q);
}
[Test, Pairwise]
public void Vshr_Imm_SU64([ValueSource("_Vshr_Imm_SU64_")] uint opcode,
[Range(0u, 3u)] uint rd,
[Range(0u, 3u)] uint rm,
[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
[ValueSource("_1D_")] [Random(RndCnt)] ulong b,
[Values(1u, 64u)] [Random(2u, 63u, RndCntShiftImm)] uint shiftImm,
[Values] bool u,
[Values] bool q)
{
uint imm6 = 64 - shiftImm;
Vshr_Imm_SU(opcode, rd, rm, z, b, imm6, u, q);
}
private void Vshr_Imm_SU(uint opcode, uint rd, uint rm, ulong z, ulong b, uint imm6, bool u, bool q)
{
if (u)
{
opcode |= 1 << 24;
}
uint imm = 1u << ((int)size + 3);
imm |= shiftImm & (imm - 1);
if (q)
{
opcode |= 1 << 6;
rd >>= 1; rd <<= 1;
rm >>= 1; rm <<= 1;
}
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
opcode |= ((imm & 0x3f) << 16) | ((imm & 0x40) << 1);
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
V128 v0 = MakeVectorE0E1(z, z);
V128 v1 = MakeVectorE0E1(a, z);
V128 v2 = MakeVectorE0E1(b, z);
opcode |= (imm6 & 0x3f) << 16;
SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
V128 v0 = MakeVectorE0E1(z, ~z);
V128 v1 = MakeVectorE0E1(b, ~b);
SingleOpcode(opcode, v0: v0, v1: v1);
CompareAgainstUnicorn();
}