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CPU (A64): Add FP16/FP32 fast paths (F16C Intrinsics) for Fcvt_S, Fcvtl_V & Fcvtn_V Instructions. Now HardwareCapabilities uses CpuId. (#1650)

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* net5.0

* CPU (A64): Add FP16/FP32 fast paths (F16C Intrinsics) for Fcvt_S, Fcvtl_V & Fcvtn_V Instructions. Switch to .NET 5.0.

Nits.

Tests performed successfully in both debug and release mode (for all instructions involved).

* Address comment.

* Update appveyor.yml

* Revert "Update appveyor.yml"

This reverts commit 27cdd59e8b.

* Remove Assembler CpuId.

* Update appveyor.yml

* Address comment.
This commit is contained in:
LDj3SNuD
2020-11-18 19:35:54 +01:00
committed by GitHub
parent eafee34fee
commit 0679084f11
9 changed files with 136 additions and 62 deletions
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11
Ryujinx.Tests/Cpu/CpuTestSimd.cs
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@ -1973,15 +1973,18 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
[Test, Pairwise] [Explicit]
[Test, Pairwise] [Explicit] // Unicorn seems to default all rounding modes to RMode.Rn.
public void F_Cvt_S_SH([ValueSource("_F_Cvt_S_SH_")] uint opcodes,
[ValueSource("_1S_F_")] ulong a)
[ValueSource("_1S_F_")] ulong a,
[Values(RMode.Rn)] RMode rMode)
{
ulong z = TestContext.CurrentContext.Random.NextULong();
V128 v0 = MakeVectorE0E1(z, z);
V128 v1 = MakeVectorE0(a);
SingleOpcode(opcodes, v0: v0, v1: v1);
int fpcr = (int)rMode << (int)Fpcr.RMode;
SingleOpcode(opcodes, v0: v0, v1: v1, fpcr: fpcr);
CompareAgainstUnicorn();
}
@ -2134,7 +2137,7 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn(fpsrMask: Fpsr.Ioc | Fpsr.Ofc | Fpsr.Ufc | Fpsr.Ixc | Fpsr.Idc);
}
[Test, Pairwise] [Explicit] // Unicorn seems to default all rounding modes to RMode.Rn.
[Test, Pairwise] [Explicit]
public void F_Cvtn_V_2D2S_2D4S([ValueSource("_F_Cvtn_V_2D2S_2D4S_")] uint opcodes,
[Values(0u)] uint rd,
[Values(1u, 0u)] uint rn,